74HC4515

4-to-16 line decoder/demultiplexer with input latches;

inverting
Rev. 3 — 2 July 2018 Product data sheet

1 General description
The 74HC4515 is a 4-to-16 line decoder/demultiplexer having four binary weighted
address inputs (A0 to A3) with latches, a latch enable input (LE), an enable input (E) and
16 inverting outputs (Q0, to Q15).
When LE is HIGH, the selected output is determined by the data on An. When LE goes
LOW, the last data present at An are stored in the latches and the outputs remain stable.
When E is LOW, the selected output, determined by the contents of the latch, is LOW.
When E is HIGH, all outputs are HIGH. The enable input E does not affect the state of
the latch. When the device is used as a demultiplexer, E is the data input and A0 to A3
are the address inputs.
Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess of VCC.

2 Features and benefits

• Inverting outputs
• CMOS input levels
• 16-line demultiplexing capability
• Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs
• Complies with JEDEC standard no. 7 A
• ESD protection:
– HBM JESD22-A114F exceeds 2000 V
– MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C

3 Applications
• Digital multiplexing
• Address decoding
• Hexadecimal/BCD decoding

4 Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC4515D −40 °C to +125 °C SO24 plastic small outline package; 24 leads; SOT137-1
body width 7.5 mm
Nexperia
74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

5 Functional diagram

Q0 11 DX 0 11 X/Y 0 11
Q1 9 1 9 1 9
Q2 10 2 10 2 10
1 LE
Q3 8 3 8 3 8
Q4 7 1 C4 4 7 1 C9 4 7
2 A0
Q5 6 5 6 5 6
Q6 5 2 0 6 5 2 9D, 1 6 5
3 A1
Q7 4 3 0 7 4 3 9D, 2 7 4
4D, G
Q8 18 21 15 8 18 21 9D, 4 8 18
21 A2
Q9 17 22 3 9 17 22 9D, 8 9 17
Q10 20 10 20 10 20
22 A3
Q11 19 23 11 19 23 EN 11 19
Q12 14 12 14 12 14
23 E
Q13 13 13 13 13 13
Q14 16 14 16 14 16
Q15 15 15 15 15 15

aaa-028693 aaa-028694

Figure 1. Logic symbol Figure 2. IEC logic symbol

2 3 21 22

A0 A1 A2 A3

LE
1 LATCHES

E
23 DECODER

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15

11 9 10 8 7 6 5 4 18 17 20 19 14 13 16 15
aaa-028695

Figure 3. Functional diagram

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74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

A0
Q0

SD
Q Q1
latch
1
Q Q2
RD

Q3

A1
Q4

SD
Q Q5
latch
2
Q Q6
RD

Q7

A2
Q8

SD
Q Q9
latch
3
Q Q10
RD

Q11

A3
Q12

SD
Q Q13
latch
4
LE Q Q14
RD

Q15
E
aaa-028696

Figure 4. Logic diagram

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74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

6 Pinning information

6.1 Pinning

74HC4515

LE 1 24 VCC
A0 2 23 E
A1 3 22 A3
Q7 4 21 A2
Q6 5 20 Q10
Q5 6 19 Q11
Q4 7 18 Q8
Q3 8 17 Q9
Q1 9 16 Q14
Q2 10 15 Q15
Q0 11 14 Q12
GND 12 13 Q13

aaa-028697

Figure 5. Pin configuration for SO24 (SOT137-1)

6.2 Pin description

Table 2. Pin description
Symbol Pin Description
LE 1 latch enable input (active HIGH)
E 23 enable input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, 11, 9, 10, 8, 7, 6, 5, 4, multiplexer outputs (active LOW)
Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 18, 17, 20, 19, 14, 13, 16, 15
A0, A1, A2, A3 2, 3, 21, 22 address inputs
GND 12 ground (0 V)
VCC 24 supply voltage

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74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

7 Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
[1]
Inputs Outputs
E A0 A1 A2 A3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15
H X X X X H H H H H H H H H H H H H H H H
L L L L L L H H H H H H H H H H H H H H H
L H L L L H L H H H H H H H H H H H H H H
L L H L L H H L H H H H H H H H H H H H H
L H H L L H H H L H H H H H H H H H H H H
L L L H L H H H H L H H H H H H H H H H H
L H L H L H H H H H L H H H H H H H H H H
L L H H L H H H H H H L H H H H H H H H H
L H H H L H H H H H H H L H H H H H H H H
L L L L H H H H H H H H H L H H H H H H H
L H L L H H H H H H H H H H L H H H H H H
L L H L H H H H H H H H H H H L H H H H H
L H H L H H H H H H H H H H H H L H H H H
L L L H H H H H H H H H H H H H H L H H H
L H L H H H H H H H H H H H H H H H L H H
L L H H H H H H H H H H H H H H H H H L H
L H H H H H H H H H H H H H H H H H H H L

[1] LE = HIGH

8 Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA
IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current - 50 mA
IGND ground current -50 - mA
Tstg storage temperature -65 +150 °C
[1]
Ptot total power dissipation SO24 - 500 mW

[1] Ptot derates linearly with 8 mW/K above 70 °C.

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74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

9 Recommended operating conditions

Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 2.0 5.0 6.0 V
VI input voltage 0 - VCC V
VO output voltage 0 - VCC V
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V - - 83 ns/V
Tamb ambient temperature -40 - +125 °C

10 Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb (°C) Unit
+25 −40 to +85 −40 to +125
Min Typ Max Min Max Min Max
VIH HIGH-level input VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
voltage
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level input VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
voltage
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level output VI = VIH or VIL
voltage
IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level output VI = VIH or VIL
voltage
IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

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74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

Symbol Parameter Conditions Tamb (°C) Unit

+25 −40 to +85 −40 to +125
Min Typ Max Min Max Min Max
II input leakage VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA
current
ICC supply current VI = VCC or GND; IO = 0 A; - - 8.0 - 80 - 160 μA
VCC = 6.0 V
CI input capacitance - 3.5 - - - - - pF

11 Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.
Symbol Parameter Conditions Tamb (°C) Unit
+25 −40 to +85 −40 to +125
Min Typ Max Min Max Min Max
[1]
tpd propagation delay An to Qn; see Figure 6
VCC = 2.0 V - 80 250 - 315 - 375 ns
VCC = 4.5 V - 29 50 - 63 - 75 ns
VCC = 5 V; CL = 15 pF - 25 - - - - - ns
VCC = 6.0 V - 23 43 - 54 - 64 ns
LE to Qn; see Figure 6
VCC = 2.0 V - 66 225 - 280 - 340 ns
VCC = 4.5 V - 24 45 - 56 - 68 ns
VCC = 6.0 V - 19 38 - 48 - 58 ns
E to Qn; see Figure 6
VCC = 2.0 V - 50 175 - 220 - 265 ns
VCC = 4.5 V - 18 35 - 44 - 53 ns
VCC = 6.0 V - 14 30 - 37 - 45 ns
[2]
tt transition time Qn; see Figure 6
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tW pulse witdh LE HIGH; see Figure 7
VCC = 2.0 V 75 14 - 95 - 110 - ns
VCC = 4.5 V 15 5 - 19 - 22 - ns
VCC = 6.0 V 13 4 - 16 - 19 - ns

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74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

Symbol Parameter Conditions Tamb (°C) Unit

+25 −40 to +85 −40 to +125
Min Typ Max Min Max Min Max
tsu set-up time An to LE; see Figure 7
VCC = 2.0 V 90 28 - 115 - 135 - ns
VCC = 4.5 V 18 10 - 23 - 27 - ns
VCC = 6.0 V 15 8 - 20 - 23 - ns
th hold time An to LE; see Figure 7
VCC = 2.0 V 0 −11 - 0 - 0 - ns
VCC = 4.5 V 0 −4 - 0 - 0 - ns
VCC = 6.0 V 0 −3 - 0 - 0 - ns
[3]
CPD power dissipation per package; VI = GND to VCC - 44 - - - - - pF
capacitance

[1] tpd is the same as tPLH and tPHL

[2] tt is the same as tTLH and tTHL
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
2 2
PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of load switching outputs;
2
Σ(CL x VCC x fo) = sum of the outputs.

11.1 Waveforms and test circuit

VI

LE input VM VM

GND

VI

An, E input VM VM

GND

tPHL tPLH

VOH
VY VY
Qn output VM VM
VX VX
VOL
tTHL tTLH
aaa-028698

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.
Figure 6. The inputs (An, LE, E) to output (Qn) propagation delays and the output transition times

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74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

VI

An input VM

GND
th th
tsu tsu
VI
transparant latched transparant latched
LE input VM

GND
tW
aaa-028168

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 7. Data set-up and hold times for An input to LE input and LE input pulse width

Table 8. Measurement points

Input Output
VI VM VM VX VY
GND to VCC 0.5VCC 0.5VCC 0.1VCC 0.9VCC

tW
VI
90 %
negative
VM VM
pulse
10 %
GND
tf tr
tr tf
VI
90 %
positive
VM VM
pulse
10 %
GND tW

VCC

VI VO
G DUT

RT CL

001aah768

Test data is given in Table 9.

Definitions for test circuit:
RT = Termination resistance; should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Figure 8. Test circuit for measuring switching times

Table 9. Test data

Input Load
VI tr, tf CL
GND to VCC 6 ns 15 pF, 50 pF

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74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

12 Package outline

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

D E A
X

y HE v M A

24 13

Q
A2 A
A1 (A 3 )

pin 1 index
θ
Lp
L

1 12 detail X
e w M
bp

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
max.
0.3 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1
0.1 2.25 0.36 0.23 15.2 7.4 10.00 0.4 1.0 0.4 8
o
o
0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0
inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT137-1 075E05 MS-013
03-02-19

Figure 9. Package outline SOT137-1 (SO24)

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74HC4515
4-to-16 line decoder/demultiplexer with input latches; inverting

13 Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model

14 Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC4515 v.3 20180702 Product data sheet - 74HC_HCT4515 v.2
Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Type numbers 74HCT4515D (SOT137-1), 74HC4515N (SOT101) and
74HCT4515N (SOT101) removed.
74HC_HCT4515 v.2 19930901 Product specification - 74HC_HCT4515 v.1

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4-to-16 line decoder/demultiplexer with input latches; inverting

15 Legal information

15.1 Data sheet status

[1][2] [3]
Document status Product status Definition
Objective [short] data sheet Development This document contains data from the objective specification for product
development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal
15.2 Definitions injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
Draft — The document is a draft version only. The content is still under
such equipment or applications and therefore such inclusion and/or use is at
internal review and subject to formal approval, which may result in
the customer’s own risk.
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
Applications — Applications that are described herein for any of these
and shall have no liability for the consequences of use of such information.
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
Short data sheet — A short data sheet is an extract from a full data sheet
without further testing or modification. Customers are responsible for the
with the same product type number(s) and title. A short data sheet is
design and operation of their applications and products using Nexperia
intended for quick reference only and should not be relied upon to contain
products, and Nexperia accepts no liability for any assistance with
detailed and full information. For detailed and full information see the
applications or customer product design. It is customer’s sole responsibility
relevant full data sheet, which is available on request via the local Nexperia
to determine whether the Nexperia product is suitable and fit for the
sales office. In case of any inconsistency or conflict with the short data sheet,
customer’s applications and products planned, as well as for the planned
the full data sheet shall prevail.
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
Product specification — The information and data provided in a Product
associated with their applications and products. Nexperia does not accept
data sheet shall define the specification of the product as agreed between
any liability related to any default, damage, costs or problem which is based
Nexperia and its customer, unless Nexperia and customer have explicitly
on any weakness or default in the customer’s applications or products, or
agreed otherwise in writing. In no event however, shall an agreement be
the application or use by customer’s third party customer(s). Customer is
valid in which the Nexperia product is deemed to offer functions and qualities
responsible for doing all necessary testing for the customer’s applications
beyond those described in the Product data sheet.
and products using Nexperia products in order to avoid a default of the
applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.

15.3 Disclaimers Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
Limited warranty and liability — Information in this document is believed
damage to the device. Limiting values are stress ratings only and (proper)
to be accurate and reliable. However, Nexperia does not give any
operation of the device at these or any other conditions above those
representations or warranties, expressed or implied, as to the accuracy
given in the Recommended operating conditions section (if present) or the
or completeness of such information and shall have no liability for the
Characteristics sections of this document is not warranted. Constant or
consequences of use of such information. Nexperia takes no responsibility
repeated exposure to limiting values will permanently and irreversibly affect
for the content in this document if provided by an information source outside
the quality and reliability of the device.
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
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contract or any other legal theory. Notwithstanding any damages that in a valid written individual agreement. In case an individual agreement is
customer might incur for any reason whatsoever, Nexperia's aggregate and concluded only the terms and conditions of the respective agreement shall
cumulative liability towards customer for the products described herein shall apply. Nexperia hereby expressly objects to applying the customer’s general
be limited in accordance with the Terms and conditions of commercial sale of terms and conditions with regard to the purchase of Nexperia products by
Nexperia. customer.

Right to make changes — Nexperia reserves the right to make changes No offer to sell or license — Nothing in this document may be interpreted
to information published in this document, including without limitation or construed as an offer to sell products that is open for acceptance or
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4-to-16 line decoder/demultiplexer with input latches; inverting

Non-automotive qualified products — Unless this data sheet expressly design and use of the product for automotive applications beyond Nexperia's
states that this specific Nexperia product is automotive qualified, the standard warranty and Nexperia's product specifications.
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia Translations — A non-English (translated) version of a document is for
accepts no liability for inclusion and/or use of non-automotive qualified reference only. The English version shall prevail in case of any discrepancy
products in automotive equipment or applications. In the event that customer between the translated and English versions.
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
15.4 Trademarks
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia Notice: All referenced brands, product names, service names and
for any liability, damages or failed product claims resulting from customer trademarks are the property of their respective owners.

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4-to-16 line decoder/demultiplexer with input latches; inverting

Contents
1 General description ............................................ 1
2 Features and benefits .........................................1
3 Applications .........................................................1
4 Ordering information .......................................... 1
5 Functional diagram ............................................. 2
6 Pinning information ............................................ 4
6.1 Pinning ............................................................... 4
6.2 Pin description ................................................... 4
7 Functional description ........................................5
8 Limiting values .................................................... 5
9 Recommended operating conditions ................ 6
10 Static characteristics .......................................... 6
11 Dynamic characteristics .....................................7
11.1 Waveforms and test circuit ................................ 8
12 Package outline .................................................10
13 Abbreviations .................................................... 11
14 Revision history ................................................ 11
15 Legal information .............................................. 12

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.

© Nexperia B.V. 2018. All rights reserved.

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 July 2018
Document identifier: 74HC4515