Tcan4550 q1
Tcan4550 q1
Tcan4550 q1
www.ti.com TCAN4550-Q1
SLLSEZ5C – JANUARY 2018 – REVISED OCTOBER 2020
SLLSEZ5C – JANUARY 2018 – REVISED OCTOBER 2020
TCAN4550-Q1 Automotive Control Area Network Flexible Data Rate (CAN FD)
Controller with Integrated Transceiver
1 Features 3 Description
• AEC-Q100: qualified for automotive applications The TCAN4550-Q1 is a CAN FD controller with an
– Temperature grade 1: –40°C to 125°C TA integrated CAN FD transceiver supporting data rates
• Functional safety quality-managed up to 8 Mbps. The CAN FD controller meets the
– Documentation available to aid functional safety specifications of the ISO11898-1:2015 high speed
system design up to ASIL-D/SIL-3 controller area network (CAN) data link layer and
meets the physical layer requirements of the
• CAN FD controller with integrated CAN FD
ISO11898–2:2016 high speed CAN specification. The
transceiver and serial peripheral interface (SPI)
TCAN4550-Q1 provides an interface between the
• CAN FD controller supports both ISO CAN bus and the system processor through serial
11898-1:2015 and Bosch M_CAN Revision 3.2.1.1 peripheral interface (SPI), supporting both classic
• Meets the requirements of ISO 11898-2:2016 CAN and CAN FD, allowing port expansion or CAN
• Supports CAN FD data rates up to 8 Mbps with up support with processors that do not support CAN FD.
to 18 MHz SPI clock speed The TCAN4550-Q1 provides CAN FD transceiver
• Classic CAN backwards compatible functionality: differential transmit capability to the bus
• Operating modes: normal, standby, sleep, and and differential receive capability from the bus. The
failsafe device supports wake up via local wake up (LWU) and
• 3.3 V to 5 V input/output logic support for bus wake using the CAN bus implementing the
microprocessors ISO11898-2:2016 Wake Up Pattern (WUP).
• Wide operating ranges on CAN bus The device includes many protection features
– ±58 V bus fault protection providing device and CAN bus robustness. These
– ±12 V common mode features include failsafe mode, internal dominant state
• Integrated low drop out voltage regulator suppling timeout, wide bus operating range and a time-out
5 V to CAN transceiver and up to 70 mA for watchdog as examples.
external devices Device Information
• Optimized behavior when unpowered PART NUMBER PACKAGE(1) BODY SIZE (NOM)
– Bus and logic terminals are high impedance TCAN4550-Q1 VQFN (20) 4.50 mm x 3.50 mm
(No load to operating bus or application)
– Power up and down glitch free operation (1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• Body electronics and lighting
• Infotainment and cluster
• Industrial transportion
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
Copyright © 2020 Texas
intellectual Instruments
property Incorporated
matters and other important disclaimers. PRODUCTION DATA. Submit Document Feedback 1
Product Folder Links: TCAN4550-Q1
TCAN4550-Q1
SLLSEZ5C – JANUARY 2018 – REVISED OCTOBER 2020 www.ti.com
Table of Contents
1 Features............................................................................1 8.3 Feature Description...................................................24
2 Applications..................................................................... 1 8.4 Device Functional Modes..........................................28
3 Description.......................................................................1 8.5 Programming............................................................ 41
4 Revision History.............................................................. 2 8.6 Register Maps...........................................................45
5 Pin Configuration and Functions...................................3 9 Application and Implementation................................ 129
6 Specification.................................................................... 4 9.1 Application Design Consideration........................... 129
6.1 Absolute Maximum Ratings ....................................... 4 9.2 Typical Application.................................................. 133
6.2 ESD Ratings .............................................................. 4 10 Power Supply Recommendations............................136
6.3 ESD Ratings, IEC ESD and ISO Transient 11 Layout......................................................................... 137
Specification ................................................................. 4 11.1 Layout Guidelines................................................. 137
6.4 Recommended Operating Conditions ........................5 11.2 Layout Example.................................................... 138
6.5 Thermal Information ...................................................5 12 Device and Documentation Support........................139
6.6 Supply Characteristics ............................................... 6 12.1 Documentation Support........................................ 139
6.7 Electrical Characteristics ............................................7 12.2 Receiving Notification of Documentation Updates139
6.8 Timing Requirements ............................................... 10 12.3 Support Resources............................................... 139
6.9 Switching Characteristics .........................................10 12.4 Trademarks........................................................... 139
6.10 Typical Characteristics............................................ 12 12.5 Electrostatic Discharge Caution............................139
7 Parameter Measurement Information.......................... 13 12.6 Glossary................................................................139
8 Detailed Description......................................................21 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 21 Information.................................................................. 140
8.2 Functional Block Diagram......................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2019) to Revision C (October 2020) Page
• Changed UVSUP rising max from 5.9 to 5.7 and added min value of 5.2...........................................................6
• Added UVSUP falling max value of 5.0................................................................................................................ 6
• Changed bit 2:0 To: 3:0 in Table 8-28 .............................................................................................................. 71
OSC1
OSC2
1
20
nWKRQ 2 19 RS T
GPIO1 3 18 FL TR
SCLK 4 17 VIO
nCS 7 14 VSUP
nINT 8 13 GND
GPO2 9 12 WAK E
10
11
No t to scale
CA NH
CA NL
(1) Note: DI = Digital Input; DO = Digital Output; HV = High Voltage; Thermal PAD and GND Pins must be soldered to GND
6 Specification
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Terminals stressed with respect to GND
(1) IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions per IEC
TS 62228. Different system-level configurations may lead to different results
(2) SAEJ2962-2 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request.
(3) ISO7637 is a system-level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system-level configurations may lead to different results.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) All TXD_INT, RXD_INT and EN_INT references are for internal nodes that represent the same functions for a physical layer
transceiver.
(2) Specified by design
(1) All TXD_INT, RXD_INT, EN_INT and CAN transceiver only references are for internal nodes that represent the same functions for a
stand-alone transceiver.
(2) The TXD_INT dominant time out (tTXD_INT_DTO) disables the driver of the transceiver once the TXD_INT has been dominant longer
than tTXD_INT_DTO, which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may
only transmit dominant again after TXD_INT has been returned HIGH (recessive). While this protects the bus from local faults, locking
the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits
(on TXD_INT) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the
tTXD_INT_DTO minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ tTXD_INT_DTO =
11 bits / 1.2 ms = 9.2 kbps.
(3) Time span from signal edge on TXD_INT input to next signal edge with same polarity on RXD output, the maximum of delay of both
signal edges is to be considered.
(4) ΔtRec = tBit(RXD) – tBit(Bus)
(5) Characterized but not 100% tested
(6) Specified by design
ISUP (mA)
ISUP (PA)
30
70
28 65
60
26
55
-40 °C
24 25 °C 50
55 °C
85 °C 45
22
100 °C 40
125 °C
20 35
6 8 10 12 14 16 18 20 22 24 6 8 10 12 14 16 18 20 22 24
VSUP (V) D001
VSUP (V) D003
VCCOUT = 0 V ICCOUT = 0 mA CAN Bus Load = 60 Ω VCCOUT = 5 V ICCOUT = 70 mA CAN Transceiver Off
Figure 6-1. ISUP vs VSUP Sleep Mode Figure 6-2. ISUP Current Across Temperature and
VSUP LDO Output Only.
CANH
Typical Bus Voltage
Vdiff
Vdiff
CANL
CANH
VCC/2
A
RXD_INT
Bias
B
Unit
CANL
A. A: Selective Wake
B. B: Standby and Sleep Modes (Low Power)
Figure 7-2. Simplified Recessive Common Mode Bias Unit and Receiver
CANH
TXD_INT
RL CL
CANL
CANL 90%
RCM
0.9 V
VO(CANL) VOD
10% 0.5 V
tR tF
CANH 1.5 V
RXD_INT
0.9 V
IO VID
0.5 V
0V
VID
tpDL
tpRH
CL_RXD_INT VO VOH
CANL
90%
70%
VO(RXD_INT)
30%
10%
VOL
tR tF
CANH RCM
VI
TXD_INT tLOOP
VI RL CL VCM 70% Falling
TXD_INT edge
RXD_INT
tBIT(Bus)
VO CL_RXD_INT
VDiff 900 mV
500 mV
VOH
70%
RXD_INT
30%
VOL
tLOOP tBIT(RXD_INT)
rising
edge
Figure 7-6. Transmitter and Receiver Timing Behavior Test Circuit and Measurement
CANH VIH
TXD_INT
TXD_INT
30%
RL CL VOD
0V
CANL VOD(D)
0.9 V
VOD
0.5 V
0V
tTXD_INT_DTO
TXD_INT
IOS VBUS
or
0V
VBUS
VBUS
0V
CVSUP
VWAKE
INH = H INH = H
INH INH
VSUP -1 V VSUP -1 V
2.0 V
1.15 V
0.4 V
VSYM
0.1
tBias
Figure 7-10. Test Signal Definition for Bias Reaction Time Measurement
tCSD
nCS
tCSH
tCSS tRSCK tFSCK
SCLK
tSISU tSIH
SDO
nCS
tSCK
tSCKH tSCKL
SCLK
tSOV
tRSO tFSO
SDO
LSB
MSB Out
Out
SDI
VSUP ~ 5.5 V
1.67 V to UVSUP
4.14 V
14 V
VSUP ± 1V
INH
tPower_Up
nWKRQ
VIO VIO on and ramp time are system dependent and not specified
FLTR
VCCOUT
tMODE_SLP_STBY_VCCOUT_ON
UVCCOUT Cleared
CLKIN is dependent on external source tCRYSTAL VIO required for Crystal/CLKIN to work.
Crystal/CLKIN This is the stable internal clock.
and timing will not be specified
STANDBY MODE
nINT Transceiver Ready
VSUP
14V
VSUP ± 1V
INH
tMODE_SLP_STBY
nWKRQ
VIO
VIO on and ramp time are system dependent and not specified
FLTR
VCCOUT
tMODE_SLP_STBY_VCCOUT_ON
UVCCOUT Cleared
CLKIN is dependent on external source tCRYSTAL VIO required for Crystal/CLKIN to work.
Crystal/CLKIN This is the stable internal clock.
and timing will not be specified
14V
VSUP
14V
VSUP ± 1V
INH
tMODE_NOM_SLP
nWKRQ
VIO
VIO off and ramp time are system dependent and not specified
FLTR
VCCOUT VCCOUT off ramp time is system dependent and not specified
VSUP
14 V
INH
nWKRQ Low
High
VIO
FLTR
5V
VCCOUT
Crystal/CLKIN
tMODE_NOM_STBY
Transceiver
8 Detailed Description
8.1 Overview
The TCAN4550-Q1 is a CAN FD controller with an integrated CAN FD transceiver supporting data rates up to 8
Mbps. The CAN FD controller meets the specifications of the ISO 11898-1:2015 high speed Controller Area
Network (CAN) data link layer and meets the physical layer requirements of the ISO 11898-2:2016 High Speed
Controller Area Network (CAN) specification providing an interface between the CAN bus and the CAN protocol
controller supporting both classical CAN and CAN FD up to 5 megabits per second (Mbps). The TCAN4550-Q1
provides CAN FD transceiver functionality: differential transmit capability to the bus and differential receive
capability from the bus. The device includes many protection features providing device and CAN bus robustness.
The device can also wake up via remote wake up using CAN bus implementing the ISO 11898-2:2016 Wake Up
Pattern (WUP). Input/Output support for 3.3 V and 5 V microprocessors using VIO pin for seamless interface.
The TCAN4550-Q1 has a Serial Peripheral Interface (SPI) that connects to a local microprocessor for the
device's configuration; transmission and reception of CAN frames. The SPI interface supports clock rates up to
18 MHz.
The CAN bus has two logical states during operation: recessive and dominant. See Figure 7-1 and Figure 7-2.
In the recessive bus state, the bus is biased to a common mode of 2.5 V via the high resistance internal input
resistors of the receiver of each node. Recessive is equivalent to logic high. The recessive state is also the idle
state.
In the dominant bus state, the bus is driven differentially by one or more drivers. Current flows through the
termination resistors and generates a differential voltage on the bus. Dominant is equivalent to logic low. A
dominant state overwrites the recessive state.
During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential
voltage of the bus is greater than the differential voltage of a single driver.
Transceivers with low power Standby Mode have a third bus state where the bus terminals are weakly biased to
ground via the high resistance internal resistors of the receiver. See Figure 7-1 and Figure 7-2. The TCAN4550-
Q1 supports auto biasing, see Section 9.1.3.2
The TCAN4550-Q1 has the ability to configure many of the pins for multiple purposes and are described in more
detail in Section 8.3 section. Much of the parametric data is based on internal links like the TXD/RXD_INT which
represent the TXD and RXD of a standalone CAN transceiver. The TCAN4550-Q1 has a test mode that maps
these signals to an external pin in order to perform compliance testing on the transceiver (TXD/RXD_INT_PHY)
and CAN core (TXD/RXD_INT_CAN) independently.
Note
• OSC1 pin is either a crystal or external clock input
• When OSC1 is used as an external clock input pin OSC2 must be connected directly to ground
• When using an external clock input on OSC1 the input voltage should be the same as the VIO
voltage rail
• The recommended crystal or clock rate to meet CAN FD 5 Mbps rates is 40 MHz
VCCINT1
TXD_INT_PHY
BIAS UNIT
TXD_INT CANH
DOMINANT
DRIVER
TIME OUT
CANL
TXD_INT
Communication Bus
OVER
EN_INT TEMP
MODE AND CONTROL LOGIC
VSUP
WAKE
WAKE WAKE
INH_CNTL
VLVRX
UNDER
VSUP VOLTAGE M
INH
U
X
WAKE UP LOGIC /
RXD_INT_PHY MONITOR
RXD_INT
LOGIC
OUTPUT Low Power Standby Bus
RXD_INT Receiver & Monitor
VIO VIO
Chip
RST
Reset
VIO
SCLK
SCLK
VIO
SDI
SDI
VIO
SDO
SDO
VIO
nCS
GPI
VIO
RXD_INT_CAN
Test Mode
TXD_INT_PHY
VIO
Test Mode
TXD_INT_CAN
GPO2
RXD_INT_PHY
VIO
Test Mode
nINT EN_INT
3P6_SLEEP
WKRQ_3P6_SLEEP
nWKRQ
WKRQ_VIO
Note
This terminal should be considered a "high voltage logic" terminal. It is not a power output thus should
be used to drive the EN terminal of the system’s power management device. It should be not used as
a switch for power management supply itself. This terminal is not reverse battery protected and thus
should not be connected outside of the system module.
After a RST has taken place, a wait time of ≥ 700 µs should be used before reading or writing to the TCAN4550-
Q1.
14V
VSUP
tPULSE_WIDTH
RST
14V
INH
nWKRQ Low
High
VIO • 700 µs
Figure 8-3. Timing for RST Pin in Normal and Standby Modes
14V
VSUP
tPULSE_WIDTH
RST
14V
INH • 250 µs
Low
Float
nWKRQ
Low
High
VIO • 700 µs
defaults to an internal 3.6 V rail that is active during sleep mode. In this configuration, if a wake event takes
place, the nWKRQ pin switches from high to low. This output can be configured to be powered from the VIO rail
through SPI programming, 16'h0800[19]. When powered off of the VIO pin, the device does not insert an interrupt
until the VIO rail is stable. When configured for VIO, this pin is an open drain output and requires an external pull
up resistor to VIO rail. This configuration bit is saved for all modes of operation and does not reset in sleep mode.
As some external regulators or power management chips may need a digital logic pin for a wake up request, this
pin can be used.
Note
• This pin is active low and is logical OR of CANINT, LWU and WKERR register 16'h0820 that are
not masked
• If a pull-up resistor is placed on this pin it must be configured for power from the VIO rail
Note
This pin is an active low and is the logical OR of all faults in registers 16'h0820 and 16'h0824 that are
not masked.
Note
• In test mode the watchdog (WD) function can be used for Mode 01 CAN FD. The pin function for
WD is used by other pins in this mode but WD_ACTION reg16'h0800[17:16] = 00 and 01 are
available and WD_BIT reg16'h0800[18] is how the timer would be reset.
TSD Protected
Standby Mode
Normal Mode
SPI Write RST: L
MO = 01 RST: L Wake Sources: WAKE
RST: L SPI Write Wake Sources: CAN, WAKE INH: H
INH: H MO = 10 INH: H Wake Pin: Active
Wake Pin: Active Wake Pin: Active All GPIO: Active
All GPIO: Active SPI Write All GPIO: Active SPI: Active
Sleep Mode
SPI: Active MO = 00 SPI: Active TSD = 1
OSC: Active
OSC: Active RST: L SWE timer OSC: Active VCCOUT: Off
VCCOUT: Enabled Wake Sources: CAN, WAKE times out VCCOUT: Enabled Timer Start
INH: floating
Wake Pin: Active
nINT Pin: Off
TSD = 1 &
nWKRQ Pin: Active
Timer Expires
Other GPIO: Off TSD = 0 & TSD State
SPI: Off Wake-up Event:
Timer Expires TSD Timer
CAN bus
SPI Write OSC: Off or
MO = 00 VCCOUT: Off WAKE Pin
RST: L
Wake Sources: CAN, WAKE UVIO = 1 Normal Mode
UVIO = 1 & UVIO State INH: H
Timer Expires UVIO Timer Wake Pin: Active
All GPIO: Off
SPI: Off
Note:
x UVIO Protected status will lose the CLKIN/Crystal. During this time the digital core will reset and the M_CAN will have to be OSC: Off
reprogrammed. If timer times out and UVIO = 1 the device goes to sleep at which time all are cleared. VCCOUT: On
x If a Thermal Shutdown and UVIO event take place at the same time the device will enter sleep mode until the faults are rectified Timer Start
Note
If an under voltage event has taken place and cleared, the interrupt flags have to be cleared before
the device can enter normal mode.
Standby Mode, only one wake interrupt is given (either LWU, CANINT ). New wake interrupts is not given in
standby mode unless the device changes to normal or sleep mode and then back to standby. This prevents CAN
traffic from spamming the processor with interrupts while in standby, and it gives the processor the first wake
interrupt that was issued.
Upon power up, a power on reset or wake event from sleep mode the TCAN4550-Q1 enters standby mode. This
starts a four minute timer, tINACTIVE, that requires the processor to either reset the interrupt flags or configure the
device to normal mode. This feature makes sure the node is in the lowest power mode if the processor does not
come up properly. This automatic mode change also takes place when the device has been put into sleep mode
and receives a wake event, WUP or LWU. To disable this feature for sleep events register 16'h0800[1]
(SWE_DIS) must be set to one. This will not disable the feature when powering up or when a power on reset
takes place.
8.4.3 Sleep Mode
Sleep mode is similar to the standby mode except the SPI interface and INH is disabled. As the low power CAN
receiver is powered off of V SUP the implementer can turn off V IO. The nWKRQ pin is powered off the VSUP supply
internal logic level regulator. This allows the TCAN4550-Q1 to provide an interrupt to the MCU when a wake
event takes place with out requiring VIO to be up. When the device goes into sleep mode the power to the
registers and memory is removed to conserve power. This requires the device to be re-configured prior to being
put into normal mode. As the SPI interface is turned off the only ways to exit sleep mode is by a wake up event,
RST pin toggle or power cycle. A sleep mode status flag is provided to determine if the device entered sleep
mode through normal operation or if a fault caused the mode change. Register 16'h0820[23] provides the status.
If a fault causes the device to enter sleep mode, this flag is set to a one.
Note
Difference between sleep and standby mode
• Sleep mode reduces whole node power by shutting off INH/nWKRQ to MCU VREG and shuts off
SPI.
• Standby mode reduces TCAN4550-Q1 power as INH and nWKRQ is enabled turning on node
MCU VREG and SPI interface is active.
Note
When entering sleep mode it is possible for the TCAN4550-Q1 to assert an interrupt due to UVCCOUT
event as the LDO is powering down. This interrupt should be ignored or can be masked out by using
16'h830[22] before initiating the go to sleep command.
Once the WUP is detected, the device starts issuing wake up requests (BWRR) on the RXD_INT signal every
time a filtered dominant time is received from the bus. The first filtered dominant initiates the WUP and the bus
monitor is now waiting on a filtered recessive, other bus traffic does not reset the bus monitor. Once a filtered
recessive is received, the bus monitor is now waiting on a filtered dominant and again, other bus traffic does not
reset the bus monitor. Immediately upon receiving of the second filtered dominant the bus monitor recognizes
the WUP and transition to BWRR output. Immediately upon verification receiving a WUP the device transitions
the bus monitor into BWRR mode, and indicates all filtered dominant bus times on the RXD_INT internal signal
by driving it low for the dominant bus time that is in excess of tWK_FILTER, thus the RXD_INT output during BWRR
matches the classical 8 pin CAN devices that used the single filtered dominant on the bus as the wake up
request mechanism from ISO 11898-2:2016.
For a dominant or recessive to be considered “filtered”, the bus must be in that state for more than tWK_FILTER
time. Due to variability in the tWK_FILTER the following scenarios are applicable.
• Bus state times less than tWK_FILTER(MIN) are never detected as part of a WUP, and thus no BWRR is
generated.
• Bus state times between tWK_FILTER(MIN) and t WK_FILTER(MAX) may be detected as part of a WUP and a BWRR
may be generated.
• Bus state times more than tWK_FILTER(MAX) is always detected as part of a WUP, and thus, a BWRR is always
be generated.
See Figure 8-6 for the timing diagram of the WUP.
The pattern and tWK_FILTER time used for the WUP and BWRR prevents noise and bus stuck dominant faults
from causing false wake requests while allowing any CAN or CAN FD message to initiate a BWRR. If the device
is switched to normal mode or an under voltage event occurs on VCC the BWRR is lost. The WUP pattern must
take place within the tWK_TIMEOUT time otherwise the device is in a state waiting for the next recessive and then a
valid WUP pattern.
Bus Wake via RXD
Wake Up Pattern (WUP) ZKHUH W ” WWK_TIMEOUT
Request
Bus
Bus VDiff
INH tMODE_SLP_STBY
nWKRQ
Figure 8-6. Wake Up Pattern (WUP) and Bus Wake via RXD_INT Request (BWRR)
TXD fault stuck dominant: example PCB failure or bad software Fault is repaired & transmission capability
restored
Normal CAN communication %XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ FRPPXQLFDWLRQ IRU WKH ZKROH QHWZRUN EXW 7;' '72
prevents this and frees the bus for communication after the time tTXD_DTO.
CAN Bus
tTXD_DTO
Signal
RXD_INT
(receiver)
W ” WWAKE Wake
No Wake Threshold W • WWAKE
UP Not Crossed Wake UP
Wake
INH
RXD_INT
*
W ” WWAKE Wake
No Wake Threshold W • WWAKE
UP Not Crossed Wake UP
Wake
INH
*
RXD_INT
Note
RXD_INT is an internal signal and can be seen in Transceiver test mode when VIO is present.
nINT EN_INT
GPIO1 TXD_INT_PHY
VCCINT2 CANH
SCLK TX
SDI SPI slave, CANL
MCAN
SDO System
Core
nCS Controller
RX
GPO2 RXD_INT_PHY
GPIO1 RXD_INT_CAN
VCCINT2 CANH
SCLK TX
SDI SPI slave, CANL
MCAN
SDO System
Core
nCS Controller
RX
GPO2 TXD_INT_CAN
VCCINT2 CANH
SCLK =1 TX
SDI SPI slave, CANL
MCAN
SDO System
Core
nCS Controller
RX
VCCINT2 CANH
SCLK TX
SDI SPI slave, CANL
MCAN
SDO System
Core
nCS Controller
RX
when specific issues arise. This feature uses the Sleep Wake Error (SWE) timer to determine if the node
processor can communicate to the TCAN4550-Q1. The SWE timer is default enabled through the SWE_DIS;
16'h0800[1] = 0 but can be disabled by writing a one to this bit. Even when the timer is disabled, a power on
reset re-enables the timer and thus be active. Failsafe Feature is default disabled but can be enabled by writing
a one to 16'h0800[13], FAILSAFE_EN.
Upon power up the SWE timer starts, tINACTIVE, the processor has typically four minutes to configure the
TCAN4550-Q1, clear the PWRON flag or configure the device for normal mode; see Figure 8-14 . This feature
cannot be disabled. If the device has not had the PWRON flag cleared or been placed into normal mode, it
enters sleep mode. The device wakes up if the CAN bus provides a WUP or a local wake event takes place, thus
entering standby mode. Once in standby mode tSILENCE and tINACTIVE timers starts. If tINACTIVE expires, the
device re-enters sleep mode.
The second failure mechanism that causes the device to use the failsafe feature, if enabled, is when the device
receives a CANINT, CAN bus wake (WUP) or WAKE pin (LWU), while in sleep mode such that the device leaves
sleep mode and enters standby mode. The processor has four minutes to clear the flags and place the device
into normal mode. If this does not happen the device enters sleep mode.
The third failure mechanism that causes the device to use the failsafe feature is when in standby or normal mode
and the CANSLNT flag persists for tINACTIVE, the device enters sleep mode. Examples of events that could
create this are CLKIN or Crystal stops working, processor is no longer working and not able to exercise the SPI
bus, a go-to-sleep command comes in and the processor is not able to receive it or is not able to respond. See
state diagram Figure 8-15 .
Standby Mode
Power On
Start Up SWE Timer
tINACTIVE
No &
Does timer Cleared Stays in STBY mode
Expire and PWRON or switches to Normal
flag cleared? mode if programmed
Timed out
Sleep Mode
RST: L
Wake Sources: CAN, WAKE
INH: floating
Wake Pin: Active
nINT Pin: Off
nWKRQ Pin: Active
Other GPIO: Off
SPI: Off
OSC: Off
VCCOUT: Off
Normal Mode
0800[13] = 1
Fail Safe Mode En
Bus Inactivity
SWE Timer
SWE Timer
tINACTIVE
tINACTIVE
Monitoring CAN
Timed out
Sleep Mode
RST: L
RST: L
Wake Sources: CAN, WAKE
Wake Sources: CAN, WAKE
INH: floating
INH: floating
Wake Pin: Active
Wake Pin: Active
nINT Pin: Off
nINT Pin: Off
nWKRQ Pin: Active
nWKRQ Pin: Active
Other GPIO: Off
Other GPIO: Off
SPI: Off
SPI: Off
OSC: Off
OSC: Off
CLKOUT: Off
VCCOUT: Off
VCCOUT: Off
writing a one to 16'h0800[18] resets the WD_TIMER timer or if configured for pin control the GPIO1 behaves as
the watchdog input bit.
The TCAN4550-Q1 has two ways of setting the trigger bit: via a SPI command and, if selected, through a GPI
(GPIO1 configured as GPI). When a GPI pin is used any rising or falling edge resets the timer. A watchdog event
can be conveyed back to the microprocessor in two methods: interrupt on nINT pin or, if selected, the GPO2 pin
can be programmed to toggle upon a WD timeout. A timeout can initiate one of three actions by the TCAN4550-
Q1: interrupt, INH toggle plus putting the device into standby mode or toggle watchdog output reset pin if
enabled. The input CLKIN or crystal values needs to be entered into reg 16'h0800[27] and is either 20 MHz or
40MHz. See Table 8-2 for the register settings for the watchdog function.
Note
• If the device enters UVIO protected mode, the watchdog timer is held in reset. When the device
returns to standby mode, the timer resumes counting.
• Once the command to enter sleep mode takes place, the WD timer is turned off and does not
trigger a watchdog event.
• If the any of the watchdog registers needs to be changed, the watchdog must be disabled and the
change made and then re-enabled.
WD_BIT_SET: write a 1 to reset timer: if times out; this bit is set and then
the selected action from register 16'h0800[17:16] takes place.
18 WD_BIT_SET W1C 1'b0
Note: This is a self-clearing bit. Writing a 1 resets the timer and then the bit
clears.
Note
The internal bias should not be relied upon as only termination, especially in noisy environments but
should be considered a failsafe protection. Special care needs to be taken when the device is used
with MCUs utilizing open drain outputs.
Note
The minimum dominant TXD_INT time allowed by the TXD_INT DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven
successive dominant bits (on TXD_INT) for the worst case, where five successive dominant bits are
followed immediately by an error frame.
Note
The short circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short circuit currents. The average short circuit current may be calculated using Equation 1.
Where
• IOS(AVG) is the average short circuit current.
• %Transmit is the percentage the node is transmitting CAN messages.
• %Receive is the percentage the node is receiving CAN messages.
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages.
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages.
• IOS(SS)_REC is the recessive steady state short circuit current and IOS(SS)_DOM is the dominant steady
state short circuit current.
Note
The short circuit current and possible fault cases of the network should be taken into consideration
when sizing the power ratings of the termination resistance, other network components, and the power
supply used to generate VSUP.
Note
If a thermal shut down event happens while the device is experiencing a VIO under voltage event the
device enters sleep mode.
Note
Once an under voltage condition and interrupt flags are cleared and the VSUP supply has returned to
valid level, the device typicallys need tMODE_CHANGE to transition to normal operation. The host
processor should not attempt to send or receive messages until this transition time has expired. If EN
is low and VSUP has an under voltage event, the device goes into a protected mode which disables the
wake up receiver and places the RXD_INT output into a high impedance state.
Note
At power up, MRAM values are unknown and thus ECC values is not valid. It is important that at least
2 words (8 bytes) of payload data be written into any TX buffer element, even if the DLC is less than 8.
Failure to do this results in a M_CAN BEU error, which puts the TCAN4550-Q1 device into
initialization mode, and require user intervention before CAN communication can continue. One way
to avoid this, the MRAM should be zeroed out after power up, a power on reset or coming out of sleep
mode.
SCLK
SDI. SDO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
ACTION L C S C S C S C S C S C S C S C L C S C S C S C S C S C S C S C P
P
INTERNAL
CLK
INTERNAL_CLK = !CS xor CLK
Note
Due to needing multiples of 32 bits on each SPI transaction, the device should be wired for parallel
operation of the SPI as a bus with control to the device via nCS and not as a daisy chain of shift
registers.
The start address must be word aligned (32-bit). Any time the registers are accessed, bits [1:0] of the address
are ignored as the addresses are always word (32-bit/4-byte) aligned. As an example for accessing the M_CAN
registers, for the register 0x1004, give the SPI address 1004, 1005, 1006 or 1007, and access register 1004.
The registers are 32 bit and only 1004 is valid in this example.
When entering the MRAM start address, the 0x8000 prefix is not necessary. For example, if the desired start
address is 0x8634, then bits SA[15:0] is 0x0634.
Table 8-7 provides programming op Codes.
Notes:
• The two low order address bits is ignored
• A length of 8’h00 indicates 256 words to be transferred
WRITE_B_FL
nCS
SCLK
SDI LENGTH[7:0]
CMD: WRITE_B_FL = 8'h61 ADDRESS [15:8] ADDRESS [7:0]
=8'H02
SDO
Reg0820[7:0]
nCS
SCLK
SDI
DATA_0[31:24] DATA_0[23:16] DATA_0[15:8] DATA_0[7:0]
SDO
nCS
SCLK
SDI
DATA_1[31:24] DATA_1[23:16] DATA_1[15:8] DATA_1[7:0]
SDO
nCS
SCLK
SDO
Reg0820[7:0]
nCS
SCLK
SDI
nCS
SCLK
SDI
Note
All addresses are the lower order 16 address bit within the defined 32 bit address space.
Upper 16 address bits are ignored.
Note
The following bits are being saved when entering sleep mode and will show up bold in register maps.
• 16'h0800 bits 0, 1, 8, 9, 10, 11, 13, 14, 15, 19, 21, 22, 23, 30 and 31.
• 16'h0820 bits 18, 19 and 21
• 16'h0830 bits 14 and 15
8.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]
Figure 8-23. Modes of Operation and Pin Configuration Registers
31 30 29 28 27 26 25 24
WAKE_CONFIG WD_TIMER CLK_REF RSVD RSVD RSVD
R/W R/W R/W R R R
23 22 21 20 19 18 17 16
GPO2_CONFIG TEST_MODE_ RSVD nWKRQ_VOLT WD_BIT_SET WD_ACTION
EN AGE
R/W R/W R R/W R/W R/W
15 14 13 12 11 10 9 8
GPIO1_CONFIG FAIL_SAFE_E RSVD GPIO1_GPO_CONFIG INH_DIS nWKRQ_CONF
N IG
R/W R/W R R/W R/W R/W
7 6 5 4 3 2 1 0
MODE_SEL RSVD RSVD WD_EN DEVICE_RESE SWE_DIS TEST_MODE_
T CONFIG
R/W/U R R R/W/U R/W/U R/W R/W
Table 8-15. Modes of Operation and Pin Configuration Registers Field Descriptions
Bit Field Type Reset Description
WAKE_CONFIG: Wake pin configuration
00 = Disabled
31:30 WAKE_CONFIG R/W 2’b11 01 = Rising edge
10 = Falling edge
11 = Bi-Directional – either edge
Table 8-15. Modes of Operation and Pin Configuration Registers Field Descriptions (continued)
Bit Field Type Reset Description
WD_TIMER: Watchdog timer
00 = 60 ms
29:28 WD_TIMER R/W 2’b00 01 = 600 ms
10 = 3 s
11 = 6 s
CLK_REF: CLKIN/Crystal Frequency Reference
27 CLK_REF R/W 1'b1 0 = 20 MHz
1 = 40 MHz
26:24 RSVD R 3'b000 Reserved
GPO2_CONFIG: GPO2 Pin GPO Configuration
00 = No Action
01 = MCAN_INT 0 interrupt (Active low)
23:22 GPO2_CONFIG R/W 2’b00
10 = Watchdog output
11 = Mirrors nINT pin (Active low)
See NOTE section
TEST_MODE_EN: Test mode enable. When set device is in test
mode
21 TEST_MODE_EN R/W 1'b0
0 = Disabled
1 = Enabled
20 RSVD R 1'b0 Reserved
nWKRQ_VOLTAGE: nWKRQ Pin GPO buffer voltage rail
configuration: See #GUID-7F8075CA-78F3-4D7E-A637-
19 nWKRQ_VOLTAGE R/W 1’b0 B9752F8F1263/T5072690-66
0 = Internal voltage rail
1 = VIO voltage rail
WD_BIT_SET: Write a 1 to reset timer: if times out this bit will
set and then the selected action from 0800[17:16] will take
18 WD_BIT_SET R/W 1’b0
place. (TCAN4x50 Only otherwise reserved) This is a self-
clearing bit. Writing a 1 resets the timer and then the bit clears
WD_ACTION: Selected action when WD_TIMER times out
00 = Set interrupt flag and if a pin is configure to reflect WD
output as an interrupt the pin will show a low.
01 = Pulse INH pin and placedevice into standby mode – high to
17:16 WD_ACTION R/W 2’b00 low to high ≈300ms
10 = Pulse watchdog output pin if enabled – high to low to high
≈300ms
11 = Reserved
NOTE: Interrupt flag is always set for a WD timeout event.
GPIO1_CONFIG: GPIO1 Pin Function Select
00 = GPO
15:14 GPIO1_CONFIG R/W 2’b00 01 = Reserved
10 = GPI – Automatically becomes a WD input trigger pin.
11 = Reserved
FAIL_SAFE_EN: Fail safe mode enable:
0 = Disabled
13 FAIL_SAFE_EN R/W 1'b0
1 = Enabled
NOTE: Excludes power up fail safe.
12 RSVD R 1'b0 Reserved
GPIO1_GPO_CONFIG: GPIO1 pin GPO1 function select
00 = SPI fault Interrupt (Active low)
11:10 GPIO1_GPO_CONFIG R/W 2’b01 01 = MCAN_INT 1 (Active low)
10 = Under voltage or thermal event interrupt (Active low)
11 = Reserved
INH_DIS: INH Pin Disable
9 INH_DIS R/W 1'b0 0 = Pin enabled
1 = Pin disabled
nWKRQ_CONFIG: nWKRQ Pin Function
8 nWKRQ_CONFIG R/W 1'b0 0 = Mirrors INH function
1 = Wake request interrupt
Table 8-15. Modes of Operation and Pin Configuration Registers Field Descriptions (continued)
Bit Field Type Reset Description
MODE_SEL: Mode of operation select
00 = Sleep
01 = Standby
7:6 MODE_SEL R/W 2'b01
10 = Normal
11 = Reserved
See NOTE section
5 RSVD R 1'b1 If this bit is written to it must be a 1
4 RSVD R 1'b0 Reserved
WD_EN: Watchdog Enable
3 WD_EN R/X/U 1’b1 0 = Disabled
1 = Enabled
DEVICE_RESET: Device Reset
0 = Current configuration
2 DEVICE_RESET R/WC 1'b0
1 = Device resets to default
NOTE: Same function as RST pin
SWE_DIS: Sleep Wake Error Disable:
0 = Enabled
1 = Disabled
NOTE: This disables the device from starting the four minute
1 SWE_DIS R/W 1'b0 timer when coming out of sleep mode on a wake event. If this is
enabled a SPI read or write must take place within this four
minute window or the device will go back to sleep. This does not
disable the function for initial power on or in case of a power on
reset.
Test Mode Configuration
0 = Phy Test with TXD/RXD_INT_PHY and EN_INT are mapped
0 TEST_MODE_CONFIG R/W 1'b0 to external pins
1 = CAN Controller test with TXD/RXD_INT_CAN mapped to
external pins
Note
• The Mode of Operation changes the mode but will read back the mode the device is currently in.
• When the device is changing the device to normal mode a write of 0 to CCCR.INIT is automatically
issued and when changing from normal mode to standby or sleep modes a write of 1 to
CCCR.INIT is automatically issued.
• When GPIO1 is configured as a GPO for interrupts the interrupts list represent the following and
are active low:
– 00: SPI Fault Interrupt. Matches SPIERR if not masked
– 01: MCAN_INT:1 m_can_int1.
– 10: Under Voltage or Thermal Event Interrupt: Logical OR of UVCCOUT, UVSUP , UVVIO , TSD
faults that are not masked.
• When GPIO1 is configured as a GPO for interrupts the interrupts list represent the following and
are active low:
– 00: SPI Fault Interrupt. Matches SPIERR if not masked
– 01: MCAN_INT:1 m_can_int1.
– 10: Under Voltage or Thermal Event Interrupt: Logical OR of UVCCOUT, UVSUP , UVVIO , TSD
faults that are not masked.
• nWKRQ pin defaults to a push-pull active low configuration based off an internal voltage rail. When
configuring this to work off of VIO the pin becomes and open drain output and a external pull up
resistor to the VIO rail is required.
8.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]
Saved in sleep mode
Figure 8-25. Test and Scratch Pad Register
31 30 29 28 27 26 25 24
Test Read and Write
R/W
23 22 21 20 19 18 17 16
Test Read and Write
R/W
15 14 13 12 11 10 9 8
Scratch Pad 1
R/W
7 6 5 4 3 2 1 0
Scratch Pad 2
R/W
8.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
This register block provides all the interrupt flags for the device. As the M-CAN interrupt flags 16'h0824 are
described in 16'h1050 MCAN register description section and will be shown here but need to go to 16'h1050 for
description. 16h’0830 is Interrupt enable to trigger an interrupt for 16'h0820.
8.6.3.1 Interrupts (address = h0820) [reset = h00100000]
Figure 8-27. Interrupts
31 30 29 28 27 26 25 24
CANBUSNOM RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RU R R R R R R R
23 22 21 20 19 18 17 16
RSVD UVSUP UVIO PWRON TSD WDTO RSVD ECCERR
R R/WC R/WC R/WC/U R/WC RU/WC R R/WC
15 14 13 12 11 10 9 8
CANINT LWU WKERR RSVD RSVD CANSLNT RSVD CANDOM
R/WC R/WC R/WC R R R/WC R R/WC
7 6 5 4 3 2 1 0
GLOBALERR nWKRQ CANERR RSVD SPIERR RSVD M_CAN_INT VTWD
R R R R R R R R
Note
PWRON Flag is cleared by either writing a 1 or by going to sleep mode or normal mode from standby
mode.
8.6.4.4 Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
Figure 8-33. Data Bit Timing & Prescaler
31 30 29 28 27 26 25 24
RSVD
R
23 22 21 20 19 18 17 16
TDC RSVD DBRP[4:0]
n R RP
15 14 13 12 11 10 9 8
RSVD DTSEG1[4:0]
R RP
7 6 5 4 3 2 1 0
DTSEG2[3:0] DSJW[3:0]
RP RP
Note
The TCAN4550-Q1 handles stop request through hardware. The means that a 1 should not be written
to CCCR.CSR (Clock Stop Request) as this will interfere with normal operation. If a Read-Modify-
Write operation is performed in Standby mode a CSR = 1 will be read back but a 0 should be written
to it.
8.6.4.8 Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
Figure 8-37. Nominal Bit Timing & Prescaler Register
31 30 29 28 27 26 25 24
NSJW[6:0] NBRP[8]
RP RP
23 22 21 20 19 18 17 16
NBRP[7:0]
RP
15 14 13 12 11 10 9 8
NTSEG1[7:0]
RP
7 6 5 4 3 2 1 0
RSVD NTSEG2[6:0]
R RP
Table 8-32. Nominal Bit Timing & Prescaler Register Field Descriptions
Bit Field Type Reset Description
Nominal (RE)Synchronization Jump Width
0x00 - 0x7F – Valid values are 0 to 127 - The actual
31:25 NSJW[6:0] RP 0x3
interpretation by the hardware of this value is such that one
more than the value programmed here is used.
Nominal Bit Rate Prescaler
0x000 - 0x1FF – Value by which the oscillator frequency is
24:16 NBRP[8:0] RP 0x0 divided for generating the bit time quanta. Valid values are 0 to
511. - The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
Nominal Time Segment Before Sample Point)
0x01-0xFF – Valid values are 1 to 255 - The actual interpretation
15:8 NTSEG1[7:0] RP 0xA
by the hardware of this value is such that one more than the
value programmed here is used.
7 RSVD R 0 Reserved
Nominal Time Segment After Sample Point
0x01-0x7F – Valid values are 1 to 127 - The actual interpretation
6:0 NTSEG2[6:0] RP 0x3
by the hardware of this value is such that one more than the
value programmed here is used.
Note
When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN
protocol error is detected, but CEL is still incremented.
Note
When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event
(error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD
CRC sequence will be shown as a Form Error, not Stuff Error
Note
The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting
CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus
activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129
occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At
the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the
waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been
monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily checkup whether the
CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery
sequence. ECR.REC is used to count these sequences.
23 22 21 20 19 18 17 16
RSVD
R
15 14 13 12 11 10 9 8
RBSA[15:8]
RP
7 6 5 4 3 2 1 0
RBSA[7:0]
RP
8.6.4.43.2 Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
Figure 8-74. Tx Buffer Add Request Transmission Occurred Register
31 30 29 28 27 26 25 24
TO31 TO30 TO29 TO28 TO27 TO26 TO25 TO24
R R R R R R R R
23 22 21 20 19 18 17 16
TO23 TO22 TO21 TO20 TO19 TO18 TO17 TO16
R R R R R R R R
15 14 13 12 11 10 9 8
TO15 TO14 TO13 TO12 TO11 TO10 TO9 TO8
R R R R R R R R
7 6 5 4 3 2 1 0
TO7 TO6 TO5 TO4 TO3 TO2 TO1 TO0
R R R R R R R R
8.6.4.43.5 Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
Figure 8-77. Tx Buffer Cancellation Finished Interrupt Enable Register
31 30 29 28 27 26 25 24
CFIE31 CFIE30 CFIE29 CFIE28 CFIE27 CFIE26 CFIE25 CFIE24
R/W R/W R/W R/W R/W R/W R/W R/W
23 22 21 20 19 18 17 16
CFIE23 CFIE22 CFIE21 CFIE20 CFIE19 CFIE18 CFIE17 CFIE16
R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8
CFIE15 CFIE14 CFIE13 CFIE12 CFIE11 CFIE10 CFIE9 CFIE8
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
CFIE7 CFIE6 CFIE5 CFIE4 CFIE3 CFIE2 CFIE1 CFIE0
R/W R/W R/W R/W R/W R/W R/W R/W
Note
The TCAN4550-Q1 was evaluated with the NX2016SA 20MHz and 40MHz crystals
9.1.3.1 Termination
Resistors equal to the characteristic impedance of the line should be used to terminate both ends of the cable to
prevent signal reflections. Unterminated drop-lines (stubs) connecting nodes to the bus should be kept as short
as possible to minimize signal reflections. The termination may be in a node but is generally not recommended,
especially if the node may be removed from the bus. Termination must be carefully placed so that it is not
removed from the bus. System level CAN implementations such as CANopen allow for different termination and
cabling concepts for example to add cable length.
Node 2 Node 3
Node n
(with termination)
TCAN4550
TCAN4550 TCAN1051/G TCAN1042/G
RTERM
RTERM
Termination may be a single 120 Ω resistor at each end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common mode voltage of the bus is desired then “split termination” may be used,
see Figure 9-2. Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common mode voltage levels at the start and end of message transmissions.
Standard Termination Split Termination
CANH CANH
RTERM/2
CAN CAN
Transceiver RTERM Transceiver
CSPLIT
RTERM/2
CANL CANL
tWK_TIMEOUT
1
Bus Biasing Inactive
2 tWK_TIMEOUT
Bus Biasing Inactive
Power Up &
Reset
Prog to
Sleep Prog to
Normal
Sleep Mode Standby Mode Normal Mode
Fail-Safe
Bus Bias: GND Bus Bias: GND Bus Bias: 2.5 V
WAKE Pin
Prog to Prog to
Standby or Sleep
Fault
Yes
tSILENCE tSILENCE Yes
Expired Expired
No No
tSILENCE
Expired WAKE
Standby Mode Pin Sleep Mode
WUP WUP Bus Bias: 2.5 V Bus Bias: 2.5 V
tSILENCE
Expired
INH
10 µF
10 nF 33 k
VBAT 330 nF 10 µF
100 nF
VIN EN
VSUP FLTR VCCOUT WAKE
Voltage
Regulator INH
(e.g. VINT
TPSxxxx) LDO(s) VLVRX
VOUT Filter
VIO
Under
CNTL POR
Voltage
VIO TCAN4550
10 µF 100 nF
GPO2
GPIO2
nINT
GPIO1 Optional:
GPIO1
GPIO Terminating Optional:
GND Node Filtering,
OSC1 OSC2 Transient and
ESD
40 MHz
Figure 9-6. Typical CAN Applications for TCAN4550-Q1 for 3.3 V µC and Crystal
10 µF
10 nF 33 k
VBAT 330 nF 10 µF
100 nF
VIN EN
VSUP FLTR VCCOUT WAKE
Voltage
Regulator INH
(e.g. VINT
TPSxxxx) LDO(s) VLVRX
VOUT Filter
VIO
Under
CNTL POR
VIO Voltage
TCAN4550
10 µF 100 nF
GPO2
GPIO2
nINT
GPIO1 Optional:
GPIO1
GPIO Terminating Optional:
OSC1 OSC2 GND Node Filtering,
Transient and
20 MHz
OSC1 OSC2 ESD
Figure 9-7. Typical CAN Applications for TCAN4550-Q1 for 3.3 V µC; Clock from MCU
140 5.5
5
120
4.5
100 4
3.5
VCCOUT (V)
80
ISUP (mA)
2.5
60
2
40 1.5
-40°C -40°C
25°C 25°C
55°C 1 55°C
20 85°C 85°C
105°C 0.5 105°C
125°C 125°C
0 0
0 3 6 9 12 15 18 21 24 27 30 0 3 6 9 12 15 18 21 24 27 30
VSUP (V) D003 VSUP (V) D005
A.VCCOUT = 5 V at 70 CAN Bus = CAN Load = 60 Ω A.VCCOUT = 5 V at 70 CAN Bus = CAN Load = 60 Ω
mA Dominant mA Dominant
Figure 9-8. ISUP vs VSUP CAN Dominant with 70 mA Figure 9-9. VCCOUT vs VSUP
Load on VCCOUT
Note
• The capacitance values selected should take into consideration the degradation over time such
that the values do not fall below the minimum values shown
• Above is a minimum amount of capacitance but due to system considerations more may be
needed
11 Layout
Robust and reliable bus node design often requires the use of external transient protection device in order to
protect against EFT and surge transients that may occur in industrial environments. Because ESD and transients
have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must
be applied during PCB design. The family comes with high on-chip IEC ESD protection, but if higher levels of
system level immunity are desired external TVS diodes can be used. TVS diodes and bus filtering capacitors
should be placed as close to the on-board connectors as possible to prevent noisy transient events from
propagating further into the PCB and system.
11.1 Layout Guidelines
Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and noise
from propagating onto the board. The layout example provides information on components around the device
itself. Transient voltage suppression (TVS) device can be added for extra protection, shown as D1. The
production solution can be either a bi-directional TVS diode or a varistor with ratings matching the application
requirements. This example also shows optional bus filter capacitors C10 and C11. A series common mode
choke (CMC) is placed on the CANH and CANL lines between TCAN4550-Q1 and connector J1.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device. Use supply and ground planes to provide low
inductance.
Note
High-frequency currents follows the path of least impedance and not the path of least resistance.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize
trace and via inductance.
• Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,
examples are C3, C4 and C5 on the FLTR, VIO, VCCOUT, pins and C6 and C7 on the VSUP supply.
• Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors, R5 and R6, with the center or split tap of the termination connected to ground via capacitor C9. Split
termination provides common mode filtering for the bus. When bus termination is placed on the board instead
of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the
bus thus also removing the termination.
• As terminal 8 (nINT) and 9 (GPO2) are open drain an external resistor to VIO is required. These can have a
value between 2 kΩ and 10 kΩ.
• Terminal 12 (WAKE) is a bi-directional triggered wake up input that is usually connected to an external switch.
It should be configured as shown with a 10 nF (C8) to GND where R2 is 33 kΩ and R3 is 3 kΩ.
• Terminal 15 (INH) can be left floating if not used but a 100 kΩ pull-down resistor can be used to discharge the
INH to a sufficient level when the INH output is high-Z.
20
1
nWKRQ 2 19 RST
FLTR
GPIO1 GND
C3
SCLK VIO
C4
GND
SDI VCCOUT
C5
GND
SDO INH
R1
GND
nCS VSUP
C6 C7
VIO
R7
GND
nINT
VIO C8
R6 R2
GPO2 9 12 VSUP
10
11
WAKE R3
To Switch
Choke
R5 R4
C9
C11 C10
CANL CANH
GND
D1
J1
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TCAN4550RGYRQ1 ACTIVE VQFN RGY 20 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TCAN
4550Q1
TCAN4550RGYTQ1 ACTIVE VQFN RGY 20 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TCAN
4550Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
• Catalog: TCAN4550
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jan-2021
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jan-2021
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGY 20 VQFN - 1 mm max height
3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020C SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.6 B
A
3.4
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
SECTION A-A
SCALE 30.000
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.08 C
0.00
2.2 0.1
2X 1.5
SYMM EXPOSED (0.2) TYP
THERMAL PAD
10 11
14X 0.5
9
12
4.2 0.1
SYMM 21
2X 3.2 0.1
3.5
A A
2
19
PIN 1 ID 1 20 0.3
20X
(OPTIONAL) 0.2
4X 0.25 0.05 0.1 C A B
0.5 0.05
20X
0.3
4223814/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020C VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.2)
4X (0.75) (0.85)
SYMM
1 20
20X (0.6)
2
19
20X (0.25)
(R0.05) TYP
(1.35)
(4.2)
SYMM 21 4X
(3.2) (4.3)
14X (0.5)
9 12
( 0.2) TYP
VIA
10 11
4X (0.25)
2X (0.75)
(3.3)
SOLDER MASK
METAL OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020C VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (0.98)
2X (0.25) 1 20
2X (0.2)
20X (0.6)
2
19
24X (0.25)
(R0.05) TYP 4X
(1.43)
21
SYMM
4X
(4.3)
(0.82)
TYP
14X (0.5)
9 12
EXPOSED METAL
TYP 10 11
4X (0.75) (0.59) TYP
SYMM
(3.3)
EXPOSED PAD 21
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223814/A 06/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated