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High-Efficiency, Quad-Output, Main Power Supply Controllers For Notebook Computers Features

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153 views35 pages

High-Efficiency, Quad-Output, Main Power Supply Controllers For Notebook Computers Features

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André da Hora

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®

ISL6237

Data Sheet March 18, 2008 FN6418.4

High-Efficiency, Quad-Output, Main Power Features

Supply Controllers for Notebook • Wide Input Voltage Range 5.5V to 25V
Computers
• Dual Fixed 1.05V/3.3V and 1.5V/5.0V Outputs or
The ISL6237 dual step-down, switch-mode power-supply Adjustable 0.7V to 5.5V (SMPS1) and 0.5V to 2.5V
(SMPS) controller generates logic-supply voltages in (SMPS2), ±1.5% Accuracy
battery-powered systems. The ISL6237 includes two
• 1.7ms Digital Soft-Start and Independent Shutdown
pulse-width modulation (PWM) controllers, 5V/3.3V and
1.5V/1.05V. The output of SMPS1 can also be adjusted from • Fixed 3.3V/5.0V, or Adjustable Output 0.7V to 4.5V,
0.7V to 5.5V. The SMPS2 output can be adjusted from 0.5V to ±1.5% (LDO): 200mA
2.5V by setting REFIN2 voltage. This device features a linear • 2.0V Reference Voltage
regulator providing 3.3V/5V, or adjustable from 0.7V to 4.5V
output via LDOREFIN. The linear regulator provides up to • Constant ON-TIME Control with 100ns Load-Step
100mA output current with automatic linear-regulator Response
bootstrapping to the BYP input. When in switchover, the LDO • Selectable Switching Frequency
output can source up to 200mA. The ISL6237 includes
• rDS(ON) Current Sensing
on-board power-up sequencing, power-good (POK_) outputs,
digital soft-start, and internal soft-stop output discharge that • Programmable Current Limit with Foldback Capability
prevents negative voltages on shutdown. • Selectable PWM, Skip or Ultrasonic Mode
Constant on-time PWM control scheme operates without • BOOT Voltage Monitor with Automatic Refresh
sense resistors and provides 100ns response to load
transients while maintaining a relatively constant switching • Independent POK1 and POK2 Comparators
frequency. The unique ultrasonic pulse-skipping mode • Soft-Start with Pre-Biased Output and Soft-Stop
maintains the switching frequency above 25kHz, which
• Independent ENABLE
eliminates noise in audio applications. Other features include
pulse skipping, which maximizes efficiency in light-load • High Efficiency - Up to 97%
applications, and fixed-frequency PWM mode, which reduces • Very High Light Load Efficiency (Skip Mode)
RF interference in sensitive applications.
• 5mW Quiescent Power Dissipation
Ordering Information
• Thermal Shutdown
PART TEMP.
NUMBER PART RANGE PACKAGE PKG. • Extremely Low Components Count
(Note) MARKING (°C) (Pb-free) DWG. #
• Pb-Free (RoHS Compliant)
ISL6237IRZ ISL6237 IRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B

ISL6237IRZ-T* ISL6237 IRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B

Applications
Tape and Reel • Notebook and Sub-Notebook Computers
*Please refer to TB347 for details on reel specifications.
• PDAs and Mobile Communication Devices
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach materials • 3-Cell and 4-Cell Li+ Battery-Powered Devices
and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free • DDR1, DDR2, and DDR3 Power Supplies
soldering operations. Intersil Pb-free products are MSL classified at • Graphic Cards
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020. • Game Consoles
• Telecommunication

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6237

Pinout
ISL6237
(32 LD 5x5 QFN)
TOP VIEW

PHASE2
UGATE2
REFIN2

POK2
OUT2
ILIM2

SKIP

EN2
32 31 30 29 28 27 26 25

REF 1 24 BOOT2

TON 2 23 LGATE2

VCC 3 22 PGND

EN_LDO 4 21 GND

NC 5 20 NC

VIN 6 19 PVCC

LDO 7 18 LGATE1

LDOREFIN 8 17 BOOT1

9 10 11 12 13 14 15 16
OUT1

ILIM1
BYP

FB1

POK1

EN1

UGATE1

PHASE1

2 FN6418.4
March 18, 2008
ISL6237

Absolute Voltage Ratings Thermal Information

VIN, EN_LDO to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +27V Thermal Resistance (Typical) θJA (°C/W) θJC (°CW)
BOOT_ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V 32 Ld QFN (Notes 1, 2) . . . . . . . . . . . . 32 3.0
BOOT_ to PHASE_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Operating Temperature Range . . . . . . . . . . . . . . . .-40°C to +100°C
VCC, EN_, SKIP, TON, Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
PVCC, POK_ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
LDO, FB1, REFIN2, LDOREFIN to GND . . . -0.3V to (VCC + 0.3V) Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
OUT_, REF to GND . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp
UGATE_ to PHASE_ . . . . . . . . . . . . . . . . . . -0.3V to (PVCC + 0.3V)
ILIM_ to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V)
LGATE_, BYP to GND . . . . . . . . . . . . . . . . . -0.3V to (PVCC + 0.3V)
PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 0.3V
LDO, REF Short Circuit to GND . . . . . . . . . . . . . . . . . . . Continuous
VCC Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1s
LDO Current (Internal Regulator) Continuous . . . . . . . . . . . . 100mA
LDO Current (Switched Over to OUT1) Continuous . . . . . . +200mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Limits established by characterization and are not production tested.
4. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.

Electrical Specifications No load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
VEN_LDO = 5V, TA = -40°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C.

MIN MAX
PARAMETER CONDITIONS (Note 4) TYP (Note 4) UNITS
MAIN SMPS CONTROLLERS

VIN Input Voltage Range LDO in regulation 5.5 25 V

VIN = LDO, VOUT1 < 4.43V 4.5 5.5 V

3.3V Output Voltage in Fixed Mode VIN = 5.5V to 25V, REFIN2 > (VCC - 1V), SKIP = 5V 3.285 3.330 3.375 V

1.05V Output Voltage in Fixed Mode VIN= 5.5V to 25V, 3.0 < REFIN2 < (VCC - 1.1V), 1.038 1.05 1.062 V
SKIP = 5V

1.5V Output Voltage in Fixed Mode VIN = 5.5V to 25V, FB1 = VCC, SKIP = 5V 1.482 1.500 1.518 V

5V Output Voltage in Fixed Mode VIN = 5.5V to 25V, FB1 = GND, SKIP = 5V 4.975 5.050 5.125 V

FB1 in Output Adjustable Mode VIN = 5.5V to 25V 0.693 0.700 0.707 V

REFIN2 in Output Adjustable Mode VIN = 5.5V to 25V 0.7 2.50 V

SMPS1 Output Voltage Adjust Range SMPS1 0.70 5.50 V

SMPS2 Output Voltage Adjust Range SMPS2 0.50 2.50 V

SMPS2 Output Voltage Accuracy REFIN2 = 0.7V to 2.5V, SKIP = VCC -1.0 1.0 %
(Referred for REFIN2)

DC Load Regulation Either SMPS, SKIP = VCC, 0 to 5A -0.1 %

Either SMPS, SKIP = REF, 0 to 5A -1.7 %

Either SMPS, SKIP = GND, 0 to 5A -1.5 %

Line Regulation Either SMPS, 6V < VIN < 24V 0.005 %/V

Current-Limit Current Source Temperature = +25°C 4.75 5 5.25 µA

ILIM_ Adjustment Range 0.2 2 V

Current-Limit Threshold (Positive, Default) ILIM_ = VCC, GND - PHASE_ 93 100 107 mV
(No temperature compensation)

3 FN6418.4
March 18, 2008
ISL6237

MIN MAX
PARAMETER CONDITIONS (Note 4) TYP (Note 4) UNITS
Current-Limit Threshold GND - PHASE_ VILIM_ = 0.5V 40 50 60 mV
(Positive, Adjustable)
VILIM_= 1V 93 100 107 mV

VILIM_ = 2V 185 200 215 mV

Zero-Current Threshold SKIP = GND, REF, or OPEN, GND - PHASE_ 3 mV

Current-Limit Threshold (Negative, Default) SKIP = VCC, GND - PHASE_ -120 mV

Soft-Start Ramp Time Zero to full limit 1.7 ms

Operating Frequency (VtON = GND), SKIP = VCC SMPS 1 400 kHz

SMPS 2 500 kHz

(VtON = REF or OPEN), SMPS 1 400 kHz

SKIP = VCC
SMPS 2 300 kHz

(VtON = VCC), SKIP = VCC SMPS 1 200 kHz

SMPS 2 300 kHz

On-Time Pulse Width VtON = GND (400kHz/500kHz) VOUT1 = 5.00V 0.895 1.052 1.209 µs

VOUT2 = 3.33V 0.475 0.555 0.635 µs

VtON = REF or OPEN VOUT1 = 5.05V 0.895 1.052 1.209 µs

(400kHz/300kHz)
VOUT2 = 3.33V 0.833 0.925 1.017 µs
VtON = VCC (200kHz/300kHz) VOUT1 = 5.05V 1.895 2.105 2.315 µs

VOUT2 = 3.33V 0.833 0.925 1.017 µs

Minimum Off-Time TA = -40°C to +100°C 200 300 425 ns

TA = -40°C to +85°C 200 300 410 ns

Maximum Duty Cycle VtON = GND VOUT1 = 5.05V 88 %

VOUT2 = 3.33V 85 %
VtON = REF or OPEN VOUT1 = 5.05V 88 %

VOUT2 = 3.33V 91 %

VtON = VCC VOUT1 = 5.05V 94 %

VOUT2 = 3.33V 91 %

Ultrasonic SKIP Operating Frequency SKIP = REF or OPEN 25 37 kHz

INTERNAL REGULATOR AND REFERENCE

LDO Output Voltage BYP = GND, 5.5V < VIN < 25V, LDOREFIN < 0.3V, 4.925 5.000 5.075 V
0 < ILDO < 100mA
LDO Output Voltage BYP = GND, 5.5V < VIN < 25V, LDOREFIN > (VCC - 1V), 3.250 3.300 3.350 V
0 < ILDO < 100mA

LDO Output in Adjustable Mode VIN = 5.5V to 25V, VLDO = 2 x VLDOREFIN 0.7 4.5 V

LDO Output Accuracy in Adjustable Mode VIN = 5.5V to 25V, VLDOREFIN = 0.35V to 0.5V ±2.5 %

VIN = 5.5V to 25V, VLDOREFIN = 0.5V to 2.25V ±1.5 %

LDOREFIN Input Range VLDO = 2 x VLDOREFIN 0.35 2.25 V

LDO Output Current BYP = GND, VIN = 5.5V to 25V (Note 3) 100 mA

LDO Output Current During Switchover BYP = 5V, VIN = 5.5V to 25V, LDOREFIN < 0.3V 200 mA

LDO Output Current During Switchover to BYP = 3.3V, VIN = 5.5V to 25V, LDOREFIN > (VCC - 1V) 100 mA
3.3V

4 FN6418.4
March 18, 2008
ISL6237

MIN MAX
PARAMETER CONDITIONS (Note 4) TYP (Note 4) UNITS
LDO Short-Circuit Current LDO = GND, BYP = GND 200 400 mA

Undervoltage-Lockout Fault Threshold Rising edge of PVCC 4.35 4.5 V

Falling edge of PVCC 3.9 4.05 V

LDO 5V Bootstrap Switch Threshold to BYP Rising edge at BYP regulation point 4.53 4.68 4.83 V
LDOREFIN = GND

LDO 3.3V Bootstrap Switch Threshold to Rising edge at BYP regulation point 3.0 3.1 3.2 V
BYP LDOREFIN = VCC

LDO 5V Bootstrap Switch Equivalent LDO to BYP, BYP = 5V, LDOREFIN > (VCC - 1V) (Note 3) 0.7 1.5 Ω
Resistance

LDO 3.3V Bootstrap Switch Equivalent LDO to BYP, BYP = 3.3V, LDOREFIN < 0.3V (Note 3) 1.5 3.0 Ω
Resistance

REF Output Voltage No external load 1.980 2.000 2.020 V

REF Load Regulation 0 < ILOAD < 50µA 10 mV

REF Sink Current REF in regulation 10 µA

VIN Operating Supply Current Both SMPSs on, FB1 = SKIP = GND, REFIN2 = VCC 25 50 µA
VOUT1 = BYP = 5.3V, VOUT2 = 3.5V

VIN Standby Supply Current VIN = 5.5V to 25V, both SMPSs off, EN_LDO = VCC 180 250 µA

VIN Shutdown Supply Current VIN = 4.5V to 25V, EN1 = EN2 = EN_LDO = 0V 20 30 µA

Quiescent Power Consumption Both SMPSs on, FB1 = SKIP = GND, REFIN2 = VCC, 5 7 mW
VOUT1 = BYP = 5.3V, VOUT2 = 3.5V

FAULT DETECTION

Overvoltage Trip Threshold FB1 with respect to nominal regulation point +8 +11 +14 %

REFIN2 with respect to nominal regulation point +12 +16 +20 %

Overvoltage Fault Propagation Delay FB1 or REFIN2 delay with 50mV overdrive 10 µs

POK_ Threshold FB1 or REFIN2 with respect to nominal output, falling -12 -9 -6 %
edge, typical hysteresis = 1%

POK_ Propagation Delay Falling edge, 50mV overdrive 10 µs

POK_ Output Low Voltage ISINK = 4mA 0.2 V

POK_ Leakage Current High state, forced to 5.5V 1 µA

Thermal-Shutdown Threshold +150 °C

Output Undervoltage Shutdown Threshold FB1 or REFIN2 with respect to nominal output voltage 65 70 75 %

Output Undervoltage Shutdown Blanking From EN_ signal 10 20 30 ms

Time

INPUTS AND OUTPUTS

FB1 Input Voltage Low level 0.3 V

High level VCC - 1.0 V

REFIN2 Input Voltage OUT2 Dynamic Range, VOUT2 = VREFIN2 0.5 2.50 V

Fixed OUT2 = 1.05V 3.0 VCC - 1.1 V

Fixed OUT2 = 3.3V VCC - 1.0 V

LDOREFIN Input Voltage Fixed LDO = 5V 0.30 V

LDO Dynamic Range, VLDO = 2 x VLDOREFIN 0.35 2.25 V

Fixed LDO = 3.3V VCC - 1.0 V

5 FN6418.4
March 18, 2008
ISL6237

MIN MAX
PARAMETER CONDITIONS (Note 4) TYP (Note 4) UNITS
SKIP Input Voltage Low level (SKIP) 0.8 V

Float level (ULTRASONIC SKIP) 1.7 2.3 V

High level (PWM) 2.4 V

TON Input Voltage Low level 0.8 V

Float level 1.7 2.3 V

High level 2.4 V

EN1, EN2 Input Voltage Clear fault level/SMPS off level 0.8 V

Delay start level 1.7 2.3 V

SMPS on level 2.4 V

EN_LDO Input Voltage Rising edge 1.2 1.6 2.0 V

Falling edge 0.94 1.00 1.06 V

Input Leakage Current VtON = 0 or 5V -1 +1 µA

VEN_ = VEN_LDO = 0V or 5V -0.1 +0.1 µA

VSKIP = 0V or 5V -1 +1 µA

VFB1 = 0V or 5V -0.2 +0.2 µA

VREFIN = 0V or 2.5V -0.2 +0.2 µA

VLDOREFIN = 0V or 2.75V -0.2 +0.2 µA

INTERNAL BOOT DIODE

VD Forward Voltage PVCC - VBOOT, IF = 10mA 0.65 0.8 V

IBOOT_LEAKAGE Leakage Current VBOOT = 30V, PHASE = 25V, PVCC = 5V 500 nA

MOSFET DRIVERS

UGATE_ Gate-Driver Sink/Source Current UGATE1, UGATE2 forced to 2V 2 A

LGATE_ Gate-Driver Source Current LGATE1 (source), LGATE2 (source), forced to 2V 1.7 A

LGATE_ Gate-Driver Sink Current LGATE1 (sink), LGATE2 (sink), forced to 2V 3.3 A

UGATE_ Gate-Driver ON-resistance BST_ - PHASE_ forced to 5V (Note 3) 1.5 4.0 Ω

LGATE_ Gate-Driver ON-resistance LGATE_, high state (pull-up) (Note 3) 2.2 5.0 Ω

LGATE_, low state (pull-down) (Note 3) 0.6 1.5 Ω

Dead Time LGATE_ Rising 15 20 35 ns

UGATE_ Rising 20 30 50 ns

OUT1, OUT2 Discharge ON-resistance 25 40 Ω

6 FN6418.4
March 18, 2008
ISL6237

Pin Descriptions
PIN NAME FUNCTION

1 REF 2V Reference Output. Bypass to GND with a 0.1µF (min) capacitor. REF can source up to 50µA for external loads.
Loading REF degrades FB and output accuracy according to the REF load-regulation error.

2 TON Frequency Select Input. Connect to GND for 400kHz/500kHz operation. Connect to REF (or leave OPEN) for
400kHz/300kHz operation. Connect to VCC for 200kHz/300kHz operation (5V/3.3V SMPS switching frequencies,
respectively.)

3 VCC Analog Supply Voltage Input for PWM Core. Bypass to GND with a 1µF ceramic capacitor.

4 EN_LDO LDO Enable Input. The LDO is enabled if EN_LDO is within logic high level and disabled if EN_LDO is less than the
logic low level.

5 NC No connect.

6 VIN Power-Supply Input. VIN is used for the constant-on-time PWM on-time one-shot circuits. VIN is also used to power
the linear regulators. The linear regulators are powered by SMPS1 if OUT1 is set greater than 4.78V and BYP is tied
to OUT1. Connect VIN to the battery input and bypass with a 1µF capacitor.

7 LDO Linear-Regulator Output. LDO can provide a total of 100mA external loads. The LDO regulate at 5V If LDOREFIN is
connected to GND. When the LDO is set at 5V and BYP is within 5V switchover threshold, the internal regulator shuts
down and the LDO output pin connects to BYP through a 0.7Ω switch. The LDO regulate at 3.3V if LDOREFIN is
connected to VCC. When the LDO is set at 3.3V and BYP is within 3.3V switchover threshold, the internal regulator
shuts down and the LDO output pin connects to BYP through a 1.5Ω switch. Bypass LDO output with a minimum of
4.7µF ceramic.

8 LDOREFIN LDO Reference Input. Connect LDOREFIN to GND for fixed 5V operation. Connect LDOREFIN to VCC for fixed 3.3V
operation. LDOREFIN can be used to program LDO output voltage from 0.7V to 4.5V. LDO output is two times the
voltage of LDOREFIN. There is no switchover in adjustable mode.

9 BYP BYP is the switchover source voltage for the LDO when LDOREFIN connected to GND or VCC. Connect BYP to 5V if
LDOREFIN is tied GND. Connect BYP to 3.3V if LDOREFIN is tied to VCC.

10 OUT1 SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. OUT1 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode.

11 FB1 SMPS1 Feedback Input. Connect FB1 to GND for fixed 5V operation. Connect FB1 to VCC for fixed 1.5V operation
Connect FB1 to a resistive voltage-divider from OUT1 to GND to adjust the output from 0.7V to 5.5V.

12 ILIM1 SMPS1 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over
a 0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM1. Connect ILIM1 to REF for a fixed
200mV threshold. The logic current limit threshold is default to 100mV value if ILIM1 is higher than VCC - 1V.

13 POK1 SMPS1 Power-Good Open-Drain Output. POK1 is low when the SMPS1 output voltage is more than 10% below the
normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK1 is low in shutdown.

14 EN1 SMPS1 Enable Input. The SMPS1 is enabled if EN1 is greater than the logic high level and disabled if EN1 is less than
the logic low level. If EN1 is connected to REF, the SMPS1 starts after the SMPS2 reaches regulation (delay start).
Drive EN1 below 0.8V to clear fault level and reset the fault latches.

15 UGATE1 High-Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1.

16 PHASE1 Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high-side gate driver.
PHASE1 is the current-sense input for the SMPS1.

17 BOOT1 Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the “Typical Application
Circuits” starting on page 21 (Figures 62, 63 and 64). See “MOSFET Gate Drivers (UGATE_, LGATE_)” on page 28.

18 LGATE1 SMPS1 Synchronous-Rectifier Gate-Drive Output. LGATE1 swings between GND and PVCC.

19 PVCC PVCC is the supply voltage for the low-side MOSFET driver LGATE. Connect a 5V power source to the PVCC pin and
bypass to PGND with a 1µF MLCC ceramic capacitor. Refer to Figure 65 - A switch connects PVCC to VCC with 10Ω
when in normal operation and is disconnected when in shutdown mode. An external 10Ω resistor from PVCC to VCC
is prohibited as it will create a leakage path from VIN to GND in shutdown mode.

20 NC No connect.

21 GND Analog Ground for both SMPS_ and LDO. Connect externally to the underside of the exposed pad.

22 PGND Power Ground for SMPS_ controller. Connect PGND externally to the underside of the exposed pad.

7 FN6418.4
March 18, 2008
ISL6237

Pin Descriptions (Continued)

PIN NAME FUNCTION

23 LGATE2 SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between GND and PVCC.

24 BOOT2 Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the “Typical Application
Circuits” starting on page 21 (Figures 62, 63 and 64) See “MOSFET Gate Drivers (UGATE_, LGATE_)” on page 28.

25 PHASE2 Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high-side gate driver.
PHASE2 is the current-sense input for the SMPS2.

26 UGATE2 High-Side MOSFET Floating Gate-Driver Output for SMPS2. UGATE1 swings between PHASE2 and BOOT2.

27 EN2 SMPS2 Enable Input. The SMPS2 is enabled if EN2 is greater than the logic high level and disabled if EN2 is less than
the logic low level. If EN2 is connected to REF, the SMPS2 starts after the SMPS1 reaches regulation (delay start).
Drive EN2 below 0.8V to clear fault level and reset the fault latches.

28 POK2 SMP2 Power-Good Open-Drain Output. POK2 is low when the SMPS2 output voltage is more than 10% below the
normal regulation point or during soft-start. POK2 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK2 is low in shutdown.

29 SKIP Low-Noise Mode Control. Connect SKIP to GND for normal Idle-Mode (pulse-skipping) operation or to VCC for PWM
mode (fixed frequency). Connect to REF or leave floating for ultrasonic skip mode operation.

30 OUT2 SMPS2 Output Voltage-Sense Input. Connect to the SMPS2 output. OUT2 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode.

31 ILIM2 SMPS2 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM2 over
a 0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM2. Connect ILIM2 to REF for a fixed
200mV. The logic current limit threshold is default to 100mV value if ILIM2 is higher than VCC - 1V.

32 REFIN2 Output voltage control for SMPS2. Connect REFIN2 to VCC for fixed 3.3V. Connect REFIN2 to a 3.3V supply for fixed
1.05V. REFIN2 can be used to program SMPS2 output voltage from 0.5V to 2.50V. SMPS2 output voltage is 0V if
REFIN2 < 0.5V.

Typical Performance Curves Circuit of Figures 62, 63 and 64, no load on LDO, OUT1, OUT2, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C.

7 VIN SKIP MODE 12 VIN ULTRA SKIP MODE

7 VIN SKIP MODE 12 VIN ULTRA SKIP MODE
7 VIN PWM MODE 25 VIN SKIP MODE
7 VIN PWM MODE 25 VIN SKIP MODE
7 VIN ULTRA SKIP MODE 25 VIN PWM MODE
7 VIN ULTRA SKIP MODE 25 VIN PWM MODE
12 VIN SKIP MODE 25 VIN ULTRA SKIP MODE
12 VIN SKIP MODE 25 VIN ULTRA SKIP MODE
12 VIN PWM MODE
12 VIN PWM MODE
100 100
90 90
80 80
EFFICIENCY (%)

70 70
EFFICIENCY (%)

60 60
50 50
40 40
30 30
20 20
10 10
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)

FIGURE 1. VOUT2 = 1.05V EFFICIENCY vs LOAD (300kHz) FIGURE 2. VOUT1 = 1.5V EFFICIENCY vs LOAD (200kHz)

8 FN6418.4
March 18, 2008
ISL6237

7 VIN SKIP MODE 12 VIN ULTRA SKIP MODE 7 VIN SKIP MODE 12 VIN ULTRA SKIP MODE
7 VIN PWM MODE 25 VIN SKIP MODE 7 VIN PWM MODE 25 VIN SKIP MODE
7 VIN ULTRA SKIP MODE 25 VIN PWM MODE 7 VIN ULTRA SKIP MODE 25 VIN PWM MODE
12 VIN SKIP MODE 25 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 25 VIN ULTRA SKIP MODE
12 VIN PWM MODE 12 VIN PWM MODE
100 100
90 90

EFFICIENCY (%)
80 80
70 70
EFFICIENCY (%)

60 60
50 50
40 40
30 30
20 20
10 10
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 3. VOUT2 = 3.3V EFFICIENCY vs LOAD (500kHz) FIGURE 4. VOUT1 = 5V EFFICIENCY vs LOAD (400kHz)

OUTPUT VOLTAGE (V)

1.530
1.064
1.062 1.525

1.060 1.520
1.058 1.515
1.056
1.510
1.054
1.052 1.505

1.050 1.500
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)

FIGURE 5. VOUT2 = 1.05V REGULATION vs LOAD (300kHz) FIGURE 6. VOUT1 = 1.5V REGULATION vs LOAD (200kHz)

3.37 5.14
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)

5.12
3.36
5.10
3.35
5.08
3.34
5.06
3.33
5.04
3.32 5.02

3.31 5.00
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)

FIGURE 7. VOUT2 = 3.3V REGULATION vs LOAD (500kHz) FIGURE 8. VOUT1 = 5V REGULATION vs LOAD (400kHz)

9 FN6418.4
March 18, 2008
ISL6237

POWER DISSIPATION (W)

2.0 2.0

1.5 1.5

1.0 1.0

0.5 0.5

0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)

FIGURE 9. VOUT2 = 1.05V POWER DISSIPATION vs LOAD FIGURE 10. VOUT1 = 1.5V POWER DISSIPATION vs LOAD
(300kHz) (200kHz)

3.0 3.0
POWER DISSIPATION (W)
POWER DISSIPATION (W)

2.5 2.5

2.0 2.0

1.5 1.5

1.0 1.0

0.5 0.5

0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)

FIGURE 11. VOUT2 = 3.3V POWER DISSIPATION vs LOAD FIGURE 12. VOUT1 = 5V POWER DISSIPATION vs LOAD
(500kHz) (400kHz)

1.064 1.068
NO LOAD PWM
1.062 1.066
1.064
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

1.060
1.062 NO LOAD PWM
1.058 1.060
1.056 1.058

1.054 MID LOAD PWM 1.056

1.054
1.052 MID LOAD PWM
MAX LOAD PWM 1.052
1.050
1.050 MAX
MAX LOAD
LOAD PWM
PWM
1.048 1.048
5 7 9 11 13 15 17 19 21 23 25 5 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

FIGURE 13. VOUT2 = 1.05V OUTPUT VOLTAGE REGULATION FIGURE 14. VOUT2 = 1.05V OUTPUT VOLTAGE REGULATION
vs VIN (PWM MODE) vs VIN (SKIP MODE)

10 FN6418.4
March 18, 2008
ISL6237

1.518 1.530

1.516 1.525
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

NO LOAD PWM
1.514 NO LOAD PWM
1.520
1.512 MID LOAD PWM
MID LOAD PWM 1.515
1.510
1.510
1.508 MAX LOAD PWM
MAX LOAD PWM

1.506 1.505

1.504 1.500
5 7 9 11 13 15 17 19 21 23 25 5 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

FIGURE 15. VOUT1 = 1.5V OUTPUT VOLTAGE REGULATION FIGURE 16. VOUT1 = 1.5V OUTPUT VOLTAGE REGULATION
vs VIN (PWM MODE) vs VIN (SKIP MODE)

3.340 3.38

3.37
3.335 NO LOAD PWM
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

3.36
NO LOAD PWM
3.330
3.35

3.325 3.34 MAX LOAD PWM

3.33
3.320
3.32
MID LOAD PWM
3.315
3.31 MID LOAD PWM
MAX LOAD PWM
3.310 3.30
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

FIGURE 17. VOUT2 = 3.3V OUTPUT VOLTAGE REGULATION FIGURE 18. VOUT2 = 3.3V OUTPUT VOLTAGE REGULATION
vs VIN (PWM MODE) vs VIN (SKIP MODE)

5.065
NO LOAD PWM 5.14

5.060
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

5.12

MAX LOAD PWM 5.10 NO LOAD PWM

5.055
MID LOAD PWM
5.08
5.050 MID LOAD PWM
5.06
5.045
5.04
MAX LOAD PWM
5.040 5.02
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

FIGURE 19. VOUT1 = 5V OUTPUT VOLTAGE REGULATION vs FIGURE 20. VOUT1 = 5V OUTPUT VOLTAGE REGULATION vs
VIN (PWM MODE) VIN (SKIP MODE)

11 FN6418.4
March 18, 2008
ISL6237

300 50
45
250
40
FREQUENCY (kHz)

35
200

RIPPLE (mV)
PWM 30
150 25 PWM
ULTRA-SKIP
20
100
ULTRA-SKIP 15
10
50 SKIP
5
SKIP
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)

FIGURE 21. VOUT2 = 1.05V FREQUENCY vs LOAD FIGURE 22. VOUT2 = 1.05V RIPPLE vs LOAD

250 50

PWM 45
200 40
PWM
FREQUENCY (kHz)

35
RIPPLE (mV)

150 30
25
20 ULTRA-SKIP SKIP
100
ULTRA-SKIP
15
50 10
SKIP 5
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)

FIGURE 23. VOUT1 = 1.5V FREQUENCY vs LOAD FIGURE 24. VOUT1 = 1.5V RIPPLE vs LOAD

600 14
PWM PWM
500 12
FREQUENCY (kHz)

10
400
RIPPLE (mV)

8 ULTRA-SKIP
300 SKIP
6
200
ULTRA-SKIP 4

100 2
SKIP

0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)

FIGURE 25. VOUT2 = 3.3V FREQUENCY vs LOAD FIGURE 26. VOUT2 = 3.3V RIPPLE vs LOAD

12 FN6418.4
March 18, 2008
ISL6237

450 40
PWM
400 35
350 30
FREQUENCY (kHz)

PWM ULTRA-SKIP
300

RIPPLE (mV)
25
250
20
200 SKIP
15
150
100 ULTRA-SKIP 10

50 5
SKIP
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)

FIGURE 27. VOUT1 = 5V FREQUENCY vs LOAD FIGURE 28. VOUT1 = 5V RIPPLE vs LOAD

5.04 3.35
5.02
BYP = 0V 3.30
5.00
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

4.98 3.25
BYP = 0V
4.96
3.20
4.94
4.92 3.15

4.90 BYP = 3.3V

3.10
4.88 BYP = 5V
3.05
4.86
4.84 3.00
0 50 100 150 200 0 50 100 150 200
OUTPUT LOAD (mA) OUTPUT LOAD (mA)

FIGURE 29. LDO OUTPUT 5V vs LOAD FIGURE 30. LDO OUTPUT 3.3V vs LOAD

50 1400

45 1200
INPUT CURRENT (mA)

INPUT CURRENT (µA)

1000
40
800
35
600
30
400
25
200

20 0.0
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

FIGURE 31. PWM NO LOAD INPUT CURRENT vs VIN FIGURE 32. SKIP NO LOAD INPUT CURRENT vs VIN
(EN = EN2 = EN_LDO = VCC) (EN1 = EN2 = EN_LDO = VCC)

13 FN6418.4
March 18, 2008
ISL6237

177.5 26.5
177.0 26.0
176.5 25.5
INPUT CURRENT (µA)

INPUT CURRENT (µA)

176.0 25.0
175.5 24.5
175.0 24.0
174.5 23.5
174.0 23.0
173.5 22.5
173.0 22.0
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

FIGURE 33. STANDBY INPUT CURRENT vs VIN FIGURE 34. SHUTDOWN INPUT CURRENT vs VIN
(EN = EN2 = 0, EN_LDO = VCC) (EN = EN2 = EN_LDO = 0)

EN1 5V/DIV
VOUT1 2V/DIV

IL1 2A/DIV

POK1 2V/DIV

FIGURE 35. START-UP VOUT1 = 5V (NO LOAD, SKIP MODE)

EN1 5V/DIV EN1 5V/DIV

VOUT1 2V/DIV VOUT1 2V/DIV

IL1 2A/DIV IL1 5A/DIV

POK1 2V/DIV POK1 2V/DIV

FIGURE 36. START-UP VOUT1 = 5V (NO LOAD, PWM MODE) FIGURE 37. START-UP VOUT1 = 5V (FULL LOAD, PWM MODE)

14 FN6418.4
March 18, 2008
ISL6237

EN2 5V/DIV EN2 5V/DIV

VOUT2 2V/DIV VOUT2 2V/DIV

IL2 2A/DIV
IL2 2A/DIV
POK2 2V/DIV POK2 2V/DIV

FIGURE 38. START-UP VOUT2 = 3.3V (NO LOAD, SKIP MODE) FIGURE 39. START-UP VOUT1 = 3.3V (NO LOAD, PWM MODE)

EN2 5V/DIV
EN2 5V/DIV

VOUT2 2V/DIV

VOUT2 2V/DIV VOUT1 2V/DIV

IL2 5A/DIV POK2 5V/DIV

POK2 2V/DIV POK1 5V/DIV

FIGURE 40. START-UP VOUT1 = 3.3V (FULL LOAD, FIGURE 41. DELAYED START-UP (VOUT1 = 5V, VOUT2 = 3.3V,
PWM MODE) EN1 = REF)

EN1 5V/DIV
EN1 5V/DIV VOUT2 2V/DIV

VOUT1 2V/DIV VOUT2 2V/DIV

VOUT1 2V/DIV
POK1 5V/DIV

POK2 5V/DIV POK1 OR POK2 5V/DIV

FIGURE 42. DELAYED START-UP (VOUT1 = 5V, VOUT2 = 3.3V, FIGURE 43. SHUTDOWN (VOUT1 = 5V, VOUT2 = 3.3V,
EN2 = REF) EN2 = REF)

15 FN6418.4
March 18, 2008
ISL6237

LGATE1 5V/DIV LGATE1 5V/DIV

VOUT1 RIPPLE 50mV/DIV

VOUT1 RIPPLE 100mV/DIV

IL1 5A/DIV IL1 5A/DIV

VOUT2 RIPPLE 50mV/DIV

FIGURE 44. LOAD TRANSIENT VOUT1 = 5V FIGURE 45. LOAD TRANSIENT VOUT1 = 5V (SKIP)

LGATE1 5V/DIV LGATE2 5V/DIV

VOUT1 RIPPLE 20mV/DIV

IL2 5A/DIV

VOUT1 RIPPLE 20mV/DIV

IL2 5A/DIV VOUT2 RIPPLE 50mV/DIV

VOUT2 RIPPLE 50mV/DIV

FIGURE 46. LOAD TRANSIENT VOUT1 = 3.3V (PWM) FIGURE 47. LOAD TRANSIENT VOUT1 = 3.3V (SKIP)

VOUT RIPPLE 20mV/DIV

EN1 5V/DIV

LDO 1V/DIV
VOUT1 0.5V/DIV

IL1 2A/DIV
LDOREFIN 0.5V/DIV

VOUT2 RIPPLE 50mV/DIV POK1 2V/DIV

FIGURE 48. LDO TRACKING TO LDOREFIN FIGURE 49. START-UP VOUT1 = 1.5V (NO LOAD, SKIP MODE)

16 FN6418.4
March 18, 2008
ISL6237

EN1 5V/DIV EN1 5V/DIV

VOUT1 0.5V/DIV

IL1 5A/DIV
IL1 2A/DIV

POK1 2V/DIV POK1 2V/DIV

FIGURE 50. START-UP VOUT1 = 1.5V (NO LOAD, PWM MODE)S FIGURE 51. START-UP VOUT1 = 1.5V (FULL LOAD,
PWM MODE)

EN2 5V/DIV EN2 5V/DIV

VOUT2 0.5V/DIV VOUT2 0.5V/DIV

IL2 2A/DIV
IL2 2A/DIV

POK2 2V/DIV POK2 2V/DIV

FIGURE 52. START-UP VOUT2 = 1.05V (NO LOAD, FIGURE 53. START-UP VOUT1 = 1.05V (NO LOAD,
SKIP MODE) PWM MODE)

EN2 5V/DIV VOUT2 0.5V/DIV EN2 5V/DIV

VOUT2 0.5V/DIV

IL2 2A/DIV VOUT1 2V/DIV

POK2 5V/DIV

POK2 2V/DIV POK1 5V/DIV

FIGURE 54. START-UP VOUT1 = 1.05V (FULL LOAD, FIGURE 55. DELAYED START-UP (VOUT1 = 1.5V,
PWM MODE) VOUT2 = 1.05V, EN1 = REF)

17 FN6418.4
March 18, 2008
ISL6237

VOUT1 2V/DIV
EN1 5V/DIV
EN1 500mV/DIV

VOUT2 2V/DIV

VOUT2 500mV/DIV
VOUT1 2V/DIV

POK1 5V/DIV

POK2 5V/DIV POK1 OR POK2 5V/DIV

FIGURE 56. DELAYED START-UP (VOUT1 = 1.5V, FIGURE 57. SHUTDOWN (VOUT1 = 1.5V, VOUT2 = 1.05V,
VOUT2 = 1.05V, EN2 = REF) EN2 = REF)

LGATE1 5V/DIV LGATE1 5V/DIV

VOUT1 RIPPLE 50mV/DIV VOUT1 RIPPLE 50mV/DIV

IL1 5A/DIV IL1 5A/DIV

VOUT2 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV

FIGURE 58. LOAD TRANSIENT VOUT1 = 1.5V (PWM) FIGURE 59. LOAD TRANSIENT VOUT1 = 1.5V (SKIP)

LGATE2 5V/DIV LGATE2 5V/DIV

VOUT1 RIPPLE 20mV/DIV

IL2 5A/DIV
IL1 5A/DIV
VOUT2 RIPPLE 20mV/DIV

VOUT2 RIPPLE 20mV/DIV

FIGURE 60. LOAD TRANSIENT VOUT1 = 1.05V (PWM) FIGURE 61. LOAD TRANSIENT VOUT1 = 1.05V (SKIP)

18 FN6418.4
March 18, 2008
ISL6237

Typical Application Circuits TABLE 1. LDO OUTPUT VOLTAGE TABLE (Continued)

The typical application circuits (Figures 62, 63 and 64) LDO VOLTAGE CONDITIONS COMMENT
generate the typical 5V/7A, 3.3V/11A, 1.25V/5A, static 3.3V LDOREFIN > VCC - 1V, Internal LDO is
voltage/10A, 1.5V/5A, and 1.05V/5A supplies found in a BYP < 3V active.
notebook computer. The input supply range is 5.5V to 25V. 2 x LDOREFIN 0.35V < LDOREFIN < 2.25V Internal LDO is
active.
Detailed Description
FREE-RUNNING, CONSTANT ON-TIME PWM
The ISL6237 dual-buck, BiCMOS, switch-mode power-
CONTROLLER WITH INPUT FEED-FORWARD
supply controller generates logic supply voltages for
notebook computers. The ISL6237 is designed primarily for The constant on-time PWM control architecture is a
battery-powered applications where high efficiency and low- pseudo-fixed-frequency, constant on-time, current-mode
quiescent supply current are critical. The ISL6237 provides a type with voltage feed forward. The constant on-time PWM
pin-selectable switching frequency, allowing operation for control architecture relies on the output ripple voltage to
200kHz/300kHz, 400kHz/300kHz, or 400kHz/500kHz on the provide the PWM ramp signal; thus the output filter
SMPSs. capacitor's ESR acts as a current-feedback resistor. The
high-side switch on-time is determined by a one-shot whose
Light-load efficiency is enhanced by automatic Idle-Mode period is inversely proportional to input voltage and directly
operation, a variable-frequency pulse-skipping mode that proportional to output voltage. Another one-shot sets a
reduces transition and gate-charge losses. Each step-down, minimum off-time (300ns typ). The on-time one-shot triggers
power-switching circuit consists of two N-Channel when the following conditions are met: the error comparator's
MOSFETs, a rectifier, and an LC output filter. The output output is high, the synchronous rectifier current is below the
voltage is the average AC voltage at the switching node, current-limit threshold, and the minimum off time one-shot
which is regulated by changing the duty cycle of the has timed out. The controller utilizes the valley point of the
MOSFET switches. The gate-drive signal to the N-Channel output ripple to regulate and determine the off time.
high-side MOSFET must exceed the battery voltage, and is
provided by a flying-capacitor boost circuit that uses a 100nF On-Time One-Shot (tON)
capacitor connected to BOOT_. Each PWM core includes a one-shot that sets the high-side
switch on-time for each controller. Each fast, low-jitter,
Both SMPS1 and SMPS2 PWM controllers consist of a triple-
adjustable one-shot includes circuitry that varies the on-time
mode feedback network and multiplexer, a multi-input PWM
in response to battery and output voltage. The high-side
comparator, high-side and low-side gate drivers and logic. In
switch on-time is inversely proportional to the battery voltage
addition, SMPS2 can also use REFIN2 to track its output from
as measured by the VIN input and proportional to the output
0.5V to 2.5V. The ISL6237 contains fault-protection circuits
voltage. This algorithm results in a nearly constant switching
that monitor the main PWM outputs for undervoltage and
frequency despite the lack of a fixed-frequency clock
overvoltage conditions. A power-on sequence block controls
generator. The benefit of a constant switching frequency is
the power-up timing of the main PWMs and monitors the
that the frequency can be selected to avoid noise-sensitive
outputs for undervoltage faults. The ISL6237 includes an
frequency regions:
adjustable low drop-out linear regulator. The bias generator
K ( V OUT + I LOAD ⋅ r DSON ( LOWERQ ) )
blocks include the linear regulator, a 2V precision reference t ON = ------------------------------------------------------------------------------------------------------ (EQ. 1)
V IN
and automatic bootstrap switchover circuit.

The synchronous-switch gate drivers are directly powered See Table 2 for approximate K- factors. Switching frequency
from PVCC, while the high-side switch gate drivers are increases as a function of load current due to the increasing
indirectly powered from PVCC through an external capacitor drop across the synchronous rectifier, which causes a faster
and an internal Schottky diode boost circuit. inductor-current discharge ramp. On-times translate only
roughly to switching frequencies. The on-times established in
An automatic bootstrap circuit turns off the LDO linear the “Electrical Specifications” table on page 4 are influenced
regulator and powers the device from BYP if LDOREFIN is by switching delays in the external high-side power MOSFET.
set to GND or VCC. See Table 1. Also, the dead-time effect increases the effective on-time,
TABLE 1. LDO OUTPUT VOLTAGE TABLE reducing the switching frequency. It occurs only in PWM mode
(SKIP = VCC) and during dynamic output voltage transitions
LDO VOLTAGE CONDITIONS COMMENT
when the inductor current reverses at light or negative load
VOLTAGE at BYP LDOREFIN < 0.3V, Internal LDO is
currents. With reversed inductor current, the inductor's EMF
BYP > 4.63V disabled.
causes PHASE to go high earlier than normal, extending the
VOLTAGE at BYP LDOREFIN > VCC - 1V, Internal LDO is on-time by a period equal to the UGATE-rising dead time.
BYP > 3V disabled.
5V LDOREFIN < 0.3V, Internal LDO is
BYP < 4.63V active.

19 FN6418.4
March 18, 2008
ISL6237

For loads above the critical conduction point, the actual

TABLE 2. APPROXIMATE K-FACTOR ERRORS

switching frequency is:
SWITCHING APPROXIMATE
FREQUENCY K-FACTOR K-FACTOR V OUT + V DROP1
SMPS (kHz) (µs) ERROR (%) f = ------------------------------------------------------- (EQ. 2)
t ON ( V IN + V DROP2 )
(tON = GND, REF, 400 2.5 ±10
or OPEN), VOUT1 where:
(tON = GND), 500 2.0 ±10
• VDROP1 is the sum of the parasitic voltage drops in the
VOUT2
inductor discharge path, including synchronous rectifier,
(tON = VCC), 200 5.0 ±10 inductor, and PC board resistances
VOUT1
• VDROP2 is the sum of the parasitic voltage drops in the
(tON = VCC, REF, 300 3.3 ±10 charging path, including high-side switch, inductor, and PC
or OPEN), VOUT2 board resistances
• tON is the on-time calculated by the ISL6237

20 FN6418.4
March 18, 2008
ISL6237

VIN: 5.5V TO 25V

5V
C5
1µF

C8
1µF
PVCC VCC LDO NC

VIN LDOREFIN GND

C10 C1
10µF BOOT1 BOOT2 10
10µF

Q3a Q1
SI4816BDY UGATE1 UGATE2 IRF7821
OUT1 – PCI-e C9 C4 OUT2-GFX
L1: 3.3µH L2: 2.2µH TRACK REFIN2/10A
1.25V/5A 0.1µF 0.22µF
PHASE1 PHASE2

Q3b Q2
C11 LGATE1 LGATE2 C2
330µF IRF7832
2 x 330µF
9mΩ 4mΩ
6.3V OUT1 PGND 6.3V

R1 VCC OUT2
EN1
7.87kΩ
5V BYP VCC
ISL6237 EN2
FB1
FB1 TIED TO GND = 5V
FB1 TIED TO VCC = 1.5V REFIN2: STATIC 0V TO 2.5V
AGND REFIN2 REFIN2 TIED TO 3.3V = 1.05V
R3 R5
R2 REFIN2 TIED TO VCC = 3.3V
200kΩ 200kΩ
10kΩ
ILIM1 ILIM2
VCC VCC
C7
SKIP 0.1µF
REF
R4 R6
EN_LDO 200kΩ 200kΩ

POK1

VCC TON POK2

PAD

FREQUENCY-DEPENDENT COMPONENTS
1.25V/1.05V SMPS tON = VCC
SWITCHING
FREQUENCY 200kHz/300kHz
L1 3.3µH

L2 2.7µH

C2 2 x 330µF

C11 330µF

FIGURE 62. ISL6237 TYPICAL GFX APPLICATION CIRCUIT

21 FN6418.4
March 18, 2008
ISL6237

VIN: 5.5V TO 25V

5V
C5
1µF
LDOREFIN TIED TO GND = 5V
C8 LDOREFIN TIED TO VCC = 3.3V
1µF
LDO
PVCC VCC LDO
VCC C6
VIN LDOREFIN F
4.7µF
C10 C1
10µF SI4816BDY BOOT1 BOOT2 10
10µF
Q3a
UGATE1 UGATE2 Q1a
OUT1 C9 C4 OUT2
L1: 3.3µH L2: 2.2µF 1.05V/5A
1.5V/5A 0.1µF 0.22µF
PHASE1 PHASE2

Q3b
C11 LGATE1 LGATE2 Q1b SI4816BDY C2
330µF 330µF
9mΩ 4mΩ
6.3V OUT1 PGND 6.3V

VCC EN1 OUT2

3.3V BYP ISL6237 VCC

EN2
VCC
FB1 TIED TO GND = 5V FB1
FB1 TIED TO VCC = 1.5V REFIN2: STATIC 0V TO 2.5V
AGND REFIN2 REFIN2 TIED TO 3.3V = 1.05V
R3 R5 REFIN2 TIED TO VCC = 3.3V
200kΩ 200kΩ
ILIM1 ILIM2
VCC VCC

SKIP C7
ON 0.1µF
REF R4 R6
EN_LDO 200kΩ 200kΩ
OFF

POK1

VCC TON POK2

PAD

FREQUENCY-DEPENDENT COMPONENTS

1.5V/1.05V SMPS tON = VCC

SWITCHING
FREQUENCY 200kHz/300kHz

L1 3.3µH

L2 2.7µH

C2 330µF

C11 330µF

FIGURE 63. ISL6237 TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT

22 FN6418.4
March 18, 2008
ISL6237

VIN: 5.5V TO 25V

C5
1µF

VCC LDO
PVCC LDO
C6
VIN LDOREFIN
4.7µF
C10 C1
10µF BOOT1 BOOT2 10µF
10

Q3 Q1
IRF7807V UGATE1 UGATE2 IRF7821
OUT1 C9 C4 OUT2
L1: 4.7µH 0.1µF L2: 4.7µH 3.3V/11A
5V/7A 0.1µF
PHASE1 PHASE2

Q4 Q2
C11 LGATE1 LGATE2 C2
IRF7811AV IRF7832
330µF 330µF
9mΩ 9mΩ
6.3V OUT1 PGND 4V
VCC
EN1 ISL6237 OUT2

BYP EN2 VCC

FB1
FB1 TIED TO GND = 5V REFIN2: STATIC 0 TO 2.5V
FB1 TIED TO VCC = 1.5V REFIN2 VCC REFIN2 TIED TO VREF3 = 1.05V
AGND REFIN2 TIED TO VCC = 3.3V
R3 R5
200kΩ 150kΩ
ILIM1 ILIM2
VCC VCC

SKIP 0.1µF
ON REF R4 R6
C7
EN LDO 200kΩ 200kΩ
OFF

POK1

GND TON POK2

PAD

FIGURE 64. ISL6237 TYPICAL 3.3V/5V SYSTEM REGULATOR APPLICATION CIRCUIT

23 FN6418.4
March 18, 2008
ISL6237

TON SKIP

BOOT1 BOOT2

UGATE1 UGATE2

PHASE1 PHASE2
PVCC PVCC

LGATE1 SMPS1 SMPS2

SYNCHRONOUS LGATE2
SYNCHRONOUS
PWM BUCK PWM BUCK
GND CONTROLLER CONTROLLER
PGND

ILIM1 ILIM2
EN1 EN2

FB1 POK1 POK2 REFIN2

OUT1 OUT2
OUT1 OUT2

BYP POK2
SW THRESHOLD
-

POK1

LDO
LDO
VCC
LDOREFIN INTERNAL
LOGIC
10Ω

VIN

PVCC
EN_LDO
POWER-ON
EN1 SEQUENCE
CLEAR FAULT
EN2 LATCH THERMAL
THERMAL REF
REF
SHUTDOWN
SHUTDOWN

FIGURE 65. DETAILED FUNCTIONAL DIAGRAM ISL6237

24 FN6418.4
March 18, 2008
ISL6237

TON
MIN. tOFF
VIN Q TRIG
ONE SHOT
+ TO UGATE_DRIVER
OUT_ R QQ
S Q
Q

REFIN2 (SMPS2)+
+
VREF +
ILIM_ +
COMP
+ SLOPE COMP +
BOOT BOOT_
UV
5µA DETECT

VCC +
TO LGATE_ DRIVER
S
+
PHASE_
OUT_
+ Q
S Q
R Q
Q

SKIP

FB +
DECODER PGOOD_
0.9VREF

FB_ +
OV_LATCH_
1.1VREF FAULT
FAULT
LATCH
UV_LATCH_ LATCH
LOGIC
+
20ms
0.7VREF
BLANKING

FIGURE 66. PWM CONTROLLER (ONE SIDE ONLY)

25 FN6418.4
March 18, 2008
ISL6237

Automatic Pulse-Skipping Switchover The switching waveforms may appear noisy and
(Idle Mode) asynchronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
In Idle Mode (SKIP = GND), an inherent automatic
results in high light-load efficiency. Trade-offs in PFM noise
switchover to PFM takes place at light loads. This switchover
vs light-load efficiency are made by varying the inductor
is affected by a comparator that truncates the low-side
value. Generally, low inductor values produce a broader
switch on-time at the inductor current's zero crossing. This
efficiency vs load curve, while higher values result in higher
mechanism causes the threshold between pulse-skipping
full-load efficiency (assuming that the coil resistance remains
PFM and non skipping PWM operation to coincide with the
fixed) and less output voltage ripple. Penalties for using
boundary between continuous and discontinuous
higher inductor values include larger physical size and
inductor-current operation (also known as the critical
degraded load-transient response (especially at low
conduction point):
input-voltage levels).
K ⋅ V OUT V IN – V OUT
I LOAD ( SKIP ) = ------------------------ -------------------------------- (EQ. 3)
2⋅L V IN DC output accuracy specifications refer to the trip level of the
error comparator. When the inductor is in continuous
where K is the on-time scale factor (see “On-Time One-Shot conduction, the output voltage has a DC regulation higher
(tON)” on page 19). The load-current level at which than the trip level by 50% of the ripple. In discontinuous
PFM/PWM crossover occurs, ILOAD(SKIP), is equal to half conduction (SKIP = GND, light load), the output voltage has
the peak-to-peak ripple current, which is a function of the a DC regulation higher than the trip level by approximately
inductor value (Figure 67). For example, in the ISL6237 1.0% due to slope compensation.
typical application circuit with VOUT1 = 5V, VIN = 12V,
L = 7.6µH, and K = 5µs, switchover to pulse-skipping Forced-PWM Mode
operation occurs at ILOAD = 0.96A or about on-fifth full load.
The low-noise, forced-PWM (SKIP = VCC) mode disables
The crossover point occurs at an even lower value if a
the zero-crossing comparator, which controls the low-side
swinging (soft-saturation) inductor is used.
switch on-time. Disabling the zero-crossing detector causes
DI VIN -V OUT the low-side, gate-drive waveform to become the
= complement of the high-side, gate-drive waveform. The
t L
IPEAK inductor current reverses at light loads as the PWM loop
strives to maintain a duty ratio of VOUT/VIN. The benefit of
INDUCTOR CURRENT

forced-PWM mode is to keep the switching frequency fairly

constant, but it comes at a cost: the no-load battery current
can be 10mA to 50mA, depending on switching frequency
ILOAD = IPEAK/2
and the external MOSFETs.

Forced-PWM mode is most useful for reducing

audio-frequency noise, improving load-transient response,
providing sink-current capability for dynamic output voltage
adjustment, and improving the cross-regulation of
0 ON-TIME TIME multiple-output applications that use a flyback transformer or
FIGURE 67. ULTRASONIC CURRENT WAVEFORMS
coupled inductor.

Enhanced Ultrasonic Mode

40µs (MAX)
(25kHz (min) Pulse Skipping)
INDUCTOR Leaving SKIP unconnected or connecting SKIP to REF
CURRENT
activates a unique pulse-skipping mode with a minimum
switching frequency of 25kHz. This ultrasonic pulse-skipping
mode eliminates audio-frequency modulation that would
otherwise be present when a lightly loaded controller
Zero-Crossing
ZERO-CROSSING automatically skips pulses. In ultrasonic mode, the controller
DETECTION
automatically transitions to fixed-frequency PWM operation
0A when the load reaches the same critical conduction point
(ILOAD(SKIP)).
FB < REG.POINT
An ultrasonic pulse occurs when the controller detects that
ON-TIME (t ON ) no switching has occurred within the last 20µs. Once
triggered, the ultrasonic controller pulls LGATE high, turning
FIGURE 68. ULTRASONIC CURRENT WAVEFORMS on the low-side MOSFET to induce a negative inductor

26 FN6418.4
March 18, 2008
ISL6237

current. After FB drops below the regulation point, the temperature rise. The ISL6237 controller has a built-in 5µA
controller turns off the low-side MOSFET (LGATE pulled low) current source as shown in Figure 70. Place the hottest
and triggers a constant on-time (UGATE driven high). When power MOSFETs as close to the IC as possible for best
the on-time has expired, the controller re-enables the thermal coupling. The current limit varies with the on-
low-side MOSFET until the controller detects that the resistance of the synchronous rectifier. When combined with
inductor current dropped below the zero-crossing threshold. the undervoltage-protection circuit, this current-limit method
Starting with a LGATE pulse greatly reduces the peak output is effective in almost every circumstance.
voltage when compared to starting with a UGATE pulse, as
A negative current limit prevents excessive reverse inductor
long as VFB < VREF, LGATE is off and UGATE is on, similar
currents when VOUT sinks current. The negative
to pure SKIP mode.
current-limit threshold is set to approximately 120% of the
positive current limit and therefore tracks the positive current
Reference and Linear Regulator (REF and
limit when ILIM_ is adjusted. The current-limit threshold is
LDO) adjusted with an external resistor for ISL6237 at ILIM_. The
The 2V reference (REF) is accurate to ±1% over current-limit threshold adjustment range is from 20mV to
temperature, making REF useful as a precision system 200mV. In the adjustable mode, the current-limit threshold
reference. Bypass REF to GND with a 0.1µF (min) capacitor. voltage is 1/10th the voltage at ILIM_. The voltage at ILIM
REF can supply up to 50µA for external loads. pin is the product of 5µA*RILIM. The threshold defaults to
An internal regulator produces a fixed 5V 100mV when ILIM_ is connected to VCC. The logic
(LDOREFIN < 0.2V) or 3.3V (LDOREFIN > VCC - 1V). In an threshold for switch-over to the 100mV default value is
adjustable mode, the LDO output can be set from 0.7V to approximately VCC - 1V.
4.5V. The LDO output voltage is equal to two times the The PC board layout guidelines should be carefully
LDOREFIN voltage. The LDO regulator can supply up to observed to ensure that noise and DC errors do not corrupt
100mA for external loads. Bypass LDO with a minimum the current-sense signals at PHASE_.
4.7µF ceramic capacitor. When the LDOREFIN < 0.2V and
BYP voltage is 5V, the LDO bootstrap-switchover to an
internal 0.7Ω P-channel MOSFET switch connects BYP to I PEAK
LDO pin while simultaneously shutting down the internal
linear regulator. These actions bootstrap the device,
INDUCTOR CURRENT

I LOAD
powering the loads from the BYP input voltages, rather than ΔI
through internal linear regulators from the battery. Similarly,
when the BYP = 3.3V and LDOREFIN = VCC, the LDO I LIMIT

bootstrap-switchover to an internal 1.5Ω P-Channel I LOAD(MAX)

MOSFET switch connects BYP to LDO pin while
simultaneously shutting down the internal linear regulator. ILIM (VAL) = I ΔI
LOAD − 2
No switchover action in adjustable mode.
TIME
Current-Limit Circuit (ILIM_) with rDS(ON)
Temperature Compensation FIGURE 69. “VALLEY” CURRENT LIMIT THRESHOLD POINT

The current-limit circuit employs a "valley" current-sensing

algorithm. The ISL6237 uses the on-resistance of the
synchronous rectifier as a current-sensing element. If the
magnitude of the current-sense signal at PHASE_ is above
ILIM_
the current-limit threshold, the PWM is not allowed to initiate a +
new cycle. The actual peak current is greater than the current-
limit threshold by an amount equal to the inductor ripple
5µA
current. Therefore, the exact current-limit characteristic and +
maximum load capability are a function of the current-limit 9R TO CURRENT
RILIM VILIM
threshold, inductor value and input and output voltage. VCC LIMIT LOGIC

For lower power dissipation, the ISL6237 uses the

R
on-resistance of the synchronous rectifier as the
current-sense element. Use the worst-case maximum value
for rDS(ON) from the MOSFET data sheet. Add some margin
for the rise in rDS(ON) with temperature. A good general rule
is to allow 0.5% additional resistance for each °C of FIGURE 70. CURRENT LIMIT BLOCK DIAGRAM

27 FN6418.4
March 18, 2008
ISL6237

MOSFET Gate Drivers (UGATE_, LGATE_) maximum operating duty cycle (this occurs at minimum input
voltage). The minimum gate to source voltage (VGS(MIN)) is
The UGATE_ and LGATE_ gate drivers sink 2.0A and 3.3A
determined by:
respectively of gate drive, ensuring robust gate drive for
C BOOT
high-current applications. The UGATE_ floating high-side V GS ( MIN ) = PVCC ⋅ --------------------------------------- (EQ. 4)
MOSFET drivers are powered by diode-capacitor charge C BOOT + C GS
pumps at BOOT_. The LGATE_ synchronous-rectifier
drivers are powered by PVCC. where:

The internal pull-down transistors that drive LGATE_ low • PVCC is 5V

have a 0.6Ω typical on-resistance. These low on-resistance • CGS is the gate capacitance of the high-side MOSFET
pull-down transistors prevent LGATE_ from being pulled up
during the fast rise time of the inductor nodes due to Boost-Supply Refresh Monitor
capacitive coupling from the drain to the gate of the low-side
In pure skip mode, the converter frequency can be very low
synchronous-rectifier MOSFETs. However, for high-current
with little to no output loading. This produces very long off
applications, some combinations of high- and low-side
times, where leakage can bleed down the BOOT capacitor
MOSFETs may cause excessive gate-drain coupling, which
voltage. If the voltage falls too low, the converter may not be
leads to poor efficiency and EMI-producing shoot-through
able to turn on UGATE when the output voltage falls to the
currents. Adding a 1Ω resistor in series with BOOT_
reference. To prevent this, the ISL6237 monitors the BOOT
increases the turn-on time of the high-side MOSFETs at the
capacitor voltage, and if it falls below 3V, it initiates an
expense of efficiency, without degrading the turn-off time
LGATE pulse, which will refresh the BOOT voltage.
(Figure 71).

Adaptive dead-time circuits monitor the LGATE_ and POR, UVLO, and Internal Digital Soft-Start
UGATE_ drivers and prevent either FET from turning on until Power-on reset (POR) occurs when VIN rises above
the other is fully off. This algorithm allows operation without approximately 3V, resetting the undervoltage, overvoltage,
shoot-through with a wide range of MOSFETs, minimizing and thermal-shutdown fault latches. PVCC
delays and maintaining efficiency. There must be low undervoltage-lockout (UVLO) circuitry inhibits switching
resistance, low-inductance paths from the gate drivers to the when PVCC is below 4V. LGATE_ is low during UVLO. The
MOSFET gates for the adaptive dead-time circuit to work output voltages begin to ramp up once PVCC exceeds its 4V
properly. Otherwise, the sense circuitry interprets the UVLO and REF is in regulation. The internal digital soft-start
MOSFET gate as "off" when there is actually charge left on timer begins to ramp up the maximum-allowed current limit
the gate. Use very short, wide traces measuring 10 to 20 during start-up. The 1.7ms ramp occurs in five steps. The
squares (50 mils to 100 mils wide if the MOSFET is 1” from step size are 20%, 40%, 60%, 80% and 100% of the positive
the device). current limit value.

5V Power-Good Output (POK_)

BOOT_ The POK_ comparator continuously monitors both output
10Ω
10
VIN voltages for undervoltage conditions. POK_ is actively held
low in shutdown, standby, and soft-start. POK1 releases and
UGATE_ digital soft-start terminates when VOUT1 outputs reach the
Q1

C BOOT
error-comparator threshold. POK1 goes low if VOUT1 output
OUT_ turns off or is 10% below its nominal regulation point. POK1
is a true open-drain output. Likewise, POK2 is used to
PHASE_
monitor VOUT2.

ISL6237 Fault Protection

ISL88734
The ISL6237 provides overvoltage/undervoltage fault
FIGURE 71. REDUCING THE SWITCHING-NODE RISE TIME protection in the buck controllers. Once activated, the
controller continuously monitors the output for undervoltage
Boost-Supply Capacitor Selection (Buck) and overvoltage fault conditions.
The boost capacitor should be 0.1µF to 4.7µF, depending on OVERVOLTAGE PROTECTION
the input and output voltages, external components, and PC When the output voltage of VOUT1 is 11% (16% for VOUT2)
board layout. The boost capacitance should be as large as above the set voltage, the overvoltage fault protection
possible to prevent it from charging to excessive voltage, but activates. This latches on the synchronous rectifier MOSFET
small enough to adequately charge during the minimum with 100% duty cycle, rapidly discharging the output
low-side MOSFET conduction time, which happens at capacitor until the negative current limit is achieved. Once

28 FN6418.4
March 18, 2008
ISL6237

negative current limit is met, UGATE is turned on for a Discharge Mode (Soft-Stop)
minimum on-time, followed by another LGATE pulse until When a transition to standby or shutdown mode occurs, or
negative current limit. This effectively regulates the the output undervoltage fault latch is set, the outputs
discharge current at the negative current limit in an effort to discharge to GND through an internal 25Ω switch. The
prevent excessively large negative currents that cause reference remains active to provide an accurate threshold
potentially damaging negative voltages on the load. Once an and to provide overvoltage protection.
overvoltage fault condition is set, it can only be reset by
toggling SHDN, EN_, or cycling VIN (POR). Shutdown Mode
The ISL6237 SMPS1, SMPS2 and LDO have independent
UNDERVOLTAGE PROTECTION
enabling control. Drive EN1, EN2 and EN_LDO below the
When the output voltage drops below 70% of its regulation precise input falling-edge trip level to place the ISL6237 in its
voltage for at least 100µs, the controller sets the fault latch low-power shutdown state. The ISL6237 consumes only
and begins the discharge mode (see the following Shutdown 20µA of quiescent current while in shutdown. Both SMPS
and Output Discharge sections). UVP is ignored for at least outputs are discharged to 0V through a 25Ω switch.
20ms (typical), after start-up or after a rising edge on EN_.
Toggle EN_ or cycle VIN (POR) to clear the undervoltage Power-Up Sequencing and On/Off Controls (EN_)
fault latch and restart the controller. UVP only applies to the EN1 and EN2 control SMPS power-up sequencing. EN1 or
buck outputs. EN2 rising above 2.4V enables the respective outputs. EN1
or EN2 falling below 1.6V disables the respective outputs.
THERMAL PROTECTION
The ISL6237 has thermal shutdown to protect the devices Connecting EN1 or EN2 to REF will force its outputs off while
from overheating. Thermal shutdown occurs when the die the other output is below regulation. The sequenced SMPS
temperature exceeds +150°C. All internal circuitry shuts will start once the other SMPS reaches regulation. The
down during thermal shutdown. The ISL6237 may trigger second SMPS remains on until the first SMPS turns off, the
thermal shutdown if LDO_ is not bootstrapped from OUT_ device shuts down, a fault occurs or PVCC goes into
while applying a high input voltage on VIN and drawing the undervoltage lockout. Both supplies begin their power-down
maximum current (including short circuit) from LDO_. Even if sequence immediately when the first supply turns off. Driving
LDO_ is bootstrapped from OUT_, overloading the LDO_ EN_ below 0.8V clears the overvoltage, undervoltage and
causes large power dissipation on the bootstrap switches, thermal fault latches.
which may result in thermal shutdown. Cycling EN_,
EN_LDO, or VIN (POR) ends the thermal-shutdown state.

TABLE 3. OPERATING-MODE TRUTH TABLE

MODE CONDITION COMMENT

Power-Up PVCC < UVLO threshold. Transitions to discharge mode after a VIN POR and after REF becomes valid. LDO
and REF remain active.

Run EN_LDO = high, EN1 or EN2 Normal operation

enabled.

Overvoltage Either output > 111% (VOUT1) or LGATE_ is forced high. LDO and REF are active. Exited by a VIN POR, or by toggling
Protection 116% (VOUT2) of nominal level. EN1 or EN2.

Undervoltage Either output < 70% of nominal after The internal 25Ω switch turns on. LDO and REF are active. Exited by a VIN POR or
Protection 20ms time-out expires and output is by toggling EN1 or EN2.
enabled.

Discharge Either SMPS output is still high in Discharge switch (25Ω) connects OUT_ to GND. One output may still run while the
either standby mode or shutdown other is in discharge mode. Activates when PVCC is in UVLO, or transition to UVLO,
mode standby, or shutdown has begun. LDO and REF active.

Standby EN1, EN2 < startup threshold, LDO and REF are active.
EN_LDO = High

Shutdown EN1, EN2, EN_LDO = low Discharge switch (25Ω) connects OUT_ to PGND. All circuitry off.

Thermal Shutdown TJ > +150°C All circuitry off. Exited by VIN POR or cycling EN_.

29 FN6418.4
March 18, 2008
ISL6237

TABLE 4. SHUTDOWN AND STANDBY CONTROL LOGIS

VEN_LDO VEN1 (V) VEN2 (V) LDO SMPS1 SMPS2

LOW LOW LOW OFF OFF OFF

“>2.5” → HIGH LOW LOW ON OFF OFF

“>2.5” → HIGH HIGH HIGH ON ON ON

“>2.5” → HIGH HIGH LOW ON ON OFF

“>2.5” → HIGH LOW HIGH ON OFF ON

“>2.5” → HIGH HIGH REF ON ON ON (AFTER SMPS1 IS UP)

“>2.5” → HIGH REF HIGH ON ON (AFTER SMPS2 IS UP) ON

Adjustable-Output Feedback (Dual-Mode FB) 3. Switching Frequency. This choice determines the basic
Connect FB1 to GND to enable the fixed 5V or tie FB1 to trade-off between size and efficiency. The optimal
frequency is largely a function of maximum input voltage
VCC to set the fixed 1.5V output. Connect a resistive
and MOSFET switching losses.
voltage-divider at FB1 between OUT1 and GND to adjust the
respective output voltage between 0.7V and 5.5V 4. Inductor Ripple Current Ratio (LIR). LIR is the ratio of the
peak-peak ripple current to the average inductor current.
(Figure 72). Choose R2 to be approximately 10k and solve
Size and efficiency trade-offs must be considered when
for R1 using Equation 5.
setting the inductor ripple current ratio. Low inductor
⎛ V OUT1 ⎞ values cause large ripple currents, resulting in the
R 1 = R 2 ⋅ ⎜ ------------------- – 1⎟
⎝ FB1
V ⎠ (EQ. 5)
smallest size, but poor efficiency and high output noise.
Also, total output ripple above 3.5% of the output
regulation will cause controller to trigger out-of-bound
where VFB1 = 0.7V nominal.
condition. The minimum practical inductor value is one
Likewise, connect REFIN2 to VCC to enable the fixed 3.3V that causes the circuit to operate at critical conduction
or tie REFIN2 to a 3.3V supply to set the fixed 1.05V output. (where the inductor current just touches zero with every
Set REFIN2 from 0 to 2.50V for SMPS2 tracking mode cycle at maximum load). Inductor values lower than this
(Figure 73). grant no further size-reduction benefit.
The ISL6237 pulse-skipping algorithm (SKIP = GND)
R3 = R4 ⋅ ⎛ ------------------- – 1⎞
VR
⎝V ⎠ (EQ. 6) initiates skip mode at the critical conduction point, so the
OUT2
inductor's operating point also determines the load
where: current at which PWM/PFM switchover occurs. The
optimum LIR point is usually found between 25% and
• VR = 2V nominal (if tied to REF) 50% ripple current.
Design Procedure VIN

Establish the input voltage range and maximum load current

before choosing an inductor and its associated ripple-current UGATE1
UGATE_
UGATE1 Q3

ratio (LIR). The following four factors dictate the rest of the ISL88732
design: OUT1
ISL6237
ISL88733
ISL88734
ISL6237
1. Input Voltage Range. The maximum value (VIN(MAX))
must accommodate the maximum AC adapter voltage. LGATE_
LGATE1
LGATE1 Q4
The minimum value (VIN(MIN)) must account for the
lowest input voltage after drops due to connectors, fuses
and battery selector switches. Lower input voltages result OUT1
VOUT_
OUT1 R1
in better efficiency.
2. Maximum Load Current. The peak load current FB1
FB_
FB1
(ILOAD(MAX)) determines the instantaneous component
stress and filtering requirements and thus drives output R2

capacitor selection, inductor saturation rating and the

design of the current-limit circuit. The continuous load
current (ILOAD) determines the thermal stress and drives FIGURE 72. SETTING VOUT1 WITH A RESISTOR DIVIDER
the selection of input capacitors, MOSFETs and other
critical heat-contributing components.

30 FN6418.4
March 18, 2008
ISL6237

Determining the Current Limit

VIN
The minimum current-limit threshold must be great enough
to support the maximum load current when the current limit
Q1
UGATE2
UGATE_
UGATE2 is at the minimum tolerance value. The valley of the inductor
ISL88732
current occurs at ILOAD(MAX) minus half of the ripple
OUT2 current; therefore:
ISL88733
ISL6237
ISL88734 I LIMIT ( LOW ) > I LOAD ( MAX ) – [ ( LIR ⁄ 2 ) ⋅ I LOAD ( MAX ) ] (EQ. 11)

LGATE_
LGATE2
LGATE2 Q2 where: ILIMIT(LOW) = minimum current-limit threshold
voltage divided by the rDS(ON) of Q2/Q4.

VOUT_
OUT2
OUT2 Use the worst-case maximum value for rDS(ON) from the
MOSFET Q2/Q4 data sheet and add some margin for the
FB_
REFIN2
REFIN2 VR rise in rDS(ON) with temperature. A good general rule is to
R3 allow 0.2% additional resistance for each °C of temperature
R4 rise.

Examining the 5A circuit example with a maximum

rDS(ON) = 5mΩ at room temperature. At +125°C reveals the
FIGURE 73. SETTING VOUT2 WITH A VOLTAGE DIVIDER FOR following:
TRACKING
I LIMIT ( LOW ) = ( 25mV ) ⁄ ( ( 5mΩ × 1.2 ) > 5A – ( 0.35 ⁄ 2 )5A )
Inductor Selection (EQ. 12)
The switching frequency (on-time) and operating point
4.17A > 4.12A (EQ. 13)
(% ripple or LIR) determine the inductor value as follows:
4.17A is greater than the valley current of 4.12A, so the
V OUT _ ( V IN + V OUT _ )
L = --------------------------------------------------------------------- (EQ. 7) circuit can easily deliver the full-rated 5A using the 30mV
V IN ⋅ f ⋅ LIR ⋅ I LOAD ( MAX )
nominal current-limit threshold voltage.

Example: ILOAD(MAX) = 5A, VIN = 12V, VOUT2 = 5V, Output Capacitor Selection
f = 200kHz, 35% ripple current or LIR = 0.35: The output filter capacitor must have low enough equivalent
series resistance (ESR) to meet output ripple and
5V ( 12V – 5V ) (EQ. 8)
L = ----------------------------------------------------------------- = 8.3μH load-transient requirements, yet have high enough ESR to
12V ⋅ 200kHz ⋅ 0.35 ⋅ 5A
satisfy stability requirements. The output capacitance must
Find a low-loss inductor having the lowest possible DC also be high enough to absorb the inductor energy while
resistance that fits in the allotted dimensions. Ferrite cores transitioning from full-load to no-load conditions without
are often the best choice. The core must be large enough tripping the overvoltage fault latch. In applications where the
not to saturate at the peak inductor current (IPEAK): output is subject to large load transients, the output
capacitor's size depends on how much ESR is needed to
IPEAK = I LOAD ( MAX ) + [ ( LIR ⁄ 2 ) ⋅ I LOAD ( MAX ) ] (EQ. 9)
prevent the output from dipping too low under a load
transient. Ignoring the sag due to finite capacitance:
The inductor ripple current also impacts transient response
V DIP
performance, especially at low VIN - VOUT_ differences. Low R SER ≤ ---------------------------------- (EQ. 14)
I LOAD ( MAX )
inductor values allow the inductor current to slew faster,
replenishing charge removed from the output filter capacitors where VDIP is the maximum-tolerable transient voltage drop.
by a sudden load step. The peak amplitude of the output In non-CPU applications, the output capacitor's size
transient (VSAG) is also a function of the maximum duty depends on how much ESR is needed to maintain an
factor, which can be calculated from the on-time and acceptable level of output voltage ripple:
minimum off-time: VP – P
⎛ ⎛ V OUT _ ⎞⎞ R ESR ≤ ----------------------------------------------- (EQ. 15)
2
( ΔI LOAD ( MAX ) ) ⋅ L ⎜ K ⎜ ------------------- + t OFF ( MIN )⎟ ⎟ L IR ⋅ I LOAD ( MAX )
⎝ ⎝ V IN ⎠⎠
V SAG = ----------------------------------------------------------------------------------------------------------------------------
⎛ IN where VP-P is the peak-to-peak output voltage ripple. The
V – V OUT⎞
2 ⋅ C OUT ⋅ V OUT K ⎜ --------------------------------⎟ - t actual capacitance value required relates to the physical size
⎝ V IN ⎠ OFF ( MIN )
(EQ. 10) needed to achieve low ESR, as well as to the chemistry of
the capacitor technology. Thus, the capacitor is usually
where minimum off-time = 0.35µs (max) and K is from selected by ESR and voltage rating rather than by
Table 2. capacitance value (this is true of tantalum, OS-CON, and
other electrolytic-type capacitors).

31 FN6418.4
March 18, 2008
ISL6237

When using low-capacity filter capacitors such as polymer Choose a synchronous rectifier (Q2/Q4) with the lowest
types, capacitor size is usually determined by the capacity possible rDS(ON). Ensure the gate is not pulled up by the
required to prevent VSAG and VSOAR from tripping the high-side switch turning on due to parasitic drain-to-gate
undervoltage and overvoltage fault latches during load capacitance, causing cross-conduction problems. Switching
transients in ultrasonic mode. losses are not an issue for the synchronous rectifier in the
buck topology since it is a zero-voltage switched device
For low input-to-output voltage differentials (VIN/ VOUT < 2),
when using the buck topology.
additional output capacitance is required to maintain stability
and good efficiency in ultrasonic mode. The amount of MOSFET Power Dissipation
overshoot due to stored inductor energy can be calculated as: Worst-case conduction losses occur at the duty-factor
2 extremes. For the high-side MOSFET, the worst-case power
I PEAK ⋅ L
V SOAR = ------------------------------------------------ (EQ. 16) dissipation (PD) due to the MOSFET's rDS(ON) occurs at the
2 ⋅ C OUT ⋅ V OUT_
minimum battery voltage:
where IPEAK is the peak inductor current. ⎛ V OUT _ ⎞ 2
PD ( Q H Resistance ) = ⎜ ------------------------⎟ ( I LOAD ) ⋅ r DS( ON ) (EQ. 18)
Input Capacitor Selection ⎝ V IN ( MIN )⎠
The input capacitors must meet the input-ripple-current
Generally, a small high-side MOSFET reduces switching
(IRMS) requirement imposed by the switching current. The
losses at high input voltage. However, the rDS(ON) required
ISL6237 dual switching regulator operates at different
to stay within package power-dissipation limits often limits
frequencies. This interleaves the current pulses drawn by
how small the MOSFET can be. The optimum situation
the two switches and reduces the overlap time where they
occurs when the switching (AC) losses equal the conduction
add together. The input RMS current is much smaller in
(rDS(ON)) losses.
comparison than with both SMPSs operating in phase. The
input RMS current varies with load and the input voltage. Switching losses in the high-side MOSFET can become an
insidious heat problem when maximum battery voltage is
The maximum input capacitor RMS current for a single
applied, due to the squared term in the CV2f switching-loss
SMPS is given by:
equation. Reconsider the high-side MOSFET chosen for
⎛ V OUT ( V IN – V OUT _ )⎞ adequate rDS(ON) at low battery voltages if it becomes
I RMS ≈ I LOAD ⎜ ------------------------------------------------------------⎟ (EQ. 17)
⎝ V IN ⎠ extraordinarily hot when subjected to VIN(MAX).

When V IN = 2 ⋅ V OUT _ ( D = 50% ) , IRMS has maximum Calculating the power dissipation in NH (Q1/Q3) due to
current of I LOAD ⁄ 2 . switching losses is difficult since it must allow for quantifying
factors that influence the turn-on and turn-off times. These
The ESR of the input-capacitor is important for determining factors include the internal gate resistance, gate charge,
capacitor power dissipation. All the power (IRMS2 x ESR) threshold voltage, source inductance, and PC board layout
heats up the capacitor and reduces efficiency. Nontantalum characteristics. The following switching-loss calculation
chemistries (ceramic or OS-CON) are preferred due to their provides only a very rough estimate and is no substitute for
low ESR and resilience to power-up surge currents. Choose bench evaluation, preferably including verification using a
input capacitors that exhibit less than +10°C temperature thermocouple mounted on NH (Q1/Q3):
rise at the RMS input current for optimal circuit longevity.
2 ⎛ C RSS ⋅ f SW ⋅ I LOAD⎞
Place the drains of the high-side switches close to each PD ( Q H Switching ) = ( V IN ( MAX ) ) ⎜ -----------------------------------------------------⎟
⎝ I GATE ⎠
other to share common input bypass capacitors. (EQ. 19)
Power MOSFET Selection
where CRSS is the reverse transfer capacitance of QH
Most of the following MOSFET guidelines focus on the
(Q1/Q3) and IGATE is the peak gate-drive source/sink
challenge of obtaining high load-current capability (>5A)
current.
when using high-voltage (>20V) AC adapters. Low-current
applications usually require less attention. For the synchronous rectifier, the worst-case power
dissipation always occurs at maximum battery voltage:
Choose a high-side MOSFET (Q1/Q3) that has conduction
⎛ V OUT ⎞ 2
losses equal to the switching losses at the typical battery PD ( Q L ) = ⎜ 1 – --------------------------⎟ I LOAD ⋅ r DS ( ON ) (EQ. 20)
⎝ V IN ( MAX )⎠
voltage for maximum efficiency. Ensure that the conduction
losses at the minimum input voltage do not exceed the The absolute worst case for MOSFET power dissipation
package thermal limits or violate the overall thermal budget. occurs under heavy overloads that are greater than
Ensure that conduction losses plus switching losses at the ILOAD(MAX) but are not quite high enough to exceed the
maximum input voltage do not exceed the package ratings
or violate the overall thermal budget.

32 FN6418.4
March 18, 2008
ISL6237

current limit and cause the fault latch to trip. To protect during each switching cycle and VSAG greatly increases
against this possibility, "overdesign" the circuit to tolerate: unless additional output capacitance is used.
I LOAD = I LIMIT ( HIGH ) + ( ( LIR ) ⁄ 2 ) ⋅ I LOAD ( MAX )
(EQ. 21) A reasonable minimum value for h is 1.5, but this can be
adjusted up or down to allow trade-offs between VSAG,
where ILIMIT(HIGH) is the maximum valley current allowed output capacitance and minimum operating voltage. For a
by the current-limit circuit, including threshold tolerance and given value of h, the minimum operating voltage can be
resistance variation. calculated as shown in Equation 22:

Rectifier Selection ( V OUT _ + V DROP )

V IN ( MIN ) = --------------------------------------------------- + V DROP2 – V DROP1 (EQ. 22)
t OFF ( MIN ) ⋅ h
Current circulates from ground to the junction of both 1 – ⎛ ------------------------------------⎞
⎝ K ⎠
MOSFETs and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is
where VDROP1 and VDROP2 are the parasitic voltage drops
negative with respect to ground. This voltage is
in the discharge and charge paths (see “On-Time One-Shot
approximately -0.7V (a diode drop) at both transition edges
(tON)” on page 19), tOFF(MIN) is from Electrical
while both switches are off (dead time). The drop is
Specifications on page 3 and K is taken from Table 2. The
I L ⋅ r DS ( ON ) when the low-side switch conducts.
absolute minimum input voltage is calculated with h = 1.
The rectifier is a clamp across the synchronous rectifier that
Operating frequency must be reduced or h must be increased
catches the negative inductor swing during the dead time
and output capacitance added to obtain an acceptable VSAG
between turning the high-side MOSFET off and the
if calculated VIN(MIN) is greater than the required minimum
synchronous rectifier on. The MOSFETs incorporate a
input voltage. Calculate VSAG to be sure of adequate
high-speed silicon body diode as an adequate clamp diode if
transient response if operation near dropout is anticipated.
efficiency is not of primary importance. Place a Schottky diode
in parallel with the body diode to reduce the forward voltage Dropout Design Example:
drop and prevent the Q2/Q4 MOSFET body diodes from
ISL6237: With VOUT2 = 5V, fsw = 400kHz, K = 2.25µs,
turning on during the dead time. Typically, the external diode
tOFF(MIN) = 350ns, VDROP1 = VDROP2 = 100mV, and
improves the efficiency by 1% to 2%. Use a Schottky diode
h = 1.5, the minimum VIN is:
with a DC current rating equal to one-third of the load current.
For example, use an MBR0530 (500mA-rated) type for loads ( 5V + 0.1V )
V IN ( MIN ) = ---------------------------------------------- + 0.1V – 0.1V = 6.65V (EQ. 23)
up to 1.5A, a 1N5817 type for loads up to 3A, or a 1N5821 0.35μs ⋅ 1.5
1 – ⎛ -------------------------------⎞
type for loads up to 10A. The rectifier's rated reverse ⎝ 2.25μs ⎠
breakdown voltage must be at least equal to the maximum
input voltage, preferably with a 20% derating factor. Calculating with h = 1 yields:

( 5V + 0.1V )
Applications Information V IN ( MIN ) = ----------------------------------------- + 0.1V – 0.1V = 6.04V
0.35μs ⋅ 1
(EQ. 24)
1 – ⎛ --------------------------⎞
⎝ 2.25μs ⎠
Dropout Performance
The output voltage-adjust range for continuous-conduction Therefore, VIN must be greater than 6.65V. A practical input
operation is restricted by the nonadjustable 350ns (max) voltage with reasonable output capacitance would be 7.5V.
minimum off-time one-shot. Use the slower 5V SMPS for the
higher of the two output voltages for best dropout PC Board Layout Guidelines
performance in adjustable feedback mode. The duty-factor Careful PC board layout is critical to achieve minimal switching
limit must be calculated using worst-case values for on- and losses and clean, stable operation. This is especially true when
off-times, when working with low input voltages. multiple converters are on the same PC board where one
Manufacturing tolerances and internal propagation delays circuit can affect the other. Refer to the ISL6237 Evaluation Kit
introduce an error to the TON K-factor. Also, keep in mind that data sheet for a specific layout example.
transient-response performance of buck regulators operated
Mount all of the power components on the top side of the board
close to dropout is poor, and bulk output capacitance must
with their ground terminals flush against one another, if
often be added (see Equation 10 on page 31).
possible. Follow these guidelines for good PC board layout:
The absolute point of dropout occurs when the inductor
• Isolate the power components on the top side from the
current ramps down during the minimum off-time (ΔIDOWN) as
sensitive analog components on the bottom side with a
much as it ramps up during the on-time (ΔIUP). The ratio ground shield. Use a separate PGND plane under the
h = ΔIUP/ΔIDOWN indicates the ability to slew the inductor OUT1 and OUT2 sides (called PGND1 and PGND2). Avoid
current higher in response to increased load, and must always the introduction of AC currents into the PGND1 and PGND2
be greater than 1. As h approaches 1, the absolute minimum ground planes. Run the power plane ground currents on the
dropout point, the inductor current is less able to increase top side only, if possible.

33 FN6418.4
March 18, 2008
ISL6237

• Use a star ground connection on the power plane to Mount the controller IC adjacent to the synchronous rectifier
minimize the crosstalk between OUT1 and OUT2. MOSFETs close to the hottest spot, preferably on the back
• Keep the high-current paths short, especially at the side in order to keep UGATE_, GND, and the LGATE_ gate
ground terminals. This practice is essential for stable, drive lines short and wide. The LGATE_ gate trace must be
jitter-free operation. short and wide, measuring 50 mils to 100 mils wide if the
MOSFET is 1” from the controller device.
• Keep the power traces and load connections short. This
practice is essential for high efficiency. Using thick copper Group the gate-drive components (BOOT_ capacitor, VIN
PC boards (2oz vs 1oz) can enhance full-load efficiency bypass capacitor) together near the controller device.
by 1% or more. Correctly routing PC board traces must be
approached in terms of fractions of centimeters, where a Make the DC/DC controller ground connections as follows:
single mΩ of excess trace resistance causes a 1. Near the device, create a small analog ground plane.
measurable efficiency penalty.
2. Connect the small analog ground plane to GND and use
• PHASE_ (ISL6237) and GND connections to the the plane for the ground connection for the REF and VCC
synchronous rectifiers for current limiting must be made bypass capacitors, FB dividers and ILIM resistors (if any).
using Kelvin-sense connections to guarantee the 3. Create another small ground island for PGND and use
current-limit accuracy with 8-pin SO MOSFETs. This is the plane for the VIN bypass capacitor, placed very close
best done by routing power to the MOSFETs from outside to the device.
using the top copper layer, while connecting PHASE_
traces inside (underneath) the MOSFETs. 4. Connect the GND and PGND planes together at the
metal tab under device.
• When trade-offs in trace lengths must be made, it is On the board's top side (power planes), make a star ground
preferable to allow the inductor charging path to be made
to minimize crosstalk between the two sides. The top-side
longer than the discharge path. For example, it is better to
star ground is a star connection of the input capacitors and
allow some extra distance between the input capacitors
and the high-side MOSFET than to allow distance synchronous rectifiers. Keep the resistance low between the
between the inductor and the synchronous rectifier or star ground and the source of the synchronous rectifiers for
between the inductor and the output filter capacitor. accurate current limit. Connect the top-side star ground
(used for MOSFET, input, and output capacitors) to the small
• Ensure that the OUT_ connection to COUT_ is short and
island with a single short, wide connection (preferably just a
direct. However, in some cases it may be desirable to
via). Create PGND islands on the layer just below the
deliberately introduce some trace length between the
OUT_ connector node and the output filter capacitor. top-side layer (refer to the ISL6237 EV kit for an example) to
act as an EMI shield if multiple layers are available (highly
• Route high-speed switching nodes (BOOT_, UGATE_, recommended). Connect each of these individually to the
PHASE_, and LGATE_) away from sensitive analog areas star ground via, which connects the top side to the PGND
(REF, ILIM_, and FB_). Use PGND1 and PGND2 as an
plane. Add one more solid ground plane under the device to
EMI shield to keep radiated switching noise away from the
act as an additional shield, and also connect the solid
IC's feedback divider and analog bypass capacitors.
ground plane to the star ground via.
• Make all pin-strap control input connections (SKIP, ILIM_,
etc.) to GND or VCC of the device. Connect the output power planes (VCORE and system
ground planes) directly to the output filter capacitor positive
Layout Procedure and negative terminals with multiple vias.
Place the power components first with ground terminals
adjacent (Q2/Q4 source, CIN_, COUT_). If possible, make
all these connections on the top layer with wide, copper-filled
areas.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

34 FN6418.4
March 18, 2008
ISL6237

Package Outline Drawing

L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 11/07

4X 3.5
5.00 A 28X 0.50
6
B
25 32 PIN #1 INDEX AREA

6
PIN 1 24 1
INDEX AREA

5.00
3 .30 ± 0 . 15

17 8
(4X) 0.15
16 9
0.10 M C A B

+ 0.07
32X 0.40 ± 0.10 4 32X 0.23 - 0.05

TOP VIEW BOTTOM VIEW

SEE DETAIL "X"

0.10 C
0 . 90 ± 0.1 C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
( 28X 0 . 5 )
SIDE VIEW
( 3. 30 )

(32X 0 . 23 )

C 0 . 2 REF 5
( 32X 0 . 60)

0 . 00 MIN.
0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

35 FN6418.4
March 18, 2008

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