M95128-W M95128-R M95128-DF

Datasheet

128-Kbit serial SPI bus EEPROM with high-speed clock

Features
• Compatible with the serial peripheral interface (SPI) bus
SO8N • Memory array
150 mil width – 128 Kbit (16 Kbytes) of EEPROM
– Page size: 64 bytes
– Additional write lockable page (Identification page)
• Write time
– Byte Write within 5 ms
– Page Write within 5 ms
TSSOP8
• Write protect
169 mil width
– quarter array
– half array
– whole memory array
• High-speed clock: 20 MHz
• Single supply voltage:
UFDFPN8 (MC) – 2.5 V to 5.5 V for M95128-W
DFN8 - 2x3 mm – 1.8 V to 5.5 V for M95128-R
– 1.7 V to 5.5 V for M95128-DF
• Operating temperature range: from -40 °C up to +85 °C
WLSCP (CS) • Enhanced ESD protection
• More than 4 million Write cycles
Product status link • More than 200-year data retention
M95128-DF • Packages
M95128-R – SO8 (ECOPACK2®)
M95128-W – TSSOP8 (ECOPACK2®)
– UFDFPN8 (ECOPACK2®)
– WLCSP (ECOPACK2®)

DS1356 - Rev 20 - October 2020 www.st.com

For further information contact your local STMicroelectronics sales office.
 M95128-W M95128-R M95128-DF
Description

1 Description

The M95128 devices are electrically erasable programmable memories (EEPROMs) organized as 16384 x 8 bits,
accessed through the SPI bus.
The M95128-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95128-R can operate with a supply
voltage from 1.8 V to 5.5 V and the M95128-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an
ambient temperature range of -40 °C / +85 °C.
The M95128-DF offers an additional page, named the Identification page (64 bytes). The Identification page can
be used to store sensitive application parameters that can be (later) permanently locked in read-only mode.

Figure 1. Logic diagram

VCC

D
C
S M95xxx Q
W
HOLD

VSS

The SPI bus signals are C, D and Q, as shown in Figure 1. Logic diagram and Table 1. Signal names. The device
is selected when Chip select (S) is driven low. Communications with the device can be interrupted when the
HOLD is driven low.

Table 1. Signal names

Signal name Function Direction

C Serial clock Input

D Serial data input Input
Q Serial data output Output
S Chip select Input
W Write protect Input
HOLD Hold Input
VCC Supply voltage -

VSS Ground -

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 M95128-W M95128-R M95128-DF
Description

Figure 2. 8-pin package connections (top view)

M95xxx
S 1 8 VCC

Q 2 7 HOLD

W 3 6 C

VSS 4 5 D

1. See Section 10 Package information for package dimensions, and how to identify pin 1.

Figure 3. WLCSP connections (top view, marking side, with bumps on the underside)

1 2 3

A HOLD Q

B S

C VCC VSS

D D

E C W

Table 2. Signals vs. bump position

Position A B C D E

1 HOLD - VCC - C

2 - S - D -

3 Q - VSS - W

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 M95128-W M95128-R M95128-DF
Memory organization

2 Memory organization

The memory is organized as shown in the following figure.

Figure 4. Block diagram

DATA REGISTER SENSE AMPLIFIERS

/S +
ECC PAGE LATCHES X DECODER

Y DECODER
ARRAY
W
I/O
STATUS
D REGISTER CUSTOM AREA
CONTROL
LOGIC HV GENERATOR
C +
SEQUENCER
HOLD ADDRESS
REGISTER

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 M95128-W M95128-R M95128-DF
Signal description

3 Signal description

During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as
specified in Section 9 DC and AC parameters). These signals are described next.

3.1 Serial data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial
clock (C).

3.2 Serial data input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data
to be written. Values are latched on the rising edge of Serial clock (C).

3.3 Serial clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial data
input (D) are latched on the rising edge of Serial clock (C). Data on Serial data output (Q) change from the falling
edge of Serial clock (C).

3.4 Chip select (S)

When this input signal is high, the device is deselected and Serial data output (Q) is at high impedance. The
device is in the Standby power mode, unless an internal Write cycle is in progress. Driving Chip select (S) low
selects the device, placing it in the Active power mode.
After power-up, a falling edge on Chip select (S) is required prior to the start of any instruction.

3.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the
device.
During the Hold condition, the Serial data output (Q) is high impedance, and Serial data input (D) and Serial clock
(C) are Don’t care.
To start the Hold condition, the device must be selected, with Chip select (S) driven low.

3.6 Write protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write
instructions (as specified by the values in the BP1 and BP0 bits of the Status register).
This pin must be driven either high or low, and must be stable during all Write instructions.

3.7 VCC supply voltage

VCC is the supply voltage.

3.8 VSS ground

VSS is the reference for all signals, including the VCC supply voltage.

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 M95128-W M95128-R M95128-DF
Connecting to the SPI bus

4 Connecting to the SPI bus

All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial
data input (D) is sampled on the first rising edge of the Serial clock (C) after Chip select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial data output (Q) is latched on
the first falling edge of the Serial clock (C) after the instruction (such as the Read from Memory array and Read
Status register instructions) have been clocked into the device.

Figure 5. Bus master and memory devices on the SPI bus

VCC

SPI interface with SDO

(CPOL, CPHA) = SDI
(0, 0) or 1, 1) SCK

C Q D VCC C Q D VCC C Q D VCC

SPI bus master

SPI memory SPI memory SPI memory

R R R
device device device
CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD

(1) (1) (1) (1) (1) (1)

VSS

1. The Write protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 5. Bus master and memory devices on the SPI bus shows an example of three memory devices connected
to an SPI bus master. Only one memory device is selected at a given time, so only one memory device drives the
Serial data output (Q) line at that time. The other memory devices are in high impedance state. The pull-up
resistor R ensures that a device is not selected if the Bus master leaves the S line in the high impedance state.
In applications where the bus master can enter a state where the whole input/output SPI bus is high-impedance at
a given time (for example, if the bus master is reset during the transmission of an instruction), it is advised to
connect the clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high-impedance,
the C line is pulled low (while the S line is pulled high). This ensures that S and C do not become high at the
same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.

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 M95128-W M95128-R M95128-DF
SPI modes

4.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two
modes:
• CPOL = 0, CPHA = 0
• CPOL = 1, CPHA = 1
For these two modes, input data is latched in on the rising edge of Serial clock (C), and output data is available
from the falling edge of Serial clock (C).
The difference between the two modes, as shown in Figure 6. SPI modes supported, is the clock polarity when
the bus master is in Stand-by mode and not transferring data:
• C remains at 0 for (CPOL = 0, CPHA = 0)
• C remains at 1 for (CPOL = 1, CPHA = 1)

Figure 6. SPI modes supported

CPOL CPHA
0 0 C

1 1 C

D MSB

Q MSB

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 M95128-W M95128-R M95128-DF
Operating features

5 Operating features

5.1 Supply voltage (VCC)

5.1.1 Operating supply voltage (VCC)

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified
[VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9 DC and AC parameters).
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write
instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually in the range between 10 and 100 nF)
close to the VCC / VSS device pins.

5.1.2 Device reset

In order to prevent erroneous instruction decoding and inadvertent Write operations during power‑up, a
power‑on‑reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches the POR threshold voltage. This threshold is lower than the minimum VCC operating voltage (see
Operating conditions in Section 9 DC and AC parameters).
At power-up, when VCC passes over the POR threshold, the device is reset and is in the following state:
• in Standby power mode,
• deselected,
• Status register values:
– the Write enable latch (WEL) bit is reset to 0
– the Write in progress (WIP) bit is reset to 0
– the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and stable level within the
specified [VCC(min), VCC(max)] range, as defined under Operating conditions in Section 9 DC and AC
parameters.

5.1.3 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip select (S)
line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to
VCC via a suitable pull-up resistor (see Figure 5. Bus master and memory devices on the SPI bus).
In addition, the Chip select (S) input offers a built-in safety feature, as the S input is
edge-sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge
has first been detected on Chip select (S). This ensures that Chip select (S) must have been high, prior to going
low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in
Section 9 DC and AC parameters.

5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage
defined in Section 9 DC and AC parameters), the device must be:
• deselected (Chip select S must be allowed to follow the voltage applied on VCC)
• in Standby power mode (there must not be any internal write cycle in progress).

5.2 Active power and Standby power modes

When Chip select (S) is low, the device is selected, and in the Active power mode. The device consumes ICC.
When Chip select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then
goes into the Standby power mode, and the device consumption drops to ICC1, as specified in DC characteristics
(see Section 9 DC and AC parameters).

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 M95128-W M95128-R M95128-DF
Hold condition

5.3 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking
sequence.
To enter the Hold condition, the device must be selected, with Chip select (S) low.
During the Hold condition, the Serial data output (Q) is high impedance, and the Serial data input (D) and the
Serial clock (C) are Don’t care.
Normally, the device is kept selected for the whole duration of the Hold condition. Deselecting the device while it
is in the Hold condition has the effect of resetting the state of the device: this mechanism can be used, if required,
to reset the ongoing processes.
Note: This resets the internal logic, except the WEL and WIP bits of the Status register.
In the specific case where the device has moved in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.

Figure 7. Hold condition activation

HOLD

Hold Hold
condition condition

The Hold condition starts when the Hold (HOLD) signal is driven low when Serial clock (C) is already low (as
shown in Figure 7. Hold condition activation).
Figure 7. Hold condition activation also shows what happens if the rising and falling edges are not timed to
coincide with Serial clock (C) being low.

5.4 Status register

The Status register contains a number of status and control bits that can be read or set (as appropriate) by
specific instructions. See Section 6.3 Read Status register (RDSR) for a detailed description of the Status
register bits.

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Data protection and protocol control

5.5 Data protection and protocol control

The device features the following data protection mechanisms:
• Before accepting the execution of the Write and Write Status register instructions, the device checks
whether the number of clock pulses comprised in the instructions is a multiple of eight.
• All instructions that modify data must be preceded by a Write enable (WREN) instruction to set the Write
enable latch (WEL) bit.
• The Block protect (BP1, BP0) bits in the Status register are used to configure part of the memory as
read‑only.
• The Write protect (W) signal is used to protect the Block protect (BP1, BP0) bits in the Status register.
For any instruction to be accepted, and executed, Chip select (S) must be driven high after the rising edge of
Serial clock (C) for the last bit of the instruction, and before the next rising edge of Serial clock (C).
Two points to note in the previous sentence:
• The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth bit of a data byte,
depending on the instruction (except for Read Status register (RDSR) and Read (READ) instructions).
• The “next rising edge of Serial clock (C)” might (or might not) be the next bus transaction for some other
device on the SPI bus.

Table 3. Write-protected block size

Status register bits

Protected block Protected array addresses
BP1 BP0

0 0 None None
0 1 Upper quarter 3000h - 3FFFh
1 0 Upper half 2000h - 3FFFh
1 1 Whole memory 0000h - 3FFFh plus Identification Page

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 M95128-W M95128-R M95128-DF
Instructions

6 Instructions

Each command is composed of bytes (MSBit transmitted first), initiated with the instruction byte, as summarized
in Table 4.
If an invalid instruction is sent (one not contained in Table 4), the device automatically enters in a Wait state until
deselected.

Table 4. Instruction set

Instruction Description Instruction format

WREN Write enable 0000 0110

WRDI Write disable 0000 0100
RDSR Read Status register 0000 0101
WRSR Write Status register 0000 0001
READ Read from Memory array 0000 0011
WRITE Write to Memory array 0000 0010

RDID (1) Read Identification page 1000 0011

WRID(1) Write Identification page 1000 0010

RDLS(1) Reads the Identification page lock status 1000 0011

LID(1) Locks the Identification page in read-only mode 1000 0010

1. Instruction available only for the M95128-D device.

For read and write commands to memory array and Identification page the address is defined by two bytes as
explained in Table 5.

Table 5. Significant bits within the address bytes

MSB address byte LSB address byte

Instruction
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

READ
x x A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
or WRITE
RDID
0 0 0 0 0 0 0 0 0 0 A5 A4 A3 A2 A1 A0
or WRID
RDLS
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
or LID

Note: A: Significant address bit.

x: bit is Don’t care.

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Write enable (WREN)

6.1 Write enable (WREN)

The Write enable latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this
is to send a Write enable instruction to the device.
As shown in Figure 8. Write enable (WREN) sequence, to send this instruction to the device, Chip select (S) is
driven low, and the bits of the instruction byte are shifted in, on Serial data input (D). The device then enters a
wait state. It waits for the device to be deselected by Chip select (S) being driven high.

Figure 8. Write enable (WREN) sequence

0 1 2 3 4 5 6 7

C
Instruction

High impedance
Q MS41478V1

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Write disable (WRDI)

6.2 Write disable (WRDI)

One way of resetting the Write enable latch (WEL) bit is to send a Write disable instruction to the device.
As shown in Figure 9, to send this instruction to the device, Chip select (S) is driven low, and the bits of the
instruction byte are shifted in, on Serial data input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip select (S) being driven
high.
The Write enable latch (WEL) bit, in fact, becomes reset by any of the following events:
• Power-up
• WRDI instruction execution
• WRSR instruction completion
• WRITE instruction completion.

Figure 9. Write disable (WRDI) sequence

0 1 2 3 4 5 6 7

C
Instruction

High Impedance
Q

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Read Status register (RDSR)

6.3 Read Status register (RDSR)

The Read Status register (RDSR) instruction is used to read the Status register. The Status register may be read
at any time, even while a Write or Write Status register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write in progress (WIP) bit before sending a new instruction to the
device. It is also possible to read the Status register continuously, as shown in Figure 10. Read Status register
(RDSR) sequence.

Figure 10. Read Status register (RDSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction

Status Register Out Status Register Out

High impedance
Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB
MS47548V1

The status and control bits of the Status register are detailed in the following subsections.

6.3.1 WIP bit

The Write in progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle.
When set to 1, such a cycle is in progress, when reset to 0, no such cycle is in progress.

6.3.2 WEL bit

The Write enable latch (WEL) bit indicates the status of the internal Write enable latch. When set to 1, the internal
Write enable latch is set. When set to 0, the internal Write enable latch is reset, and no Write or Write Status
Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
• Power-up
• Write Disable (WRDI) instruction completion
• Write Status Register (WRSR) instruction completion
• Write (WRITE) instruction completion

6.3.3 BP1, BP0 bits

The Block protect (BP1, BP0) bits are non volatile. They define the size of the area to be software-protected
against Write instructions. These bits are written with the Write Status register (WRSR) instruction. When one or
both of the Block protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3. Write-
protected block size) becomes protected against Write (WRITE) instructions. The Block protect (BP1, BP0) bits
can be written provided that the Hardware Protected mode has not been set.

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Write Status register (WRSR)

6.3.4 SRWD bit

The Status register Write Disable (SRWD) bit is operated in conjunction with the Write protect (W) signal. The
Status register Write Disable (SRWD) bit and Write protect (W) signal enable the device to be put in the Hardware
Protected mode (when the Status register Write Disable (SRWD) bit is set to 1, and Write protect (W) is driven
low). In this mode, the non-volatile bits of the Status register (SRWD, BP1, BP0) become read-only bits and the
Write Status register (WRSR) instruction is no longer accepted for execution.

Table 6. Status register format

b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP

Status register Write protect

Block protect bits
Write enable latch bit
Write in progress bit

6.4 Write Status register (WRSR)

The Write Status register (WRSR) instruction is used to write new values to the Status register. Before it can be
accepted, a Write enable (WREN) instruction must have been previously executed.
The Write Status register (WRSR) instruction is entered by driving Chip select (S) low, followed by the instruction
code, the data byte on Serial Data input (D) and Chip select (S) driven high. Chip select (S) must be driven high
after the rising edge of Serial clock (C) that latches in the eighth bit of the data byte, and before the next rising
edge of Serial clock (C). Otherwise, the Write Status register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 11 below.

Figure 11. Write Status register (WRSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction Status Register In

D 7 6 5 4 3 2 1 0

MSB

High impedance
Q
MS47556V1

Driving the Chip select (S) signal high at a byte boundary of the input data triggers the
self-timed Write cycle that takes tW to complete (as specified in AC tables in Section 9 DC and AC parameters).
While the Write Status register cycle is in progress, the Status register may still be read to check the value of the
Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle tW, and 0 when the Write cycle is
complete. The WEL bit (Write enable latch) is also reset at the end of the Write cycle tW.

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Write Status register (WRSR)

The Write Status register (WRSR) instruction enables the user to change the values of the BP1, BP0 and SRWD
bits:
• The Block protect (BP1, BP0) bits define the size of the area that is to be treated as read-only, as defined in
Table 3. Write-protected block size.
• The SRWD (Status register Write Disable) bit, in accordance with the signal read on the Write protect pin
(W), enables the user to set or reset the Write protection mode of the Status register itself, as defined in
Table 7. Protection modes. When in Write-protected mode, the Write Status register (WRSR) instruction is
not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction,
including the tW Write cycle.
The Write Status register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the Status register.
Bits b6, b5, b4 are always read as 0.

Table 7. Protection modes

Memory content
SRWD
W signal Mode Write protection of the Status register Protected
bit Unprotected area(1)
area (1)

1 0 Status register is writable (if the WREN

Software- instruction has set the WEL bit).
0 0 Write- Ready to accept
protected
The values in the BP1 and BP0 bits can be protected Write instructions
(SPM)
1 1 changed.

Hardware- Status register is Hardware write-protected.

Write- Ready to accept
0 1 protected The values in the BP1 and BP0 bits cannot be protected Write instructions
(HPM) changed.

1. As defined by the values in the Block protect (BP1, BP0) bits of the Status register. See Table 3. Write-protected block size.

The protection features of the device are summarized in Table 7.

When the Status register Write Disable (SRWD) bit in the Status register is 0 (its initial delivery state), it is
possible to write to the Status register (provided that the WEL bit has previously been set by a WREN instruction),
regardless of the logic level applied on the Write protect (W) input pin.
When the Status register Write Disable (SRWD) bit in the Status register is set to 1, two cases should be
considered, depending on the state of the Write protect (W) input pin:
• If Write protect (W) is driven high, it is possible to write to the Status register (provided that the WEL bit has
previously been set by a WREN instruction).
• If Write protect (W) is driven low, it is not possible to write to the Status register even if the WEL bit has
previously been set by a WREN instruction. (Attempts to write to the Status register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area, which are Software-
protected (SPM) by the Block protect (BP1, BP0) bits in the Status register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered by:
• either setting the SRWD bit after driving the Write protect (W) input pin low,
• or driving the Write protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the Write
protect (W) input pin.
If the Write protect (W) input pin is permanently tied high, the Hardware-protected mode (HPM) can never be
activated, and only the Software-protected mode (SPM), using the Block protect (BP1, BP0) bits in the Status
register, can be used.

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Read from Memory array (READ)

6.5 Read from Memory array (READ)

As shown in Figure 12, to send this instruction to the device, Chip select (S) is first driven low. The bits of the
instruction byte and address bytes are then shifted in, on Serial data input (D). The address is loaded into an
internal address register, and the byte of data at that address is shifted out, on Serial data output (Q).

Figure 12. Read from Memory array (READ) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C

Instruction 16-Bit Address

D 15 14 13 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
Q 7 6 5 4 3 2 1 0 7
MSB

Note: Depending on the memory size, as shown in Table 5. Significant bits within the address bytes, the most
significant address bits are Don’t care.
If Chip select (S) continues to be driven low, the internal address register is incremented automatically, and the
byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be
continued indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving Chip select (S) high. The rising edge of the Chip select (S) signal can
occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

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Write to Memory array (WRITE)

6.6 Write to Memory array (WRITE)

As shown in Figure 13, to send this instruction to the device, Chip select (S) is first driven low. The bits of the
instruction byte, address byte, and at least one data byte are then shifted in, on Serial data input (D).
The instruction is terminated by driving Chip select (S) high at a byte boundary of the input data. The self-timed
Write cycle, triggered by the Chip select (S) rising edge, continues for a period tW (as specified in AC
characteristics in Section 9 DC and AC parameters), at the end of which the Write in Progress (WIP) bit is reset
to 0.

Figure 13. Byte Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction 16-bit address Data byte

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

High impedance
Q

Note: Depending on the memory size, as shown in Table 5. Significant bits within the address bytes, the most
significant address bits are Don’t care.
In the case of Figure 13, Chip select (S) is driven high after the eighth bit of the data byte has been latched in,
indicating that the instruction is being used to write a single byte. However, if Chip select (S) continues to be
driven low (as shown in Figure 14), the next byte of input data is shifted in, so that more than a single byte,
starting from the given address towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If
more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of roll-
over, the bytes exceeding the page size are overwritten from location 0 of the same page.
The instruction is not accepted, and is not executed, under the following conditions:
• if the Write enable latch (WEL) bit has not been set to 1 (by executing a Write enable instruction just before),
• if a Write cycle is already in progress,
• if the device has not been deselected, by driving high Chip select (S), at a byte boundary (after the eighth
bit, b0, of the last data byte that has been latched in),
• if the addressed page is in the region protected by the Block protect (BP1 and BP0) bits.
Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed
byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as
“1”.

DS1356 - Rev 20 page 18/48

 M95128-W M95128-R M95128-DF
Write to Memory array (WRITE)

Figure 14. Page Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

Instruction 16-Bit Address Data Byte 1

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Data Byte 2 Data Byte 3 Data Byte N

D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0

1. Depending on the memory size, as shown in Table 5. Significant bits within the address bytes, the most
significant address bits are Don’t care.

DS1356 - Rev 20 page 19/48

 M95128-W M95128-R M95128-DF
Read Identification page (available only in M95128-D devices)

6.6.1 Cycling with error correction code (ECC x4)

M95128 devices offer an error correction code (ECC) logic. The ECC is an internal logic function transparent for
the SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at
addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.). Inside a group, if a single bit out of the four bytes
happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value.
The read reliability is therefore much improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently.
In this case, the ECC function also writes/cycles the three other bytes located in the same group. As a
consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the
four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must
remain below the maximum value defined in Table 13. Cycling performance by groups of four bytes.

6.7 Read Identification page (available only in M95128-D devices)

The Identification page (64 bytes) is an additional page that can be written and (later) permanently locked in
Read-only mode.
This page is read with the Read Identification page instruction (see Table 4. Instruction set ). The Chip select
signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial data
input (D). Address bit A10 must be 0, upper address bits are Don't care, and the data byte pointed to by the lower
address bits [A5:A0] is shifted out on Serial data output (Q). If Chip select (S) continues to be low, the internal
address register is automatically incremented, and the byte of data at the new address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary, otherwise unexpected data are
read (e.g. when reading the ID page from location 24d, the number of bytes must be lower than or equal to 40d,
as the ID page boundary is 64 bytes).
The read cycle is terminated by driving Chip select (S) high. The rising edge of the Chip select (S) signal can
occur at any time during the cycle. The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.

Figure 15. Read Identification page sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction 16-bit address

D 15 14 13 3 2 1 0
MSB

Data Out 1 Data Out 2

High impedance
Q 7 6 5 4 3 2 1 0 7
MSB

DS1356 - Rev 20 page 20/48

 M95128-W M95128-R M95128-DF
Write Identification page (available only in M95128-D devices)

6.8 Write Identification page (available only in M95128-D devices)

The Identification page (64 bytes) is an additional page that can be written and (later) permanently locked in
Read-only mode.
Writing this page is achieved with the Write Identification page instruction (see Table 4. Instruction set). The Chip
select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are
then shifted in on Serial data input (D). Address bit A10 must be 0, upper address bits are Don't care, the lower
address bits [A5:A0] define the byte address within the Identification page. The instruction sequence is shown in
Figure 16. Write Identification page sequence.

Figure 16. Write Identification page sequence

S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C

Instruction 16-bit address Data byte

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

High impedance
Q

6.9 Read Lock status (available only in M95128-D devices)

The Read Lock status instruction (see Table 4. Instruction set) is used to check whether the Identification page is
locked or not in Read-only mode. The Read Lock status sequence is defined with the Chip select (S) first driven
low. The bits of the instruction byte and address bytes are then shifted in on Serial data input (D). Address bit A10
must be 1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on
Serial data output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If Chip select (S)
continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip select
(S) high.
The instruction sequence is shown in Figure 17. Read Lock status sequence.

Figure 17. Read Lock status sequence

S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

C
Instruction 16-bit address

D 15 14 13 3 2 1 0

MSB
Data Out 1 Data Out 2
High impedance
Q 7 6 5 4 3 2 1 0 7

MSB

DS1356 - Rev 20 page 21/48

 M95128-W M95128-R M95128-DF
Lock ID (available only in M95128-D devices)

6.10 Lock ID (available only in M95128-D devices)

The Lock ID instruction permanently locks the Identification page in read-only mode. Before this instruction can be
accepted, a Write enable (WREN) instruction must have been executed.
The Lock ID instruction is issued by driving Chip select (S) low, sending the instruction code, the address and a
data byte on Serial data input (D), and driving Chip select (S) high. In the address sent, A10 must be equal to 1,
all other address bits are Don't Care. The data byte sent must be equal to the binary value xxxx xx1x, where x =
Don't Care.
Chip select (S) must be driven high after the rising edge of Serial clock (C) that latches in the eighth bit of the data
byte, and before the next rising edge of Serial clock (C). Otherwise, the Lock ID instruction is not executed.
Driving Chip select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration
is tW (as specified in AC characteristics in Section 9 DC and AC parameters). The instruction sequence is shown
in Figure 18. Lock ID sequence.
The instruction is discarded, and is not executed, under the following conditions:
• If a Write cycle is already in progress
• If Block protect bits (BP1,BP0) = (1,1)
• If a rising edge on Chip select (S) happens outside of a byte boundary.
• If the Write enable latch (WEL) bit has not been set to 1 (by executing a Write enable instruction just before)

Figure 18. Lock ID sequence

S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C

Instruction 16-bit address Data byte

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

High impedance
Q

DS1356 - Rev 20 page 22/48

 M95128-W M95128-R M95128-DF
Power-up and delivery state

7 Power-up and delivery state

7.1 Power-up state

After power-up, the device is in the following state:
• Standby power mode
• deselected (after power-up, a falling edge is required on Chip select (S) before any instructions can be
started)
• not in the Hold condition
• the Write enable latch (WEL) is reset to 0
• Write in progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status register are unchanged from the previous power-down (they are non-
volatile bits).

7.2 Initial delivery state

The device is delivered with the memory array and Identification page bits set to all 1s (each byte = FFh). The
Status register Write Disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0.

DS1356 - Rev 20 page 23/48

 M95128-W M95128-R M95128-DF
Maximum ratings

8 Maximum ratings

Stressing the device outside the ratings listed in Table 8 may cause permanent damage to the device. These are
stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the
operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Table 8. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

TAMB Ambient operating temperature –40 130

TSTG Storage temperature –65 150 °C

TLEAD Lead temperature during soldering See note (1)

VO Output voltage –0.50 VCC + 0.6

VI Input voltage –0.50 6.5 V

VCC Supply voltage –0.50 6.5

IOL DC output current (Q = 0) - 5

mA
IOH DC output current (Q = 1) - 5

VESD Electrostatic discharge voltage (human body model) (2) - 4000 V

1. Compliant with JEDEC standard J-STD-020E (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395
specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July
2011).
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant
with ANSI/ESDA/JEDEC JS-001-2012, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

DS1356 - Rev 20 page 24/48

 M95128-W M95128-R M95128-DF
DC and AC parameters

9 DC and AC parameters

This section summarizes the operating conditions and the DC/AC characteristics.

Table 9. Operating conditions (M95128-W, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 2.5 5.5 V

TA Ambient operating temperature –40 85 °C

Table 10. Operating conditions (M95128-R, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.8 5.5 V

TA Ambient operating temperature -40 85 °C

Table 11. Operating conditions (M95128-DF, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.7 5.5 V

TA Ambient operating temperature –40 85 °C

Table 12. AC measurement conditions

Symbol Parameter Min. Max. Unit

CL Load capacitance - 100 pF

- Input rise and fall times - 50 ns

- Input pulse voltages 0.2 VCC to 0.8 VCC V

- Input and output timing references voltages 0.3 VCC to 0.7 VCC V

Figure 19. AC measurement I/O waveform

Input and Output

Input Levels
Timing Reference Levels
0.8 ₓ VCC
0.7 ₓ VCC

0.3 ₓ VCC
0.2 ₓ VCC

DS1356 - Rev 20 page 25/48

 M95128-W M95128-R M95128-DF
DC and AC parameters

Table 13. Cycling performance by groups of four bytes

Symbol Parameter Test condition Min. Max. Unit

TA ≤ 25 °C, VCC(min) < VCC < VCC(max) - 4,000,000

Ncycle Write cycle endurance(1) Write cycle(2)
TA = 85 °C, VCC(min) < VCC < VCC(max) - 1,200,000

1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where
N is an integer. The Write cycle endurance is defined by characterization and qualification.
2. A Write cycle is executed when either a Page write, a Byte write, a WRSR, a WRID or an LID instruction is decoded. When
using the Byte write, the Page write or the WRID instruction, refer also to Section 6.6.1 Cycling with error correction code
(ECC x4).

Table 14. Memory cell data retention

Parameter Test condition Min. Unit

Data retention(1) TA = 55 °C 200 Year

1. The data retention behaviour is checked in production, while the 200-year limit is defined from characterization and
qualification results.

Table 15. Capacitance

Symbol Parameter Test condition(1) Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V - 8 pF

Input capacitance (D) VIN = 0 V - 8 pF

CIN
Input capacitance (other pins) VIN = 0 V - 6 pF

1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz

DS1356 - Rev 20 page 26/48

 M95128-W M95128-R M95128-DF
DC and AC parameters

Table 16. DC characteristics (M95128-W, device grade 6)

Symbol Parameter Test conditions specified in Table 9 and Table 12 Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC - ±2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC - ±2 µA

VCC= 2.5 V, C = 0.1 VCC / 0.9 VCC

- 2
at 10 MHz, Q = open
ICC Supply current (Read) mA
VCC= 5.5 V, C = 0.1 VCC / 0.9 VCC
- 5
at 20 MHz, Q = open
During tW, S = VCC,
ICC0 (1) Supply current (Write) - 3 mA
2.5 V < VCC < 5.5 V

S = VCC, VCC= 5.5 V,

- 3
VIN = VSS or VCC
Supply current
ICC1 µA
(Standby) S = VCC, VCC= 2.5 V,
- 2
VIN = VSS or VCC

VIL Input low voltage - –0.45 0.3 VCC V

VIH Input high voltage - 0.7 VCC VCC+1 V

VCC = 2.5 V and IOL = 1.5 mA or

VOL Output low voltage - 0.4 V
VCC = 5 V and IOL = 2 mA

VCC = 2.5 V and IOH = –0.4 mA or

VOH Output high voltage 0.8 VCC - V
VCC = 5 V and IOH = –2 mA

1. Characterized only, not tested in production.

Table 17. DC characteristics (M95128-R, device grade 6)

Test conditions in addition to those defined in Table 10

Symbol Parameter Min Max Unit
and Table 12 (1)

ILI Input leakage current VIN = VSS or VCC - ±2 µA

ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - ±2 µA

VCC= 1.8 V, C = 0.1 VCC or 0.9 VCC

ICC Supply current (Read) - 2 mA
at 5 MHz , Q = open

ICC0 (2) Supply current (Write) VCC = 1.8 V , during tW, S = VCC - 3 mA

Supply current
ICC1 VCC = 1.8 V, S = VCC, VIN = VSS or VCC - 1 µA
(Standby)
VIL Input low voltage 1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V

VIH Input high voltage 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC+1 V

VOL Output low voltage IOL = 0.15 mA, VCC = 1.8 V - 0.3 V

VOH Output high voltage IOH = –0.1 mA, VCC = 1.8 V 0.8 VCC - V

1. If the application uses the M95128-R with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, refer to Table 16 rather then the
above table.
2. Characterized only, not tested in production.

DS1356 - Rev 20 page 27/48

 M95128-W M95128-R M95128-DF
DC and AC parameters

Table 18. DC characteristics (M95128-DF, device grade 6)

Symbol Parameter Test conditions in Table 11 and Table 12(1) Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC - ±2 µA

ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - ±2 µA

VCC = 1.7 V, C = 0.1 VCC or 0.9 VCC,

ICC Supply current (Read) - 2 mA
at 5 MHz, Q = open

ICC0(2) Supply current (Write) VCC = 1.7 V, during tW, S = VCC - 3 mA

ICC1 Supply current (Standby) VCC = 1.7 V, S = VCC, VIN = VSS or VCC - 1 µA

VIL Input low voltage 1.7 V ≤ VCC < 2.5 V –0.45 0.25 VCC V

VIH Input high voltage 1.7 V ≤ VCC < 2.5 V 0.75 VCC VCC+1 V

VOL Output low voltage IOL = 0.15 mA, VCC = 1.7 V - 0.3 V

VOH Output high voltage IOH = –0.1 mA, VCC = 1.7 V 0.8 VCC - V

1. If the application uses the M95128-DF devices at 2.5 V ≤ VCC < 2.5 V and –40 °C ≤TA ≤+85 °C, refer to Table 16. DC
characteristics (M95128-W, device grade 6) rather than to the above table. If the application uses the M95128-DF devices at
1.8 V ≤ VCC < 2.5 V and –40 °C ≤ TA ≤ +85 °C, refer to Table 17. DC characteristics (M95128-R, device grade 6), rather
than to the above table.
2. Characterized only, not tested in production.

DS1356 - Rev 20 page 28/48

 M95128-W M95128-R M95128-DF
DC and AC parameters

Table 19. AC characteristics (M95128-W, device grade 6)

Test conditions specified in Table 9 V ≥ 2.5V VCC ≥ 4.5V

Unit
Symbol Alt. Parameter Min. Max. Min. Max.

fC fSCK Clock frequency D.C. 10 D.C. 20 MHz

tSLCH tCSS1 S active setup time 30 - 15 - ns

tSHCH tCSS2 S not active setup time 30 - 15 - ns

tSHSL tCS S deselect time 40 - 20 - ns

tCHSH tCSH S active hold time 30 - 15 - ns

tCHSL - S not active hold time 30 - 15 - ns

tCH (1) tCLH Clock high time 40 - 20 - ns

tCL (1) tCLL Clock low time 40 - 20 - ns

tCLCH (1) tRC Clock rise time - 2 - 2 µs

tCHCL (1) tFC Clock fall time - 2 - 2 µs

tDVCH tDSU Data in setup time 10 - 5 - ns

tCHDX tDH Data in hold time 10 - 10 - ns

tHHCH - Clock low hold time after HOLD not active 30 - 15 - ns

tHLCH - Clock low hold time after HOLD active 30 - 15 - ns

tCLHL - Clock low setup time before HOLD active 0 - 0 - ns

tCLHH - Clock low setup time before HOLD not active 0 - 0 - ns

tSHQZ (2) tDIS Output disable time - 40 - 20 ns

tCLQV tV Clock low to output valid - 40 - 20 ns

tCLQX tHO Output hold time 0 - 0 - ns

tHHQV tLZ HOLD high to output valid - 40 - 20 ns

tHLQZ (2) tHZ HOLD low to output High-Z - 40 - 20 ns

tW tWC Write time - 5 - 5 ms

1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
2. Characterized only, not tested in production.

DS1356 - Rev 20 page 29/48

 M95128-W M95128-R M95128-DF
DC and AC parameters

Table 20. AC characteristics (M95128-R, device grade 6)

Test conditions specified in Table 10

VCC ≥ 1.8V VCC ≥ 2.5V VCC≥ 4.5V

Symbol Alt. Parameter Unit
Min. Max. Min. Max. Min. Max.

fC fSCK Clock frequency - 5 - 10 - 20 MHz

tSLCH tCSS1 S active setup time 60 - 30 - 15 - ns

tSHCH tCSS2 S not active setup time 60 - 30 - 15 - ns

tSHSL tCS S deselect time 90 - 40 - 20 - ns

tCHSH tCSH S active hold time 60 - 30 - 15 - ns

tCHSL - S not active hold time 60 - 30 - 15 - ns

tCH (1) tCLH Clock high time 80 - 40 - 20 - ns

tCL (1) tCLL Clock low time 80 - 40 - 20 - ns

tCLCH (2) tRC Clock rise time - 2 - 2 - 2 µs

tCHCL (2) tFC Clock fall time - 2 - 2 - 2 µs

tDVCH tDSU Data in setup time 20 - 10 - 5 - ns

tCHDX tDH Data in hold time 20 - 10 - 10 - ns

tHHCH - Clock low hold time after HOLD not active 60 - 30 - 15 - ns

tHLCH - Clock low hold time after HOLD active 60 - 30 - 15 - ns

tCLHL - Clock low setup time before HOLD active 0 - 0 - 0 - ns

tCLHH - Clock low setup time before HOLD not active 0 - 0 - 0 - ns

tSHQZ (2) tDIS Output disable time - 80 - 40 - 20 ns

tCLQV tV Clock low to output valid - 80 - 40 - 20 ns

tCLQX tHO Output hold time 0 - 0 - 0 - ns

tHHQV tLZ HOLD high to output valid - 80 - 40 - 20 ns

tHLQZ(2) tHZ HOLD low to output High-Z - 80 - 40 - 20 ns

tW tWC Write time - 5 - 5 - 5 ms

1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
2. Characterized only, not tested in production.

DS1356 - Rev 20 page 30/48

 M95128-W M95128-R M95128-DF
DC and AC parameters

Table 21. AC characteristics (M95128-DF, device grade 6)

Test conditions specified in Table 11

VCC ≥ 1.7V VCC ≥ 2.5V VCC≥ 4.5V

Symbol Alt. Parameter Unit
Min. Max. Min. Max. Min. Max.

fC fSCK Clock frequency - 5 - 10 - 20 MHz

tSLCH tCSS1 S active setup time 60 - 30 - 15 - ns

tSHCH tCSS2 S not active setup time 60 - 30 - 15 - ns

tSHSL tCS S deselect time 90 - 40 - 20 - ns

tCHSH tCSH S active hold time 60 - 30 - 15 - ns

tCHSL - S not active hold time 60 - 30 - 15 - ns

tCH (1) tCLH Clock high time 80 - 40 - 20 - ns

tCL (1) tCLL Clock low time 80 - 40 - 20 - ns

tCLCH (2) tRC Clock rise time - 2 - 2 - 2 µs

tCHCL tFC Clock fall time - 2 - 2 - 2 µs

tDVCH tDSU Data in setup time 20 - 10 - 5 - ns

tCHDX tDH Data in hold time 20 - 10 - 10 - ns

tHHCH - Clock low hold time after HOLD not active 60 - 30 - 15 - ns

tHLCH - Clock low hold time after HOLD active 60 - 30 - 15 - ns

tCLHL - Clock low setup time before HOLD active 0 - 0 - 0 - ns

tCLHH - Clock low setup time before HOLD not active 0 - 0 - 0 - ns

tSHQZ (2) tDIS Output disable time - 80 - 40 - 20 ns

tCLQV tV Clock low to output valid - 80 - 40 - 20 ns

tCLQX tHO Output hold time 0 - 0 - 0 - ns

tHHQV tLZ HOLD high to output valid - 80 - 40 - 20 ns

tHLQZ(2) tHZ HOLD low to output High-Z - 80 - 40 - 20 ns

tW tWC Write time - 5 - 5 - 5 ms

1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
2. Characterized only, not tested in production.

DS1356 - Rev 20 page 31/48

 M95128-W M95128-R M95128-DF
DC and AC parameters

Figure 20. Serial input timing

tSHSL

tCHSL tSLCH tCH tCHSH tSHCH

C
tDVCH tCHCL tCL tCLCH

tCHDX

D MSB IN LSB IN

High impedance
Q

Figure 21. Hold timing

S
tHLCH

tCLHL tHHCH

C
tCLHH

tHLQZ tHHQV

HOLD

Figure 22. Serial output timing

S
tCH tSHSL
C

tCLQV tCLCH tCHCL tCL tSHQZ

tCLQX

tQLQH
tQHQL

ADDR
D LSB IN

DS1356 - Rev 20 page 32/48

 M95128-W M95128-R M95128-DF
Package information

10 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

10.1 SO8N package information

SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package.

Figure 23. SO8N – Outline

h x 45˚

A2 A
c
ccc
b
e

0.25 mm
D GAUGE PLANE

k
8

E1 E
1 L
A1
L1

1. Drawing is not to scale.

Table 22. SO8N – Mechanical data

millimeters inches (1)

Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.750 - - 0.0689
A1 0.100 - 0.250 0.0039 - 0.0098
A2 1.250 - - 0.0492 - -
b 0.280 - 0.480 0.0110 - 0.0189
c 0.170 - 0.230 0.0067 - 0.0091
D 4.800 4.900 5.000 0.1890 0.1929 0.1969
E 5.800 6.000 6.200 0.2283 0.2362 0.2441
E1 3.800 3.900 4.000 0.1496 0.1535 0.1575
e - 1.270 - - 0.0500 -
h 0.250 - 0.500 0.0098 - 0.0197
k 0° - 8° 0° - 8°
L 0.400 - 1.270 0.0157 - 0.0500
L1 - 1.040 - - 0.0409 -
ccc - - 0.100 - - 0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.

DS1356 - Rev 20 page 33/48

 M95128-W M95128-R M95128-DF
SO8N package information

Figure 24. SO8N - Recommended footprint

0.6 (x8)

3.9
6.7
1.27

1. Dimensions are expressed in millimeters.

DS1356 - Rev 20 page 34/48

 M95128-W M95128-R M95128-DF
TSSOP8 package information

10.2 TSSOP8 package information

TSSOP8 is an 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package.

Figure 25. TSSOP8 – Outline

8 5
c

E1 E

1 4

A1 L
A A2
CP L1

b e

1. Drawing is not to scale.

Table 23. TSSOP8 – Mechanical data

millimeters inches (1)

Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
CP - - 0.100 - - 0.0039
D 2.900 3.000 3.100 0.1142 0.1181 0.1220
e - 0.650 - - 0.0256 -
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1 4.300 4.400 4.500 0.1693 0.1732 0.1772
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
α 0° - 8° 0° - 8°

1. Values in inches are converted from mm and rounded to four decimal digits.

DS1356 - Rev 20 page 35/48

 M95128-W M95128-R M95128-DF
TSSOP8 package information

Figure 26. TSSOP8 – Recommended footprint

2.3

1.0

7.0

0.65

0.35

1. Dimensions are expressed in millimeters.

DS1356 - Rev 20 page 36/48

 M95128-W M95128-R M95128-DF
UFDFPN8 (DFN8) package information

10.3 UFDFPN8 (DFN8) package information

UFDFPN8 is an 8-lead, 2 × 3 mm, 0.55 mm thickness ultra thin profile fine pitch dual flat package.

Figure 27. UFDFPN8 - Outline

D A B
N
A
ccc C
A1
Pin #1 C
ID marking
E eee C
Seating plane A3
Side view

1 2 2x aaa C
2x aaa C
Top view

D2 Datum A
e b
1 2
L1
L3 L L3

Pin #1
ID marking E2
e/2 L1
e Terminal tip
K
L Detail “A”
Even terminal
ND-1 x e
Bottom view See Detail “A”

1. Maximum package warpage is 0.05 mm.

2. Exposed copper is not systematic and can appear partially or totally according to the cross section.
3. Drawing is not to scale.
4. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating
(not connected) in the end application.

DS1356 - Rev 20 page 37/48

 M95128-W M95128-R M95128-DF
UFDFPN8 (DFN8) package information

Table 24. UFDFPN8 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.450 0.550 0.600 0.0177 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020

b(2) 0.200 0.250 0.300 0.0079 0.0098 0.0118

D 1.900 2.000 2.100 0.0748 0.0787 0.0827

D2 1.200 - 1.600 0.0472 - 0.0630
E 2.900 3.000 3.100 0.1142 0.1181 0.1220
E2 1.200 - 1.600 0.0472 - 0.0630
e - 0.500 - 0.0197
K 0.300 - - 0.0118 - -
L 0.300 - 0.500 0.0118 - 0.0197
L1 - - 0.150 - - 0.0059
L3 0.300 - - 0.0118 - -
aaa - - 0.150 - - 0.0059
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020

eee(3) - - 0.080 - - 0.0031

1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.
3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.

Figure 28. UFDFPN8 - Recommended footprint

1.400
0.500 0.300

0.600

1.200

1.300

1. Dimensions are expressed in millimeters.

DS1356 - Rev 20 page 38/48

 M95128-W M95128-R M95128-DF
WLCSP8 (CS) package information

10.4 WLCSP8 (CS) package information

WLCSP8 is a 8 bumps, 1.289 x 1.099 mm, 0.4 mm pitch wafer level chip scale package

Figure 29. WLCSP8 - Outline

bbb Z
D e2
X Y e
F
Detail A
E e1
e3
H
aaa A
Reference (4X) G
A2
Orientation
Wafer back side Side view Bump side

Bump

A1
eee Z

b Z
Ø ccc M Z X Y
Ø ddd M Z
Detail A Seating plane
Rotated 90 °

1. Drawing is not to scale

2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3. Bump position designation per JESD 95-1, SPP-010.

DS1356 - Rev 20 page 39/48

 M95128-W M95128-R M95128-DF
WLCSP8 (CS) package information

Table 25. WLCSP8 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.540 0.580 0.0197 0.0213 0.0228

A1 - 0.190 - - 0.0075 -
A2 - 0.350 - - 0.0138 -

b(2) - 0.270 - - 0.0106 -

D - 1.289 1.309 - 0.0507 0.0515

E - 1.099 1.119 - 0.0433 0.0441
e - 0.800 - - 0.0315 -
e1 - 0.693 - - 0.0273 -
e2 - 0.400 - - 0.0157 -
e3 - 0.400 - - 0.0157 -
F - 0.203 - - 0.0080 -
G - 0.245 - - 0.0096 -
H - 0.203 - - 0.0080 -
aaa - 0.110 - - 0.0043 -
bbb - 0.110 - - 0.0043 -
ccc - 0.110 - - 0.0043 -
ddd - 0.060 - - 0.0024 -
eee - 0.060 - - 0.0024 -

1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

Figure 30. WLCSP8 - Recommended footprint

0.400

0.800

0.693

0.400

8 bumps x Ø 0.270

1. Dimensions are expressed in millimeters.

DS1356 - Rev 20 page 40/48

 M95128-W M95128-R M95128-DF
Ordering information

11 Ordering information

Table 26. Ordering information scheme

Example: M95 128 -D W MN 6 T P \K

Device type
M95 = SPI serial access EEPROM
Device function
128 = 128 Kbit (16384 x 8)
Device family
Blank = Without Identification page
D = With additional Identification page
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V

Package(1)
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (DFN8)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C
Device tested with standard test flow
Option
blank = tube packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free (ECOPACK2®)

Process(2)
/K = Manufacturing technology code

1. All packages are ECOPACK2® (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants).
2. These process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST
Sales Office for further information

Note: Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and
therefore not approved for use in production. ST is not responsible for any consequences resulting from such
use. In no event will ST be liable for the customer using any of these engineering samples in production. ST
Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

DS1356 - Rev 20 page 41/48

 M95128-W M95128-R M95128-DF

Revision history

Table 27. Document revision history

Date Revision Changes

Section 3.8: Supply voltage (VCC) and Section 5.4: Write Status Register (WRSR) updated.
Note added to Section 5.6: Write to Memory Array (WRITE).
ICC modified in Table 12: DC characteristics (M95128, device grade 3).
17-Feb-2009 11 VRES added to DC characteristics tables 12, 20, 14 and 23.
Note added to Table 36: AC characteristics (M95080-R, M95080-DR device grade 6).
Note added below Figure 20: UFDFPN8, 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline.
Small text changes.
Section 5.6.1: ECC (error correction code) and write cycling modified (applies to all devices).
TLEAD, IOL and IOH added to Table 6: Absolute maximum ratings.
12-Jan-2010 12 Note added to Table 23: DC characteristics (current and new M95080-R and M95080-DR products).
Process modified in Table 45: Ordering information scheme.
All packages are ECOPACK2 compliant.
Section 5.6.1: ECC (error correction code) and write cycling and Table 24: Available M95128x products (package,
02-Mar-2010 13
voltage range, temperature grade) updated.
03‑Jan-2012 14 Updated UFDFPN8 package data.
Datasheet revision 14 split into:
- M95128-125 datasheet for automotive products (range 3),
- M95128-W M95128-R M95128-DF (this datasheet) for standard products (range 6).
Updated:
– Cycling: 4 million cycles
06‑Aug‑2012 15
– Data retention: 200 years
– Max clock frequency: 5 [email protected] V, 10 [email protected] V, 20 [email protected] V.
Added:
– Identification page (for M95128-D devices)
– 1.7 V/5.5 V range (F suffix)
- Added “Additional Write lockable page (Identification page)” and replaced “(ECOPACK®)” with “(ECOPACK2®)” in
Features.
– Updated Table 2: Write-protected block size.
19‑Dec‑2012 16
– Updated Section 7.2: Initial delivery state.
– Replaced Figure 38 and Table 54 (UFDFPN8 package).
– Added Note (1) to Table 25: Ordering information scheme.
Replaced “ball” by “bump” in the entire document.
Updated Features and WLCSP package figure on cover page.
Updated Figure 3: WLCSP connections (top view, marking side, with bumps on the underside) and Figure 4: Block
diagram.
Removed Caution note on UV exposure in Section 1: Description.
20‑May‑2015 17
Updated Section 5.1.3: Power-up conditions, Section 5.3: Hold condition and tables in Section 6: Instructions.
Updated Table 7: Absolute maximum ratings and its footnotes.
Updated Table 15: DC characteristics (M95128-W, device grade 6).
Updated Section 10: Package information with changes in each of Sections 10.1: SO8N package information, 10.2:
TSSOP8 package information, 10.3: UFDFN8 package information and Section 10.4: WLCSP package information.

DS1356 - Rev 20 page 42/48

 M95128-W M95128-R M95128-DF

Date Revision Changes

Updated Table 25: Ordering information scheme and added Note: on Engineering samples.
Updated Disclaimer
Updated title of Table 8: Operating conditions (M95128-W, device grade 6), Table 19: AC characteristics (M95128-R,
device grade 6) and Table 20: AC characteristics (M95128-DF, device grade 6).
Updated title and footnotes of Table 15: DC characteristics (M95128-W, device grade 6) Table 16: DC
21‑Sep‑2015 18 characteristics (M95128-R, device grade 6), Table 17: DC characteristics (M95128-DF, device grade 6) and Table
18: AC characteristics (M95128-W, device grade 6).
Updated footnote 1 of Table 7: Absolute maximum ratings.
Added footnote 4 to Figure 26.
Updated Section 6.6.1: Cycling with Error Correction Code (ECC) and Section 10.4: WLCSP package information.
Updated Figure 6: SPI modes supported, Figure 8: Write Enable (WREN) sequence and Figure 9: Write Disable
(WRDI) sequence.
22‑Feb‑2017 19
Updated caption of Figure 25: TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.65 mm pitch, package
outline and of Figure 22: TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.65 mm pitch, package
mechanical data.
Added:
• Table 2. Signals vs. bump position
• Figure 24. SO8N - Recommended footprint
27‑Oct‑2020 20
• Figure 26. TSSOP8 – Recommended footprint
Updated:
• Figure 4. Block diagram

DS1356 - Rev 20 page 43/48

 M95128-W M95128-R M95128-DF
Contents

Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.4 Chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5 Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.6 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Operating features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
5.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.2 Active power and Standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3 Read Status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DS1356 - Rev 20 page 44/48

 M95128-W M95128-R M95128-DF
Contents

6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.4 Write Status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.5 Read from Memory array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.6 Write to Memory array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.6.1 Cycling with error correction code (ECC x4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.7 Read Identification page (available only in M95128-D devices) . . . . . . . . . . . . . . . . . . . . . . . 20

6.8 Write Identification page (available only in M95128-D devices) . . . . . . . . . . . . . . . . . . . . . . . 21
6.9 Read Lock status (available only in M95128-D devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.10 Lock ID (available only in M95128-D devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.2 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.3 UFDFPN8 (DFN8) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.4 WLCSP package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

DS1356 - Rev 20 page 45/48

 M95128-W M95128-R M95128-DF
List of tables

List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Signals vs. bump position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 3. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Significant bits within the address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Protection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Operating conditions (M95128-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Operating conditions (M95128-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Operating conditions (M95128-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. DC characteristics (M95128-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. DC characteristics (M95128-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. DC characteristics (M95128-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. AC characteristics (M95128-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20. AC characteristics (M95128-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. AC characteristics (M95128-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 22. SO8N – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 23. TSSOP8 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. UFDFPN8 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 25. WLCSP8 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 26. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

DS1356 - Rev 20 page 46/48

 M95128-W M95128-R M95128-DF
List of figures

List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. WLCSP connections (top view, marking side, with bumps on the underside). . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Write disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Read Status register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Write Status register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Read from Memory array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Read Identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. Write Identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. Read Lock status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21. Hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 22. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23. SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 24. SO8N - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 25. TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 26. TSSOP8 – Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27. UFDFPN8 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28. UFDFPN8 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 29. WLCSP8 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 30. WLCSP8 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DS1356 - Rev 20 page 47/48

 M95128-W M95128-R M95128-DF

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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DS1356 - Rev 20 page 48/48