TEACHING RATE CONVERSION USING HARDWARE-BASED DSP

Thad B. Welch Cameron H. G. Wright Michael G. Morrow

Dept. of Electrical Engineering Dept. of Elec. and Comp. Engineering Dept. of Elec. and Comp. Engineering
U.S. Naval Academy, MD University of Wyoming, WY University of Wisconsin - Madison, WI
[email protected] [email protected] [email protected]

ABSTRACT

To enable us to affordably teach software defined radio at

the undergraduate level, we developed a low cost system that
allows realistic hardware projects and demonstrations. This
new board connects a Texas Instruments C67x DSP starter kit
(DSK) to an Analog Devices AD9857 quadrature modulator.
This modulator is capable of operating at up to 200 million
samples per second (MS/s), with a carrier (or intermediate
frequency) of up to 80 MHz. Baseband 14-bit in-phase and
quadrature (I/Q) data are presented to the modulator, which
can be programmed to interpolate the data at rates from 4× to
252×. The AD9857 is interfaced to the DSK using an Altera
Cyclone FPGA which provides queuing of the I/Q data and
the logic for control/programming of the modulator.
This paper describes the associated hardware and software
issues and briefly describes recommended classroom use.
Index Terms— Communications engineering education,
signal processing

Fig. 1. The complete TI C6713 and AD9857 based rate con-

1. INTRODUCTION version system.

The convergence of digital communications and digital signal

processing is gaining emphasis in many engineering colleges. 2. DESCRIPTION OF THE HARDWARE
The implementation of these communication systems using
high performance digital signal processors (DSPs) and field As shown in Figure 1, this new board interconnects a Texas
programmable gate arrays (FPGAs) is nothing new. In gen- Instruments (TI) C6711 or C6713 DSP starter kit (DSK) to an
eral, these concepts and techniques can be discussed under Analog Devices (AD) quadrature modulator (AD9857).
the umbrella term of software defined radio (SDR). To under- This modulator is capable of operating at up to 200 mil-
stand a SDR, one needs to understand rate conversion. While lion samples per second (MS/s), with a resulting carrier or
the basics of the rate conversion theory have been well estab- intermediate frequency of up to 80 MHz (i.e., 40% of the sys-
lished for decades, the inclusion of these topics at the under- tem’s sample frequency). An onboard 32-bit direct digital
graduate level can be fraught with teaching dangers. If re- synthesizer (DDS) is used to generate the carrier waveform
alistic hardware projects and hardware-based demonstrations values. Baseband 14-bit in-phase and quadrature (I/Q) data
are to be included as part of a course, the cost can escalate are presented to the modulator, which can be programmed to
rapidly. With most commercially available boards costing interpolate the data at rates from 4× to 252×. The block dia-
more than $10,000 apiece, buying multiple units to support gram of the modulator is shown in Figure 2.
such a course is prohibitively expensive. To support our desire The AD9857 is interfaced to the DSK using an Altera Cy-
to teach these topics at the undergraduate level, we felt it was clone FPGA. The FPGA provides queuing of the I/Q data,
necessary to develop a low cost DSP board that would allow and the logic for control/programming of the modulator. The
us to implement the realistic hardware projects and hardware- FPGA daughtercard and the required adapter board are shown
based demonstrations previously mentioned. in Figure 3.

1­4244­0728­1/07/$20.00 ©2007 IEEE III ­ 717 ICASSP 2007

 Form Approved
Report Documentation Page OMB No. 0704-0188

Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and
maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information,
including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington
VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it
does not display a currently valid OMB control number.

1. REPORT DATE 3. DATES COVERED

2. REPORT TYPE
2007 00-00-2007 to 00-00-2007
4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER
Teaching Rate Conversion Using Hardware-Based DSP 5b. GRANT NUMBER

5c. PROGRAM ELEMENT NUMBER

6. AUTHOR(S) 5d. PROJECT NUMBER

5e. TASK NUMBER

5f. WORK UNIT NUMBER

7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATION

REPORT NUMBER
Dept. of Electrical Engineering,U.S. Naval Academy,
MD,Annapolis,MD,21402-5000
9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR’S ACRONYM(S)

11. SPONSOR/MONITOR’S REPORT

NUMBER(S)

12. DISTRIBUTION/AVAILABILITY STATEMENT

Approved for public release; distribution unlimited
13. SUPPLEMENTARY NOTES
See also ADM002013. Proceedings of the 2007 IEEE International Conference on Acoustics, Speech, and
Signal Processing (ICASSP), Held in Honolulu, Hawaii on April 15-20, 2007. Government or Federal
Rights
14. ABSTRACT

15. SUBJECT TERMS

16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF 18. NUMBER 19a. NAME OF
ABSTRACT OF PAGES RESPONSIBLE PERSON
a. REPORT b. ABSTRACT c. THIS PAGE Same as 4
unclassified unclassified unclassified Report (SAR)

Standard Form 298 (Rev. 8-98)

Prescribed by ANSI Std Z39-18
 Fig. 2. The block diagram of the AD9857 (courtesy of Analog Devices).

Fig. 3. Adapter board and FPGA daughtercard stacked on top

of a TI C6713 DSK. The HPI daughtercard in the foreground
Fig. 4. The modified winDSK6 graphical user interface.
is required to operate this system from winDSK6.

3. THE INTERFACE AND CONTROL SOFTWARE

To allow for both rapid experimentation and demonstration,

the winDSK6 program (see Figure 4) was modified to allow
for direct control of the hundreds options and register settings
that control the AD9857 EVM (evaluation module). In par-
ticular, a new button called CommDSK_RF was added to the
graphical user interface (GUI) of winDSK6. The standard re-
lease of winDSK6 does not include the CommDSK_RF but-
ton, but this special version is available upon request.
In Figure 4, notice that the cursor arrow is resting on the
CommDSK_RF button. Clicking on this button opens a win- Fig. 5. Controls for the AD9857 modulator and the TI C6713
dow similar to that shown in Figure 5. baseband data generator.

III ­ 718
 4. SYSTEM OPERATION

The AD9857 quadrature digital up-converter device has three

distinct operating modes: quadrature modulation, single-tone
generation, or interpolating DAC mode. The hardware we de-
signed is capable of operating the AD9857 in all three modes.
However, this paper focuses on the quadrature modulator mode.
To reduce the design risk and complexity associated with de-
signing a complete AD9857 board, we chose to utilize the
evaluation board supplied by Analog Devices. (One impor-
tant note for anyone attempting to reproduce this work is that
the AD9857 evaluation board will not operate correctly from
its signal headers unless a pull-up resistor is attached to “U2
pin 5” on the development board.) Fig. 7. The functional block diagram of the FPGA logic.
The AD9857 requires a data source that provides 14-bit
interleaved in-phase and quadrature (I/Q) data. Direct con-
vice has an SPI-compatible serial interface for configuration
nection to the DSK external memory interface is not practical
and programming. The FPGA implements an SPI transceiver
given the data rates desired, so an adapter board based on the
to send and read configuration data stored in the AD9857 reg-
Altera Cyclone FPGA was developed. In order to make the
isters.
FPGA daughtercard design usable for other projects, it was
The software application that was developed provides com-
designed with a generic interface exposing as many available
plete control over the AD9857 data path. This application
FPGA input/output pins as possible. This interface is not di-
is an extension of our previous work that provided a com-
rectly compatible with the connectors on the AD9857 eval-
plete quadrature modulator at carrier frequencies in the audio
uation board. A simple adapter board was designed to pro-
band [1–6]. With digital up-conversion, the carrier frequency
vide the necessary signals and connectors to interface to the
may now be as high as 80MHz. The DSP supplies baseband
AD9857 evaluation board. The block diagram of the com-
data in a number of modulation schemes with variable pulse
plete system is shown in Figure 6.
shaping features. That data is then sent to the AD9857. The
The FPGA daughtercard provides the direct control of the
AD9857 provides additional interpolation, and then modu-
AD9857. Three modulation data sources are supported: base-
lates the signal onto the desired carrier frequency.
band pulse shaped data from the DSP, ramps on the I or Q
data channels, or pseudorandom (PN) data. The functional
block diagram of the FPGA logic is shown in Figure 7. If 5. SYSTEM PERFORMANCE
the ramp or PN data source is selected, the board operates au-
tonomously without DSP data. If baseband data from the DSP With the complete system shown in Figure 1 connected to
is used, a 64-word FIFO is used to reduce the interrupt over- a host PC running winDSK6 (upgraded for commDSK_RF
head incurred in sending the data. Depending on the baseband functionality) and an external clock attached to the AD9857
modulation scheme and pulse shaping used, baseband sample EVM, proper operation can be verified by measuring the out-
rates in excess of 500kS/s can be achieved. The AD9857 de- put of the system. A typical system output as displayed on
a spectrum analyzer (SA) or vector signal analyzer (VSA) is
shown in Figure 9.
In Figure 9, a slight amount of carrier leakage is clearly
present. The central portion of the signal is the desired sig-
nal’s spectral content, with the remaining skirting effect due
to the rate conversion process. The rapid roll-off of the sig-
nal’s power near the edges of the display is due to on-board
analog filtering. Finally, the horizontal portions of the display
indicate the system’s noise floor. The constellation diagram
associated with this signal is shown in Figure 8.

6. CLASSROOM USE

Previous offerings of our DSP course have discussed rate con-

version but have reinforced student knowledge by using the
Fig. 6. Complete system block diagram. ubiquitous homework problem set and its associated Matlab

III ­ 719
 The winDSK6 and other software packages we have de-
veloped are freely available for educational, non-profit use,
and we invite user suggestions for improvement (see [7]). In-
terested parties are also invited to contact the authors via e-
mail. The HPI daughtercard is available for purchase from
Educational DSP, LLC as a fully assembled unit [8].

8. REFERENCES

[1] T. B. Welch, C. H. G. Wright, and M. G. Morrow,

“Caller ID: An opportunity to teach DSP-based demodu-
lation,” in Proceedings of the IEEE International Confer-
ence on Acoustics, Speech, and Signal Processing, vol. V,
Fig. 8. Constellation diagram for the example signal. pp. 569–572, Mar. 2005. Paper 2887.

[2] T. B. Welch, R. W. Ives, M. G. Morrow, and C. H. G.

Wright, “Using DSP hardware to teach modem design
and analysis techniques,” in Proceedings of the IEEE In-
ternational Conference on Acoustics, Speech, and Signal
Processing, vol. III, pp. 769–772, Apr. 2003.

[3] C. H. G. Wright, T. B. Welch, D. M. Etter, and M. G. Mor-

row, “Teaching hardware-based DSP: Theory to prac-
tice,” in Proceedings of the IEEE International Con-
ference on Acoustics, Speech, and Signal Processing,
vol. IV, pp. 4148–4151, May 2002. Paper 4024 (invited).

[4] M. G. Morrow, T. B. Welch, C. H. G. Wright, and G. W. P.

York, “Demonstration platform for real-time beamform-
Fig. 9. Typical spectral display. Carrier frequency: 1 MHz, ing,” in Proceedings of the IEEE International Confer-
modulation scheme: 16-QAM, raised-cosine pulse shaping ence on Acoustics, Speech, and Signal Processing, May
(roll-off factor = 0.5), and a baseband data rate of 150 kbps. 2001. Paper 1146.

[5] M. G. Morrow and T. B. Welch, “winDSK: A windows-

exercise. The extension to a real-time rate conversion system based DSP demonstration and debugging program,”
is not a trivial step. If student involvement in parameter selec- in Proceedings of the IEEE International Conference
tion and signal monitoring (for proper operation) is desired, on Acoustics, Speech, and Signal Processing, vol. 6,
significant time must be devoted to both the theory of the pp. 3510–3513, June 2000. (invited).
rate conversion process (as implemented in Figure 2) and the
[6] M. G. Morrow, T. B. Welch, and C. H. G. Wright, “An
inherent limitations associated with this, and any, real-time
introduction to hardware-based DSP using winDSK6,” in
system. This transition from a theoretical result to an actual
Proceedings of the 2001 ASEE Annual Conference, June
signal output can be very frustrating if not handled properly.
2001. Session 1320.
We prefer to handle these issues with added classroom time
devoted to the rate conversion topic. [7] M. G. Morrow, “University of Wisconsin at Madison,”
2005. http://eceserv0.ece.wisc.edu/~morrow/
7. CONCLUSIONS software/.

[8] Educational DSP (eDSP), L.L.C., “DSP resources for TI

If you wish to educate your students about the implementa- DSKs,” 2005. http://www.educationaldsp.com/.
tion of communication systems using both high performance
digital signal processors (DSPs) and field programmable gate
arrays (FPGAs) without spending tens of thousands of dollars
for an individual board, consider this approach to solving the
problem. This approach was very well received by our stu-
dents and has also reinforced RF and communication system
test and measurement skills.

III ­ 720