Cadence Tutorial 3

Contents
Cadence Tutorial 3 ........................................................................................................................................ 1
Overview ................................................................................................................................................... 2
Schematic .................................................................................................................................................. 2
Simulation ................................................................................................................................................. 2
Setup ..................................................................................................................................................... 2
Analyses ................................................................................................................................................ 3
Variables................................................................................................................................................ 3
Outputs ................................................................................................................................................. 3
Measurements ...................................................................................................................................... 3
Layout........................................................................................................................................................ 5
Opening the Layout Tool ....................................................................................................................... 5
Palette ................................................................................................................................................... 5
Short Keys ............................................................................................................................................. 6
Creating an NMOS Transistor................................................................................................................ 6
Creating a PMOS Transistor .................................................................................................................. 8
Bulk for PMOS ....................................................................................................................................... 9
Bulk for NMOS..................................................................................................................................... 11
Vias ...................................................................................................................................................... 12
Pins ...................................................................................................................................................... 12
P-Cells .................................................................................................................................................. 13
Three-Input NAND .............................................................................................................................. 13
DRC ...................................................................................................................................................... 13
Rules Document .................................................................................................................................. 14
LVS ....................................................................................................................................................... 14
180 nm 3-Input NAND............................................................................................................................. 16
Schematic ............................................................................................................................................ 16
Simulation ........................................................................................................................................... 16
Layout.................................................................................................................................................. 16
Grading Rubric ........................................................................................................................................ 16
Overview
Create a 3-input NAND gate in schematic. Simulate to optimize sizing of the width of the PMOS and
NMOS. Then layout. Use both GPDK 45 nm and GPDK 180 nm to compare.

Schematic
Create the following schematic using the 45 nm library.

Be sure to use “analogLib” parts for VDD and GND. Change the value for the widths of the PMOS to
120n*wp. Change the value for the widths of the NMOS to 120n*wn. This will allow you to parameterize
the width of the PMOS and the width of the NMOS to find the best value.

Simulation

Setup
In the model libraries, change the section to “tt” for typical. Then go to Setup → Stimuli. This is a
different way to stimulate the circuit. You want to test all combinations of A, B, and C inputs to prove
that the NAND gate functions correctly. To do this, use the following values. Recognize that this will test
all input combinations (000, 001, 010, ..., 111). In inputs, check the “enabled” box and change the
function to pulse. Then, type the following values. Click “apply” when changes between inputs.

A B C
Voltage 1 0 0 0
Voltage 2 1.1 1.1 1.1
Period 50n 100n 200n
Pulse Width 25n 50n 100n
Rise Time 100p 100p 100p
Fall Time 100p 100p 100p

Change to global sources and make VDD a DC source of 1.1 V. Press okay when finished.

Analyses
Now go to Analyses → Choose and select “tran” for 800n. This will allow us to see multiple cycles to
ensure our NAND is functioning correctly.

Variables
Go to Variables → Copy from Cellview and set wp = 1 and wn = 1 for now.

Outputs
Be sure to measure all input and output voltages. Check the box to plot. Press netlist and run.

Measurements
Your plot should pop up next. Go to Graph → Split All Strips to separate the voltages onto their own
graphs. You’ll notice that the output is not a perfect square wave. This is because we do not have the
circuit driving anything. If you double click on a line, you can change the line style from a “fine” to
“thick.” Please do this for all graphs you must submit.

Click on your output voltage. Go to Measurements → Transient Measurement. A box that looks like the
one below should open. It shows the edge and the measurements. Click “show edge browser” to know
what edge you are measuring. You can use this to measure the fall time and rise time of the output. The
fall time is defined here at the time it takes for the output to change from 80% of its initial value to 20%
of its value. The rise time is the time it takes for the output to change from 20% its final value to 80%.
This is shown in the picture below using a rise time between 10% and 90%. A well-designed NAND will
have similar fall and rise times in most situations. Notice the difference between the fall time and the
rise time.
Now we will run a parametric simulation. You only need to plot the output for this graph. Go to Tools →
Parametric Analysis and select “wp” as your variable. Sweep it from 1 to 1.5. How do the fall times and
rise times change as wp increases while wn remains at 1?

We will do the same and sweep wn. Change your variable to wn and sweep from 1 to 1.5 How do the fall
times and rise times change as wn increases while wp remains at 1?

Remember, there is a minimum width. Find the values for wp and wn that will give you the same values
for the rise time and the fall time. Change the widths of your transistors accordingly.
Layout

Opening the Layout Tool

In Library Manager, go to File → New → Cellview and change the type to “layout” for your three-input
NAND gate.

Palette
This includes your layers. You will use these to create your transistors. The major ones we will use are
listed in the table below.

Name Function
Poly Polysilicon – used for your gates
Oxide Active
Pimp P implantation – used to form your PMOS
Nimp N implantation – used to form your NMOS
Cont Contact
Metal1 Metal layer 1, there are more metals that you can use if necessary
Nwell PMOS transistors must be placed in an Nwell
PWdummy Dummy layer used by the tool to enclose your NMOS transistors
Short Keys

Key Function
R Rotate
S Stretch
M Move
C Copy
U Undo
K Can create a ruler
Shift + K Deletes all rulers
Shift + Z Zoom out
Ctrl + Z Zoom in
Shift + F Show all layers
Ctrl + F Hide all layers

Creating an NMOS Transistor

Press “k” to open the ruler tool and measure out 0.045. At 45 nm, this is the length of our transistor – it
corresponds to the polysilicon gate. Press “r” and draw a rectangle like the one below with the correct
length. Press shift + K to delete your rulers.

Now add the active area. This determines the width of the transistor. At default, it was set to 120 nm,
however if you changed it for your proper sizing, use that value. Draw a rectangle across the gate using
the oxide layer.
Add the N-implant layer across the top of your transistor. It must extend to the top and bottom edges of
the gate.

Add the PWdummy layer.

Add contacts if you are connecting the drain/source to metal.

Add metal1 layer over the contacts. You will route the metal to make these connections.
Creating a PMOS Transistor
Make a gate with length 45 nm.

Add the active area with width 120 nm (or use your value found through simulation).

Add the P-implant layer.

Add an N-well.

Add contacts for drain/source connections.

Add metal 1 layer.

Bulk for PMOS

The bulk connection is sometimes called a body contact or a tap, as it is connected to either the
substrate or the well for the transistor. You only need one bulk per well. The bulk connection for a
PMOS is the fourth terminal that is always connected to VDD. Start with a 60 nm by 60 nm contact.
The contact must be enclosed by 70 nm of an active area. Add this with an oxide layer.

Now add N-implant as overlap. It also must have a 70 nm enclosure of the active area.

Add metal 1 on top of the contact for connections and add the N-well layer barrier.
Bulk for NMOS
The bulk connection for an NMOS transistor is the fourth connection that you should always connect to
GND. Start with a 60 nm by 60 nm contact.

Surround it with 70 nm active enclosure.

Add 70 nm P-implant enclosure.

Place a PWdummy layer and metal 1 layer for contact connections.

Vias
A via is used to connect between two metal layers. To create a via, press “o” and this window will open.

Change the via definition so that it is the two layers you are connecting and place at the metal
intersection.

Pins
You do not need to place pins on your layout like you do in the schematic. If you place a pin of the
incorrect name on a net, you will get an error. Additionally, pins are terminals for your design and do not
match the number of terminals in a schematic.

Still, if you want to add pins to your layout, go to create → pin to do so. You can change the mode from
“manual” to “auto” to make it easier to fill in the boxes. Enter the name and place the pin on your
layout.
P-Cells
P-cells are basic cells used by your library that already have a layout. Press “i” to create an instance and
navigate to the “gpdk045” library. Change the length and the width of the transistor so that it matches
the lengths and widths chosen in your schematic for that transistor. You will not be able to edit
individual layers of this transistor once placed.

Three-Input NAND
Now create the entire layout for your three input NAND. You do not have to make the smallest layout
possible, but please take care to try to make it condense. I recommend starting with a hand layout of
the general design you are going for and then working on getting the proper lengths and widths for your
transistors. From there, add metal connections.

The image below shows a generic layout for a two-input NAND. Think about what adjustments you need
to make to create a three-input NAND.

DRC
To check that you are meeting the design rules, first save your design. Then go to Verify → DRC and
press “ok”. To pass DRC, you should check your log window and see “total errors found: 0”. All your
designs for this class must have a clean DRC for full credit.
Rules Document
There is a folder titled “GPDK045_Docs” on your desktop. Inside it, there is a file titled
“gpdk045_drc.pdf.” Use this file to meet the design rules for this technology.

You can scroll to a set of rules for a specific layer and there will be a table. The table lists the rule names,
the description of the rule, and the minimum value you must meet. When you get a DRC error, it will list
the names of the rules you are violating, so you can refer to this document to better understand your
violations. Additionally, each rule in the table has a picture below the table that shows how the distance
is referred. The active table is shown below as an example.

Learn how to use this document as it will help you understand layout more clearly and be faster at fixing
DRC errors.

LVS
Now we want to compare your schematic against your layout to make sure that they match. The first
step to do this is to extract your layout. Go to Verify → Extract to do so. Then, go to Verify → LVS and fill
in the boxes to compare your schematic and extracted views. The picture below shows this.
Press run to run the LVS tool. A box showing the results should pop up like the one shown. If your layout
is correct, the netlists will match.

If your netlists do not match, evaluate your layout to see what could be different. I recommend
systematically checking your schematic against your layout by looking at the connections for the drain,
gate, and source for each transistor. If multiple drains are connected, make sure you have the right
amount of connections.

Furthermore, go to Verify → LVS and click the “output” button. This is your si.out file. It lists the number
of PMOS and NMOS transistors, nets, and terminals in both the schematic and layout. The number of
terminals do not need to match. Use this to figure out if your layout how too many or too few nets. You
may be forgetting to connect two nets together.

Finally, open the extracted view of your layout and go to Verify → LVS and click on the “error display”
button. This may give you some idea of what is not matching.

If LVS will not run at all, follow these steps. Go back to your schematic and press check and save. Then,
return to your layout, save, and run DRC and the extraction once again. Repopulate the boxes in the LVS
window. Check that the rules library is correct and that the correspondence file is not checked.
180 nm 3-Input NAND

Schematic
Create the schematic below using GPDK 180 nm. Change the width of the PMOS to 2u*wp and the width
of the NMOS to 2u*wn.

Simulation
Run the same simulations as previously but remember that VDD for 180 nm process is 1.8 V. Find the
optimum values for wp and wn using parametric analysis.

Layout
You do not have to layout the three-input NAND in 180 nm. However, please consider how the size of
the design would change given your lengths and widths.

Grading Rubric
100 points total
Submit a report on canvas including the following screenshots and answering the following questions:
1. Screenshot of your transient plot for a NAND with a PMOS-width to NMOS-width ratio of 1 for
the 45 nm process. (10 points)
2. What is the fall time and the rise time of the NAND with a PMOS-width to NMOS-width ratio of
1 for the 45 nm process? What is the optimum PMOS-width to NMOS-width ratio, based on your
parametric simulation for the 45 nm process? Wp = ? and Wn = ? Include a screenshot showing
your rise and fall times for these widths. (10 points)
3. Screenshot of your transient plot for a NAND with a PMOS-width to NMOS-width ratio of 1 for
the 180 nm process. (10 points)
4. What is the fall time and the rise time of the NAND with a PMOS-width to NMOS-width ratio of
1 for the 180 nm process? What is the optimum PMOS-width to NMOS-width ratio, based on
your parametric simulation for the 180 nm process? Wp = ? and Wn = ? Include a screenshot
showing your rise and fall times for these widths. (10 points)
5. How are the rise times and fall times different between 45 nm and 180 nm processes? Why do
you think this is so? How is the sizing different? Why do you think this is so? (10 points)
6. Screenshot of your 45 nm three-input NAND layout. Use rulers to show that you have the
correct lengths and widths for your transistors. (10 points)
7. Based on the widths and lengths you found for a well-designed NAND in 180 nm and 45 nm
processes, describe how you think the area of your NAND would change. Give a ratio of what
you would expect for the area for a 180 nm process to the area for a 45 nm process. (10 points)
8. Screenshot showing your DRC response. Be sure to include your Gatorlink in the log window for
full credit. You should have zero errors, however if you are unable to do so, please upload this
anyway. (10 points)
9. Screenshot showing the result of the LVS check. Be sure that your Gatorlink is included in the
picture. (Either from your log window or the box that pops up is fine.) For full credit, your
netlists should match. (10 points)
10. Include the full text for your output file from LVS. (10 points)