Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

Semiconductor
Memories
December 20, 2002

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 Chapter Overview

 Memory Classification
 Memory Architectures
 The Memory Core
 Periphery
 Reliability
 Case Studies

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 3

No New Major Memory Technology in last 45+ Years

 SRAM, DRAM, EPROM all 35 year old technologies

1st Shipment Technology

1969 SRAM
1970 DRAM
1971 Floating Gate NVM
1989 ETOX Flash
1995 NAND Flash Derivatives
1997 MLC ETox

 BUT next 10 years will be different since Moore’s law (simple scaling) is
ending
 Technology teams will more resource to pursue More than Moore
improvements

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 Source: https://computationstructures.org/lectures/caches/caches.html

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Semiconductor Memory Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random EPROM Mask-Programmed

Access Access
E2PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
CAM

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 Memory Architecture: Decoders
M bits M bits

S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage

Decoder
Word 2 A1 Word 2
cell cell
N
words SN 2
A K2 1
2
Word N 2 2 Word N 2 2
SN 2 1
Word N 2 1 Word N 2 1
K 5 log2N

Input-Output Input-Output
(M bits) (M bits)

Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals:
N words == N select signals
K = log2N

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 Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing to
rail-to-rail amplitude

Selects appropriate
word

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© Digital Integrated Circuits2nd Memories
Read-Write Memories (RAM)
 STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential

 DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

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 6-transistor CMOS SRAM Cell

WL

V DD
M2 M4
Q
M5 Q M6

M1 M3

BL BL

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 bitline and bitline # and pre-charge circuit
Pre charge Pre charge Pre charge Pre charge
enable V enable enable enable
VDD DD VDD VDD VDD

Need 2 WL Address
Word line decoder
and Drivers
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 Column decodes, Write circuit, Sense Amp with buffer
Pre charge Pre charge Pre charge Pre charge
VDD enable VDD V enable VDD enable enable
DD VDD

Need 2 WL Address
Word line decoder
and Drivers
Need 2 column
address
Column decoder
Selected Bit line / + SA
bitline # Data
Write -
Data enable Read enable

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 CMOS SRAM Analysis (Read)
WL

V DD
BL M4
BL
Q= 0
Q= 1 M6
M5

V DD M1 V DD V DD

Cbit Cbit

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 CMOS SRAM Analysis (Read)
1.2
1
Voltage Rise (V)

0.8
0.6
0.4
0.2
Voltage rise [V]
0
0 0.5 1 1.2 1.5 2 2.5 3
Cell Ratio (CR)

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 CMOS SRAM Analysis (Write)
WL
V DD
M4

Q= 0 M6
M5 Q= 1

M1
V DD
BL = 1 BL = 0

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 CMOS SRAM Analysis (Write)

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6T-SRAM — Layout

VDD
M2 M4

Q Q
M1 M3

GND
M5 M6 WL

BL BL

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 SRAM Layout

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Type 4: Industry Standard “Wide” SRAM Cell

Identify Access transistors and 2 inverters

Array specific Design Rules (restricted access)
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SRAM Cell

http://ctho.org/pics/45nm_SRAM_Cell_labeled.jpg

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 SRAM Layout

Make sure you can identify

6T unit cell

• PFETs, NFETs,
• BL, BL#, VSS, Ground nodes,
• Feedback connections

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 TSMC 28nm SRAM

Note 1D diffusion and gates

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 TSMC 28nm SRAM

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would n-well mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would n-well mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would P-well mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would P-well mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would Gate mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would Gate mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would Gate mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would Gate mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would n+ S / D mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would n+ S/ D mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would Contact mask look like to fabricate?

Note 1D diffusion and gates

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 TSMC 28nm SRAM
What would Contact mask look like to fabricate?

Note 1D diffusion and gates

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 Resistance-load SRAM Cell
WL
V DD
RL RL

Q Q
M3 M4

BL M1 M2 BL

Static power dissipation -- Want R L large

Bit lines precharged to V DD to address t p problem

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 Periphery

 Decoders
 Sense Amplifiers

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 Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion

(N)AND Decoder
__ _ _ _ _ __ _ _
_

NOR Decoder

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 Hierarchical Decoders
Multi-stage implementation improves performance
•••

WL 1

WL 0

A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3

•••
NAND decoder using
2-input pre-decoders
A1 A0 A0 A1 A3 A2 A2 A3

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 Dynamic Decoders
Precharge devices GND GND VDD

WL 3
VDD
WL3

WL 2
WL2 VDD

WL1
WL 1
V DD
WL0
WL 0

VDD f A0 A0 A1 A1
A0 A0 A1 A1 f

2-input NOR decoder 2-input NAND decoder

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Sense Amplifiers
make D V as small
C  DV as possible
tp = ----------------
Iav

large small

Idea: Use Sense Amplifer

small
transition s.a.

input output

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 Differential Sense Amplifier
V DD

M3 M4
y Out

bit M1 M2 bit

SE M5

Directly applicable to
SRAMs

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 Differential Sensing ― SRAM
V DD V DD
PC

BL BL V DD V DD
EQ
y M3 M4 2y

WL i
x M1 M2 2x x 2x

SE M5 SE

SE
SRAM cell i

V DD
Diff.
x Sense 2x Output
Amp y

SE
Output
(a) SRAM sensing scheme (b) two stage differential amplifier

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 Latch-Based Sense Amplifier (DRAM)
EQ
BL BL
VDD

SE

SE

Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.

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 Charge-Redistribution Amplifier
V ref

VL VS
M1

C small
M2 M3 C large

Transient Response

Concept

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 Charge-Redistribution Amplifier―
EPROM V DD

SE M4 Load
Out

Cout Cascode
V casc M3 device

Ccol
Column
WLC M2 decoder

BL
M1 CBL EPROM
WL array

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 Alpha-particles (or Neutrons)
a -particle
WL V DD
BL
SiO 2
n1 1 2
1 2
2
1 2
1 2
1 2
1

1 Particle ~ 1 Million Carriers

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Yield

Yield curves at different stages of process maturity

(from [Veendrick92])

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 Redundancy
Row
Redundant Address
rows
Fuse
:
Bank
Redundant
columns
Memory
Array

Row Decoder
Column Decoder Column
Address

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 Error-Correcting Codes
Example: Hamming Codes

e.g. B3 Wrong
with
1

1 =3

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Redundancy and Error Correction

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 Sources of Power Dissipation in
Memories
V DD

CHIP I DD 5 S C iD V if1S I DCP

nC DE V INT f m

selected mi act
C PT V INT f

I DCP
n

ROW non-selected m(n 2 1)i hld

DEC ARRAY

mC DE V INT f
PERIPHERY
COLUMN DEC

V SS

© Digital Integrated Circuits2nd From [Itoh00] Memories

 Data Retention in SRAM
1.30u

1.10u
0.13 m m CMOS
900n
Ileakage

700n

500n Factor 7

(A)300n 0.18 m m CMOS

100n

0.00 .600 1.20 1.80

VDD

SRAM leakage increases with technology scaling

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 Suppressing Leakage in SRAM
V DD
low-threshold transistor V DD V DDL
sleep
V DD,int sleep
V DD,int

SRAM SRAM SRAM

cell cell cell SRAM SRAM SRAM
cell cell cell

V SS,int
sleep

Inserting Extra Resistance Reducing the supply voltage

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 Static CAM Memory Cell
Bit Bit Bit Bit
Word Bit Bit
M8 M9
M4 M5
CAM ••• CAM
M6 M7

Word ••• ••• Word S S

int
CAM ••• CAM M3 M2
Match
M1

Wired-NOR Match Line

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 CAM in Cache Memory
Address Decoder

Hit Logic
CAM SRAM
ARRAY ARRAY

Input Drivers Sense Amps / Input Drivers

Address Tag Hit R/W Data

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 DRAM and NAND Flash

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 3-Transistor DRAM Cell
BL 1 BL 2

WWL

RWL WWL

M3 RWL

M1 X X V DD 2 V T
M2
V DD
CS BL 1

BL 2 V DD 2 V T DV

No constraints on device ratios

Reads are non-destructive
Value stored at node X when writing a “1” = V WWL-VTn

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3T-DRAM — Layout
BL2 BL1 GND

RWL
M3

M2

WWL
M1

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 1-Transistor DRAM Cell

Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
DV = VBL – V PRE = V BIT – V PRE ------------
C S + CBL

Voltage swing is small; typically around 250 mV.

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 Sense Amp Operation

V BL V(1)

V PRE
D V(1)

V(0)
Sense amp activated t
Word line activated

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DRAM Cell Observations
The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
 Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
 When writing a “1” into a DRAM cell, a threshold voltage is
lost. This charge loss can be circumvented by bootstrapping
the word lines to a higher value than VDD

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 1-T DRAM Cell
Capacitor

M 1 word
line
Metal word line
SiO2
Poly
n+ n+ Field Oxide Diffused
bit line
Inversion layer
Poly
induced by Polysilicon
Polysilicon
plate bias gate plate

Cross-section Layout

Uses Polysilicon-Diffusion Capacitance

Expensive in Area

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 Advanced 1T DRAM Cells
Word line
Cell plate Capacitor dielectric layer
Insulating Layer

Cell Plate Si

Capacitor Insulator Transfer gate Isolation

Refilling Poly
Storage electrode

Storage Node Poly

Si Substrate
2nd Field Oxide

Trench Cell Stacked-capacitor Cell

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© Digital Integrated Circuits2nd Memories
© Digital Integrated Circuits2nd Memories
NAND Flash Non-Volatile Flash Cards

Compact Flash SmartMedia

Memory Stick

MultiMedia and Secure

Digital Cards

Memory cards various standards:

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 Non-Volatile Memories
The Floating-gate transistor (FAMOS)

Floating gate Gate

D
Source Drain

tox G

tox
S
n+ p n+_
Substrate

Device cross-section Schematic symbol

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 Floating-Gate Transistor Programming

20 V 0V 5V

10 V 5V 20 V 0V 5V
2 5V 2 2.5 V

S D S D S D

Avalanche injection Removing programming Programming results in

voltage leaves charge trapped higher V T .

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 A “Programmable-Threshold” Transistor

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 Basic Operations in a NOR Flash Memory―
Erase

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 Basic Operations in a NOR Flash Memory―
Write

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 Basic Operations in a NOR Flash Memory―
Read

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 DRAM vs. NAND flash

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 NAND Flash Programming
 Charge on floating gate determines Vt
 Logic 1: negative Vt
 Logic 0: positive Vt
 Cells erased to 1 by applying a high body voltage so
that electrons tunnel off floating gate into substrate
 Programmed to 0 by applying high gate voltage

20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 78
 NAND Flash
 High density, low cost / bit
– Programmed one page
at a time
– Erased one block at a
time
 Example:
– 4096-bit pages
– 16 pages / 8 KB block
– Many blocks / memory

20: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 79
 NAND FLASH cell

Diffusion (a)
Gate
Y-pitch 1 bit

x-pitch
(b)

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 FLASH NAND Bit
Diffusion Scaling
Diffusio
Y-pitch Gate nGate
Y-
pit
ch
x-pitch x-pitch

Control gate
Floating gate
S D STI

Y-pitch x-pitch

1 bit : Poly-gate on diffusion…hard to beat

© Digital Integrated Circuits2nd Memories
 Chipworks 90nm NAND:
Cross section along “a”
Diffusion
Gate

Y-pitch 1 bit

x-pitch

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 Planar 2D NAND
Cross Section along “b”
Diffusion
Gate
Y-pitch 1 bit

x-pitch

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 Read-Only Memory Cells
BL BL BL
VDD
WL
WL WL
1

BL BL BL

WL WL
WL
0
GND

Diode ROM MOS ROM 1 MOS ROM 2

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 MOS OR ROM
BL[0] BL[1] BL[2] BL[3]

WL[0]
V DD
WL[1]

WL[2]
V DD

WL[3]

V bias

Pull-down loads

© Digital Integrated Circuits2nd Memories

 MOS NOR ROM
V DD
Pull-up devices

WL[0]

GND
WL [1]

WL [2]

GND
WL [3]

BL [0] BL [1] BL [2] BL [3]

© Digital Integrated Circuits2nd Memories

MOS NOR ROM Layout
Cell (9.5l x 7l)

Programmming using the

Active Layer Only

Polysilicon
Metal1

Diffusion

Metal1 on Diffusion

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MOS NOR ROM Layout
Cell (11l x 7l)

Programmming using
the Contact Layer Only

Polysilicon
Metal1

Diffusion

Metal1 on Diffusion

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 MOS NAND ROM
V DD
Pull-up devices

BL [0] BL [1] BL [2] BL [3]

WL [0]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row

© Digital Integrated Circuits2nd Memories

 MOS NAND ROM Layout
Cell (8l x 7l)

Programmming using
the Metal-1 Layer Only

No contact to VDD or GND necessary;

drastically reduced cell size
Loss in performance compared to NOR ROM

Polysilicon

Diffusion

Metal1 on Diffusion

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 NAND ROM Layout
Cell (5l x 6l)

Programmming using
Implants Only

Polysilicon

Threshold-altering
implant
Metal1 on Diffusion

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 Equivalent Transient Model for MOS NOR ROM
Model for NOR ROM V DD

BL
rword
WL Cbit

cword

 Word line parasitics

 Wire capacitance and gate capacitance
 Wire resistance (polysilicon)
 Bit line parasitics
 Resistance not dominant (metal)
 Drain and Gate-Drain capacitance

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 Equivalent Transient Model for MOS NAND ROM

V DD
Model for NAND ROM
BL

CL
r bit

cbit
r word
WL

cword

 Word line parasitics

 Similar to NOR ROM
 Bit line parasitics
 Resistance of cascaded transistors dominates
 Drain/Source and complete gate capacitance

© Digital Integrated Circuits2nd Memories