ESAOTE S.p.A.

November 2005

Rev.B

7350
SERVICE MANUAL

8310063000
Introduction

This manual describes for the Service technicians the 7350 system functions
and the block diagram of the boards that implements these functions.

The service manual is available in English only.

The manual is addressed to all the Service centres directly authorised by

ESAOTE. All the operations described in this manual are not critical from a
safety point of view.

Do not attempt to service 7350 unless this service manual has been consulted
and understood.

The enter and context menu keys are respectively indicated as ENTER and
UNDO keys in this manual.

The RGB monitor is not considered to be a field serviceable item, therefore

the manual doesn’t include its block and electric diagrams.

ii
Sections Overview
This Service Manual is composed of the following sections:

• Section 1: 7350 Service Characteristics

• Section 2: Disassembling/Assembling
• Section 3: 7350 Block Diagram
• Section 4: Parts Lists
• Section 5: Configurations and Calibrations
• Section 6: Maintenance Procedures
• Section 7: Troubleshooting
• Section 8: Check Lists
• Section 9: Boards Electric Diagrams

In this manual a WARNING pertains to possible injury to the operator. A

CAUTION describes the precautions which are necessary to protect the
equipment. Be sure that you understand and observe each of the
cautions and warnings.

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iv
Table of Contents
Section 1

1- Service Characteristics ..........................................................................................................1

Identifying the Boards......................................................................................................................1
Configuration Screen .......................................................................................................................1
General .........................................................................................................................................2
Boards ..........................................................................................................................................2
Firmware ......................................................................................................................................3
Demo Licenses.............................................................................................................................4
Machine Self-test .............................................................................................................................4
Configuration Conflicts....................................................................................................................5
Updating the Device.........................................................................................................................5
2- Equipment ..............................................................................................................................7
Disassembling Equipment ...............................................................................................................7
Service Procedures...........................................................................................................................7
USB Pen Drive and Re-writable CD................................................................................................8
3- Precautions .............................................................................................................................9

Section 2

1- How to remove the 7350 covers ............................................................................................1

Right and Left covers.......................................................................................................................2
Tools ............................................................................................................................................2
Removal procedure ......................................................................................................................2
Assembly procedure.....................................................................................................................2
Right and Left bumpers....................................................................................................................2
Tools ............................................................................................................................................2
Removal procedure ......................................................................................................................2
Assembly procedure.....................................................................................................................2
Rear cover ........................................................................................................................................3
Tools ............................................................................................................................................3
Removal procedure ......................................................................................................................3
Assembly procedure.....................................................................................................................3
Spare code ....................................................................................................................................3
Rear bumper.....................................................................................................................................4
Tools ............................................................................................................................................4
Removal procedure ......................................................................................................................4
Assembly procedure.....................................................................................................................4
Spare code ....................................................................................................................................4
Upper Metallic Covers .....................................................................................................................4
Tools ............................................................................................................................................4
Removal procedure ......................................................................................................................4
Assembly procedure.....................................................................................................................4
Upper Metallic Small Cover ............................................................................................................5
Tools ............................................................................................................................................5
Removal procedure ......................................................................................................................5
Assembly procedure.....................................................................................................................5

v
Upper Plastic Cover .........................................................................................................................5
Tools ............................................................................................................................................5
Removal procedure ......................................................................................................................5
Assembly procedure.....................................................................................................................6
Spare part .....................................................................................................................................6
Front cover .......................................................................................................................................6
Tools ............................................................................................................................................6
Removal procedure ......................................................................................................................6
Assembly procedure.....................................................................................................................7
Front bumper....................................................................................................................................7
Tools ............................................................................................................................................7
Removal procedure ......................................................................................................................7
Assembly procedure.....................................................................................................................8
Posterior Wheel Cover .....................................................................................................................8
Tools ............................................................................................................................................8
Removal procedure ......................................................................................................................8
Assembly procedure.....................................................................................................................8
Posterior Wheel................................................................................................................................8
Tools ............................................................................................................................................8
Removal procedure ......................................................................................................................9
Assembly procedure.....................................................................................................................9
Anterior Wheel.................................................................................................................................9
Tools ............................................................................................................................................9
Removal procedure ......................................................................................................................9
Assembly procedure...................................................................................................................10
Front Lifting Handles.....................................................................................................................10
Tools ..........................................................................................................................................10
Removal procedure ....................................................................................................................10
Assembly procedure...................................................................................................................11
Rear Lifting Handle .......................................................................................................................11
Tools ..........................................................................................................................................11
Removal procedure ....................................................................................................................11
Assembly procedure...................................................................................................................11
Encoder and Function Buttons.......................................................................................................12
Tools ..........................................................................................................................................12
Removal procedure ....................................................................................................................12
Assembly procedure...................................................................................................................13
Front Handle ..................................................................................................................................13
Tools ..........................................................................................................................................13
Removal procedure ....................................................................................................................13
Assembly procedure...................................................................................................................13
Gel Holder......................................................................................................................................13
Tools ..........................................................................................................................................13
Removal procedure ....................................................................................................................13
Assembly procedure...................................................................................................................14
Probe Holder ..................................................................................................................................14
Tools ..........................................................................................................................................14
Removal procedure ....................................................................................................................14
Assembly procedure...................................................................................................................14
Cable Hook ....................................................................................................................................14
Tools ..........................................................................................................................................14

vi
 Removal procedure ....................................................................................................................14
Assembly procedure...................................................................................................................14
ECG Cable Holder .........................................................................................................................14
Tools ..........................................................................................................................................14
Removal procedure ....................................................................................................................15
Assembly procedure...................................................................................................................15
Left Probe Support .........................................................................................................................15
Tools ..........................................................................................................................................15
Removal procedure ....................................................................................................................15
Assembly procedure...................................................................................................................15
Spare code ..................................................................................................................................15
Right Probe Support.......................................................................................................................15
Tools ..........................................................................................................................................15
Removal procedure ....................................................................................................................15
Assembly procedure...................................................................................................................15
Keyboard Group.............................................................................................................................16
Tools ..........................................................................................................................................16
Removal procedure ....................................................................................................................16
Assembly procedure...................................................................................................................16
Tools ..........................................................................................................................................17
Removal procedure ....................................................................................................................17
Assembly procedure...................................................................................................................17
Softkey Rear Cover........................................................................................................................18
Tools ..........................................................................................................................................18
Removal procedure ....................................................................................................................18
Assembly procedure...................................................................................................................19
Softkey Upper Cover .....................................................................................................................19
Tools ..........................................................................................................................................19
Removal procedure ....................................................................................................................19
Assembly procedure...................................................................................................................20
2- How to remove/reassemble the 7350 boards and other subassemblies ...........................21
Boards position ..............................................................................................................................22
Right Chassis boards......................................................................................................................22
Tools ..........................................................................................................................................22
Removal procedure ....................................................................................................................22
Assembly procedure...................................................................................................................23
Input board .....................................................................................................................................23
Tools ..........................................................................................................................................23
Removal procedure ....................................................................................................................23
Assembly procedure...................................................................................................................24
SPS board.......................................................................................................................................24
Tools ..........................................................................................................................................24
Removal procedure ....................................................................................................................24
Assembly procedure...................................................................................................................25
SPS fan...........................................................................................................................................25
Tools ..........................................................................................................................................25
Removal procedure ....................................................................................................................26
Assembly procedure...................................................................................................................26
Boards fan ......................................................................................................................................26
Tools ..........................................................................................................................................26
Removal procedure ....................................................................................................................26

vii
 Assembly procedure...................................................................................................................27
Left Chassis Boards .......................................................................................................................27
Printer ECG board..........................................................................................................................27
Tools ..........................................................................................................................................27
Removal procedure ....................................................................................................................27
Assembly procedure...................................................................................................................27
Connectors board ...........................................................................................................................28
Tools ..........................................................................................................................................28
Removal procedure ....................................................................................................................28
Assembly procedure...................................................................................................................28
Combo Drive..................................................................................................................................28
Tools ..........................................................................................................................................28
Removal procedure ....................................................................................................................28
Assembly procedure...................................................................................................................29
PC Chassis .....................................................................................................................................29
Tools ..........................................................................................................................................29
Removal procedure ....................................................................................................................29
Assembly procedure...................................................................................................................30
PC Assembly board........................................................................................................................30
Tools ..........................................................................................................................................30
Removal procedure ....................................................................................................................30
Assembly procedure...................................................................................................................30
Programmed Hard Disk .................................................................................................................31
Tools ..........................................................................................................................................31
Removal procedure ....................................................................................................................31
Assembly procedure...................................................................................................................31
PC Fan............................................................................................................................................31
Tools ..........................................................................................................................................31
Removal procedure ....................................................................................................................31
Assembly procedure...................................................................................................................32
Trackball ........................................................................................................................................33
Tools ..........................................................................................................................................33
Removal procedure ....................................................................................................................33
Assembly procedure...................................................................................................................33
Key Switch board and Key Switch Membranes and Supports ......................................................34
Tools ..........................................................................................................................................34
Removal procedure ....................................................................................................................34
Assembly procedure...................................................................................................................34
Key TGC board and Shut Down Membrane..................................................................................35
Tools ..........................................................................................................................................35
Removal procedure ....................................................................................................................35
Assembly procedure...................................................................................................................35
PC Keyboard ..................................................................................................................................35
Tools ..........................................................................................................................................35
Removal procedure ....................................................................................................................35
Assembly procedure...................................................................................................................35
Keyboard Cover .............................................................................................................................36
Tools ..........................................................................................................................................36
Removal procedure ....................................................................................................................36
Assembly procedure...................................................................................................................36
Spare Part ...................................................................................................................................36

viii
 Loudspeaker ...................................................................................................................................37
Tools ..........................................................................................................................................37
Removal procedure ....................................................................................................................37
Assembly procedure...................................................................................................................38
Softkey Group ................................................................................................................................39
Tools ..........................................................................................................................................39
Removal procedure ....................................................................................................................39
Assembly procedure...................................................................................................................39
Spare Part ...................................................................................................................................40
Appendix A -Parts Accessing Times ..............................................................................................41
Accessing Times to the Chassis section.........................................................................................41
Covers ........................................................................................................................................41
Boards ........................................................................................................................................42
Other subassemblies...................................................................................................................42
Accessing Times to the Keyboard section .....................................................................................43
Covers ........................................................................................................................................43
Boards ........................................................................................................................................43
Other subassemblies...................................................................................................................43
Accessing Times to the Softkey section ........................................................................................44
Covers ........................................................................................................................................44
Boards ........................................................................................................................................44
Other subassemblies...................................................................................................................44

Section 3

1- 7350 Block Diagram...............................................................................................................1

TRX boards ......................................................................................................................................7
TRXCW board .................................................................................................................................9
Control board .................................................................................................................................11
Doppler board ................................................................................................................................13
MAINS POWER, SPS and SPR boards ........................................................................................21
KEY TGC, KEY SWITCH and SOFT KEY boards .....................................................................22

Section 4

1- Traceability.............................................................................................................................1
2- Parts list ..................................................................................................................................3
7350 Code 9707350000 100-230V 50/60 Hz ..............................................................................3
7350 Covers and Membranes...........................................................................................................4
Chassis Section ............................................................................................................................4
Keyboard Section.........................................................................................................................5
Softkey Section ............................................................................................................................5
Spare Parts List ................................................................................................................................6
Chassis section .............................................................................................................................6
Keyboard section..........................................................................................................................7
Softkey section.............................................................................................................................7
3- Hard Disk Replacement ........................................................................................................9
Procedure .........................................................................................................................................9
4- Main Power Cables ..............................................................................................................11

ix
Section 5

1- Service Menu ..........................................................................................................................1

Settings Option.................................................................................................................................1
Language Settings Folder.............................................................................................................2
Licenses Folder ............................................................................................................................3
Save and Load Configuration ..........................................................................................................3
Upgrading the 7350..........................................................................................................................4
Firmware Upgrade .......................................................................................................................4
Windows Upgrade........................................................................................................................5
Processors Re-synchronization ....................................................................................................5
2- Hard Disk Configuration Menu ...........................................................................................7
Properties .........................................................................................................................................7
Network Configuration ....................................................................................................................7
IP Address Configuration.................................................................................................................9
Export Log Files to USB................................................................................................................10
Recover Archive ............................................................................................................................10
Exams not Archived.......................................................................................................................10
Hard Disk Menu in Archive Review..............................................................................................10
3- PC Printer Configuration Menu and PC Printer Installation.........................................13
Operations ......................................................................................................................................13
Configuration .................................................................................................................................14
Print to PC printer now ..................................................................................................................14
PC Printer Installation....................................................................................................................14
Installation of a PC Printer with pre-installed driver .................................................................15
Installation of a PC Printer.........................................................................................................16
Installation of a Network PC Printer..........................................................................................17
4- Mitsubishi CP750E - Print Size Settings............................................................................21
Procedure .......................................................................................................................................21
5- Sony UP-21 MD - Print Size Settings .................................................................................25
Procedure .......................................................................................................................................25
6- Mitsubishi CP900E - Print Size Settings............................................................................27
Procedure .......................................................................................................................................27
7- AG MD835 - VTR Settings..................................................................................................29
Procedure .......................................................................................................................................29
Play Back Quality and Frame Position ..........................................................................................30
VTR Soft Keys...........................................................................................................................30
8- MD3000 - VTR Settings.......................................................................................................33
Procedure .......................................................................................................................................33
Play Back Quality and Frame Position ..........................................................................................35
VTR Soft Keys...........................................................................................................................35
9- Measure Configuration .......................................................................................................37
Measure Configuration ..................................................................................................................37
Appendix A -Cables Assembly........................................................................................................39
VTR Cables Set REF 9102909000 ............................................................................................39
B/W Printer Cables Set REF 9102910000..................................................................................39
RGB Printer Cables Set REF 9102911000 .................................................................................39

x
Section 6

1- Maintenance Procedures .......................................................................................................1

Trackball ..........................................................................................................................................1
Tools ............................................................................................................................................1
Removal procedure ......................................................................................................................1
PC Assembly Battery Cell ...............................................................................................................2
Procedure .....................................................................................................................................2
Tools ............................................................................................................................................3
Procedure .....................................................................................................................................3
2- Safety Test...............................................................................................................................5
Definitions....................................................................................................................................5
7350 safety test - Operating Procedures ..........................................................................................7
Tools ............................................................................................................................................7
Measurement of the Impedance of Protective Earth connection .................................................8
Measurement of Earth leakage current ........................................................................................8
Measurement the Enclosure Leakage Current .............................................................................8
Measurement the Patient Leakage Current (ECG cable) .............................................................9
Measurement the Patient Auxiliary Current ................................................................................9
Probe safety tests............................................................................................................................10

Section 7

1- Error messages .......................................................................................................................1

Communication error with the CONTROL BOARD (TGC) and Communication error with the
CONTROL BOARD........................................................................................................................1
Suggestion....................................................................................................................................1
2- Hardware error messages .....................................................................................................3
3- Archiving troubleshooting.....................................................................................................5
Hard Disk Crossed Icon ...................................................................................................................5
Suggestion....................................................................................................................................5
Hard Disk Grey Icon ........................................................................................................................5
Suggestion....................................................................................................................................5
CD Burner and USB Pen Drive Crossed Icons................................................................................6
Suggestion....................................................................................................................................6
4- Shut Down Log File................................................................................................................7
Procedure .........................................................................................................................................7

Section 8

1- Check List ...............................................................................................................................1

Technical Check List .......................................................................................................................1
Maintenance Check List...................................................................................................................2

section 9

1- Schematic Diagrams ..............................................................................................................1

Section 1...........................................................................................................................................v

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7 3 5 0 – S E R V I C E M A N U A L
Chapter

1 - Service
Characteristics
The aim of this introductory chapter is to illustrate some of the characteristics of
the 7350 of fundamental importance to the technical staff, in particular, where to
find the equipment status and how to keep it up to date.

Identifying the Boards

Most boards of the 7350 are identified:

• by its Reference (950..) and its description, which is always indicated

on the labels bar.
• by the Serial Number (SN), indicated on the labels bar.

Board Board Serial

Reference Number

• by the Configuration Index (CI), indicated by two decimal figures on

the labels bar. The Configuration Index represents the HW level of
the board. The Configuration Index is loaded in specific components
mounted on each board.
• when applicable, by its Firmware (FW) level, displayed in the System
Configuration screen, Firmware Option (see below).
The PC Assembly, Connectors, Printer ECG, Key TGC and Key Switch boards
are not equipped with flap thus this information is on labels affixed on the printed
circuit.

Configuration Screen
From the keyboard you can display the Configuration Screen. To do this, press the
key and select SYSTEM CONFIGURATION option. The unit will show:

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The system configuration screen is organized in four folders:

• General
• Boards
• Firmware
• Demo licenses
To select a folder, use the trackball to position the cursor over the correct tab and
press ENTER.

General
The screen displays:

Serial number It is the unit serial number

System Software The displayed data indicate:

• the release resident in the Processor board (RES).

• the Output Data System release (ODS).
• the installed SW release (STD followed by all numbers).
Video standard It reports which video standard (PAL or NTSC) has been set.

Modules and The active licences are listed in these fields.

Licenses
Boards
The BOARDS option has two columns.

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The “Board” column lists all the installed boards. The “CI” column lists the
Configuration Index (the [NN] figures) of the installed boards.

Firmware
The unit displays:

The Firmware option shows the installed boards equipped with Flash EPROM
(“Board” column) and their Firmware version.

Please note that the Flash EPROMs located on the boards are partitioned into
several sectors. Each sector of the Flash is independent and therefore each of them
can be separately programmed.

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Demo Licenses
See further in this Service technician can activate the available Demo licenses.
manual to know how
to activate a Demo
license

A demo license lasts two hundreds (200) working hours. The “Demo licenses”
display allows to check the status of the activated demo licenses to be checked.

To exit from the System Configuration screen press OK.

The System Configuration screen can be saved on USB pen drive through
EXPORT option. The system creates a .txt file containing all Configuration Screen
information.

When units ship from Esaote, prints of the initial configuration are placed in a
pocket located on the bottom cover of the device. The technical staff will be
responsible for keeping these prints up to date when the configuration of the
device changes.

Machine Self-test
At power-on, the Processor board executes a self-test to check:

• the Configuration Index and the FW level of the boards

• which SW release is installed
The result of this self-test is displayed for a short time, before the Exam Start
window appears. However you can access to the Configuration Screen in Real
Time or in Freeze by pressing the key and selecting the SYSTEM
CONFIGURATION option.

The initial self-test has a dual function:

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• “Self-configuration”
If new features have been added (e.g. a new license has been installed), the CPU
automatically reconfigures itself to manage the new devices. The Configuration
display indicates the changes made: with reference to the same example above, the
screen will show the new license name on the “Licenses” field.

• Control
The Processor board checks for internal conflicts and, if there are any, displays a
warning message.

Configuration Conflicts
If there are conflicts between the HW levels of boards or between HW and SW,
the system stops at the General Configuration screen and displays a warning
message detailing the reason of the conflict. For example, the unit displays the
following message:

System Configuration Error: Board(s) not available or not compatible

In the BOARDS option, all the fields that caused the conflict are displayed in red.
If the cause is a board having a configuration index incompatible with the HW
level of the device, the Configuration Index field of that board will be red. This
screen thus represents a useful diagnostic tool for technical staff. This screen may
be bypassed by pressing the CANCEL key and access gained to the Exam Start
window.

Updating the Device

Each unit has a The 7350 is designed so as to minimize the number of update procedures that
Combo drive installed require changing or replacing hardware in the system. This is possible due to the
on the left-hand side
use of Flash EPROM which may be updated by means of a Compact Disk without
having to disassemble the device.

The SW used on the machine is installed physically on the Processor board: the
procedure for updating the SW release does not require any boards or CI’s to be
changed. As we have seen, the release installed appears on the Configuration
display.

The same philosophy is used for storing all the probe control tables. Whenever the
number of probes managed by the 7350 is changed, the new Acoustic Output
Data must be loaded from a CD.

The release installed in the Flash EPROM is controlled using the Firmware option
of the Configuration screen.

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If there are conflicts caused by the firmware release installed, the characters of
these fields will be displayed in red.

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Chapter

2 - Equipment
In this chapter are listed the tools you need in order to access the 7350 internal
parts, to activate the Service procedures and to perform a functional test of the
unit.

Disassembling Equipment
In order to access the 7350, the following tools are needed:
The disassembling Tool Dimension
procedures are
Dynamometric Phillips electric screwdriver Large, medium and
detailed in Section 2
small tips
Short Philips screwdriver Small tip
Slotted screwdriver Large and small tips
Box wrench 10 and 5 mm
Allen screwdriver 6, 5, 4, 3 and 2 mm
Tweezer -
Point pliers Small tip
The use of an electric screwdriver allows the access time to be minimized. Low
torques are recommended.

In order not to damage the parts during the disassembling procedures, it is

CAUTION
recommended to use the torques values indicated in Section 2.

Service Procedures
Service key The service procedures that require an interaction with the unit, as for example the
P/N 8610264000 language setting, can be activated only through the service key. The service key is
provided with an USB connector and can be inserted in any of the two USB ports
placed on the front panel.

The key must be inserted before switching on the unit, to be able to access to the
several service menus. If the procedure is not carried out properly, the system
doesn’t allow the access to the menu and, in some cases, the following message is
shown:

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The symbol shown on the left is used in this manual to indicate all the procedures
that require the use of the key.

USB Pen Drive and Re-writable CD

To perform a complete check of the unit, it is suggested to always have an USB
pen drive and a re-writable CD. These tools allow the service technician to test the
functioning of the Combo drive and of the USB ports.

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Chapter

3 - Precautions
A series of precautions that must be observed each time you perform an operation
on the 7350 are emphasised below:

• the equipment must always be switched off before carrying out any
service operation. In the same way, all the probes and peripherals
(external monitor, printer, video-recorder...) must also be
disconnected.
• the boards may only be removed when the equipment is powered off.
• an electrostatic discharge occurring through the contact with the
operator, can irreparably damage the electronic components on 7300
boards, that are sensitive to electro-static discharges: we therefore
recommend that you take precautions to prevent these discharges each
time a board has to be removed/installed. In operational terms, this
means:
o the machine must rest on an electro-static mat connected to
earth.
o the service technician must also be connected to the same
earth each time he removes or installs the boards.
o the boards and components must always be moved in their
special electro-static containers.
o for the service on the field, use the specific kits including the
anti-static mat.
The chapter entitled “7350 Parts List” details the sub-assemblies that are to be
considered sensitive to electro-static discharges (ESD).

When the board is ESD sensitive, you can find on the PCB master this symbol.

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SECTION 1 10
 1
7 3 5 0 – S E R V I C E M A N U A L
Chapter

1 - How to remove the

7350 covers
This chapter describes how to remove/assemble the covers of the 7350 and the
monitor. In order to carry out all the removal procedures, you must disconnect and
remove all the connected peripherals, the probes and power cable.

The disassembling instructions are separately given for each part of the unit
(Monitor, Softkey section,..).

Chassis Section
This section describes the procedures to access all the covers of the Chassis
section. The procedures refer to the unit in its close position with the wheels
locked.

Unit Back Side Unit Front Side

Monitor

Softkey
System close position
Section

Keyboard
Section
Chassis
Section

Rear lifting
handle Front lifting
handles

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 7 3 5 0 – S E R V I C E M A N U A L

Right and Left covers

Right cover Tools
REF 9102961000 No tool is required.
Left cover
REF 9102962000

¼h

Removal procedure
• Pull the cover outwards.
Assembly procedure
Carry out the inverse of the removal procedure.

Upper
covers
Covers (Grey
plastic)
Bumpers
(Green
plastic)

Right and Left bumpers

Right bumper Tools
REF 9102963000 No tool is required.
Left bumper
REF 9102964000

¼h

Removal procedure
• Pull the bumper outwards.
Assembly procedure
Carry out the inverse of the removal procedure.

Once both the cover and the bumper have been removed you get access to the
boards baskets. The PC Basket is on the left side and the Boards Basket is in the
right side. For further details please refer to the next chapter.

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Rear cover
Rear cover Tools
REF 9102965000 Tool Dimension
Phillips electric Medium tip
screwdriver
Straight head screwdriver Large tip

¼h

Removal procedure
• Remove both lateral covers.
• Unscrew the two (2) straight head screws that keeps the cover closed
and open it.
• Unscrew the two (2) screws fixing the piston to the rear cover.

• Free the rear covers from the two upper lateral cogs and remove it.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 0,6 Nm

Spare code
The spare code includes the rear cover, the closing screws, the rear label and the
adhesive pocket, where the system configuration printouts must be inserted.

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Rear bumper
Rear bumper Tools
REF 9102966000 No tool is required.

¼h

Removal procedure
• Remove both lateral covers.
• Open the bumper by lifting and pulling it up.
• Place the bumper in correspondence with the large holes of the
metallic support.
• Apply a slight pressure on the screws to push them inwards and
remove the bumper.
Assembly procedure
Carry out the inverse of the removal procedure.

Spare code
The spare code includes the rear bumper with the two axle boxes and screws.

Upper Metallic Covers

Upper Metallic Tools
Cover No tool is required.
REF 9102869500
Upper Lateral
Metallic Covers
REF 8108201500

¼h

Removal procedure
• Remove the upper metallic covers by pulling them up. The covers are
secured by eight magnets.
Assembly procedure
Carry out the inverse of the removal procedure.

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Upper Metallic Small Cover

Upper Metallic Tools
Small Cover Tool Dimension
REF 8107946500 Philips head screwdriver Medium tip

¼h

Removal procedure
• Remove the upper metallic covers by pulling them up. The covers are
secured by eight magnets.
• Unscrew the two (2) screws (the screw position is shown in the below
photo) fixing the metallic upper small cover to the chassis and remove
it.

• Remove the cover.

Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 1,4 Nm

Upper Plastic Cover

Upper Plastic Tools
Cover Tool Dimension
REF 9102968000 Box wrench 10 mm
Philips head screwdriver Large and Small tip

¼h

Removal procedure
• Remove the upper metallic covers by pulling them up.
• Remove the metallic upper small cover.

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• Unscrew the nine (9) Philips head screws that fix the upper plastic
cover to the chassis.
• Remove the upper plastic cover.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 1,4 Nm

Spare part
The spare upper plastic over includes all the magnets and the two belts.

Front cover
Front cover Tools
REF 8107601500 Tool Dimension
Phillips electric Medium tip
screwdriver

¼h

Removal procedure
• Remove both lateral covers.
• Remove the upper metallic large covers by pulling them up.
• Remove the upper metallic small cover.
• Loose the four (4) Philips head screws that fix laterally the front cover
to the unit chassis.
• Loose the two (2) screws placed up, inside the upper part of the
chassis. (see the below photo).

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• Lift the front cover upwards and remove it.

Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 1,4 Nm

Front bumper
Front Bumper Tools
REF 9102967000 Tool Dimension
Allen screwdriver 5 mm
Philips head screwdriver Small tip

¼h

Removal procedure
• Remove the front cover.
• Unscrew the two (2) Allen screws fixing the bumper. The left screw
position is shown in the below photo.

• Unscrew the two (2) Philips head screws placed under the bumper.

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• Remove the bumper.

Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 1,4 Nm

Posterior Wheel Cover

Posterior Wheel Tools
Cover Tool Dimension
REF 8107410000 Straight head screwdriver -

¼h

Removal procedure
• Remove the wheel cover using the screwdriver as lever to part the
cover from the wheel.
Assembly procedure
Carry out the inverse of the removal procedure.

Posterior Wheel
Posterior Wheel Tools
REF 8107810500 Tool Dimension
Pointer pliers Small tip

¼h

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It is strongly recommended to perform this operation in two persons.

C A U T I O N
Removal procedure
• Remove the monitor.
• Be sure that the keyboard is blocked in its close position.
• Rotate the front wheels so that they can be locked.
• Remove the posterior wheel cover.
• Tip the unit laterally to gain access to the wheel to be removed.
• With the pliers open the ring fixing the wheel to its rotation axis and
remove the ring.

• Remove the wheel.

Assembly procedure
Carry out the inverse of the removal procedure.

Anterior Wheel
Anterior Wheel Tools
REF 1000000109 Tool Dimension
Allen screwdriver 6 mm

¼h

It is strongly recommended to perform this operation in two persons.

C A U T I O N
Removal procedure
• Remove the monitor.

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• Be sure that the keyboard is blocked in its close position.

• Rotate the front wheels so that they can be locked.
• Tip the unit laterally to gain access to the wheel to be removed.
• Unscrew the four (4) screws fixing the wheel to the chassis and
remove the wheel.
Assembly procedure
Carry out the inverse of the removal procedure.

Front Lifting Handles

The lifting handles are stuck to the chassis: it is necessary to break them to remove
them.

Right Lifting Tools

Handle Tool Dimension
REF 8107691000 Allen screwdriver 6 mm
Left Lifting Handle Philips head screwdriver Medium tip
REF 8107692000 Straight head screwdriver Medium tip
Glue -

¼h

Removal procedure
• Remove both the lateral cover and the bumper covering the lifting
handle.
• Remove the front bumper.
• Using the straight head screwdriver as lever unglue the handle from
the chassis.

• Clean the metallic surface from any plastic residual.

SECTION 2 10
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Assembly procedure
• Spread the glue inside the handle.
• Place the handle on the chassis so that the internal handle tongue
match the chassis shape.

Rear Lifting Handle

Rear Lifting Tools
Handle Tool Dimension
REF 8107649000 Box wrench 10 mm
Philips head screwdriver Large and Small tip

¼h

Removal procedure
• Remove the rear bumper.
• Disconnect all the cables from the unit plugs.
• Unscrew the five (5) Philips head screws that fix the plugs chassis to
the main chassis.

A B

• Extract the plug chassis.

• Unscrew the four (4) wrenches placed inside the insulation
transformer box.
• Remove the rear lifting handle.
Assembly procedure
Carry out the inverse of the removal procedure.
Recommandation Torque = 1,4 Nm

Recommandation Torque (A and B screws) = 3 Nm

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Keyboard Section
This section describes the procedures to access all the covers of the Keyboard
section. The procedures refer to the unit in its open position with the wheels
locked.

Unit Back Side Unit Front Side

System Open
Position

Encoder and Function Buttons

Small Encoder Tools
REF 8107851000 No tool is required.
Large Encoder
REF 8107469000
Power Button
REF 8107471503
Audio Button
REF 8107471505
Depth Button
REF 8107471527
Doppler Button
REF 8107471504
B/M Button
REF 8107471509

¼h

Removal procedure
• The encoders are tongued to the key board. Seize the encoder to be
removed and pick it up. The button is free once removed the encoder.

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Assembly procedure
Carry out the inverse of the removal procedure.

Front Handle
Front cover Tools
REF 8107851000 Tool Dimension
Allen screwdriver 4 mm

¼h

Removal procedure
• Unscrews the three (3) screws fixing the handle to the keyboard
chassis. The screws are placed on the lower side of the handle.

• Release the screws that fix the Keyboard group (see next paragraphs
for further details).
• Slightly tilt the key board group up and extract the front handle.
Assembly procedure
Carry out the inverse of the removal procedure.

Once removed the front handle, you get access to the Keyboard group.

Gel Holder
Gel holder Tools
REF 8107913000 No tool is required.

¼h

Removal procedure
The gel holder is not fixed. Remove it by pulling it up.

SECTION 2 13
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Assembly procedure
Carry out the inverse of the removal procedure.

Probe Holder
Probe holder Tools
REF 9102619000 Tool Dimension
Phillips electric Medium tip
screwdriver

¼h

Removal procedure
• Unscrews the one (1) screw fixing the probe holder to the probe
support. The screw is placed on the lower side of the support.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 0,6 Nm

Cable Hook
Cable hook Tools
REF 8107368000 Tool Dimension
Phillips electric Medium tip
screwdriver

¼h

Removal procedure
• Unscrews the one (1) screw fixing the hook to the probe support. The
screw is placed on the lower side of the support.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 0,6 Nm

ECG Cable Holder

ECG cable holder Tools
REF 9102623000 Tool Dimension
Phillips electric Medium tip
screwdriver

¼h

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Removal procedure
• Unscrews the two (2) screws fixing the hook to the probe support.
The screws are placed on the lower side of the support.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 0,6 Nm

Left Probe Support

Left probe support Tools
REF 9102969000 Tool Dimension
Allen screwdriver 4 mm

¼h

Removal procedure
• Remove the ECG cable holder
• Remove the two (2) probe holders and cable hooks.
• Unscrews the three (3) Allen screws fixing the support to the keyboard
chassis. The screws are placed on the lower side of the support.
Assembly procedure
Carry out the inverse of the removal procedure.

Spare code
The left probe support spare code includes the Pedof probe holder.

Right Probe Support

Right probe Tools
support Tool Dimension
REF 8107852000 Allen screwdriver 4 mm

¼h

Removal procedure
• Remove the Gel holder by pulling it up.
• Remove the three (3) probe holders and cable hooks.
• Unscrews the three (3) Allen screws fixing the support to the keyboard
chassis. The screws are placed on the lower side of the chassis.
Assembly procedure
Carry out the inverse of the removal procedure.

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Keyboard Group
Tools
Tool Dimension
Allen screwdriver 3 mm

¼h

Removal procedure
• Remove the front handle.

• Unscrews the nine (9) Allen screws fixing the group to the keyboard
chassis. The screws are placed on the lower side of the chassis (screws
position is indicated by the arrows in the above shot).
• Move the Keyboard group frontwards and then upwards.
• Disconnect the three (3) flat cables that connect the Keyboard group
to the chassis.
• Remove the group.

Assembly procedure
Carry out the inverse of the removal procedure.

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Once removed the front handle, you get access to the trackball, the Key TGC
board, the Key Switch board, PC keyboard, the mouse keys and the keyboard
membranes.

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Monitor
Tools
Tool Dimension
Straight head screwdriver Medium tip

¼h

Removal procedure
• Place the monitor horizontally.
• Disconnect the power and video signal cables from the monitor.
• Unscrew the two (2) screws fixing the monitor to the chassis. The
screws are placed at the base of the monitor rear side.
• Push the monitor backward and raise it up being careful to monitor
weight.
Assembly procedure
Carry out the inverse of the removal procedure.

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Softkey Section

Softkey Rear Cover

Softkey rear cover Tools
REF 8108034000 Tool Dimension
Philips electric Medium tip
screwdriver
Allen scredriver 2 mm

¼h

Softkey Upper Softkey

Cover Rear
Cover

Removal procedure
• Place the monitor horizontally.
• Unscrew the two (2) Allen screws place in the upper part of the cover.

• Unscrew the three (3) screws placed on the lower part of the cover.
The screws positions are indicated in the above photo. Rotate the
keyboard to unscrew the “B” screw.
• Pull the cover out.

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Assembly procedure
Carry out the inverse of the removal procedure, being careful to correctly position
the monitor cables (as shown in the below photo).

Recommandation Torque = 1,4 Nm

Softkey Upper Cover

Softkey Upper Tools
Cover Tool Dimension
REF 8107715000 Philips electric Medium tip
screwdriver
Allen scredriver 5 and 2 mm

¼h

Removal procedure
• Remove the Monitor.
• Remove the Softkey rear cover.
• Unscrew the three (3) Allen screws shown in the below shot and
remove the monitor support.

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Be careful to the screws: if they fall down, they can go into the unit chassis.
C A U T I O N
We strongly recommend to close the hole using a piece of paper or a piece
of material.

• Remove the monitor support.

• Remove the cover.
Assembly procedure
Carry out the inverse of the removal procedure.

Once removed the Softkey upper cover, you get access to loudspeakers and the
Softkey group.

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7 3 5 0 – S E R V I C E M A N U A L
Chapter

2 - How to
remove/reassemble the
7350 boards and other
subassemblies
This chapter describes how to remove/re-assemble:

• the 7350 boards

• the programmed Hard Disk
• the PC fan
• the SPS and boards fans
• the Combo driver
• the trackball
• the PC keyboard
• the keyboard cover
• the keyboard membranes and mouse keys
• the loudspeakers
• the softkey group
For accessing to these subassemblies covers have to be removed: refer to the
previous chapter for detailed instructions.

SECTION 2
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Chassis Section

Boards position
Most boards are placed inside the right side of the chassis. The left side of the
chassis contains the PC Assembly, the Connectors and the Printer ECG boards.
The Mother board is affixed to the board’s chassis.

Right Chassis boards

In the right side of the chassis the following boards are installed:

Boards REF
INPUT board 9501215000
TRX boards 9501212000
TRXCW board 9501214000
CONTROL board 9501216000
DOPPLER board 9501217000
VIDEO board 9501219000
PROCESSORS board 9501218000
SPR board 9501220000
SPS board 9501100000
In the right chassis are also located the SPS and boards fans.

With the exception of the Input and the SPS boards, all other boards are simply
installed in the chassis. Specific instructions are given for the Input and the SPS
boards; for all other boards refer to the below procedure.

Tools
Tools Dimension
Straight head screwdriver Large tip

¼h

Removal procedure
• Remove right cover and bumper.
• Unscrew the four (4) screws fixing the right shield to the chassis
• Free the board opening the two locking tabs.

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 7 3 5 0 – S E R V I C E M A N U A L

The beside spot shows

the tabs that block
the boards. One tab
is opened and the
other two are in their
close position.

• Extract each board from the chassis, using the two black pull tabs.
Assembly procedure
Carry out the inverse of the removal procedure. Press the board firmly until it is
possible to close both the pull tabs and the locking tabs.

To facilitate boards insertion, it is useful to remove the closest metallic shields to

N O T E
gain better access to the boards.

Be careful to properly oriented the SPR board when installing it.. The board has to
N O T E
be inserted with its labels bar right-oriented.

Input board
Input board Tools
REF 9501215000 Tools Dimension
Straight head screwdriver Large tip
Phillips electric Medium tip
screwdriver

¼h

Removal procedure
• Remove right cover and bumper.
• Remove the front cover and bumper.
• Unscrew the four (4) screws fixing the right shield to the chassis.
• Unscrew the four (4) Philips head screws fixing the lateral metal stirrup
to the chassis.

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23
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• Unscrew the eleven (11) Philips head screws (placed in the unit front
side) fixing the Input board to the chassis.
• Free the board by opening the two tabs and then pull outwards using
the two black pull tabs.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque (for stirrup) = 1,4 Nm

Recommandation Torque (for board) = 0,6 Nm

SPS board
SPS board Tools
REF 9501100000 Tools Dimension
Straight head screwdriver Large tip
Philips head screwdriver Medium tip

¼h

Removal procedure
• Remove right cover and bumper.
• Unscrew the four (4) screws fixing the right shield to the chassis.

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24
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• Free the SPS shield by opening the two tabs and pull the shield
outwards using the two black pull tabs.
• Remove the shield.
• Disconnect the cable (placed in unit rear panel) from the SPS
connector.

SPS
Connector

• Unscrew the two (2) Philips head screws that fix the SPS board to the
chassis. The screws are placed beside the SPS connector.
• Free the board by opening the two tabs and then pull outwards using
the two black pull tabs.
Assembly procedure
Carry out the inverse of the removal procedure.

Be careful to properly oriented the SPS board when installing it.. The board has to
N O T E
be inserted with its labels bar right-oriented.

Recommandation Torque = 1,4 Nm

SPS fan
SPS Fan Tools
REF 9102821000 Tools Dimension
Straight head screwdriver Large and medium tip
Philips head screwdriver Medium tip
Short Philips screwdriver Small tip
Grab -

¾h

SECTION 2
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 7 3 5 0 – S E R V I C E M A N U A L

Removal procedure
• Remove the right cover and bumper.
• Unscrew the four (4) screws fixing the right shield to the chassis.
• Remove the SPR and the SPS boards and all their shields to gain full
access to the fan clamps.
• Unplug the fan cable from the Mother board (VENT connector).
• Loose the six (6) Philips head screws that fix the lower metallic cover.
• Remove the lower metallic cover.
• Using the screwdriver space the fan from the chassis.
• Pull the fan till one elastic clamp is free.
• Repeat the operation for all other clamps.
Assembly procedure
Carry out the inverse of the removal procedure. The grab can be used to facilitate
the insertion of the elastic clamps.

Recommandation Torque (for cover) = 0,6 Nm

Recommandation Torque (for board) = 1,4 Nm

Boards fan
SPS Fan Tools
REF 9102932000 Tools Dimension
Straight head screwdriver Large and medium tip
Philips head screwdriver Medium tip
Short Philips screwdriver Small tip
Grab -

¾h

Removal procedure
• Remove the right and left covers and bumpers.
• Unscrew the four (4) screws fixing the right shield to the chassis.
Repeat the operation for the left shield.
• Remove the Input, TRX, TRXCW and the Control boards and all their
shields to gain full access to the fan clamps.
• Unplug the fan cable from the Mother board. The cable is connected
on the PC Assembly board (Left chassis boards).
• Loose the six (6) Philips head screws that fix the lower metallic cover.
• Remove the lower metallic cover.
• Using the screwdriver space the fan from the chassis.

SECTION 2
26
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• Pull the fan till one elastic clamp is free.

• Repeat the operation for all other clamps.
Assembly procedure
Carry out the inverse of the removal procedure. The grab can be used to facilitate
the insertion of the elastic clamps.

Recommandation Torque (for cover and board) = 0,6 Nm

Recommandation Torque (for stirrup) = 1,4 Nm

Left Chassis Boards

In the left side of the chassis the following boards are installed:

Boards REF
PC ASSEMBLY board 9501225000
PRINTER ECG board 9501227000
CONNECTORS board 9501226000
In the left chassis are also the located the Combo driver, the programmed Hard
Disk and the PC fan.

The PC Assembly board can be removed once disassembled the PC Chassis from
the unit; the other two board can be removed without dismounting it.

Printer ECG board

Printer ECG board Tools
REF 9501227000 Tools Dimension
Straight head screwdriver Large tip
Box wrench 5 mm

¼h

Removal procedure
• Remove left cover and bumper.
• Unscrew the four (4) screws fixing the left shield to the chassis.
• If necessary, disconnect all the external cables from Printer ECG
connectors (C21-C29 connectors on the rear panel).
• Disconnect the flat cable coming from the Mother board from the
Printer ECG board.
• Unscrew the six (6) screws (placed on the rear panel) that fix the board
to the PC Chassis. The screws are beside the C21, C28 and C29
connectors.
Assembly procedure
Carry out the inverse of the removal procedure.

SECTION 2
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Connectors board
Connectors board Tools
REF 9501226000 Tools Dimension
Straight head screwdriver Large tip
Box wrench 5 mm

¼h

Removal procedure
• Remove left cover and bumper.
• Unscrew the four (4) screws fixing the left shield to the chassis.
• If necessary, disconnect all the external cables from Connectors
connectors (C12-C20 connectors on the rear panel).
• Disconnect the flat cable coming from the Mother board from the
Connectors board
• Unscrew the six (6) screws (placed on the rear panel) that fix the board
to the PC Chassis. The screws are beside the C12, C19 and C20
connectors.
Assembly procedure
Carry out the inverse of the removal procedure.

Combo Drive
Combo drive Tools
REF 9730650084 Tools Dimension
Straight head screwdriver Large tip
Philips electric Medium tip
screwdriver

¼h

Removal procedure
• Remove left cover and bumper.
• Remove the front cover.
• Unscrew the four (4) screws fixing the left board shield to the chassis.
• Disconnect the three (3) cables from the combo.
• Unscrew the four (4) Philips head screws fixing the combo metallic
support to the chassis.
• Remove the combo support.
• Unscrew the eight (8) Philips head screws that fix the combo to its
support.

SECTION 2
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• Remove the combo drive.

Assembly procedure
Carry out the inverse of the removal procedure being careful to place the cables
behind the PC chassis so that they are not overlaid the fan.

Recommandation Torque (for support) = 1,4 Nm

Recommandation Torque (for combo) = 0,6 Nm

PC Chassis

Tools
Tools Dimension
Straight head screwdriver Large tip
Phillips electric Medium tip
screwdriver

¼h

PC Chassis

Removal procedure
• Remove left cover and bumper.
• Unscrew the four (4) screws fixing the left shield to the chassis.
• Disconnect all the external cables from the rear panel connectors (C1-
C29 connectors on the rear panel).

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 7 3 5 0 – S E R V I C E M A N U A L

• Disconnect the flat cables from the Printer ECG, Connectors and PC
Assembly boards.
• Disconnect all the cables coming from the Combo drive, the fan and
the chassis.
• Unscrew the ten (10) Philips head screws (placed on the rear panel)
that fix the PC Chassis to the main one.
• Tilt the PC Chassis and remove it.

Assembly procedure
Carry out the inverse of the removal procedure, being careful to keep all cables far
from the fan.

Recommandation Torque = 1,4 Nm

Once removed the PC Chassis you gain access to the PC Assembly board, the
programmed Hard Disk and the PC fan.

PC Assembly board
PC Assembly Tools
board Tools Dimension
REF 9501225000 Straight head screwdriver Large tip
Phillips electric Medium tip
screwdriver
Box wrench 5 mm

½h

Removal procedure
• Remove the PC Chassis.
• Free the board from the two plastic blocks.
• Unscrew the four (4) screws (placed on the rear panel) that fix the
board to the PC Chassis. The screws are beside the C1 and C11
connectors.
• Extract the board from the chassis.
Assembly procedure
Carry out the inverse of the removal procedure, being careful to keep all cables far
from the fan.

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Programmed Hard Disk

Programmed HD Tools
REF 9102867000 Tools Dimension
Straight head screwdriver Large tip
Phillips electric Medium tip
screwdriver
Box wrench 5 mm

½h

Removal procedure
• Remove the PC Chassis.
• Remove the PC Assembly board.
• Unscrew the four (4) Philips head screws that fix the hard Disk to the
PC Assembly board.
• Remove the Hard Disk.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 0,6 Nm

PC Fan
PC Fan Tools
REF 9102821000 Tools Dimension
Straight head screwdriver Large and medium tip
Philips head screwdriver Medium tip
Grab

½h

Removal procedure
• Remove the PC Chassis.
• Using the screwdriver space the fan from the PC chassis as shown in
the below spot.

SECTION 2
31
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• Pull the fan till one elastic clamp is free.

• Repeat the operation for all other clamps.
Assembly procedure
Carry out the inverse of the removal procedure. The grab can be used to facilitate
the insertion of the elastic clamps.

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Keyboard Section
The Key Switch and Key TGC boards are in the Keyboard Section together with
the trackball, the PC keyboard, the mouse keys, the membranes, their supports and
the keyboard cover.

Trackball
Trackball Tools
REF 3400000053 Tools Dimension
Allen screwdriver 3 mm
Phillips electric Medium and Small tip
screwdriver
Straight head screwdriver Small tip

¼h

Removal procedure
• Remove the Keyboard group.
• Using the straight head screwdriver disconnect the trackball cables.
• Unscrew the four (4) Philips head screws fixing the trackball support
to the keyboard group.
• Remove the trackball support.
• Unscrew the three (3) flathead screws fixing the trackball to its
support.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 0,4 Nm

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Key Switch board and Key Switch Membranes

and Supports
Key Switch board Tools
REF 9501221000 Tools Dimension
B/M Membrane Allen screwdriver 3 mm
REF 817987000 Phillips electric Medium and Small tip
B/M Membrane screwdriver
Support Straight head screwdriver Small tip
REF 8107985000
Doppler Membrane
REF 8107986000
Doppler Membrane
Support
REF 8107984000

½h

Removal procedure
• Remove the Keyboard group.
• Remove the five (5) encoders from the key board by pulling them up.
The encoders are Audio, Doppler gain, Depth, B/M gain and Power.
• Remove the trackball.
• Disconnect the two (2) flat cables from Key Switch board.
• Unscrew the thirty-three (33) Philips head screws fixing the board to
the group.
• Remove the two membrane supports by pulling them up.
• Remove the two keys membranes by lifting them up.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 0,4 Nm

Once removed the Key Switch board you gain access to the mouse keys, that are
free.

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Key TGC board and Shut Down Membrane

Key Switch board Tools
REF 9501223000 Tools Dimension
Shut Down Allen screwdriver 3 mm
Membrane Phillips electric Medium and Small tip
REF 810746000 screwdriver

½h

Removal procedure
• Remove the Keyboard group.
• Remove the seven (7) TGC caps.
• Disconnect the two (2) flat cables from Key TGC board.
• Unscrew the thirteen (13) Philips head screws fixing the board to the
group.
• Remove the shut down membrane by lifting it up.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 0,4 Nm

Once removed the Key TGC board you gain access to the PC keyboard and to
the TGC potentiometers.

PC Keyboard
Tools
PC Keyboard Tools Dimension
REF 9102971000 Allen screwdriver 3 mm
Phillips electric Medium and Small tip
screwdriver
½h

Removal procedure
• Remove the Keyboard group.
• Remove the Key TGC board.
• Disconnect the flat cable from the Key TGC board.
• Remove the PC keyboard by pulling it up.
Assembly procedure
Carry out the inverse of the removal procedure.

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Keyboard Cover
Keyboard cover Tools
REF 9102970000 Tools Dimension
Allen screwdriver 3 mm
Phillips electric Medium and Small tip
screwdriver
Straight head screwdriver Small tip

½h

Removal procedure
• Remove the Keyboard group.
• Remove the trackball.
• Remove the Key TGC and Key Switch boards.
Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque = 0,4 Nm

Spare Part
The spare part includes both the plastic and silver covers and the logo labels.

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Softkey Section
The Softkey group and the Loudspeakers are in the Softkey section.

Loudspeaker
Loudspeaker Tools
REF 9102834000 Tools Dimension
Allen screwdriver 2 and 5 mm
Phillips electric Large, medium and
screwdriver small tips

½h

Removal procedure
• Remove the Monitor
• Remove the Softkey rear and upper covers.
• Unscrew the two (2) Philips head screws (large tip) shown in the below
photo.

1 2

• Unscrew the four (4) Philips head screws (medium tip) placed in the
lower side of the monitor support. The below photo shows the
position of left screws: there are two screws for each side.

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• Remove the softkey chassis by disconnecting the flat cable and the two
loudspeakers cables.

• Unscrews the four (4) Philips head screws (small tip) fixing the
loudspeaker to the Softkey group
Assembly procedure
Carry out the inverse of the removal procedure.

SECTION 2
38
 7 3 5 0 – S E R V I C E M A N U A L

Recommandation Torque (for 1 and 2 screws) = 3 Nm

Recommandation Torque (for A and B screws) = 1,4 Nm

Recommandation Torque (for loudspeaker) = 0,6 Nm

Softkey Group
Softkey Group Tools
REF 9102972000 Tools Dimension
Allen screwdriver 2 and 5 mm
Phillips electric Large, medium and
screwdriver small tips

½h

Removal procedure
• Remove the Monitor
• Remove the Softkey cover.
• Gain access to the loudspeakers and Softkey group, as explained in the
previous paragraph
• Remove the two loudspeakers.
• Unscrew the six (6) Philips head screws fixing the loudspeakers chassis
to the Softkey group.

Assembly procedure
Carry out the inverse of the removal procedure.

Recommandation Torque (for chassis) = 0,6 Nm

SECTION 2
39
7 3 5 0 – S E R V I C E M A N U A L

Spare Part
The spare part includes the unit labels

SECTION 2
40
 A
7 3 5 0 – S E R V I C E M A N U A L
Appendix

Appendix A - Parts
Accessing Times
This evaluation refers to the 7350 only: the system is considered removed from the
cart and free from all the peripherals and probes.

Note: the accessing time has been qualified by multiples of 15 minutes

Accessing times have been get using the tools set detailed in Chapter 2, Section1.

Accessing Times to the Chassis section

Covers
Part Parts to be removed Time
Right cover - ¼h
Left cover - ¼h
Right bumper - ¼h
Left bumper - ¼h
Rear cover Left and Right covers ¼h
Rear bumper - ¼h
Upper metallic covers - ¼h
Upper metallic small cover Upper metallic covers + n.2 screws ¼h
Upper plastic cover Upper metallic covers, Upper metallic small ¼h
cover + n.11 screws
Front cover Left and Right covers, Upper metallic covers, ¼h
Upper metallic small cover + n.6 screws
Front bumper Left and Right covers, Upper metallic covers, ¼h
Upper metallic small cover, Front cover +
n.10 screws
Posterior wheel cover - ¼h
Posterior wheel Posterior wheel cover ¼h
Anterior wheel - ¼h
Right lifting handle Left and Right covers, Left and Right ¼h
bumpers, Upper metallic covers, Upper
metallic small cover, Front cover, Front
bumper + n.10 screws
Left lifting handle Left and Right covers, Left and Right ¼h
bumpers, Upper metallic covers, Upper
metallic small cover, Front cover, Front
bumper + n.10 screws
Rear lifting handle Rear bumper, Plugs chassis + n.9 screws ¼h

SECTION 2
41
7 3 5 0 – S E R V I C E M A N U A L

Boards
Part Parts to be removed Time
Input board Right cover, Right bumper, Right shield, ¼h
Stirrup + n.15 screws
TRX board Right cover, Right bumper and Right shield ¼h
TRXCW board Right cover, Right bumper and Right shield ¼h
Control board Right cover, Right bumper and Right shield ¼h
Doppler board Right cover, Right bumper and Right shield ¼h
Video board Right cover, Right bumper and Right shield ¼h
Processor board Right cover, Right bumper and Right shield ¼h
SPR board Right cover, Right bumper and Right shield ¼h
SPS board Right cover, Right bumper, Right shield, SPS ¼h
shield + n.2 screws
Printer ECG board Left cover, Left bumper, Left shield + n.6 ¼h
screws
Connectors board Left cover, Left bumper, Left shield + n.6 ¼h
screws
PC Assembly board Left cover, Left bumper, Left shield, PC ½h
chassis + n.14 screws

Other subassemblies
Part Parts to be removed Time
SPS fan Right cover, Right bumper, Right shield, SPR ¾h
board and shields, SPS board and shield,
Lower metallic cover + n.8 screws
Boards fan Right cover, Right bumper, Right shield, Left ¾h
cover, Left bumper, Left shield, Input board,
TRX board, TRXCW board, Control board,
Internal board shields + n.21 screws
PC fan Left cover, Left bumper, Left shield, PC ½h
chassis + n.10 screws
Combo driver Left cover, Left bumper, Left shield + n.12 ¼h
screws
Programmed Hard Disk Left cover, Left bumper, Left shield, PC ½h
Chassis, PC Assembly board + n.18 screws

SECTION 2
42
7 3 5 0 – S E R V I C E M A N U A L

Accessing Times to the Keyboard section

Covers
Part Parts to be removed Time
Encoder - ¼h
Function button - ¼h
Front handle n.3 screws ¼h
Probe holder n.1 screw ¼h
Gel holder - ¼h
Cable hook n.1 screw ¼h
ECG cable holder n.2 screws ¼h
Left probe support ECG cable holder, Probe holders, Cable ¼h
hooks + n.9 screws
Right probe support Gel holder, Probe holders, Cable hooks + ¼h
n.9 screws
Keyboard cover Front handle, Trackball, Key Switch board, ½h
Key TGC board + n.62 screws

Boards
Part Parts to be removed Time
Key Switch board Front handle, Trackball, Membranes + n.51 ½h
screws
Key TGC board Front handle, PC keyboard, Membrane + ½h
n.13 screws

Other subassemblies
Part Parts to be removed Time
Trackball Front handle + n.10 screws ¼h
PC Keyboard Front handle + n.13 screws ½h
Key Switch membranes Front handle, Trackball + n.51 screws ½h
Key TGC membrane Front handle, Trackball + n.51 screws ½h

SECTION 2
43
7 3 5 0 – S E R V I C E M A N U A L

Accessing Times to the Softkey section

Covers
Part Parts to be removed Time
Softkey rear cover n.5 screws ¼h
Softkey upper cover Monitor, Softkey rear cover + n.8 screws ¼h

Boards
Part Parts to be removed Time
Softkey group Softkey rear cover, Softkey upper cover, ½h
Loudspeakers + n.28 screws

Other subassemblies
Part Parts to be removed Time
Loudspeaker Softkey rear cover, Softkey upper cover + ½h
n.18 screws

SECTION 2
44
 1
7 3 5 0 – S E R V I C E M A N U A L
Chapter

1 - 7350 Block Diagram

This chapter contains the block diagram descriptions for each board. The general Block Diagram
shows the relationships of each board having a unique function within the overall unit.

SECTION 3 1
7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 2
 1 2 3 4 5 6 7 8 9 10 11

950 1215 000 950 1217 000

F
"7350" INPUT 950 1214 000 "7350" DOPPLER
"7350" TRXCW

HARDWARE ICONF0-5 HARDWARE LC0-15, LCA04, LCRW, /LS* (to/from PROCESSORS) CPU INTERFACE
CONFIGURATION CONFIGURATION CONF0-5

PEDOF TX ELT CW
PEDOF DSIN, DCOS
PEDOF RX ELR PULSER/RECEIVER A/D CONVERTER

PA / Pedof SWITCH

CW Processing
Notch FILTER
PROCESSING

Wall FILTER
E
SWITCH
SPKN1,2, SPKR1,2 (to KEY TGC)
MATRIX
ADV*, REC*, LINE* (to/from CONNECTORS, PC)
PEDOF

PW CFM
DEMODULATION DEMODULATION
950 1216 000 FILTERs FILTERs
AUDIO
"7350" CONTROL WALL FILTERs MTI
MATRIX CONTROLS CW CONTROLS PROCESSING
SELPED FFT CORRELATION
PARAMETERs PARAMETERs
ESTIMATION ESTIMATION
PROBE A

CFMON, CFMOFF
MLN0-3, /ACFM

CONFOE0-2 FRONT END DOPPLER, CFM DDOT, DLINE, /DL DOPPLER, CFM
D CWCH1-32 HARDWARE TIMING TIMING
CONFIGURATION
CONF0-5 CONTROL
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

950 1212 000

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

TRX2
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

"7350" TRX
192 CHANNEL SWITCHES

950 1212 000 TRX1 DPD07

"7350" TRX SCAN CORRELATION CFMD0-17
PROBE B

BWD0-7, CND0-7 SCAN CONVERTER

CONF0-5 XY_ADD0-8, SCAN_MODE0-9 (to VIDEO)
OPERATION
HARDWARE AVG_DATA0-15 (to VIDEO)
CW CONTROL CONFIGURATION CONF0-5

96 CER
SCAN CONVERTER
TIMING Timing signals (to/from PROCESSORS)
C 96 CER IMAGE
96 TX/RX
PROCESSING

32 MUX
PROBE C

32 VCA+A/D BDIG0-15

32 + 32 RF DATA DDIG0-19
ADIG0-15 ADDER PROCESSING
32 ADDERs

TRX TIMING

B CONTROL INTERFACE CPU INTERFACE LC0-15, LCA04, LCRW, /LS* (to/from PROCESSORS)

RLB0-15, SADD0-19, CONTROLS

FRONT END TIMING CONTROLS

PROBE SELECT (SELA/B, SELB/C)

PROBE
PROBE CODE (RLB0-9, PBA/B, PBB/C, PED) PROBE CONTROLS
CODE
CONTROL

A
837 0147 042 Rev.A

TGC (to TRX1,2)

FORM:

ANALOGICAL GAIN CONTROLS POT0-6, POTREF (from KEY TGC)

DGAIN (to TRXCW)

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" BLOCK DIAGRAM
A2 ANDREUCCETTI DONNINI ANDREUCCETTI 24/02/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 970 7350 000 SB A 1 2
DOCUMENT NOT YET VALIDATED DOCUMENTO NON ANCORA VALIDATO
 1 2 3 4 5 6 7 8 9 10 11

950 1218 000

9730640012
"7350" PROCESSORS 2x 9102834000
F QWERTY keyboard Loudspeakers

+5_STB (from SPS)

AUX signals (from PRINTER ECG)
SWITCH_ON_OFF (to PC)
Timing signals (to/from CONTROL) POT0-6, POTREF (to CONTROL) 950 1223 000 950 1224 000
ROW0-15, COL0-15, "7350" KEY TGC "7350" KEY SOFTKEY
FPGA1 ROW0-15, COL0-15, TRK*, ENC*, BUZZER
TRK*, ENC*, BUZZER (to/from PROCESSORS)
910 2821 000
(to/from KEY TGC) SPKN1,2, SPKR1,2 (from DOPPLER)

950 1221 000 3400000053

RS232 signals "7350" KEY SWITCH Trackball
CPU 68340 (to CONNECTORS)
CPU_* RS232 signals 950 1225 010
E (to PRINTER ECG) "7350" PC

+5_STB (from SPS)

MM_* POWER ON
DUAL PORT EEPROM driver EEPROM SWITCH_ON_OFF (from KEY TGC)
MODULE 950 1220 000
POWER_ON_OFF (to SPS)
"7350" SPR

Compact Floppy 950 1172 000

Hard disk
Flash disk "61xx" UHP, USB Head LC0-15, LCRW, /LSPS CPU INTERFACE
FPGA0 DSP0, DSP1 (to/from PROCESSORS)

4 x USB in/out
PCI_* signals FLYBACK HI
D PC Keyboard, Mouse +VAT, -VAT
KB_*, MS_* FLYBACK LOW
PC Headphone, Microphone
VGA_LVP,N0-4 (to VIDEO)
PC
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

LAN in/out
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

LINE* (to/from DOPPLER) standard ETX

+12V
module RS232 PC COM1 +VT
driver MULTIPLE
+6V, -6V
LC0-15, LCA04, LCRW, /LS* (to/from OTHERS) BUCK SYNC.
9730650084 VCC
CDRW PC monitor out +3V3, +3V3A & FILTER
GRA0-15, VMA0-29, VMD0-15, VM*, /VM* +2V2, +2V2A

950 1219 000

"7350" VIDEO
C
ID_SPS0-4 +15V_ECHO

950 1227 000

CPU INTERFACE LC0-15, LCA04, LCRW, /LS* RGBsync Video out
"7350" PRINTER ECG 950 1100 000 910 2821 000
(to/from PROCESSORS) Remote control (1) POWER_ON_OFF "61xx" SPS
SDRAM Remote control (2) (from PC)
MODULE
+5_STB (to KEY TGC, PC)
PRINTER DRIVER PRN_*
Float ECG buffer ECG in +15V_PC (to PC)
+12V_VENT

FPGA
ECG SECTION ECG*, PHYSIO AUX in
MEMORY INPUT FILTER PFC FULL BRIDGE
CPU_* RS232 signals (from PROCESSORS)

B AUX signals (to PROCESSORS) RS232 (debug)

AVG_DATA0-15 (from CONTROL)

XY_ADD0-8, SCAN_MODE0-9 (from CONTROL)

FPGA FRAME ECHO MAINS VAC +15V_TEL

VIDEO MEMORY 9102854000
950 1226 000 DISPLAY CRT
"7350" CONNECTORS 950 1140 000
VGA_LVP,N0-4 (from PC)
"61xx" MAINS POWER
RGBsync Video out (1)

VIDEO LCD driver LCD_* (to LCD) RGBsync Video out (2)

ENCODER SVHS in/out N

MAINS 110/220 SWITCH
SVGA_*, CRT_HSYNC, CRT_VSYNC B/W C-Video out L
A FUSES
VIDEO C-Video in
837 0147 042 Rev.A

VTR_* 4 PERIPHERALS
DECODER Audio in/out
FORM:

ADV*, REC* (to/from DOPPLER) MAINS VAC MAINS VAC INPUT

RS232 signals (from PROCESSORS) RS232 VTR control

SHEET DESCRIPTION:
"7350" BLOCK DIAGRAM
A2 Document Revision: SHEET: OF:

by EpD Number: 970 7350 000 SB A 2 2

7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 3
7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 4
7 3 5 0 – S E R V I C E M A N U A L

Input board
The probes are physically connected to the Input board: this board's main function is that of
connecting the active connector to the Front End.

Four (4) connectors are fitted to the board: three of them are 192 channels connectors for the
electronic probes (PROBE CONNECTOR), and the fourth is for the Doppler probe (PEDOF
CONNECTOR). The selection of the probe is made by signals coming from the Control board.

The connectors of the electronic probes are connected to the 192 CHANNEL SWITCHES block
that sends signals (dual 96 CHANNELS bi-directional buses) coming from the active electronic
probe to the Front End.

The PROBE CODE READER block sends (on request) the active probe identification code to the
Control board.

The HARDWARE CONFIGURATION block has the board configuration which is displayed in the
System Configuration screen.

SECTION 3 5
 1 2 3 4 5 6 7 8 9 10 11

Pedof TX (ELT from TRXCW)

F PEDOF Pedof RX (ELR to TRXCW)
CONNECTOR
HARDWARE CONFIGURATION ICONF0-5 (to TRXCW)

192 CHs
E
PROBE A
96 CHANNELs (CER to/from TRX1)
CONNECTOR 192 CHANNEL SWITCHES
96 CHANNELs (CER to/from TRX2)

D
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

PROBE SELECTION SELA/B, SELB/C (from CONTROL)

192 CHs

PROBE A

C
CONNECTOR

PROBE A

PROBE B OTHER SIGNALS SELECTION TEMP*, MPH1-4, AUX* (to/from CONTROL)

PROBE C

192 CHs
PROBE A

CONNECTOR PBA/B, PBB/C, PED (from CONTROL)

PROBE CODE READER
RLB0-9 (to CONTROL)
A
837 0147 042 Rev.A
FORM:

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" INPUT BLOCK DIAGRAM
A2 ANDREUCCETTI DONNINI ANDREUCCETTI 25/02/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1215 000 SB A 1 1
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 6
7 3 5 0 – S E R V I C E M A N U A L

TRX boards
Two TRX boards are installed in the unit. Each TRX board manages the Reception/Transmission of
the signal from and to the probes. Each board manages 96 channels, therefore the 7350 manages
electronic probes with 192 elements. The two boards are identical and interchangeable.

The transmission pulses, generated by the TXn TRXCELL (n=1-96 high voltage transmitters), are
sent directly to the electronic probe (CER signals). The signals coming from the probe are connected
to the PREn TRXCELL blocks where they are preamplified. They then enter the 32 MUX
RX_CELL blocks to be selected and/or summed before being sent to the internal bus.

The internal bus is a 64 channels one: each TRX board will therefore manage 32 channels to be
obtained as output. The 96 ECH input signals (64 in case of PA probe), are switched or summed with
a proper delay, in order to reduce the channels number.

For each TRX board, the 32 output signals of the MUX enter the VGA+AD DIG CELL blocks, a
variable gain amplifier chain that depends on the TGC curve set by the user. In the same blocks each
signal is digitally converted.

The signals then enter the two receiving blocks RX1 and RX2 (two FPGA devices) that delay, sum
and filter the signals so that the output of the board is a 16 bit data, which represents the RF signal,
that are sent to the Control board.

The Control board loads all the information concerning the delays for the reception into RAM
blocks, delays that are depending on the active probe. The appropriate delays are then sent to the
specific FPGA. The CONTROL block is the interface between the RAM blocks and the Control
board.

SECTION 3 7
 1 2 3 4 5 6 7 8 9 10 11

FDL,/ADD SC

49 32
FDA-C0 3 ADCK0 +1V5A,+1V5B,+1V8A,+1V8B,+2V5
TXH0 CER1 ECH1
F TX 1 PRE 1 ECH1 SCA-B0 2 ADCK0-15
RXCT
ECH65
POWER DISTRIBUTION +2V2
TXL0 TRXCELL(1/4) TRXCELL(1/4) BCH1
VGA+A/D 1 AD000-9 16 20
MUX 1
/ADD TGC

CK40
ECH129
DIG-CELL(1/2) MUX
RX_CELL(1/2) CWCH1

TXH1 CER2 2 GSEL0-1

INTERFACE
ECH2
TX 2 PRE 2 XC2V100 RXADD 10 RX
ADDATA 10X16
TXL1
TRXCELL(2/4) TRXCELL(2/4) RAM 256Kx16 INTERFACE
160

RXADB,RXOEB,RXWEB,RXCEB,RXADSCB
CLOCK DISTRIBUTION
16 7 TRXCK0
RX2
TXH2 CER3
12
ECH3
TX 3 PRE 3
TXL2
TRXCELL(3/4) TRXCELL(3/4)

16

XTXRES,MOD,STB 3

E CONF

PREV0-15,RXSP
CK40

IDX1
6

CONF

6
ADCK16-32

CONFOE
16

CK40
RXADD 10
XC2V1000
RAM 256Kx16
ADDATA 10X16

160 RXADA,RXOEA,RXWEA,RXCEA,RXADSCA
16

FEXPRG,FEXCCLK,FEXDATA,FEWE,FECS0-3
RX1 12
XINIT,XDONE

D XC2S300E
32 CH MUX
96CH TRANSMITTER 16 XILINX BOOT
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

96CH PREAMP CONTROL FEXINIT,FEXDONE

RXCT

32CH VGA+A/D 20 11

CK40

IDX0
XTXSTB,RES,MOD

CK40
TXH RLB

C 96 TX 16
XC2S300
RAM 256Kx16
INTERFACE
TXADD,TXOE,TXWE,TXCE,TXADSC
16

TXL 22
TX

96

16

TXCT

DREADY0
10

CONTROL
FERW

INTERFACE
FEPRG

DTSB,DRES
B
TXSTB,TXRES,RXSTB,TXFRAME

CWCH
4

RAM 128Kx8
LQ
DDATA0-7 (to TRXCW) CW
P? 5
SIGA,B 8
INTERFACE
2
19
FES
RX
C 3
PEDOF
8

SADD

20
SWITCH SUMA,B 3

NF

A ECH32
FDA-C15 3 ADCK31
FILA;B
2
837 0147 042 Rev.A

SCA-B15

CK40
2 NOTCH FILTER
ECH96 BCH32
VGA+A/D 32
FORM:

AD310-9 2
SELPED

MUX 32
TXH95 CER160 ECH160 /ADD TGC
ECH160
TX 96 PRE 96
RX_CELL(2/2) CWCH32
DIG-CELL(2/2)
TXL95 2 GSEL0-1
TRXCELL(4/4) TRXCELL(4/4)

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" TRX BLOCK DIAGRAM
A2 ANDREUCCETTI

Nr. O.V.:
DONNINI ANDREUCCETTI 28/02/05
Document Revision: SHEET: OF:

by EpD E.O.C. EVENT: Number: 950 1212 000 SB A 1 1

DOCUMENTO FIRMATO ELETTRONICAMENTE DOCUMENT ELECTRONICALLY SIGNED
7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 8
7 3 5 0 – S E R V I C E M A N U A L

TRXCW board
The TRXCW board manages the Reception of the Phased Array probes CW Doppler signals and the
Reception/Transmission of the Pedof probe CW signal.

The SWITCH MATRIX block is involved in the CW Doppler reception. It receives the 32 CWCH
signals coming form the VOLTAGE TO CURRENT Converter block and selects the appropriated
tap of the DELAY LINE block with the right delay for the focalization.

The NOTCH FILTER eliminates the Doppler frequency emitted in the event of CW. The signal is
then sent to the following blocks where the Doppler signal is demodulated, amplified and filtered
before being processed by the Doppler board.

On the board the 80 MHz oscillator is mounted (MASTER CLOCK GENERATOR). The CLOCK
DIVIDER generates the sub-multiples of the basic oscillation that are then sent to Control and TRX
boards.

SECTION 3 9
 1 2 3 4 5 6 7 8 9 10 11

ICONF0-5 (from INPUT) HARDWARE CONFIGURATION CONF0-5, /CONFOE2 (to/from CONTROL)

BUFFER & SETTING

TRXCK0-1 (to TRX1, TRX2)

80 MHz MASTER CLOCK GENERATOR CLOCK DIVIDER

D40M (to CONTROL)

E
CK80 (to TRX1)

SELPED (from CONTROL)

ELR (from INPUT) PEDOF RECEIVER RF SWITCH 32 TAPs DELAY LINE

D 31 1 0
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

ELT (to INPUT) PEDOF TRANSMITTER

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

32 INPUT to 32 OUTPUT
CHCH0-31 32 Channels
CWCH1-32 (from TRX1)
SWITCH MATRIX VOLTAGE to CURRENT Converter
XETXP,N (from TRX2)

DDATA0-7, DSTB0-3, DRES (from TRX1)

TP3, TP7 TP2, TP6 TP1, TP8 TP1, TP8

B
33 KHz DSIN, DCOS
NOTCH FILTER CONTROLLED AMPLIFIER DEMODULATORs AMPLIFIER WALL FILTERs AMPLIFIER
LOW PASS FILTER (to DOPPLER)

TP9
NF0-2 (from TRX1) XRF1-2, /XRF1-2 HF0-2 (from CONTROL)
(from TRX2)

DGAIN (from CONTROL)

A
837 0147 042 Rev.A
FORM:

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" TRXCW BLOCK DIAGRAM
A2 ANDREUCCETTI DONNINI ANDREUCCETTI 25/02/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1214 000 SB A 1 1
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 10
7 3 5 0 – S E R V I C E M A N U A L

Control board
The Control board is a complex board that implements several functions:

1. it initialises the TX, RX1 and RX2 blocks in the TRX boards. (FPGA CONFIGURATION
and TRX CONTROL INTERFACE blocks)

2. it programs all the RAMs on the Front End boards involved in the signal reception.
(FOCALIZATION DELAY block)

3. it manages the Front End boards (TRX) during the acquisition scanning (SCANNER
CONTROL block).

4. it processes the radio-frequency signal. (RF DATA PROCESSING, RF LINE MEMORY

and DYNAMIC FILTER blocks)

5. it detects the TGC gains so that the corresponding curve can be generated. (TGC & GAIN
block)

6. it manages a mechanical probe. (MOTOR INTERFACE block)

7. it detects the temperature sensor of the connected probe (TGC & GAIN block).

8. it sends the Clocks to the other digital boards. (CLK block)

9. it implements the scan conversion, generating the memory writing addresses (RHO, THETA
- X, Y CONVERSION, RHO-THETA INTERPOLATION blocks)

10. it applies post processing elaboration (persistence) process to BW, CFM and Contrast data
(PERSISTENCE MEMORY, PERSISTENCE & AVERAGE PROCESS blocks).

11. it manages the scanning generating the proper timings for the Doppler board (PRF TIMING
block).

12. it identifies the connected probes and the active one (PROBE READ & SELECTION
block).

SECTION 3 11
 1 2 3 4 5 6 7 8 9 10 11

Processors Bus
(LA 0-4, LD0-15
LRW, LSCNT, LSSCAN,
LSGW, LSGR)
Control DSP
F Control DSP Bus Processor Interface CK40E
(Tca 0-19, Processor Interface POS
Tcd 0-31) to PROCESSORS
Scanner
to TRX1, TRX2 SCSTOP
Control TRX Control SADD 0-19, RLB 0-15, LQ 0-2,
Micro
TCINT 0-3 FES 0-2, FEPRG, FERW, HF0-2, MOT0, MOT1, PROBE
& Interface TXSTB, TXRES, RXSTB, PI, TXFRAME DL, ML, IL, ACFM0-1
FEXDONE0-1, FEXINIT0-1, X-Y(0-8)
FEXCCLK0-1,FEXPROG0-1 TXS, TCLK, DPTCK
FPGA Scan Converter
to
SCAN_MODE(0-9) VIDEO
TCRESET,FLASH
Configuration TXS, DPTCK
Interface SCCTRL 0-13, SCCTRLRW, SCCTRLCS
(Rho,Theta) - (X,Y)
MCYCLE_START
& to on board FPGA Conversion MRESET_DONE from
VIDEO
E
XDATA 0-7, RFXPROG, RFCSA-B
Focalization CK40B FPGA Configuration DDOT,DLINE from
RFXDONE, RFXINIT, RFXCCLK DOPPLER
CK40A Interface DP1D(0-7)
Delay SCXPROG, SCXCS0-1, SCXDONE,
QM1D(0-15)
Line Line
SCXINIT, SCXCCLK, Ping Pong Ping Pong
Memory Memory
1 2 DP2D(0-7)
BW1WE,BW1OE
BW1A(0-18) QM2D(0-15)
from/to CFM1A(0-18)
KEY TGC
Ping Pong Memory BW2WE,BW2OE
POT 0-6 BW2A(0-18)
TGC, DGAIN Control CFM2A(0-18)
POTREF to TRX1, TRX2
TGC & Gain
TEMP 1-2, TSENSE, PSENSE, POFFS
D
VREF CFMPWE,CFMPOE
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

CFMPA(0-18)
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

BWPWE,BWPOE
from/to
RF Line Board CNPWE,CNPOE
INPUT TCRESET,FLASH
Memory BWPA(0-18)
Boot
CK40D

TXS, DPTCK
from
TRX1
ADIG 0-15 RF Data
BWD0-7, CND0-7
from Processing Frame Frame

SCCLK0,SCCLK1
TRX2 BDIG 0-15 DDOP 0-19 to DOPPLER

THETA_WEIGHT(0-3)
Ping Pong Persistence Ping Pong

LINK(0-15)

RHO_WEIGHT(0-3)
C
Memory Memory
Memory
CONF 0-5 1 2
RFI 0-15 FIROUTCK Board to/from
REAL 0-15
IMG 0-15 Revision CONFOE 0-2 TRX1, TRX2,
TRXCW

CFM1D(0-15) BW2D(0-7)
CK40 A-F
BW1D(0-7) BWPD(0-7) CFM2D(0-15)
Dynamic Filter CFMPD(0-23)
from D5M GSEL0-1 to TRX1, TRX2 CNPD(0-7)
TRXCW to SPR
CK40C TXS, TCLK, DPTCK to DOPPLER, VIDEO
D40M
CLK D40A
B to PROCESSORS CFMON, CFMOFF, MLN0-3, ACFM, DL
to DOPPLER
PRF Timing
D40B MOT0, MOT1, PROBE
to DOPPLER to PROCESSORS
DL, ML, IL, ACFM0-1
D40C
RHO - THETA
to VIDEO MOT0, MOT1, PROBE
Interpolation SCAN_MODE(0-9)
DL, ML, IL, ACFM0-1
Probe Read SELPED, SELA/B, PED, PBA/B TXS, TCLK, DPTCK
AVG_DATA(0-15)
to
& Selection to INPUT, TRX1, TRX2 VIDEO
MCYCLE_START
SCSTOP MRESET_DONE from
CK40F VIDEO
DSP Persistence
Tcint 0-3 Test DAC
&
Interrupt BWD0-7, CND0-7 CFMD(0-17)
A Average DPD(0-7) from
837 0147 042 Rev.A

DDOT,DLINE
process DOPPLER
FORM:

MPH 1-4
MOTOR Interface to INPUT

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" CONTROL BLOCK DIAGRAM
A2 ANDREUCCETTI DONNINI ANDREUCCETTI 25/02/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1216 000 SB A 1 1
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 12
7 3 5 0 – S E R V I C E M A N U A L

Doppler board
The Doppler board receives the signals from the front end and extracts the Doppler (CFM, PW and
CW) information. The PW and CFM radio frequency signals are digital data coming from Control
board while the CW signal, coming from TRXCW board, is analogical.

The CFM SIGNAL DEMODULATION & LP FILTERING block filters the CFM data, de-
modulates it to extract the phase and quadrature components. The MTI FILTERING block extracts
the high frequency components of the signal that are associated with the moving targets. The
AUTOCORRELATION & CFM PARAMETERS ESTIMATION extracts information concerning
the speed, variance and power of the color signal.

The PW SIGNAL DEMODULATION & LP FILTERING + CW SIGNAL DIGITIZING block

demodulates the Doppler signal and digitizes the CW Doppler signal. The DOPPLER
PROCESSING block receives the demodulated digital Doppler signals, extracts its audio component
and calculates the Fourier transform.

SECTION 3 13
 1 2 3 4 5 6 7 8 9 10 11

XIL1_40M XIL1_40M XIL2_40M , XIL3_40M

XIL1_TXS XIL1_TXS XIL2_TXS , XIL3_TXS

XIL1_DPTCLK XIL1_DPTCLK XIL2_DPTCLK , XIL3_DPTCLK

F

RFII MTI CORRELATOR

AUTOCORRELATION VEL
SIN I

to CONTROL BOARD
CFM SIGNAL
CSIN(15:0) CFI(15:0)
&
DEMODULATION MTI FILTERING
E
CFM IN CFM POW
DDIG(15:0)

& (DC REMOVAL)

COS Q PARAMETERS
LP FILTERING CCOS(15:0) CFQ(15:0) VAR
from CONTROL BOARD

ESTIMATION CFMD(15:0)

D
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

CPU INTERFACE DSP

PW IN PW SIGNAL DATA & COMMANDS

DDIG(15:0)
DOPPLER FFT DATA to CONTROL BOARD
PROCESSORS

DEMODULATION ED(31:0)
C DPD(7:0)
BOARD

CPU & ADDRESSES

from

PROCESSING
LATCHES LP FILTERING EA(23:0)

LCA(4:0) , LC(15:0)
LSDOP, LCRW
+
(AUDIO & FFT) AUDIO SIGNAL to VTR, LOUDSPEAKERS & PC BOARD
CW SIGNAL ADVOUT , RECOUT
from SPKR1, SPKN1 , SPKR2 , SPKN2
TRXCW CW IN DIGITIZING LINEINADV , LINEINREC
BOARD DSIN , DCOS

XIL0_40M
B
XIL1_40M

XIL0_40M DSP_CLK GENERAL XIL2_40M

XIL0_TXS XIL3_40M
D40B
XIL0_DPTCLK from TIMING DSP_CLK

CONTROL TXS XIL0_TXS

BOARD & XIL1_TXS

DPTCLK
XIL2_TXS
EXTERNAL AUDIO SOURCES from XIL3_TXS
LSGW
BOARD
from VTR & PC BOARD PROCESSORS XIL0_DPTCLK

ADVIN , RECIN , LINEOUTADV, LINEOUTREC BOARD LSGR XIL1_DPTCLK

A
CONFIGURATION XIL2_DPTCLK
837 0147 042 Rev.A

XIL3_DPTCLK
FORM:

BOARD CONFIGURATION
LC(5:0)

SCHEMA GENERALE
SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:
"7350" DOPPLER BLOCK DIAGRAM
A2 ANDREUCCETTI DONNINI ANDREUCCETTI 25/02/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1217 000 SB A 1 4
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
 Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.
FORM:
837 0147 042 Rev.A The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

by EpD
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

SHEET

A2
B
C
F

A
E

D
1

RFII & MTI

2

LC(15:0) , LA(4:0) , LCRW , LSDOP

XIL1_DPTCLK
XIL1_40M

DDIG(15:0)
3
4

&

LP FILTERING
DEMODULATION

TP2
TP3
5

TESTSIN(15:8)

TESTCOS(15:8)
CSIN(15:0)

CCOS(15:0)
6
7

AD_MTI(10:0) , LN(3:0)
&

BANK
TRACES
DIGITAL

MEMORY
CFM GAIN
HIGH PASS FILTER
8

1J(15:0) , 2J(15:0) , 3J(15:0) , 4J(15:0)

9

CFI(15:0)

CFQ(15:0)

Number:
Document
DESCRIPTION:
TP8
TP5
10

950 1217 000 SB

Revision:
A
"7350" DOPPLER BLOCK DIAGRAM
SHEET:
11

2
OF:
4
 1 2 3 4 5 6 7 8 9 10 11

AD(9:0) , ADA(15:10) , ADB(14:10) , ADP(17:10) , ADQ(14:10) , ADR(14:10)

F

XIL2_40M XIL3_40M

LC(15:0) , LA(4:0) , LCRW , LSDOP LC(15:0) , LA(4:0) , LCRW , LSDOP

XIL2_DPTCLK XIL3_DPTCLK

OCI(15:0)

E OCQ(15:0) M1O(15:0)

MEMORY MEMORY
M1X(23:0) M2O(15:0)
POWER
M2X(23:0) DPO(15:0)

AUTOCORRELATION BANK
CFI(15:0)
BANK CFI(15:0)
ESTIMATION
DPX(23:0) Q(15:0)

AVERAGING DPY(23:0) &

D TP10
CFM POWER
&
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

CFQ(15:0) CFQ(15:0) PARAMETERS CFMD(15:12) , CFMD(7)

PERSISTANCE
CFMD(11:8) , CFMD(1:0)

EXTRACTION
CFMD(6:2)

VELOCITY
C
TP12

TX(8:0) TY(8:0) VE(7:0) VA(7:0) T0(8:1)

VELOCITY
&
VARIANCE
TABLES

A
837 0147 042 Rev.A
FORM:

CORRELATOR
SHEET DESCRIPTION:
"7350" DOPPLER BLOCK DIAGRAM
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SB A 3 4

 1 2 3 4 5 6 7 8 9 10 11

XIL0_40M DSP_CLK

LC(15:0) , LA(4:0) , LCRW , LSDOP

XIL0_DPTCLK

CPU

DDIG(15:0)
DOPPLER
INTERFACE

EA(23:0)
SIGNAL
&
D

DOPPLER PROCESSING
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

ED(31:0)
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

SIGNAL (AUDIO & FFT)

DPD(7:0)

SININ , COSIN
PREPROCESSING
DSIN , DCOS A/D
C

ACLKX0 , ADX0 , ADLL , ADLR

B
AUDIO DAC
&
ADVIN , RECIN , LINEOUTADV , LINEINADV ADVOUT , RECOUT , LINEINADV , LINEINREC , SPKR1 , SPKN1, SPKR2 , SPKN2
AUDIO ANALOG

PROCESSING

A
837 0147 042 Rev.A
FORM:

DOPPLER SIGNAL PROCESSING

SHEET DESCRIPTION:
"7350" DOPPLER BLOCK DIAGRAM
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SB A 4 4

7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 14
7 3 5 0 – S E R V I C E M A N U A L

Video board

The Video board can be divided into three sections:

1. The Image Memory section is where the acquired echo information is physically stored
(SDRAM MODULE block). The section inputs are the acquired echo signal coming from
Control board (acquired echo data), from Processor board (digital archived data) and from
Connectors board (VTR analogical signals). The SDRAM block is controlled through SDRAM
CONTROLLER, that provides the Memory addresses and controls.

2. The ECG section where physiological signals, coming from the Printer ECG board (the ECG)
is processed for presentation on the screen. The ECG signal is sent to the ECG & PHYSIO
ELABORATION block via the ECG & PHYSIO CONTROL INTERFACE. The block filters
the notch, extracts the ECG sync timing and sends the ECG signal to the Processor board
(for possible synchronizing with the ECG being acquired). The ECG data are written into
MEMORY ECG TRACE block. This block sends the data to the Video section for the screen
presentation.

3. The Video section generating the output signals for external monitors and peripherals. The
image data from Image Memory section, the ECG trace and the Graphic data enter the RGB
LOOK UP TABLES block that supply the digital Video signal to be converted to standard
RGB. For the standard television presentation, the data is sent to VIDEO DAC that convert in
the RGB analogue output signals. The data are sent also to the VIDEO ENCODER blocks for
the color printer and the VTR output. The VHS or S-VHS signals can arrive as input to the
Video board from a VTR. The signal from VTR enters the VIDEO DECODER block whose
outputs are sent to the Memory section.

SECTION 3 15
 1 2 3 4 5 6 7 8 9 10 11

TIMEBASE
(CONTROL)
F SDRAM MODULE
CLOCK
& CONTROLS TCLK
IMAGE SCAN

U17
(CONTROL)

SCAN SDRAM
AVG_DATA VTR
DATA

VIDEO
CONVERTER
XY_ADD CONTROLLER PATH
E PATH DECODER

(CONNECTORS BOARD)
SCAN_MODE

VTR IN/OUT
ARCHIVE DATA
(PROCESSORS)
& CONTROLS

U27, U28, U33, U34 U21

DIGITAL

IMAGE
VMA, VMD PROCESSOR WRITEBACK
VISUALIZATION
VIDEO
PATH PATH PATH
FRAME ENCODER

D MEMORY
FPGA U23

PRINTER ECG BOARD)

Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

U30
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

PRINTER OUT
ECG SECTION
(see pag.2/2) VIDEO
ENCODER
FPGA U31

ECG TRACE TV OUT

C GENERATOR
BUFFER

(CONNECTORS BOARD)
U35
RGB

CRT OUT
LOOK UP VIDEO DAC
TABLES
(PROCESSORS)

INTERFACE
GRAPHIC
DATA

GRA GRAPHIC U20

BUFFER
VIDEO SCALER
B
(PROCESSORS)
PULSES

VIDEO
SYNC

VID_HSYNC VIDEO SYNC LVDS

(MOTHER BOARD)
U41
VID_VSYNC GENERATOR RECEIVER

LCD OUT
LVDS
TRANSMITTER

PC DISPLAY IN
(PC BOARD)
A VGA_LVP
837 0147 042 Rev.A

VGA_LVN
FORM:

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" VIDEO BLOCK DIAGRAM
A2 ANDREUCCETTI DONNINI ANDREUCCETTI 25/02/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1219 000 SB A 1 2
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
 1 2 3 4 5 6 7 8 9 10 11

from from
F PRINTER ECG PROCESSORS
Control DSP BOARD BOARD
Processor
Control DSP Bus Bus
MEMORY ECG
(LA 0-4, LD0-15
(Emifa 0-19, Emifd 0-31)
TRACE LSGW, LSGR)
ECG & PHYSIO ( Tmsclk,Emifclk2,
Elaboration Emifce (0-3),Tmsint(0-3)
eawe,eaoe,eare) ECG PHYSIO
&
CIRCUIT CIRCUIT
FPGA MDAT(0-15),MADD(0-11)
RESET,FLASH
Configuration MBADD(0,1)
E &
TFT Brightness
CLK40A Control Ecgsclk,Ecgconv,Ecgdata

Phsclk,Phconv,Phdata

ECG to PROCESSORS BOARD

ECG & PHYSIO

Control Interface Trace(0-1)

to on board Video Fpga

D
Vid_Hsync,Vid_Vsync
FLASH BOOT from on board Video Fpga
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

Processor
Interface VMA(0-29),VMD(0-15)
to/from PROCESSORS BOARD
C
FLASH PROGR

FPGA
VXDATA 0-7, VXPROG, VXCS(0-1)
Configuration to on board FPGA
VXDONE(0-1), VXINIT(0-1), VXCCLK
RAM Interface
ECG SAMPLES
BRD(0-7), BRCS, BRWR
PHYSIO SAMPLES to on board D/A
B
TFT Brightness Lcdsleep to KEY TGC BOARD
Control Interface
CLK40B

A from D40C CLK CLK40 A-C

CONTROL
837 0147 042 Rev.A

BOARD
ECG SECTION
FORM:

SHEET DESCRIPTION:
"7350" VIDEO BLOCK DIAGRAM
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1219 000 SB A 2 2

7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 16
7 3 5 0 – S E R V I C E M A N U A L

Processor board
The Processor board contains the central processor (68340 block). The board is interfaced to the PC
board (containing an other CPU) through the block PCI/68K DUAL PORT COMMUNICATION
MEMORY block.

The central processor manages the system, contains the resident program and the AOD probe
management tables. Management of graphic memory, physically located on the board itself
(GRAPHIC MEMORY block), takes place through the GRAPHIC MEMORY MANAGER and
DRAWING ENGINE blocks thus making it possible to superimpose the graphics on the echo
image.

The central processor also manages the interface with keyboard, trackball and encoders
(PERIPHERALS MANAGER and KEYBOARD ENCODERS TRACKBALL blocks), the remote
control of VTR, through serial interface, and the footswitch.

The EEPROM block, residing on the Mother board, contains all the general machine information
(configuration, setup).

The two DSP blocks at start up program the two FPGA 0 and 1. Their principal function is to
interface the Image Memory with the PC board. In the DSP1 block also the JPEG compression
takes place.

SECTION 3 17
 1 2 3 4 5 6 7 8 9 10 11

FPGA #0
ECG Memory

(VIDEO board)
F

VMD(15..0), VMA(29..0), VMMODE, VMRW, -WMACK

-VMDS, -VMAS, -VMBH, -VMBL
ECG Image Memory
DSP/ Image Memory
ED(31..0), EA(21..2) Manager Image Memory
-AWE, -FPGA_WR
Dual Port FIFO
DSP #0
(VIDEO board)

Communication Memory

-LSVID, -LSECG, -LSPS, -LSSCAN

SDRAM
glue logic -LSDOP, -LSGR, -LSGW, -LSCNT, LC(15..0)
(16MB)
Latches (OTHER boards)
E
PCI / 68k

FLASH Dual Port

(2MB)
SRAM
Communication Memory
(1MB)

CPU_D(15..0), CPU_A(23..0), -CPU_AS, -CPU_DS

CPU_RW, CPU_SIZE1, CPU_SIZE0, CPU_FC(3..0)

FLASH
(4MB)

-DSP_SAFE, -EXTDEV

D
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

FPGA #1

CLKX0R1, FSX0R1, DX0R1

CLKX1R0, FSX1R0, DX1R0
-TXD, RTS, DTR
-RXD, CTS, DSR, DCD
Debug I/O (PRINTER ECG board)
PCI_AD(31..0), -PCI_CBE(3..0)
-PCI_REQ0, -PCI_GNT0
68k Bus
-PCI_DEVSEL, -PCI_FRAME, -PCI_RST 68340
-PCI_INTA, -PCI_INTB, -PCI_INTC glue logic
-PCI_IRDY, -PCI_STOP, -PCI_TRDY
-TXD1, RTS1, DTR1
PCI Bus -RXD1, CTS1, DSR1, DCD1
VTR Output (CONNECTORS board)
(to /from PC board)

Drawing Engine
C XED(15..0), XEA(21..2)
-XAWE, -XFPGA_WR

DSP #1

Graphics Memory

Manager DM_A(12..0), DM_DQ(15..0)

DM_DQML, DM_DQMH
Graphic
-DM_RAS, -DM_CAS, -DM_WE
SDRAM
DM_BA1, DM_BA0, -DM_CS
(16MB)

Memory

FLASH
(2MB)
B
Pheripherals Manager
KB_CLK, KBDAT, MS_CLK, MS_DAT
Serialize/Deserializer
(to /from PC board)

ROW(15..0), COL(15..0)
ENCLA, ENCLB, ENCRA, ENCRB
MM_SO, MM_SI, -MM_HOLD
TRKXA, TRKXB, TRKYA, TRKYB
-MM_CS, -MM_WP, -MM_SCK
GRA(15..0), VID_HSYNC, VID_VSYNC -ECG, -POS, -ESCAN, -TBASE, -MOT0, -MOT1, -TIMING, _PROBE

A Keyboard, Encoders,
VIDEO Board
837 0147 042 Rev.A

Trackball, Interrups
EEPROM (MOTHER board)
FORM:

Not on this board element

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" PROCESSORS BLOCK DIAGRAM
A2 ANDREUCCETTI DONNINI ANDREUCCETTI 25/02/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1218 000 SB A 1 1
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 18
7 3 5 0 – S E R V I C E M A N U A L

PC board
The PC board contains the PC STANDARD ETX MODULE block, a CPU that manages digital
filing and contains the LAN and USB connectors. Two USB connectors are duplicated on the front
panel through the “61XX” UHP, USB Head board.

The ETX block has access to the Image and ECG memories on Video board through the
DSP/IMAGE MEMORY DUAL PORT COMMUNICATION MEMORY and ECG IMAGE
MEMORY MANAGER blocks on Processor board.

The internal Hard Disk is physically mounted on the PC board.

SECTION 3 19
 1 2 3 4 5 6 7 8 9 10 11

E /WDATA, /WGATE, /STEP

/DIR, MOT, /RDATA
Floppy /HDSEL, /TRK0, /INDEX

Disk
PC Headphone, Microphone +5_STB (from SPS)
POWER ON
SWITCH_ON_OFF (from KEY TGC)
MODULE
RS232 POWER_ON_OFF (to SPS)
PC COM1
driver

PC monitor out

950 1172 000

PS_ON 5V_SB, /PWRBTN "61xx" UHP, USB Head

PCI Bus
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

+/-USB0
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

USB

PCI_AD(31..0), -PCI_CBE(3..0)
-PCI_REQ0, -PCI_GNT0 /USB_OVCR
USB Driver
-PCI_DEVSEL, -PCI_FRAME, -PCI_RST
-PCI_INTA, -PCI_INTB, -PCI_INTC
-PCI_IRDY, -PCI_STOP, -PCI_TRDY +/-USB1
(to /from PROCESSORS board) USB

+/-USB2
USB

PC Keyboard,
PC Standard ETX module USB Driver

C PC Mouse +/-USB3
USB

+/-LAN_TXD
KB_CLK, KBDAT, MS_CLK, MS_DAT (to/from PROCESSORS board) LAN
+/-LAN_RXD

insulated LAN
transform

Secondary IDE Bus

Audio CD L/R
SIDE_D(15..0), SIDE_A(2..0), -SIDE_IOWR, -SIDE_IOR
-SIDE_DRQ, -SIDE_AK, -IOCS16, -HDRST Primary IDE Bus
-SIDE_CS3, -SIDE_CS1, SIDE_INT, SIDE_RDY
B
PIDE_D(15..0), PIDE_A(2..0)
-PIDE_IOWR, -PIDE_IORD
910 2821 000 VCC -PIDE_DRQ, -PIDE_AK
-IOCS16, -PIDE_CS3, -PIDE_CS1
+12 +12 PIDE_INT, PIDE_RDY, -HDRST

Compact
9730650084 FLASH
CDRW HARD
REGULATOR FAN Regulator
DISK

A
837 0147 042 Rev.A

+15V_PC +12
FORM:

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" PC BLOCK DIAGRAM
A2 ANDREUCCETTI
DONNINI ANDREUCCETTI 25/02/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1225 000 SB A 1 1
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
7 3 5 0 – S E R V I C E M A N U A L

SECTION 3 20
7 3 5 0 – S E R V I C E M A N U A L

MAINS POWER, SPS and SPR boards

The Main Pwer, SPS and SPR boards form the unit Power Supply.

The SPS board is connected to the mains power through the MAINS POWER board. It is an Alpha
Bridge, universal switching board (100-240 V) with PFC control. The layout has an EMI/RFI filter
with the straightened and isolation transfer in cascade. The board outputs are the two 15V DC power
supply for the SPR and the PC board and the 12V DC power supply for the fan.

The SPR board contains the DC converters that supply the VCC, +3V3, +2V2, +/-6, +VT DC
power supplies for all the boards and the high voltage +/-VAT for the transmitters.

SECTION 3 21
 1 2 3 4 5 6 7 8

LINE SECTION

D N FUSE

L
DIODE 4x PFC
FILTER BRIDGE
(+375V)

8820060000
(CAVALLOTTO)
/EN +12L

Test Points

4 PERIPHERALS
MAINS VAC
+/-VR

950 1140 000

N N
"61xx" MAINS POWER
/EN (Enable) +12L +12L /EN
C L L

PERIPH. ECHO 4x
FUSEs FUSEs
ON / OFF FLYBACK DC / DC
CONTROL BRIDGE
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

N
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

MAINS
L
SWITCH

+15V_TEL +5_STB +Vout GND

B
Test Points
+15
+5_STB
(to PC, KEY TGC)

GND

FILTER
POWER_ON_OFF (from PC) ON / OFF FILTER +15V_ECHO

/FAULT (from other BOARDs)

CONTROL

VCC FILTER +15V_PC

FILTER +15V_TEL
& FUSE

A REGUL. +12V_VENT
837 0147 043 Rev.A
FORM:

Temperature SENSOR

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

SPS BLOCK DIAGRAM
A3 ANDREUCCETTI DONNINI ANDREUCCETTI 28/02/05
Document Revision: SHEET: OF:

by EdP
Nr. O.V.:
E.O.C. EVENT: Number: 950 1100 000 SB A 1 1
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
 1 2 3 4 5 6 7 8

BUCK
+12V
VCC
SYNC.

D
+3V3

BUCK
LC
+3V3A
FILTER
SYNC.

LINEAR
+15V_ECHO (from SPS) +2V2
REGULATOR

BUCK LC
+2V2A
FILTER
SYNC.

BUCK
+6V
C SYNC.

BUCK
-6V
SYNC.
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

BUCK
+VT
SYNC.

B
+VAT
FLYBACK LINEAR
PS* (JTAG from VIDEO)
HI
REGULATOR
-VAT

LC0-15, LCRW, /LSPS (from PROCESSORS) CONTROLLER

D5M (from CONTROL)

FLYBACK LINEAR
LOW
REGULATOR

A
+12V
837 0147 043 Rev.A
FORM:

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" SPR BLOCK DIAGRAM
A3 ANDREUCCETTI DONNINI ANDREUCCETTI 28/02/05
Document Revision: SHEET: OF:

by EdP
Nr. O.V.:
E.O.C. EVENT: Number: 950 1220 000 SB A 1 1
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
7 3 5 0 – S E R V I C E M A N U A L

KEY TGC, KEY SWITCH and SOFT KEY boards

For mechanical reasons, the keyboard controls are splitted into three boards: KEY TGC, KEY
SWITCH and SOFT KEY boards.

Under the control of the Processor board, the Keyboard is the interface board so that it manages
the alphanumeric keys, the trackball and the gain encoders.

The TGC board mounts eight (8) potentiometers and the three (3) keyboard leds.

Through the Soft Key board pass also the two audio signals for the loudspeakers.

SECTION 3 22
 1
7 3 5 0 – S E R V I C E M A N U A L
Chapter

1 - Traceability
The traceability of a 7350 part can be based on:

• its Serial Number (S/N)

• its Lot Number
The Serial Number of a 7350 part is composed of two (2) or more figures. It is
reported in a label affixed to:

• board: on the labels bar or on the printed circuit

• unit: on the rear panel
The Lot Number of a 7350 part is always composed of ten (10) numbers: the first
four numbers correspond to the manufacturing year of the part, the remaining six
are progressive figures. It is located on a label affixed to the part chassis.

The following 7350 Part Lists identify all parts that are treaceable and their
corresponding traceability key.

SECTION 4 1
7 3 5 0 – S E R V I C E M A N U A L

SECTION 4 2
 2
7 3 5 0 – S E R V I C E M A N U A L
Chapter

2 - Parts list

7350 REF 9707350000 100-230V 50/60 Hz

REFERENCE DESCRIPTION QTY TRACEABILITY ESD

9501215000 INPUT 1 S/N Y

9501212000 TRX 2 S/N Y
9501214000 TRXCW 1 S/N Y
9501216000 CONTROL 1 S/N Y
9501217000 DOPPLER 1 S/N Y
9501218000 PROCESSOR 1 S/N Y
9501219000 VIDEO 1 S/N Y
9501220000 SPR 1 S/N Y
9501100000 SPS 1 S/N Y
9501225010 PC ASSEMBLY 1 S/N Y
9501226000 CONNECTORS 1 S/N Y
9501227000 PRINTER ECG 1 S/N Y
9501223000 KEY TGC 1 S/N Y
9501221000 KEY SWITCH 1 S/N Y
9102972000 SOFTKEY GROUP 1 - Y

ESD: Electrostatic Discharge

Read carefully the instructions in Section 2 for spare parts composition and
N O T E
assembling.

SECTION 4 3
 7 3 5 0 – S E R V I C E M A N U A L

7350 Covers and Membranes

Neither any 7350 cover nor membrane are considered a traceable part or to be sent
in advance.

Chassis Section

REFERENCE DESCRIPTION QTY

9102963000 RIGHT BUMPER 1

9102964000 LEFT BUMPER 1
9102967000 FRONT BUMPER 1
9102966000 REAR BUMPER 1
9102961000 RIGHT COVER 1
9102962000 LEFT COVER 1
8107601500 FRONT COVER 1
9102965000 REAR COVER 1
9102869500 UPPER METALLIC COVER 1
8108201500 UPPER LATERAL METALLIC 2
COVERS
8107946500 UPPER METALLIC SMALL 1
COVER
9102968000 UPPER PLASTIC COVER 1
8107410000 POSTERIOR WHEEL COVER 2
8107691000 RIGHT LIFTING HANDLE 1
8107692000 LEFT LIFTING HANDLE 1
8107649000 REAR LIFTING HANDLE 1

Read carefully the instructions in Section 2 for spare parts composition and
N O T E
assembling.

SECTION 4 4
 7 3 5 0 – S E R V I C E M A N U A L

Keyboard Section

REFERENCE DESCRIPTION QTY

8107851000 FRONT HANDLE 1

9102619000 PROBE HOLDER 5
8107368000 CABLE HOOK 5
9102623000 ECG CABLE HOLDER 1
8107913000 GEL HOLDER 1
9102969000 LEFT PROBE SUPPORT 1
8107852000 RIGHT PROBE SUPPORT 1
9102970000 KEYBOARD COVER 1
8107987000 B/M MEMBRANE 1
8107985000 B/M MEMBRANE SUPPORT 1
8107986000 DOPPLER MEMBRANE 1
8107984000 DOPPLER MEMBRANE 1
SUPPORT
8107460000 SHUT DOWN MEMBRANE 1

Softkey Section

REFERENCE DESCRIPTION QTY

8108034000 SOFTKEY REAR COVER 1

8107715000 SOFTKEY UPPER COVER 1

Read carefully the instructions in Section 2 for spare parts composition and
N O T E
assembling.

SECTION 4 5
 7 3 5 0 – S E R V I C E M A N U A L

Spare Parts List

No Spare Part is considered a traceable part or to be sent in advance.

Chassis section

REFERENCE DESCRIPTION QTY

9102821000 SPS FAN 1

9102932000 BOARDS FAN 1
9102821000 PC ASSEMBLY BOARD FAN 1
9730650084 COMBO DRIVE 1
9102867000 PROGRAMMED HDD 1
1000000109 FRONT WHEEL 2
8107810500 POSTERIOR WHEEL 2
883023014 50 CNT COMBO DATA FLAT CABLE 1
8830766000 COMBO POWER CABLE 1
8830753000 COMBO AUDIO CABLE 1
2600000188 12.5V 250V T SPS FUSE 1
26222100023 5A 250V T FUSE (230V) 2
26222100102 4A 250V T FUSE (230V) 2
2600000029 6.3A 250V T FUSE (115V) 2
2600000101 10A 250V T FUSE (115V) 2

Read carefully the instructions in Section 2 for spare parts composition and
N O T E
assembling.

SECTION 4 6
 7 3 5 0 – S E R V I C E M A N U A L

Keyboard section

REFERENCE DESCRIPTION QTY

3400000053 TRACKBALL 1
9102971000 PC KEYBOARD 1
8105816000 TGC SLIDER CAP 7
8107470000 SMALL ENCODER 3
8107469000 LARGE ENCODER 2
8107471503 POWER BUTTON 1
8107471505 AUDIO BUTTON 1
8107471527 DEPTH BUTTON 1
8107471504 DOPPLER BUTTON 1
8107471509 B/M BUTTON 11
8197468500 RIGHT MOUSE KEY 1
8197466500 LEFT MOUSE KEY 1
8107467500 CENTRAL MOUSE KEY 1
3400000039 TGC SLIDER POT 7
8830892000 TRACKBALL CABLE 1
8830232029 KEYBOARD FLAT CABLES 2
Read carefully the instructions in Section 2 for spare parts composition and
N O T E
assembling.

Softkey section

REFERENCE DESCRIPTION QTY

9102834000 LOUDSPEAKER 2
8830299013 35 CNT SOFTKEY FLAT CABLE 1
Read carefully the instructions in Section 2 for spare parts composition and
N O T E
assembling.

SECTION 4 7
7 3 5 0 – S E R V I C E M A N U A L

SECTION 4 8
 3
7 3 5 0 – S E R V I C E M A N U A L
Chapter

3 - Hard Disk
Replacement
Whenever the programmed Hard Disk has to be replaced, please carefully follow
the detailed procedure below.

Note

The programmed Hard Disk is always delivered by Esaote with the

last software release installed. Please remind to install the last software
release in the unit if not already done.

Procedure
Once the Hard Disk has been replaced and the PC Assembly board has been
reinstalled, set the following parameter:

• Press key and select GENERAL PRESET.

• Set the Data/Times.
• Press OK to confirm.
• Wait till the message appears, press OK and then turn the unit off by
pressing the Shut Down key. Turn the unit on.
• If necessary, re-configure the network (Hard Disk Configuration
menu).
• If necessary, set the DICOM Server and Printer configurations.
See Section 5 for PC • If necessary, install the PC printer and set the printing preferences of
printer installation
procedure
the PC printer (PC Printer Configuration menu).

If the presets (such as User Presets, Probe Presets, Application Measurements

presets) have been previously saved through the option “Save & Load Presets” of
the key, they can be loaded to be restored only when the “Save & Load
Preset” operations are done with the same software release.

SECTION 4 9
7 3 5 0 – S E R V I C E M A N U A L

SECTION 4 10
 4
7 3 5 0 – S E R V I C E M A N U A L
Chapter

4 - Main Power Cables

The 7350 unit is equipped with power cord cables having the following
characteristics:

Device Plug Conductors Section Length

Socket #
CEE plug EN60320/C1 VII (7) VII 3 1,5 mm2 2,5 m
9 type; type; 16A-
16A-250V 250V
(European)
CEI plug EN60320/C1 Type I/3 /16 3 1,5 mm2 2,5 m
9 type; type; 16A-
16A-250V 250V
(Italian)
NEMA plug EN60320/C1 NEMA 5-15 3 AWG 3m
9 type; type; 15A- 14
15A-250V 250V
(Medical
grade)

According to the IEC 60601-1 standard these cables are marked by a competent
body (TUV, UL, IMQ,..).

If these cables can’t be used in your country because of the plug, they can be only
replaced by other power cord cable having the same characteristics including the
Safety mark.

SECTION 4
11
7 3 5 0 – S E R V I C E M A N U A L

SECTION 4
12
 1
7 3 5 0 – S E R V I C E M A N U A L
Chapter

1 - Service Menu
The key provides access to the Service menu. The key can be pressed both in
real-time and in freeze state. The system displays this window:
The Service key is
required

Select the SERVICE option with the trackball and press ENTER to continue. The
system displays the following Service menu:

To access the different folders, position the trackball on the required folder tab and
press ENTER.

Settings Option
This options is internally organized in folders This procedure makes it possible:

SECTION 5 1
 7 3 5 0 – S E R V I C E M A N U A L

• To chose the default language and logo

• To set the ECG notch filter
• To activate Demo licenses
Once entered the SETTINGS option, the system displays:

The menu is organized in three folders.

Parameter Setting • Position the trackball on the field to be changed and press ENTER to
confirm.
• Use the alphanumeric keyboard to type in the characters.
• In the drop down menus, select the required option and press ENTER
to confirm.
• Press OK to confirm.
The Tab ' key is used to jump over quickly from field to field; the keys Pgup c
and Pgdn d open the drop down menus and scroll among the relevant options.
After the modifications have been confirmed, the system displays the following
message:

Language Settings Folder

This procedure is used for choosing the default language, notch filter and logo.

Languages One of the following languages can be set as default one:

• English

SECTION 5 2
 7 3 5 0 – S E R V I C E M A N U A L

• Italian
• French
• German
• Spanish
With the exception of Italian, German, Spanish and French language countries, all
N O T E
7350 units delivered by Esaote have English as the default language.

Logo The logo is used in the screen as the sector orientation icon. Either Esaote (E) or
Biosound (B) logo can be set. No logo can be selected too.

ECG AC Filter According to the mains frequency used in the country, the Notch filter for the
ECG signal must be selected. This is the filter that removes the mains frequency
interference from the ECG signal.

7350 is already set according with the Mains frequency of the country where it will
N O T E
be delivered.

Licenses Folder
This procedure enables activations of the available Demo licenses and, when
necessary, to disable licenses. Demo licenses last two hundreds (200) working
hours before expiring; once expired, it can not be re-activated. If a demo license is
installed, it is possible to check its expiring date.

To activate a demo license position the trackball on the desired field and press
ENTER to confirm. Use the same procedure to disable licenses.

In this example, the

CnTI demo license
can be activated

Save and Load Configuration

This procedure allows to save and retrieve all the factory settings (both user and
service presets), the unit Serial Number and the unit licenses (demo licenses are not
saved!) in the internal E2PROM.

SECTION 5 3
 7 3 5 0 – S E R V I C E M A N U A L

We strongly recommend to save the system configuration whenever the Service

technician modifies the settings and whenever the unit is upgraded.

Upgrading the 7350

Usually the procedure to upgrade a 7350 with a new software release has three
main steps:

• Firmware upgrade
• Windows upgrade
• Internal processor re-synchronization
Typically the support used to upgrade the unit is a CD containing all necessary
files.

The upgrading procedure will remove the drivers of all PC printers added by the
N O T E
service. The PC printer driver CDs are necessary to install again the printers.

The upgrading procedure will cancel the network settings. Before starting the
upgrade, copy all the settings so that the network can be configured again.

The upgrading could remove the Dicom settings. Before proceeding with the
upgrade, copy the Dicom configuration so that Dicom can be configured again
should it be necessary.

Firmware Upgrade
The firmware upgrade is performed through the Service menu.

Firmware 1. Turn on the unit with the Service key inserted.

upgrading
procedure
2. Enter Real-Time.
3. Press and verify if there are archived exams. If so, open the first
and last exams and annotate which images are archived and if the
report exists (the same check will be asked at the end of the
upgrading).
4. Access to the Service menu.
5. Select the option “Firmware upgrades” using the trackball and the
ENTER key to confirm.

SECTION 5 4
 7 3 5 0 – S E R V I C E M A N U A L

6. The system displays the window (left) allowing

the selection of the upgrade source drive.
Choose the drive and press OK to confirm.

7. The system shows a list of the files to be

installed. All the files marked with a cross will
be loaded. Press OK to start the programming
procedure

8. The upgrade procedure is automatically

executed: once reprogramming has been
started, a series of screens indicating the
progress of the upgrade procedure appears on
the display.

9. At the end of upgrading procedure, the

system displays the Start Exam window.
If the upgrade procedure has not been carried out correctly, an error message will
be displayed to indicate which file has not been reprogrammed correctly. In this
case, the procedure must be repeated.

Windows Upgrade
Upgrading 10. Leaving the upgrading CD inserted, switch the unit off, remove the service
procedure key and then switch the unit on again.

The service key must be removed in order to be sure that the upgrading procedure
N O T E
ends successfully.

11. At start up the HD programming from CD is automatically started. The

upgrade progress can be controlled by pressing the keys Ctrl + Alt +
from Real-Time: the upgrade status bar is displayed on unit screen. The
upgrade is finished when the following string appears on the screen:

a:\ghost>

12. Extract the CD and switch the unit off and on again.

Processors Re-synchronization
Upgrading 13. Wait for the Start End window. During this step (that could last some
procedure minutes) the HD icon stays grey since the system is re-programming its
devices.

14. Press the key.

15. Select “General preset” option.

16. Once you have accessed to the preset menu, press OK to confirm.

SECTION 5 5
7 3 5 0 – S E R V I C E M A N U A L

17. Wait till the hourglass disappears and then switch the system off by
pressing the shut down key.

18. Turn the unit on and enter Real-Time.

19. Press FREEZE and then POINTER. Verify that there is no purple shadow
around the displayed mouse cursor. If so, insert the upgrading CD and
repeat the procedure starting from point 10.

20. Press and verify the correspondence of the first and last exams.
Should any inconsistency be noted, run the “Recover archive” procedure
(Hard Disk menu).

At the end of the upgrading procedure, insert again the service key to configure, if
necessary, the PC printer, the network and the Dicom server. Remind to save the
new configuration (“Save & Load Configuration” option of the Service menu) and
to print out the new System configuration screen.

Note

If the upgrading procedure is interrupted before its completion,

remember to start it again from the beginning.

SECTION 5 6
 2
7 3 5 0 – S E R V I C E M A N U A L
Chapter

2 - Hard Disk
Configuration Menu
This procedure can be activated only if the Service key is inserted before switching
on the unit.
The Service key is
required To activate the HD Configuration menu the trackball has to be switched to pointer
mode: press FREEZE and then the key to activate it.

Place the pointer on the Hard Disk icon and press UNDO key. The system displays
the following Hard Disk configuration menu:
Hard Disk icon

Place the pointer on the desired option and press ENTER to confirm the selection.

Properties
See the Operator The system displays the free disk space, the name and the IP address of the unit
manuals for further and its AE Title. This option is always available (i.e. it does not require the Service
details
key to be shown).

Network Configuration
This option allows the network to be configured. It is necessary to have a working
knowledge of networking environments. Prior to starting the configuration
procedure, determine characteristics of the network like the addressing mode (fixed
or DHCP), the default gateway IP address, if a DNS server is present and so on.
Thus it is suggested to contact the network administrator before proceeding with
the configuration.

SECTION 5 7
 7 3 5 0 – S E R V I C E M A N U A L

The Network board inside 7350 works at 100 Mbit per second.
N O T E

Once activated, the equipment displays the Windows® XP Network configuration

menu.

Configuration • Double click on Local Area Connection Network icon.

procedure
• The system displays the following screen:

• Place the cursor on the “Internet Protocol (TCP/IP) option” and

highlight it by pressing ENTER.

SECTION 5 8
7 3 5 0 – S E R V I C E M A N U A L

• Place the cursor on “Properties” button and activate it by pressing

ENTER.

• The system displays the following TCP/IP configuration menu:

This menu allows selecting either a fixed IP address or a DHCP (Dynamic

Host Configuration Protocol) address and to set the DNS addresses, when
necessary.

• Set the desired parameters and press OK to confirm.

The network settings will be operative at next start up.

IP Address Configuration
This option allows the user to set the network or to modify some parameters. In
this window the user can define a dinamic or static addressing. In this latter case
the user can set or modify the IP address, the subnet mask and the gateway
address.

SECTION 5 9
 7 3 5 0 – S E R V I C E M A N U A L

Export Log Files to USB

This option allows the user to save onto a USB key the log files. To save the log
files, insert a USB dongle into one of the two connectors on the front panel and
activate the procedure.

Whenever a problem occurs in the field it is strongly recommended to provide

N O T E
Esaote Service with the unit log file.

Recover Archive
The system has been designed to preserve as much data integrity as possible . This
procedure allows rebuilding of the archive, if the hard disk is corrupted.

Do not switch the unit off while this procedure is running. The Hard Disk
W A R N I N G
could be damaged.

Exams not Archived

See the Operator This option shows the list of exams which have been performed and not archived
manuals for further into the local database. From this window you can select the exams to be saved
details
onto the local hard disk.

Hard Disk Menu in Archive Review

When in Archive Review the Hard Disk configuration menu is different:

The Service key is

required

The last two options of the menu allows to back up and to restore the whole
internal archive or part of it (the exams are in the native format).

Back Up The internal archive can be stored either in an USB pen drive or in a remote disk
Procedure (shared directory in a PC).

• Press ARCHIVE REVIEW key.

• If necessary, select the exams to be backed up.
• Place the pointer on the HD icon and press UNDO.

SECTION 5 10
 7 3 5 0 – S E R V I C E M A N U A L

• Select the “BACKUP ARCHIVE” option.

• The system displays the following shot:

• Press the DESTINATION button to select the back up folder.

Note

The backup folder has to be empty! The DESTINATION button allows

to create a new folder.

• Once selected press START to copy the internal archive.

During the back up procedure the STOP button interrupts the copy of the internal
archive.

Restore Procedure • Press ARCHIVE REVIEW key.

• If necessary, select the exams to be backed up.
• Place the pointer on the HD icon and press UNDO.
• Select the “RESTORE ARCHIVE” option.
• The system displays the following shot:

SECTION 5 11
7 3 5 0 – S E R V I C E M A N U A L

• Press the SOURCE button to select the back up folder.

• Once selected press START to copy the internal archive.
During the restore procedure the STOP button completes the copy of the exam
under process and then stops the restore of the internal archive.

SECTION 5 12
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7 3 5 0 – S E R V I C E M A N U A L
Chapter

3 - PC Printer
Configuration Menu and
PC Printer Installation
The listed procedures can be activated only if the Service key is inserted before
switching on the unit.
The Service key is
required 7350 manages both USB and Inkjet printers. Please refer to web site for the list of
the printers directly managed by 7350.

Once one of this printers is connected, the system automatically recognizes it and
shows the PC Printer Icon on screen.
PC Printer icon
To activate the PC Printer Configuration menu the trackball has to be switched to
pointer mode: press FREEZE and then the key to activate it.

Place the pointer on the printer icon and press UNDO key. The system displays the
following menu:

Place the pointer on the desired option and press ENTER to confirm the selection.

Operations
See the “Operator The operator can control the print queue and set print preferences .
manuals” for further
details

SECTION 5 13
 7 3 5 0 – S E R V I C E M A N U A L

This option is always available (i.e. it does not require the Service key to be shown).

Configuration
This option allows the default printer to be set if more printers have been
configured.

Place the cursor on the PC printer icon and press UNDO key to open the menu.
Select “Set as default printer” to activate it.

Print to PC printer now

See the “Operator This option allows immediate printing without waiting to complete the set printer
manuals” for further format. This option is always available (i.e. it does not require the Service key to be
details
shown).

PC Printer Installation
7350 supports both Laser and Inkjet USB PC printers. Some printers drivers are
already installed on the unit:

Printer Model
Laser B/W HP 1150
Laser CFM Tally 8008
Inkjet Epson C86, HP 1100
These printers can be directly connected to the system.
Refer to the protected Anyway it is possible to connect to the unit any other PC printer, once the printer
web site for further driver is installed on the unit itself.
instructions on PC
printers installation

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Installation of a PC Printer with pre-installed driver

Procedure
• Connect the PC printer to one of the unit USB connector.
• Turn both the printer and the system on.
• Enter real-time.
• Press MENU key.
• Select “Peripherals” option.
• The system displays the following menu:

• REC/PRINT fields 1 and 2 are used to select the required peripheral

to be remotely controlled by the keys 1 and 2. Select “Windows
printer” in the desired field to activate the PC printer.
• Once the printer has been set, select the print format on the second
drop-down menu. The available formats are listed below together with
their pertaining icon.

1x1 format 2x2 format

2x1 format 3x2 format

• Press OK to confirm.
• Wait for the message asking to restart the unit and then switch the unit
off.
• At next start up the unit will display on the right side of the header bar
the PC printer icon alongside with the icon of the selected format.

PC Printer
Icon

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Installation of a PC Printer
Before starting the installation procedure be sure to have the printer installation
driver CD with you. The procedure runs like a printer installation in Windows.

Procedure
• Connect the PC printer to one of the unit USB connectors.
• Turn both the printer and the system (with the service key inserted)
on.
• Enter real time and press ARCHIVE REV key.
• Press Ctrl + Esc keys to display Windows bar menu.
• Select “Settings” and the “Printers and Faxes” option, as shown in the
below screenshot.

• The system displays the following Windows Printer and Faxes menu:

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• Select option “Add a printer”. The systems displays the Windows new
hardware wizard for printers.

• Select “Install from a list or specific location” as shown in the screenshot and
then press “Next”
• Insert the printer driver CD in the unit.
• Please note that only the printer driver has to be installed! Any other
printer program which might be listed or proposed during this
installation phase has to be disactivated.
• Select “Include this location in the search” and browse selecting only the
Windows-XP printer drivers in the installation CD and then press
“Next”.
• The system starts copying files. When the operation is completed press
“Finish”. The installed printer is displayed in the “Printer and Faxes”
window.
• Print a test page to make sure the printer is functioning properly.
• Proceed with the printer configuration through the MENU key, as
already explained for the printer with already installed drivers.

Installation of a Network PC Printer

It is necessary to have a working knowledge of networking environments: it is
suggested to contact the network administrator before proceeding with the
configuration.

The described procedure refers only to “Point to Point ad hoc” connection: this
connection has to be a stand alone one. During the installation the printer IP
address is required: read the printer instructions to know how to get and set it.

Note

The software release STD ≥ 4.01 is required.

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Procedure • Insert the Service Key into the system and switch it on.
• Enter Real-Time, press ARCHIVE REVIEW and wait until the archive is
displayed.
• Switch the printer on.
• After the printer startup is done, connect the printer with the cross
cable to the unit.
• Press Ctrl + Esc keys to display Windows bar menu.
• Select “Settings” and then “Network connection” to set the unit IP address.
The unit IP address must be different from the Printer one (in the
following pages and shots the printer IP address is supposed to be
192.168.0.246 with subnet mask 255.255.255.0, the unit IP address is
supposed to be 192.168.0.245 with the same subnet mask).
• Double click on “Local Area Network”, highlight the TCP/IP protocol
and then press “Properties”.
• Set the unit IP and subnet mask addresses.

• Press “OK” to confirm and close the window.

• Press Ctrl + Esc keys again to display Window.
• Open the window “Printer and Faxes”” from “Settings” submenu.
• Press “Add a Printer”.
• Press “Next” and insert the printer installation driver CD.

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• Select “Local printer” and verify that the box “Automatically detect and
install my Plug & Play printer” is not checked, then press “Next”.
• Select the “Create a New Port” option, set “Standard TCP/IP Port” and
press “Next”.

• Insert the IP address of the Printer (192.168.0.246) in the Add

Standard TCP/IP Printer Port Wizard and a brief description of this
port.

• After the port is configured, a report dialog is presented. Press “Finish”

to close the wizard.
• Press “Have disk” in the Add Printer Wizard to select the proper driver
to be installed and proceed with the installation. Please note that only
the printer driver has to be installed! Any other printer program which
might be listed or proposed during this installation phase has to be
disactivated.
• Press Ctrl + Esc keys again to display Windows bar menu.

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• Select “Settings” and then “Printer and Faxes”.

• Right-click on the printer icon and then choose “Properties” from the
menu to set the printing characteristics.
• Set the printer as the default one.
• Print a test page to make sure the printer is functioning properly.
• Proceed with the printer configuration through the MENU key, as
already explained for the printer with already installed drivers.

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Chapter

4 - Mitsubishi CP750E -
Print Size Settings
Enclosed you will find the instructions to optimise the settings of the Mitsubishi
RGB printer. All the printers delivered by Esaote with the 7350 are already set
according with the Video standard of the country where they will be delivered.

Procedure
1. Connect the RGB printer to the 7350 via the RGB printer cables set
Reference 9102911000 (do not connect the Remote Control cable).
RGB printer icon
2. Verify that the printer input switch, placed in the rear panel, are correctly
set:

Switch Set
RGB 75 Ohm
SYNC High
3. Connect the printer outputs to an RGB monitor via RGB cable.

4. Switch the 7350, the printer and the monitor on.

5. Enter Real-Time and press the key.

6. Select GENERAL PRESET, select the Video tab, set the Video standard and
wait for the re-start message.

7. Press the key again and select PERIPHERALS.

8. Set “Mitsubishi Thermal color printer” in one of the fields REC/PRINT 1

or 2..

9. Press OK to confirm and wait for the re-start message.

10. Switch the unit off by pressing the Shut Down key.

11. Switch the unit on.

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12. Connect the Remote Control cable to the RGB printer (REMOTE input
on the printer front panel).

13. Press the printer [DISPLAY] button: it will display the unit screen on the
monitor.

14. Press the [MENU] button to display the Printer Main Menu.

15. With the [∨] and [∧] buttons select the SIGNAL option and enter it by
pressing the [>] button.

16. With the [∨] and [∧] buttons highlight the INPUT option.

17. Scroll the INPUT menu with the [<] and [>] operations buttons and select
the same video standard set in the 7350.

18. With the [<] and [>] operations buttons select the CUSTOM option and
enter it by pressing the [>] button.

19. Set the following values (use the [>] and [<]operation buttons to change
each field, use the [∨] and [∧]operation buttons to scroll the menu):

Field PAL NTSC

H width 894 762
H dots 673 643
V dots 512 484
H posi 160 95
V posi 73 30

20. Verify the settings since the values are correlated.

21. Press the [SET] button four (4) times to store these values and go back to
the main Menu.

22. If the image is unstable, adjust V BP (SIGNAL option) and then press the
[SET] button two (2) times. Go back to the main Menu.

23. Select [COLOR] and set the following parameters:

Parameter PAL NTSC

Brt 6 5
Cont -7 -7
24. If necessary, adjust the parameter RSUB and BSUB to obtain a good grey
scale. Press the [SET] button two (2) times to save the settings and go back
to the main Menu.

25. Press the [SET] button two (2) times to cancel the printer menu from the
external monitor.

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26. Switch the printer off. Turn the printer on while pressing the [MEMORY]
key: the Service menu will be displayed on the monitor after few seconds.

27. Highlight the KEY option with the [<] and [>] operations buttons and
enter it by pressing the [>] button.

28. Set M&P to ON and press [SET] button two (2) times to exit from Service
menu.

29. Press the [DISPLAY] button to deactivate the printer display.

30. Verify that the unit remote controls the printer by pressing the 1 or 2 key
(depending on the settings).

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Chapter

5 - Sony UP-21 MD -
Print Size Settings
Enclosed you will find the instructions to optimise the settings of the Sony RGB
printer. All the printers delivered by Esaote with the 7350 are already set according
with the Video standard of the country where they will be delivered.

Procedure
1. Install the RGB printer on the cart and connect it to the 7350 via the RGB
printer cables set REF 9102911000, leaving the printer remote control
RGB printer icon cable disconnected.

2. Before turning the printer on, select the required video standard on the
printer rear panel.

3. Connect the printer outputs to an RGB monitor via RGB cable. Anyway,
the printer settings can be directly controlled using the LCD display of the
printer itself.

4. Switch both the printer, the monitor and the 7350 on.

5. Enter Real-Time and press the key.

6. Select GENERAL PRESET, select the Video tab, set the Video standard and
wait for the re-start message.

7. Press the key again and select PERIPHERALS.

8. Set “Sony Thermal color printer” in one of the fields REC/PRINT 1 or 2.

9. Press OK to confirm and wait for the re-start message.

10. Switch the unit off by pressing the Shut Down key.

11. Switch the unit on.

The following 12. Press the printer [MENU] button: it will activate the printer settings menu.
instruction refer to the You can scroll through it by pressing the [<] and [>]buttons and, once an
printer keys

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option is selected, you can scroll its menu by pressing the [∧] and [∨]
buttons.

13. Once the value to be changed is selected, you have to press the [<] and
[>]buttons to modify it.

14. For the COLOR ADJUST and LAYOUT SETUP, WINDOW sub
menu, any modification has to be confirmed by pressing [SAVE] and then
[EXEC].

15. The table shows which value has to be set for the mentioned parameters:

Menu Option Parameter PAL NTSC

COLOR ADJUST CYN-RED 0 0
MAG-GRN 0 0
YEL-BLU 0 0
DARK 0 0
LIGHT 0 0
SHARPNESS 15 15
INTERPOL OFF OFF
LAYOUT SETUP MEMORY FRAME FRAME
WINDOW HSTART 12 0
VSTART 8 0
HWIDTH 936 936
VWIDTH 556 472
PRINTER SET UP GAMMA NORMAL NORMAL
INPUT SETUP INPUT SEL RGB RGB
GAIN -2 -2
OFFSET 1 1
AGC OFF OFF

16. Press [MENU] to exit from the configuration procedure.

17. Connect the remote control cable and check the settings by making a
demo print.

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Chapter

6 - Mitsubishi CP900E -
Print Size Settings
Enclosed you will find the instructions to optimise the settings of the Mitsubishi
RGB printer. All the printers delivered by Esaote with the 7350 are already set
according with the Video standard of the country where they will be delivered.

The Mitsubishi Model CP900E is a PAL video standard thermal printer.

N O T E

Procedure
1. Install the RGB printer on the cart and connect it to the 7350 via the RGB
printer cables set REF 9102911000 (do not connect the Remote Control
RGB printer icon cable).

2. Verify that the printer input switch, placed in the rear panel, are correctly
set:

Switch Set
RGB 75 Ohm/High
SYNC High
3. Connect the printer outputs to an RGB monitor via RGB cable.

4. Switch both the printer, the monitor and the 7350 on.

5. Enter Real-Time and press the key.

6. Select GENERAL PRESET, select the Video tab and verify that the PAL
video standard is set. If necessary, set it and wait for the re-start message.

7. Press the key again and select PERIPHERALS.

8. Set “Mitsubishi Thermal color printer” in one of the fields REC/PRINT 1

or 2..

9. Press OK to confirm and wait for the re-start message.

10. Switch the unit off by pressing the Shut Down key.

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11. Connect the remote control to the printer (input on the printer front
panel).
The following 12. Press the printer [DISPLAY] button: it will display the system screen on
instruction refer to the the monitor.
printer keys on the
remote control
13. Press the [FIELD/FRAME] till the message FRAME is displayed on the
lower side of the screen.

14. Press the [MENU] key to display the printer menu on the monitor.

15. Select the INPUT option by pressing the [∧] and [∨] buttons.

16. Select the RGB option by pressing the [>] and [<] buttons.

17. Press the [SET] key two (2) times to save the configuration.

18. Press the keys [MENU] and then [CLEAR] + [STOP] to display the
service menu.

19. Select the GAMMA ADJ option by pressing the [∧] and [∨] buttons. Press
the [>] key to access to its configuration menu.

20. The table shows which value has to be set for the mentioned parameters:

Parameter Value
COLOR ALL
HI -16
MID 0
LOW 15
POINT 32 128 223

21. Press the [SET] key two (2) times to save the configuration. Wait for
GAMMA SETTING message to stop flashing before proceeding with the
settings.

22. Press again the keys [MENU] and then [CLEAR] + [STOP] to display the
service menu.

23. Highlight the KEY SET option by pressing the [∧] and [∨] buttons. Press
the [>] key to access to its configuration menu.

24. Verify that the MEN&PRN parameter is set to ON. If necessary, set it.

25. Press the [SET] key several times to close the Service menu.

26. Press again the [DISPLAY] button to de-activate the printer menu.

Verify that the unit remote controls the printer by pressing the 1 or 2 key
(depending on the settings).

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Chapter

7 - AG MD835 - VTR
Settings
The AG-MD835 VTR can be remotely controlled by the 7350. The VTR must be
provided with its RS232C serial interface board. In order to avoid the flickering
when in play-back, the VTR must be properly set.

All the VTRs delivered by Esaote with the 7350 are already set according with this
procedure.

Procedure
1. Connect the VTR to the 7350 through the VTR cables set REF
9102109000 (do not connect the Serial cable).
VTR icon
2. Switch both the VTR and the 7350 on.

3. Enter Real-Time and press the key.

4. With the trackball select PERIPHERALS.

5. Cancel any settings in the fields REC/PRINT 1 and 2. Wait for the re-start
message.

6. Press again the key, select the GENERAL PRESET option, then the
VIDEO tab and set the desired Video standard and the input signal to S-
VHS.

7. Press OK to confirm and wait for the re-start message.

8. Switch the unit off by pressing the Shut Down key.

9. Turn the unit on and enter Real-Time.

10. Press the key in the 7350 keyboard and then the P L A Y soft key.

11. Switch the switch [MENU] (located under the door on front panel) to
SET and the switch [MODE LOCK]to OFF: the VTR Menu options will
be displayed.

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12. Select the Serial Interface setting page (press the VTR [REC] and [PLAY]
operation buttons to scroll the menu pages).

13. Use the [FF] key to select each setting field (highlighted by a flashing bar).

14. Set the following values (use the operation button [STOP] or [REW] to
change the default settings):

Field Value
BIT LENGTH 7
STOP BIT STOP-1
PARITY ODD
BAUD RATE 9600

15. Go back to the VTR menu and select the VISS option.

16. Verify that VISS is set to OFF. If necessary, set it.

17. Switch the [MENU] switch to OFF.

18. Press again the key and with the trackball select PERIPHERALS.

19. Set MD835 either in the REC/PRINT 1 or 2 fields.

20. Press OK to confirm and wait for the re-start message.

21. Turn the unit off by pressing the Shut Down key.

22. Connect the Serial cable.

23. Turn the unit on.

24. Verify that the VTR remote control works correctly.

Play Back Quality and Frame Position

The key activates the VTR Service Soft key menu. The displayed menu is:
The Service key is FORWAR
required D NEXT
PLAY PAUSE REWIND PREV STOP EJECT

By pressing the soft key N E X T / P R E V you gain access to the service menu:

SATUR↑ CONTRAST↑ BRIGHTN↑ OFFSET Y → OFFSET Y ↑ NEXT

PLAY PAUSE SATUR↓ CONTRAST↓ BRIGHTN↓ OFFSET X ← OFFSET Y ↓ PREV STOP EJECT

VTR Soft Keys

The soft key are used for adjusting the contrast, the brightness and saturation of
the Play-Back colors and for setting the video recorder position. To carry out the

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procedure, a Video recorder with a pre-recorded video cassette must be connected

to the 7350.

Press P L A Y to see the recorded images on the display. As soon as one service soft
key is pressed, the system displays the set numeric values of the parameters on the
right sight of the screen. You have direct control over the procedure as the changes
in the settings are displayed immediately.

We recommend using the 7350 Real Time screen as a recorded image.

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Chapter

8 - MD3000 - VTR
Settings
The MD3000 VTR can be remotely controlled by the 7350. The VTR must be
provided with its RS232C serial interface board. In order to avoid the flickering
when in play-back, the VTR must be properly set.

All the VTRs delivered by Esaote with the 7350 are already set according with this
procedure.

Procedure
1. Remove the RS232 board from the VTR.
VTR icon 2. Set the switches SW5001 and SW5002 as shown in the below figure.

3. Install the RS232 board in the VTR.

4. Connect the VTR to the 7350 using the VTR cables set REF 9102909000
(do not connect the Serial cable).

5. Switch both the VTR and the 7350 on.

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6. Enter Real-Time and press the key.

7. With the trackball select PERIPHERALS.

8. Cancel any settings in the fields REC/PRINT 1 and 2. Wait for the re-start
message.

9. Press again the key, select the GENERAL PRESET option, then the
VIDEO tab and set the desired Video standard and the Input signal to S-
VHS.

10. Press OK to confirm and wait for the re-start message.

11. Switch the unit off by pressing the Shut Down key.

12. Turn the unit on and enter Real-Time.

13. Press the key in the 7350 keyboard and then the P L A Y soft key.

14. Press the VTR [MENU] key till its menu will be displayed on the screen.

15. Press [MENU] key several times till the Serial Interface board setting page
is displayed.

16. The key [FREAME/FIELD] toggles through settings parameters while

the key [JIOG-SHUTTLE] modifies the parameter value. Set the following
values:

Field Value
TRANSIMISSION RATE 9600
DATA BIT LENGTH 7 BIT
STOP BIT LENGTH 1 BIT
PARITY CHECK ODD

17. Go back to main menu. Select VISS option.

18. Verify that VISS is set to OFF; if necessary, set it.

19. Press the key [MENU] several times till the VTR menu disappears.

20. Connect the Serial cable to the VTR.

21. Press the key , select PERIPHERALS and set MD3000 either in the
REC/PRINT 1 or 2 fields.

22. Wait for the re-start message and turn the unit off by pressing the Shut
Down key.

23. Verify that the VTR remote control works correctly.

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Play Back Quality and Frame Position

The key activates the VTR Service Soft key menu. The displayed menu is:
The Service key is FORWAR
required D NEXT
PLAY PAUSE REWIND PREV STOP EJECT

By pressing the soft key N E X T / P R E V you gain access to the service menu:

SATUR↑ CONTRAST↑ BRIGHTN↑ OFFSET Y → OFFSET Y ↑ NEXT

PLAY PAUSE SATUR↓ CONTRAST↓ BRIGHTN↓ OFFSET X ← OFFSET Y ↓ PREV STOP EJECT

VTR Soft Keys

The soft key are used for adjusting the contrast, the brightness and saturation of
the Play-Back colors and for setting the video recorder position. To carry out the
procedure, a Video recorder with a pre-recorded video cassette must be connected
to the 7350.

Press P L A Y to see the recorded images on the display. As soon as one service soft
key is pressed, the system displays the set numeric values of the parameters on the
right sight of the screen. You have direct control over the procedure as the changes
in the settings are displayed immediately.

We recommend using the 7350 Real Time screen as a recorded image.

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Chapter

9 - Measure
Configuration
Service personnel can modify measurement descriptions.

The Service key is

Measure Configuration
required

The measurements descriptions, abbreviations and labels of both Cardiac and

Vascular applications can be modified by the Service personnel.

Procedure • Press key.

• Select “Application Measurement” option.
• Select the desired application.
• The system displays the application measurement menu. To modify
the description, place the cursor on the desired field and press ENTER.
• With the alphanumeric keyboard enter the new description.
It is possible to change only the descriptions but NOT the calculation combined to
C A U T I O N
the measure. Each measure is associated to a specific preset calculation (a velocity
measure can be freely named but it will always measure a velocity).

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Apppendix

Appendix A - Cables Assembly

The peripherals cables sets are composed of the following reference:

VTR Cables Set REF 9102909000

Reference Desciption
8830325001 Video S-VHS In-Out cable
8830922000 Audio OUT cable
8830922001 Audio IUN cable
8830923000 Serial cable
8820005000 Auxiliary power cable

B/W Printer Cables Set REF 9102910000

Reference Desciption
8830925004 BNC cable
8830924001 B/W remote control cable
8820005000 Auxiliary power cable

RGB Printer Cables Set REF 9102911000

Reference Desciption
8830925000 SYNC cable
8830925001 R cable
8830925002 G cable
8830925003 B cable
8830924002 RGB remote control cable
8820005000 Auxiliary power cable

The next pages contains the assembly drawing of all the cables (with the exception of the auxiliary
power cable).

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Chapter

1 - Maintenance
Procedures
The maintenance procedures are:

• Trackball
• Replacement of the PC ASSEMBLY battery cell
• Replacement of the TGC potentiometer

Trackball
We recommend this maintenance procedure be carried out once a year

Tools
Tool Dimension
Allen screwdriver 3 mm
Phillips electric screwdriver Medium and Small tip
Straight head screwdriver Small tip
Paintbrush -

Removal procedure
• Remove the keyboard group.
• Remove the trackball.
• Unscrew the three Philips head screws shown in the below picture.
• Remove the ball and clean it.
• Clean the encoders with a paint brush (Do not use a cleaning spray!).

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B
A

• Reassemble the trackball.

PC Assembly Battery Cell

The PC ASSEMBLY board contains a Lithium battery. We strongly recommend
to replace the battery cell every three (3) years. If the PC ASSEMBLY board has to
be stored, it will be necessary to first remove the battery.

The Esaote supplier is 3V 210mA/h GP Model CR2032

(www.gpbatteries.com.hk).
Corroded cells Avoid contact with a leaking battery as the contents are harmful.

Irritation, including caustic burns and injury may occur following exposure
WARNING
to a leaking battery.

Do not expose the battery to high temperature. Dispose batteries according

to local regulation

Procedure
• Remove the left cover and bumper.
• Remove the left board shield.
• Remove PC ASSEMBLY board.
• Replace the battery cell paying attention to cell orientation. The cell
positive side of the cell (indicated with +) must be placed upwards.
Incorrect replacement of the battery can cause battery explosion.
WARNING

• Install the PC ASSEMBLY board and close the unit.

• Power the unit and switch it on.
• Enter Real Time and press key.
• Select GENERAL PRESET.
• Set the data and time and press OK to confirm.

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TGC Potentiometer Replacement

This procedure has to be followed whenever one or more TGC potentiometers are
damaged and they have to be replaced.

Tools
Tool Dimension
Soldering unit Medium tip
Allen screwdriver 3 mm
Philips electric screwdriver Medium and small tips
Potentiometer -
Tin sucker -

Procedure
• Remove the Keyboard group.
• Remove the Key TGC board.
• Remove the membrane.
• Unsolder the broken slider from the underside
• Replace the broken lever
• Re-solder the slider.

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Chapter

2 - Safety Test
Every 7350 unit complies with EN60601-1 (IEC 60601-1) standard. The 7350 is
Class I Type B and BF (Ultrasound probe) and CF (ECG) applied parts.

We strongly recommend performing Safety Tests every time new peripherals are
powered through the cart or you had to replace any of the following parts:

• SPS board
• SPR board
• Printer ECG board (ECG connector)
Anyway we suggest repeating the safety tests every two years. If the system is used
in the Intensive or Coronary Care, we suggest repeating the safety tests once a year.

Whenever the measured values exceed the reference ones (see the following
WARNING
table) don’t use the unit and send it to ESAOTE

The parameters to be tested are the following:

• Impedance of Protective Earth Connection

• Earth Leakage Current
• Enclosure Leakage Current
• Patient Leakage Current
• Patient Auxiliary Current
This chapter defines safety Parameters and their range according to EN60601-1
standard and describes the safety tests to be carried out on the equipment.

Definitions
1) Impedance of Protective Earth Connection

The impedance between the Protective Earth (PE) terminal of the mains input
connector and any accessible metal part.

2) Earth Leakage Current

The current that flows from the mains terminals (P=Phase, N=Neutral) to the
Protective Earth (PE) through the insulation.

SECTION 6 5
 7 3 5 0 – S E R V I C E M A N U A L

3) Enclosure Leakage Current

The current that flows between the enclosure and the Protective Earth (PE)
terminal.

4) Patient Leakage Current

The current that flows through the applied parts (ECG and US probe) towards the
Protective Earth (PE).

5) Patient Auxiliary Current

The current that flows between two different applied parts (for instance between
two ECG electrodes).

The table below provides the user with a list of the parameters to be checked, the
maximum values and references to the IEC 60601-1 standard (1988), II Edition.

Parameter Max Value N.C. Max Value EN 60601-1

S.F.C.

Impedance of protective earth connection (with 0.2 Ω - 18.f

Mains Power cable)
Earth leakage current 0.5 mA 1 mA 19.4.f
Enclosure leakage current 0.1 mA 0.5 mA 19.4.g
Patient leakage current CF 0.01 mA ac CF 0.05 mA ac 19.4.h
B/BF 0.1 mA ac B/BF 0.5 mA ac
Patient leakage current - CF 0.05 mA 19.4 h
(mains on applied part) BF 0.5 mA
Patient auxiliary current CF 0.01 mA CF 0.05mA 19.4.j
B/BF 0.1 mA B/BF 0.5 mA
N.C. Normal Condition
S.F.C. Single Fault Condition

The test must be carried out by skilled personnel using equipment compliant with
N O T E
the reference standard indicated. ESAOTE recommends the use of the automatic
BIO-TEK 601-PRO equipment manufactured by BIO-TEK Instruments INC.
(www.biomedequip.com) or equivalent equipment.

SECTION 6 6
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7350 safety test - Operating Procedures

Tools

Tool Dimension
BIOTEK 601 Pro or -
equivalent
Metal foil maximum size 20 x 10 cm

Note

Before proceeding with the safety test, be sure of the equipment

calibration.

Procedure

• Power the automatic testing equipment through mains supply and the
equipment under test through the automatic equipment, as shown in
the Fig.1

Fig.1

• The ECG cable must be connected to the 7350 ECG connector and
the Applied parts terminals in the automatic equipment (see Fig.1).
• Set the automatic equipment according to its user manual in order to
perform a Class I, Type CF equipment test..

SECTION 6 7
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Measurement of the Impedance of Protective Earth connection

• Connect the test lead to 7350 equipotential node.
• Activate the procedure for measuring the Impedance of Protective
Earth on the automatic equipment.
• Check that the value indicated complies with the indications given in
the reference table for normal condition (NC).
If the measured value is higher than the value in the table, do not use the
equipment and send to ESAOTE.

Measurement of Earth leakage current

• Activate the procedure for measuring the earth leakage current on the
automatic equipment:
1.1 Check that the value indicated complies with the indications
given in the reference table for normal condition (NC).

1.2 Repeat the procedure simulating a break in a power conductor,

by means of the automatic equipment, and check that the value
indicated complies with the indications given in the reference table
for the single fault condition (SFC).

• Repeat the above measurement procedures inverting the polarity of

the power conductors, by means of the automatic equipment
If any measured value is higher than the value in the table, do not use the
equipment and replace the power cable. Repeat the procedure with the new cable
and if the values continue to be higher, send the equipment to ESAOTE.

Measurement the Enclosure Leakage Current

• Connect the test lead to the metal foil.
1.1 Place the metal foil in close contact with the unit and activate
the procedure for measuring the enclosure leakage current on the
automatic equipment; varying the foil position, check that the
value indicated complies with the indications given in the reference
table for the normal condition (NC)

1.2 Repeat the procedure simulating a break in the earth wire, by

means of the automatic equipment, and check that the value
indicated complies with the indications given in the reference table
for the single fault condition (SFC).

1.3 Repeat the procedure simulating a break in a power conductor,

by means of the automatic equipment, and check that the value
indicated complies with the indications given in the reference table
for the single fault condition (SFC).

• Repeat the above measurement procedures inverting the polarity of

the power conductors, by means of the automatic equipment.

SECTION 6 8
7 3 5 0 – S E R V I C E M A N U A L

If any of the measured values are higher than the value in the table, do not use the
equipment and send it to ESAOTE.

Measurement the Patient Leakage Current (ECG cable)

• Insert the ECG cable leads in the applied parts terminals in the
automatic equipment.
1.1 Activate the procedure for measuring the Patient leakage
current on the automatic equipment and check that the value
indicated complies with the indications given in the reference table
for the normal condition (NC).

1.2 Repeat the procedure simulating a break in the earth wire, by

means of the automatic equipment, and check that the value
indicated complies with the indications given in the reference table
for the single fault condition (SFC).

1.3 Repeat the procedure simulating a break in a power conductor,

by means of the automatic equipment, and check that the value
indicated complies with the indications given in the reference table
for the single fault condition (SFC).

1.4 Repeat the procedure simulating the application of the mains

voltage, by means of the automatic equipment, to the plugs on the
patient cable and check that the value indicated complies with the
indication given in the reference table for the single fault condition
(SFC).

• Repeat the above measurement procedures inverting the polarity of

the power conductors, by means of the automatic equipment.
• If any of the measured values are higher than the value in the table, do
not use the equipment and replace the ECG patient cable. Repeat the
procedure with the new cable and if the values continue to be higher,
send the equipment to ESAOTE.
Measurement the Patient Auxiliary Current
• Activate the procedure for measuring the patient auxiliary current on
the automatic equipment and check that the value indicated complies
with the indications given in the reference table for the normal
condition (NC).
• Repeat the procedure simulating a break in the earth wire, by means of
the automatic equipment, and check that the value indicated complies
with the indications given in the reference table for the single fault
condition (SFC).
• Repeat the procedure simulating a break in a power conductor, by
means of the automatic equipment, and check that the value indicated
complies with the indications given in the reference table for the single
fault condition (SFC).

SECTION 6 9
 7 3 5 0 – S E R V I C E M A N U A L

• Repeat the above measurement procedures inverting the polarity of

the power conductors, by means of the automatic equipment.
If any of the measured values are higher than the value in the table, do not use the
equipment and replace the ECG patient cable. Repeat the procedure with the new
cable and if the values continue to be higher, send the equipment to ESAOTE.

The defective patient cable or power cable must not be used

WARNING

Probe safety tests

For any probe in use with the unit, repeat the procedure for measuring the Patient
Leakage Current test (without application of mains voltage on applied part),
wrapping the probe enclosure with the metal foil and connecting the test lead to it.
The test must be performed in any Real Time mode application. The probe must
be connected to the unit

1.1 Activate the procedure for measuring the Patient leakage

current on the automatic equipment and check that the value
indicated complies with the indications given in the reference table
for the normal condition (NC).

1.2 Repeat the procedure simulating a break in the earth wire, by

means of the automatic equipment, and check that the value
indicated complies with the indications given in the reference table
for the single fault condition (SFC).

1.3 Repeat the procedure simulating a break in a power conductor,

by means of the automatic equipment, and check that the value
indicated complies with the indications given in the reference table
for the single fault condition (SFC).

Repeat the above measurement procedures inverting the polarity of the power
conductors, by means of the automatic equipment.

If any of the measured values are higher than the value in the table, do not use the
probe and send it to ESAOTE.

Any break in the probe case or in the probe cable can cause an electrical
WARNING
hazard. Do not use the probe and send it back to ESAOTE for repair.

SECTION 6 10
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7 3 5 0 – S E R V I C E M A N U A L
Chapter

1 - Error messages

Communication error with the CONTROL

BOARD (TGC) and Communication error with
the CONTROL BOARD
When system displays one of the following messages:

Communication error with the CONTROL BOARD (TGC)

Please, contact the service department !
Press <PROBE> to continue

Communication error with the CONTROL BOARD

Please, contact the service department !
Press <PROBE> to continue

there is a communication problem between the PC Assembly board and the

Control board.

Suggestion
• Replace the Control board and verify if the problem disappears.
• If not, re-install the Control board.
• Replace the PC Assembly board and verify if the problem disappears.
• If not, contact Esaote central service.

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SECTION 7 2
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7 3 5 0 – S E R V I C E M A N U A L
Chapter

2 - Hardware error
messages
If an Hardware failure is present so that the PROCESSOR can’t access some of
the boards, the unit will display an error message in red on the right side of the
screen. In that situation power the unit on and off several times to verify that the
message persists (it could be caused by a board failing to initialise correctly).

If the message persists, the fault could be:

Message Fault Solution

03 ECG PRINTER ECG board Replace the PRINTER ECG board
04 POWER SPR or SPS board Replace one board a time
05 DOPPLER DOPPLER board Replace the DOPPLER board.
07 CONTROL CONTROL board Replace the CONTROL boar
08 TGC CONTROL board Replace the CONTROL board
09 SCAN CONTROL board Replace the CONTROL board
12 E2PROM MOTHER/PROCESSOR Replace the PROCESSOR board. If
boards not solved, send the unit back to
Esaote
14 GRAPHIC PROCESSOR board Replace the PROCESSOR board

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SECTION 7 4
 3
7 3 5 0 – S E R V I C E M A N U A L
Chapter

3 - Archiving
troubleshooting
From the Real Time screen is possible to check if the Archiving services are
correctly functioning. The icons are shown over a blue background when they can
be activated. While data are being saved, the specific support icon is outlined by a
yellow flashing frame. The frame disappears when the operation ends.

Hard Disk Crossed Icon

The crossed out icon indicates that the communication between the ETX board
and the central processor on the PC ASSEMBLY board has been interrupted
sometime.

Suggestion
Torn the unit off and on and check if the Hard Disk icon is displayed with no
cross. If the problem persists, re-install the software release following the
instruction given in section 5.

If this does not work, replace the Hard Disk (see Section 4, Chapter 3 for Hard
Disk replacing instruction).

Hard Disk Grey Icon

When the Hard Disk icon stays grey, it means that there has never been
communication between the ETX board and the PC ASSEMBLY board.

Suggestion
Torn the unit off and on and check if the Hard Disk icon is displayed on a blue
background. If the problem persists, re-install the software release following the
instruction given in section 5.

If this does not work, replace the Hard Disk (see Section 4, Chapter 3 for Hard
Disk replacing instruction).

SECTION 7 5
7 3 5 0 – S E R V I C E M A N U A L

CD Burner and USB Pen Drive Crossed Icons

The crossed out icon indicates management problems of the specific archival
support.

Suggestion
The interactive icon menu allows the operator to understand which operation has
failed, and, if necessary, to repeat (RETRY) or cancel the failed operation.

If the operation continuously fails, replace the support and repeat the operation. If
this does not work, replace the PC ASSEMBLY board.

SECTION 7 6
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7 3 5 0 – S E R V I C E M A N U A L
Chapter

4 - Shut Down Log File

The Shut Down key activates the shut down procedure. This procedure has to be
followed before turning the unit off by pressing the main switch placed in the unit
The Service key is rear panel.
required
7350 is a PC based system; data loss or driver damage may occur if the system is
N O T E
turned off while working. The shut down procedure avoids these problems.

The Shut Down Log file allows the service to verify if the procedure is correctly
followed.

Procedure
1. Turn the unit on with the service key inserted.

2. Enter Real-Time and press .

3. Press the keys Ctrl + Esc to display the Windows menu.

4. Select Document/My Documents option.

5. Select in the drive D the Biolabwork directory and then the directory
Dam.

6. The file DamShutDown_0 is displayed by double-clicking it, as shown in

the below shot.

SECTION 7
7
 7 3 5 0 – S E R V I C E M A N U A L

The line “Starting

dam” locates when
the unit has been
turned on; the line
“Fast shutdown
called by user” locates
when the unit has
been turned off by
pressing the Shut
Down key.

The Shut Down log file can be copied in an USB pen drive for any service need.

SECTION 7
8
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7 3 5 0 – S E R V I C E M A N U A L
Chapter

1 - Check List
This chapter proposes two different check lists. The first one (Technical Check
List) suggests a set of inspection steps to be performed each time service personnel
modify the HW/SW composition (for example a board replacement or functional
upgrade); the other one (Maintenance Check List) suggests a check list intended for
a general equipment inspection like yearly maintenance.

Technical Check List

Once any HW/SW change, modification or upgrade is finished and the unit is
ready to be closed, perform the following:
The Service key is
required
• Make a note of any new boards or parts which have been replaced.
References can be found in the Traceable Part List section of the
manual.
• Close the unit.
• Switch the unit on with the service key inserted.
• Enter Real-Time, press the key and select SYSTEM
CONFIGURATION.

• Print the new System Configuration screen and place it in the pocket
placed in the rear cover of the unit.
• When applicable, verify that the functional upgrade is working
properly.
• Press again the key and select the SERVICE option
• Press ENTER and select SAVE CONFIGURATIONS.
• Save the configuration by pressing ENTER.
• Switch the unit off.
• Verify the unit functioning using the Maintenance Check List as
reference

SECTION 8 1
 7 3 5 0 – S E R V I C E M A N U A L

Maintenance Check List

• Check the unit for any external damage.
The Service key is • Check the wheels and their functioning.
required
• Check that the unit labels (Serial Number, Reference and Certification)
are present.
• Check that the User Manual is enclosed and its revision is relevant to
the installed software release.
• Check the power cable status (no cut, plug condition).
• Check the connectors in the front panel.
• If installed, check the ECG Cable status.
• Clean the trackball.
• Check that the control panel orientation works properly: the control
panel must be both oriented, closed and locked.
• Switch the unit on, enter Real-Time, press the key and select
SYSTEM CONFIGURATION.

• Compare the configuration prints located in the pocket of the unit

with the configuration information shown on the System
Configuration screen.
• If necessary, set local time and date.
• Check that the fan works properly.
• If necessary, adjust the monitor brightness and contrast.
• Check the keyboard functions.
For probes check • For all probes, check the external status (cable, housing and labeling).
refer also to
“Transducers and • Verify that all transducers are correctly identified in each connector.
Consumables”
manual • Check that the unit is functioning properly, for each of the modalities
listed below verify:
• B Mode: General Gain (B/M Gain Encoder), TGC, TX
Focus, Power and all Soft keys controls.
• M Mode: General Gain (B/M Gain Encoder) and all Soft keys
controls.
• B + CFM: CFM Gain (C/D Gain Encoder), CFM ROI and
all Soft keys controls.
• CW/PW: Doppler Gain (C/D Gain Encoder), Audio and all
Soft keys controls.
• ECG ( ): ECG level and position.

SECTION 8 2
7 3 5 0 – S E R V I C E M A N U A L

• Insert a re-writable CD and save images. Then erase them (CD burner
menu).
• Insert a USB pen drive in one of the ports and save images.
• Repeat the operation in the other USB port.
• When equipped with a VTR, check:
• VTR cable and connection.
• When applicable, remote control setting and its functioning.
• Play back quality and Frame position (Service soft keys menu).
• Audio quality.
• When equipped with a printer:
• Printer cable and connection
• When applicable, remote control setting and its functioning.
• Print quality.

SECTION 8 3
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SECTION 8 4
 1
7 3 5 0 – S E R V I C E M A N U A L
Chapter

1 - Schematic Diagrams
This chapter contains the Schematic Diagrams of the 7350 boards.

Note: the schematics of the INPUT, TRX, TRXCW2, SPS and SPR boards are confidential
so they aren’t included in this manual.

SECTION 9 1
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SECTION 9 2
 1 2 3 4 5 6 7 8 9 10 11

+3V3
U17
L8 TMS320VC5502 +3V3 UP1
330U 29F040-120
60 PVDD PSENSE 61
+3V3 U7 +3V3 R144 TCOE 24 OE
C238 C239 TCD[0:31] 22
CK40A 63 X2/CLKIN D0/HPID0/EMIFD0 152 TCD0 CY7C1327 1K00 TCSEPROM CE
F 470N 47N
151 TCD1 ECLK 89 4
31 WE
D1/HPID1/EMIFD1 CLK VDDQ TCD[0:15]
62 150 TCD2 11
X1 D2/HPID2/EMIFD2 VDDQ
149 TCD3 83 20 TCA0 12 13 TCD0
D3/HPID3/EMIFD3 TB1 ADV VDDQ
TCA[0:18]
A0 O0
TB46 54 CLKOUT D4/HPID4/EMIFD4 147 TCD4 84 ADSP VDDQ 27 TCA1 11 A1 O1 14 TCD1
146 TCD5 TCADSC 85 54 TCA2 10 15 TCD2
D5/HPID5/EMIFD5 ADSC VDDQ A2 O2
TCA0 112 145 TCD6 61 TCA3 9 17 TCD3
TCA[0:19] A2/HPIA0/EMIFA2 D6/HPID6/EMIFD6 VDDQ A3 O3
TCA1 111 143 TCD7 TCA0 37 70 TCA4 8 18 TCD4
A3/HPIA1/EMIFA3 D7/HPID7/EMIFD7 A0 VDDQ A4 O4
TCA2 110 142 TCD8 TCA1 36 77 TCA5 7 19 TCD5
A4/HPIA2/EMIFA4 D8/HPID8/EMIFD8 A1 VDDQ A5 O5
TCA3 108 140 TCD9 TCA2 35 TCA6 6 20 TCD6
A5/HPIA3/EMIFA5 D9/HPID9/EMIFD9 A2 A6 O6
TCA4 107 139 TCD10 TCA3 34 TCA7 5 21 TCD7
A6/HPIA4/EMIFA6 D10/HPID10/EMIFD10 A3 A7 O7
TCA5 106 138 TCD11 TCA4 33 TCA8 27
A7/HPIA5/EMIFA7 D11/HPID11/EMIFD11 A4 A8
TCA6 104 137 TCD12 TCA5 32 TCA9 26
A8/HPIA6/EMIFA8 D12/HPID12/EMIFD12 A5 A9
TCA7 103 136 TCD13 TCA6 100 TCA10 23
A9/HPIA7/EMIFA9 D13/HPID13/EMIFD13 A6 TCD[0:31] A10
TCA8 102 135 TCD14 TCA7 99 TCA11 25
A10/HPIA8/EMIFA10 D14/HPID14/EMIFD14 A7 A11
TCA9 101 134 TCD15 TCA8 82 58 TCD0 TCA12 4
A11/HPIA9/EMIFA11 D15/HPID15/EMIFD15 A8 DQ0 A12
TCA10 99 133 TCD16 TCA9 81 59 TCD1 TCA13 28
+3V3 A12/HPIA10/EMIFA12 D16/PGPIO4/EMIFD16 A9 DQ1 A13
TCA11 98 132 TCD17 TCA10 80 62 TCD2 TCA14 29
R12 A13/HPIA11/EMIFA13 D17/PGPIO5/EMIFD17 A10 DQ2 A14
E TCA12 96 A14/HPIA12/EMIFA14 D18/PGPIO6/EMIFD18 131 TCD18 TCA11 44 A11 DQ3 63 TCD3 TCA15 3 A15
4K7
TCA13 95 129 TCD19 TCA12 45 68 TCD4 TCA16 2
A15/HPIA13/EMIFA15 D19/PGPIO7/EMIFD19 A12 DQ4 A16
TCA14 93 128 TCD20 TCA13 46 69 TCD5 TCA17 30
R15 A16/HPIA14/EMIFA16 D20/PGPIO8/EMIFD20 A13 DQ5 A17
TCA15 92 A17/HPIA15/EMIFA17 D21/PGPIO9/EMIFD21 127 TCD21 R40 TCA14 47 A14 DQ6 72 TCD6 TCA18 1 A18
4K7
TCA16 90 126 TCD22 33 TCA15 48 73 TCD7
A18/PGPIO0/EMIFA18 D22/PGPIO10/EMIFD22 A15 DQ7
TCWE
TCA17 89 125 TCD23 TCA16 49 8 TCD8 UP2
R14 A19/PGPIO1/EMIFA19 D23/PGPIO11/EMIFD23 A16 DQ8 +3V3
TCA18 88 123 TCD24 TCA17 50 9 TCD9
4K7 A20/PGPIO2/EMIFA20 D24/PGPIO12/EMIFD24 A17 DQ9 29F040-120
TCA19 87 122 TCD25 43 12 TCD10
A21/PGPIO3/EMIFA21 D25/PGPIO13/EMIFD25 NC(A18) DQ10 24
120 TCD26
+3V3 TCA[0:17]
88 13 TCD11 R145 OE
R17 D26/PGPIO14/EMIFD26 GW DQ11 22 CE
TCINT0 8 119 TCD27 18 TCD12 1K00
4K7 INT0 D27/PGPIO15/EMIFD27 DQ12 31 WE
TCINT1 10 118 TCD28 TCWE 87 19 TCD13
INT1 D28/PGPIO16/EMIFD28 BWE DQ13
TCINT2 11 116 TCD29 TCBE0 93 22 TCD14
R16 INT2 D29/PGPIO17/EMIFD29 BWS0 DQ14
TCA0 12 13 TCD8
TCINT3 13 115 TCD30 TCBE1 94 23 TCD15 A0 O0
1K00 INT3 D30/PGPIO18/EMIFD30 BWS1 DQ15 TCA[0:18]
4K7 TCA1 11 14 TCD9
14 114 TCD31 R146 A1 O1
NMI/WDTOUT D31/PGPIO19/EMIFD31
TCA2 10 15 TCD10
15 R43 31 A2 O2
IACK 4K7 MODE R148 TCA3 9 17 TCD11
TCRESET 162 86 TCADSC A3 O3
R13 RESET C0/PGPIO20/ARE 4K7 TCA4 8 18 TCD12
85 TCOE TCSRAM 98 74 A4 O4
4K7 C1/PGPIO21/AOE CE1 DP0
TCA5 7 19 TCD13
D BOOTM0 5 84 97 24 A5 O5
GPIO0 C2/PGPIO22/AWE CE2 DP1
TCA6 6 20 TCD14
R9 BOOTM1 4 GPIO1 C3/PGPIO23/ARDY 82 92 CE3
A6 O6
BOOTM2 3 81 TCSRAM R143 TCA7 5 A7 O7 21 TCD15
4K7 GPIO2 C4/PGPIO24/CE0
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

TCOE 86 4K7 TCA8 27

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

CLKSOURCE 2 79 TCSCTRL OE A8
GPIO4 C5/PGPIO25/CE1
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

TCA9 26
R10 EMIFEN 1 GPIO6 C6/PGPIO26/CE2 78 TCSFLASH A9
64 TCA10 23
4K7 SERIAL2EN 176 72 TCSEPROM ZZ A10
GPIO7 C7/PGPIO27/CE3
TCA11 25
XCCLKA 55 71 TCBE0 A11
XF C8/PGPIO28/BE0
TCA12 4
R7 C9/PGPIO29/BE1 70 TCBE1 A12
TCA13 28
4K7 TB33 17 CLKR0 C10/PGPIO30/BE2 69 TCBE2 A13
R147 R153 R142 TCA14 29
18 68 TCBE3 A14
DR0 C11/PGPIO31/BE3 +3V3 TCA15 3
R8 TB36 19 FSR0 C12/PGPIO32/SDCKE 67 R37
4K7 4K7 4K7 +3V3 U12 +3V3 A15
TCA16 2
4K7 TB37 20 CLKX0 C13/PGPIO33/SOE 66 TB48 1K00 CY7C1327 A16
TCA17 30
TB38 22 DX0 C14/PGPIO34/HOLD 58 ECLK 89 4
A17
CLK VDDQ TCA18 1
R183 TB39 23 FSX0 C15/PGPIO35/HOLDA 57
11
A18
VDDQ
4K7 24 CLKR1 MONTARE SU ZOCCOLO
83 ADV VDDQ 20
25 DR1 ECLKIN 74 R42 84 ADSP VDDQ 27
R18 26 FSR1 ECLKOUT1 76 TB47 33 TCADSC 85 54
ADSC VDDQ
28 75 ECLK
C 4K7 CLKX1 ECLKOUT2 61
VDDQ
27 DX1 EMIFCLKS 64 TCA0
R41 37 A0 VDDQ 70 +3V3
R21 30 FSX1 TCA1 36 A1 VDDQ 77 UP3
XDONEA 31 175 XDATA0 1K00
4K7 DR2 HD0/PGPIO36 TCA2 35 A2 28F128J3A
32 173 XDATA1
DX2 HD1/PGPIO37 TCA3 34 32 43
A3 A0 VCCQ
R25 HD2/PGPIO38 172 XDATA2 R39 TCA4 33 TCA0 28
A4 A1
FLASH 38 170 XDATA3 1K00 TCA[0:19]
1K00 SP0/GPIO3/CLKX2 HD3/PGPIO39 TCA5 32 TCA1 27 33 TCD0
A5 A2 DQ0 TCD[0:15]
TB43 37 SP1/UARTTX/CLKR2 HD4/PGPIO40 169 XDATA4
TCA6 100 TCA2 26 35 TCD1
A6 A3 DQ1
XPROGA 35 167 XDATA5
SP2/GPIO5/FSX2 HD5/PGPIO41 TCA7 99 TCA3 25 38 TCD2
R31 34 166 XDATA6
A7 A4 DQ2
SP3/UARTRX/FSR2 HD6/PGPIO42 TCA8 82 58 TCD16 TCA4 24 40 TCD3
4K7 A8 DQ0 A5 DQ3
40 164 XDATA7 XDATA[0:7]
SCL HD7/PGPIO43 TCA9 81 59 TCD17 TCA5 23 44 TCD4
A9 DQ1 A6 DQ4
41 SDA TCA10 TCD18 TCA6 TCD5
80 A10 DQ2 62 22 A7 DQ5 46
R24 HC0/PGPIO44/HAS 43 XINITA +3V3 TCA11 44 63 TCD19 TCA7 20 49 TCD6
A11 DQ3 A8 DQ6
TCTCK 160 42 HP0
4K7 TCK HC1/PGPIO45/HBIL R34 TCA12 45 A12 DQ4 68 TCD20 TCA8 19 A9 DQ7 51 TCD7
TCTDI 158 TDI 4K7 TCA13 46 69 TCD21 TCA9 18 34 TCD8
A13 DQ5 A10 DQ8
TCTDO 156 46 HP1
R30 TDO HCNTL0 TCA14 47 A14 DQ6 72 TCD22 TCA10 17 A11 DQ9 36 TCD9
TCTMS 161 45 HP2
4K7 TMS HCNTL1 TCA15 48 73 TCD23 TCA11 13 39 TCD10
A15 DQ7 A12 DQ10
TCTRST 159 44 XCSA
TRST HCS TCA16 49 8 TCD24 TCA12 12 41 TCD11
B A16 DQ8 A13 DQ11
TCEMU0 155 48 XWE HP[0:6]
EMU0 HR/W TCA17 50 9 TCD25 TCA13 11 45 TCD12
R33 TCEMU1 154 51 HP3
A17 DQ9 A14 DQ12
EMU1 HDS1 43 12 TCD26 TCA14 10 47 TCD13
4K7 NC(A18) DQ10 A15 DQ13
49 HP4 TCA[0:17]
HDS2 88 13 TCD27 TCA15 8 50 TCD14
GW DQ11 A16 DQ14
52 HP5
HRDY R184 DQ12 18 TCD28 TCA16 7 A17 DQ15 52 TCD15
R32 TCTIM0 7 TIM0 HINT 59 HP6
1K00 TCWE 87 19 TCD29 TCA17 6 TB2
BWE DQ13 A18
TCTIM1 6 163
4K7 TIM1 HPIENA TCBE2 93 22 TCD30 FADD[20:23] TCA18 5 14
BWS0 DQ14 A19 CE0 TCSFLASH
TCBE3 94 23 TCD31 TCA19 4 2
BWS1 DQ15 A20 CE1
R187 FADD20 3 A21 CE2 29
+3V3 TB45 31 FADD21 1
1K00 MODE R157 A22
TB44 4K7
FADD22 30 A23 WE 55 FHWE
TCSRAM 98 74 FADD23 56 54
CE1 DP0 NC OE TCOE
R35 97 CE2 DP1 24 RP 16 FHRES
R185 92 CE3 R150 FSTS 53 STS
R6 1K00
4K7 4K7 FVPEN 15 VPEN BYTE 31
4K7 P6 TCOE 86 OE R166
TCTRST 1K00
TCTMS 1 2
TCTDI R152 64 ZZ
3 4
A R149 R160
5 6 R5 1K00
4K7
837 0147 042 Rev.A

TCTDO 7 8 1K00 4K7 R158

1K00
TCTCK 4K7 4K7
9 10 R156 +3V3 R151
FORM:

R159 R167 R155 R154

11 12
4K7 4K7 4K7
TCEMU0 13 14 TCEMU1 4K7

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" CONTROL BOARD
A2 GAMBACCIANI DONNINI ANDREUCCETTI 05/04/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: IND200500179 Number: 950 1216 000 SE C 1 11
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
 1 2 3 4 5 6 7 8 9 10 11

+3V3
U42
74LCX245
+3V3
R265 19 G RLB[0:15]
1 T/R
1K00
F 9 A1 B1 11 RLB0
U30 R261 R260 TB71
R217 4K7 4K7 U30 8 A2 B2 12 RLB1
XC2S100E TB62 1K00 RLB2
R220 U45 XC2S100E 7 A3 B3 13
4K7 +3V3 6 14 RLB3
XDATA[0:7] 74LCX245 A4 B4
BANK 0 BANK 2 5 15 RLB4
R212 19 BANK 4 BANK 6 A5 B5
1K00 G
R223 R221 4 16 RLB5
TCD[0:15] 4K7 1 A6 B6
TCD0 A3 B16 XDATA0 4K7
R218 4K7
T/R LD[0:15]
3 17 RLB6
I/O I/O(DIN,D0) LD12 M10 J1 A7 B7
FEXDONE0I 18 2 FEXDONE0 I/O I/O
TCD1 A4 C15 RFCSA B1 A1 2 18 RLB7
I/O I/O,(DOUT,BUSY) LD13 M11 J2 A8 B8
FEXINIT0I 17 3 FEXINIT0 I/O(VREFBank4) I/O
TCD2 A5 C16 RFCSB B2 A2
I/O I/O(VREFBank2) LD14 N9 J3
FEXDONE1I 16 4 FEXDONE1 I/O I/O
TCD3 A6 D14 RFXPROG B3 A3
I/O I/O LD15 N10 J4
FEXINIT1I 15 5 FEXINIT1 I/O I/O,(TRDY)
TCD4 A7 D15 SCXPROG B4 A4
I/O I/O LA0 N11 K1
TCD5 B3 D16 RFXDONE R213 R224 FEXPROG1 14 B5 A5 6 I/O I/O(VREFBank6) TXFRAMEI
I/O I/O(VREFBank2) LA1 N12 K2
4K7 FEXPROG0 13 7 I/O I/O RXSTBI
TCD6 B4 E13 RFXINIT 4K7 B6 A6

LA[0:4]
I/O I/O LA2 P9 K3
12 8 I/O I/O PII
TCD7 B5 I/O(VREFBank0) I/O E14 SCXINIT R264 B7 A7
LA3 P10 K4
11 9 I/O I/O TB84I
TCD8 B6 E15 XDATA1 33 B8 A8
I/O I/O,(D1) LA4 P11 K5
I/O I/O
TCD9 B7 E16 SCXDONE FEXCCLK0
I/O I/O LRW P12 L1 +3V3
I/O I/O
TCD10 C4 I/O I/O F12 R227 R263 SCXCS0 P13 L2
E TCD11 C5 F13 33 R251 R250 I/O I/O U62
I/O(VREFBank0) I/O 0 LSSCAN R9 L3
RFXCCLK 4K7 I/O(DLL) I/O
TCD12 C6 I/O I/O,(D2) F14 XDATA2 FEXCCLK1 4K7 LSFE R10 L4 74LCX245
I/O(VREFBank4) I/O
TCD13 C7 F15 SCCTRLRW 19
I/O I/O R228 TB83 R11 I/O I/O(VREFBank6) L5 G
TCD14 D5 F16 SCCTRLCS 1
I/O I/O(VREFBank2) 0 R12 M1 T/R
SCXCCLK I/O(VREFBank4) I/O
TCD15 D6 G12 SCCTRL13
I/O I/O R13 M2 2 18 LQ0
I/O I/O(VREFBank6) A1 B1
TCA0 D7 G13 SCCTRL12
I/O(VREFBank0) I/O R14 M3 3 17 LQ1 LQ[0:2]
I/O I/O A2 B2
TCA1 D8 G14 SCCTRL11
I/O(DLL) I/O T10 M4 4 16 LQ2
I/O I/O A3 B3
TCA2 E6 G15 XDATA3 R165 R225
I/O I/O,(D3) POS T11 N1 5 15 FES0
I/O I/O A4 B4
TCA3 E7 G16 SCCTRL10 82 82
I/O I/O FEXDONE0I T12 N2 6 14 FES1
I/O I/O A5 B5 FES[0:2]
H13 SCCTRL9
I/O FEXINIT0I T13 N3 7 13 FES2
C132 C333 I/O I/O A6 B6
H14 SCCTRL8
I/O FEXDONE1I T14 P1 8 12 TXSTB
I/O I/O A7 B7
H15 SCCTRL7 100P 100P
I/O FEXINIT1I P2 9 11 TXRES
I/O A8 B8
TCWE C8 H16 SCCTRL6
GCK3,I I/O,(IRDY) LSCNT T9
+3V3 GCK0,I
U44
+3V3 E8 G11
+3V3 +3V3 TP11
VCCOBank0 VCCOBank2 74LCX245 +3V3 L9 VCCOBank4 VCCOBank6 J5
F7 VCCOBank0 VCCOBank2 H11 XDATA0 TB56 19 L10 J6 TP12
G VCCOBank4 VCCOBank6
F8 H12
VCCOBank0 VCCOBank2 XDATA1 TB66 T/R 1 M9 VCCOBank4 VCCOBank6 K6 U60
D TCA[0:19]
XDATA2 TB75 SADD[0:19]
SADD0 18 B1 A1 2 74LCX245
BANK 1 BANK 3
SADD1 17 3 BANK 5 BANK 7 19
XDATA3 TB69 B2 A2 G
SADD2 16 4 1
TCA4 A8 J13 SCCTRL5 B3 A3 T/R
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

I/O(DLL) I/O,(TRDY) C1
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

SADD3 15 5 I/O TB53

TCA5 A9 J14 XDATA4 B4 A4 2 18
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

I/O I/O,(D4) M6 C2 TXREFBE A1 B1

SADD4 14 6 I/O I/O
TCA6 A10 J15 SCCTRL4 B5 A5 3 17
I/O I/O M7 D1 FADD20 A2 B2
SADD5 13 7 I/O(VREFBank5) I/O
TCA7 A11 J16 SCCTRL3 B6 A6 4 16
I/O I/O N5 D2 FADD21 A3 B3
SADD6 12 8 I/O I/O
TCA8 A12 K12 SCCTRL2 B7 A7 5 15 HF0
I/O I/O N6 D3 FADD22 A4 B4
SADD7 11 9 I/O I/O
XWE A13 K13 SCCTRL1 B8 A8 6 14 HF1 HF[0:2]
I/O(WRITE) I/O(VREFBank3) SCCTRL[0:13] N7 E1 FADD23 A5 B5
I/O I/O
XCSA A14 K14 SCCTRL0 7 13 HF2
I/O(CS) I/O N8 E2 FHWE A6 B6
I/O I/O
TCA9 B9 I/O I/O K15 LD0 74LCX245 P4 E3 FSTS 8 A7 B7 12 FEPRG
I/O I/O(VREFBank7)
TCA10 B10 K16 LD1 19 9 11 FERW
I/O I/O U63 G P5 E4 FVPEN A8 B8
I/O I/O
TCA11 B11 L12 LD2 1
I/O(VREFBank1) I/O T/R P6 F1 FHRES
I/O I/O
TCA12 B12 L13 XDATA5
I/O I/O,(D5) SADD8 18 2 P7 F2
B1 A1 I/O I/O U61
TCA13 B13 L14 LD3
I/O I/O SADD9 17 3 P8 F3
B2 A2 I/O I/O
TCA14 C9 I/O I/O(VREFBank3) L15 LD4
SADD10 16 4 R4 F4 74LCX245
B3 A3 I/O I/O(VREFBank7)
TCA15 C10 L16 XDATA6 19
I/O I/O,(D6) SADD11 15 5 R5 F5 G
B4 A4 I/O(VREFBank5) I/O
TCA16 C11 M13 LD5 1
I/O I/O SADD12 14 6 R6 G1 T/R
C B5 A5 I/O(VREFBank5) I/O
TCA17 C12 M14 LD6
I/O I/O SADD13 13 7 R7 G2 9 11 RLB8
B6 A6 I/O I/O(VREFBank7) A1 B1
TCA18 D9 M15 LD7
I/O(VREFBank1) I/O(VREFBank3) SADD14 12 8 R8 G3 8 12 RLB9
B7 A7 I/O(DLL) I/O A2 B2
TCA19 D10 M16 LD8
I/O I/O SADD15 11 9 T3 G4 7 13 RLB10
B8 A8 I/O I/O A3 B3
TCSCTRL D11 N14 LD9
I/O I/O T4 G5 6 14 RLB11
U43 I/O I/O A4 B4
TCSEPROM D12 N15 LD10
I/O(VREFBank1) I/O T5 H1 5 15 RLB12
I/O I/O,(IRDY) A5 B5
TCOE E10 I/O I/O N16 LD11 LD[0:15] 74LCX245 T6 H2 4 16 RLB13
I/O I/O A6 B6
SCXCS1 E11 P15 XINITA 19
I/O I/O,(INIT) G T7 H3 3 17 RLB14
I/O I/O A7 B7
DPTCLK2 B8 P16 XDATA7 1
GCK2,I I/O,(D7) T/R CK40B T8 H4 2 18 RLB15
GCK1,I I/O A8 B8
SADD16 18 2
+3V3 E9 J11
B1 A1 TB82 +3V3
VCCOBank1 VCCOBank3 +3V3 SADD17 17 3 L7 G6
B2 A2 +3V3 VCCOBank5 VCCOBank7
F9 VCCOBank1 VCCOBank3 J12 SADD18 16 B3 A3 4 L8 VCCOBank5 VCCOBank7 H5
F10 VCCOBank1 VCCOBank3 K11 SADD19 15 B4 A4 5 M8 VCCOBank5 VCCOBank7 H6
TXFRAME 14 B5 A5 6 TXFRAMEI TP10
RXSTB 13 7
B6 A6 RXSTBI
PI 12 8
B7 A7 PII
TB84 11 B8 A8 9 TB84I +3V3

R47 R46 R48

4K7 4K7 4K7
R302
33
+3V3 XTCK
U30
XC2S100E J2
TB54
T2 M0 TDI C13 1 2
R1 B14 XTD1 XTDO 3 4
R36 M1 TDO
R3 B1 XTMS 5 6
33 M2 TMS
XCCLKA A15 A2 7 8
CCLK TCK
XPROGA R16 XTDI 9 10
PROGRAM
XDONEA T15 DONE
A
837 0147 042 Rev.A

1K00 1K00
R58
FORM:

R57

SHEET DESCRIPTION:
"7350" CONTROL BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 2 11

 1 2 3 4 5 6 7 8 9 10 11

82 R181 R201
100P C159 TCLK0 0

82 R177 R206
100P C181 0
DPTCLK0

F 100P C282 82 R209 33 R203

DPTCLK1

100P C286 82 R211 33 R202

DPTCLK2

100P C302 82 R215 33 R205

TXS1

82 R180 R204
100P C158 0
TXS0

U27 U27 U27 U27

RFI[0:15] XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4
TB58 TB72
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

E RFI15 B4 IO IO/GCLK3P F12 FIROUTCK HWC0 C21 IO IO M21 TB80 AB19 IO/DOUT IO/GCLK7S AA11 TCWE V5 IO IO L2
RFI14 A4 IO IO/GCLK2S F13 HWC1 C22 IO IO M20 TB81 RFXINIT AA19 IO/INIT_B IO/GCLK6P Y11 LSCNT U5 IO IO L3
RFI13 C4 E12 E18 M19 XDATA0 V18 W11 LA0 Y2 L4 TCINT0
IO IO/GCLK1P IO/VRP2 IO IO/D0 IO/GCLK5S IO/VRN6 IO
RFI12 C5 D12 PBB/CI F18 M18 XDATA1 V17 V11 LA1 Y1 L5 TCINT1
IO IO/GCLK0S IO/VRN2 IO IO/D1 IO/GCLK4P IO/VRP6 IO
RFI11 B5 C12 REAL0 PBA/BI D21 M17 XDATA2 W18 U11 LA2 LA[0:4] V4 K1 TCINT2
IO/VRP0 IO IO IO/VREF3 IO/D2/ALT_VRP4 IO IO IO/VREF7
RFI10 A5 B12 REAL1 PEDI D22 N17 XDATA3 Y18 U10 LA3 V3 K2 TCINT3
IO/VRN0 IO/VREF1 IO/VREF2 IO IO/D3/ALT_VRN4 IO/VREF5 IO/VREF6 IO
RFI9 D6 A13 REAL2 E19 N22 TB79 MPADLDAC AA18 AB10 LA4 TB49 W2 K3

REAL[0:15]
IO/VREF0 IO IO IO IO/VREF4 IO IO IO
RFI8 C6 IO IO B13 REAL3 SELB/CI E20 IO IO N21 TB78 MPADLOAD AB18 IO IO AA10 LD0 W1 IO IO K4 TCOE
RFI7 B6 C13 REAL4 SELA/BI E21 N20 MPADDATA W17 Y10 LD1 SCSTOP U4 L6 TCSCTRL
IO IO IO IO IO/VRP4 IO IO IO
RFI6 A6 D13 REAL5 SELPEDI E22 N19 MPADCK Y17 W10 LD2 U3 K6 TCSEPROM
IO IO IO IO IO/VRN4 IO LD[0:15] IO IO
E7 E13 REAL6 F19 N18 MOTORON AA17 V10 LD3 CTRLD3 V2 K5 TCD0
IO IO IO IO IO IO IO IO
E8 IO IO/VREF1 E14 REAL7 F20 IO IO P18 TB70 AB17 IO IO/VREF5 V9 LD4 DL V1 IO IO J5 TCD1
D7 IO IO A14 REAL8 GSEL0I F21 IO IO/VREF3 P22 TB77 V16 IO IO AB9 LD5 ML U2 IO IO/VREF7 J1 TCD2
RFI5 C7 IO/VREF0 IO B14 REAL9 GSEL1I F22 IO/VREF2 IO P21 TB76 V15 IO IO AA9 LD6 IL U1 IO/VREF6 IO J2 TCD3
RFI4 B7 C14 REAL10 G18 P20 W16 Y9 LD7 ACFM0 T5 J3 TCD4
IO IO IO IO IO IO IO IO
RFI3 A7 D14 REAL11 H18 P19 Y16 W9 LD8 ACFM1 R5 J4 TCD5
IO IO IO IO IO/VREF4 IO IO IO
CFMON
D8 A15 REAL12 G19 R22 AA16 AB8 LD9 T4 H1 TCD6
IO IO/VREF1 IO IO IO IO/VREF5 IO IO
D RFI2 C8 IO IO B15 REAL13 G20 IO IO R21 CFMOFF TB68 AB16 IO IO AA8 LD10 TB52 T3 IO IO H2 TCD7
RFI1 B8 IO IO C15 REAL14 MOT1 G21 IO IO R20 W15 IO IO Y8 LD11 TB51 T2 IO IO H3 TCD8
RFI0 A8 IO IO D15 REAL15 MOT0 G22 IO IO R19 Y15 IO IO W8 LD12 TB50 T1 IO IO H4 TCD9
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

E9 F14 IMG0 H19 R18 AA15 U9 LD13 TCTIM0 R4 J6 TCD10

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

IO IO IO IO/VREF3 IO IO IO IO/VREF7
TB67
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

F9 E15 IMG1 H20 P17 AB15 V8 LD14 TCTIM1 R3 H5 TCD11

IO/VREF0 IO IO/VREF2 IO IO IO IO/VREF6 IO
CTAUX4 D9 A16 IMG2 PROBE H21 T22 MLN0 U14 AB7 LD15 TCA0 R2 G1 TCD12
IMG[0:15]

IO IO IO IO IO IO IO IO
TCA[0:19]
CTAUX5 C9 B16 IMG3 H22 T21 MLN1 V14 AA7 LRW TCA1 R1 G2 TCD13
IO IO IO IO IO/VREF4 IO IO IO
CTAUX6 B9 C16 IMG4 J17 T20 W14 Y7 TCA2 P6 G3 TCD14 TCD[0:15]
IO IO/VREF1 IO IO IO IO/VREF5 IO IO
CTAUX7 A9 D16 IMG5 J18 T19 Y14 W7 HP0 TCA3 P5 G4 TCD15
IO IO IO IO IO IO IO IO
E10 E16 IMG6 J19 U22 MLN2 AA14 AB6 HP1 TCA4 P4 F1
CTAUX[0:7]

IO/VREF0 IO IO IO IO IO IO IO

HP[0:6]
F10 IO IO E17 IMG7 J20 IO IO U21 MLN3 TB65 AB14 IO IO AA6 HP2 TCA5 P3 IO IO F2 DACCLK
CTAUX0 D10 A17 IMG8 J21 U20 U13 Y6 HP3 TCA6 P2 F3 DACDATA0
IO IO IO IO/VREF3 IO/VREF4 IO IO IO/VREF7
CTAUX1 C10 B17 IMG9 J22 U19 V13 W6 HP4 TCA7 P1 F4 DACDATA1
IO IO IO/VREF2 IO IO IO IO/VREF6 IO
CTAUX2 B10 C17 IMG10 K17 T18 W13 V7 HP5 TCA8 N6 G5 DACDATA2
IO IO IO IO IO IO/VRP5 IO IO
CTAUX3 A10 D17 IMG11 K18 U18 Y13 V6 HP6 TCA9 N5 F5 DACDATA3
IO IO/VREF1 IO IO IO IO/VRN5 IO IO
E11 A18 K19 V22 AA13 AB5 TCA10 N4 E1 DACDATA4
IO/VREF0 IO/VRP1 IO IO IO IO IO IO
F11 IO IO/VRN1 B18 K20 IO IO V21 ACFM TB64 AB13 IO IO/VREF5 AA5 TCA11 N3 IO IO E2 DACDATA5
D11 C18 IMG12 K21 V20 U12 Y5 XDATA4 TCA12 N2 E3 DACDATA6
C IO/GCLK7P IO IO IO IO/VREF4 IO/D4/ALT_VRP5 IO IO
C11 D18 IMG13 K22 V19 V12 W5 XDATA5 TCA13 N1 E4 DACDATA7
IO/GCLK6S IO IO IO IO IO/D5/ALT_VRN5 IO IO
B11 IO/GCLK5P IO A19 IMG14 L17 IO IO/VREF3 W22 DREADY0 TB61 W12 IO/GCLK3S IO/D6 AB4 XDATA6 TCA14 M6 IO IO/VREF7 D1 DACDATA8
A11 B19 IMG15 L18 W21 Y12 AA4 XDATA7 TCA15 M5 D2 DACDATA9
IO/GCLK4S IO IO/VREF2 IO IO/GCLK2P IO/D7 IO/VREF6 IO
L19 Y22 DREADY1 TXREFBE AA12 Y4 XWE TCA16 M4 C1 DACDATA10
IO IO/VRP3 IO/GLCK1S IO/RDWR_B IO IO/VRN7
L20 Y21 CK40C AB12 AA3 RFCSA TCA17 M3 C2 DACDATA11
IO IO/VRN3 IO/GCLK0P IO/CS_B IO IO/VRP7
L21 W20 TCA18 M2 E5 DACDATA12
IO IO IO IO
+3V3 +3V3
L22 AA20
+3V3 TB57 +3V3 TCA19 M1 E6 DACDATA13
IO IO IO IO

G11 VCCOBank0 VCCOBank1 G14 L16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 L7
G10 VCCOBank0 VCCOBank1 G13 K16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 K7
G9 G12 J16 P16 T14 T11 P7 J7 +3V3
VCCOBank0 VCCOBank1 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T10 N7 VCCOBank6 VCCOBank7 H6
F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 M16 T12 VCCOBank4 VCCOBank5 T9 M7 VCCOBank6 VCCOBank7 G6

J4
B 33 R230 2 1 RFTEST1
R222 33 4 3 RFTEST2 +3V3
+3V3 R26 +5V
6 5 U19 10
8 7 THS5671A
10 9 DACCLK 28 24
CLK AVDD
+3V3
25 MODE
100N C14 C17
1K00 COMP1 19 C12 47U
33 DACDATA0 14
SMP R235 +3V3
TB55 R229 U27 D0 100N
U37 DACDATA1 13 23
D1 COMP2
XC2V1000-4 DACDATA2 12
74LCX245 RFXCCLK Y19 C19 XTCK
D2
100N C13
33 CCLK TCK DACDATA3 11 22
R234 19 G RFXPROG A2 D3 XTD2
D3 IOUT1
TXS PROG_B TDI DACDATA4 10
1 D4 RFTEST1
T/R RFXDONE AB20 D20 XTD3
DONE TDO DACDATA5 9 21
D5 IOUT2
33 R233 SELPEDI 2 A1 B1 18 SELPED AB2 M0 TMS B20 XTMS
DACDATA6 8
RFTEST2
DPTCK D6 100N
SELA/BI 3 17 SELA/B W3 D5
A2 B2 M1 DXN DACDATA7 7 16 C16
D7 EXTLO
SELB/CI 4 16 SELB/C AB3 A3
A3 B3 M2 DXP DACDATA8 6 17
33 R232 D8 EXTIO
TCLK
PEDI 5 A4 B4 15 PED B3 HSWAP_EN VBATT A21 DACDATA9 5 18 TP5 TP4
D9 BIASJ
A PBA/BI 6 A5 B5 14 PBA/B AB21 PWRDWN_B RSVD A20 DACDATA10 TP7
PBB/CI PBB/C
4 D10 2K2 R28 R27
837 0147 042 Rev.A

7 A6 B6 13 1K00 DACDATA11 3 D11 SLEEP 15 R29 47 47

GSEL0I 8 A7 B7 12 GSEL0 R207 DACDATA12 2 D12
FORM:

GSEL1I 9 11 GSEL1
A8 B8 DACDATA13 1 20
D13 AGND
DACDATA[0:13]

SHEET DESCRIPTION:
"7350" CONTROL BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 3 11

 1 2 3 4 5 6 7 8 9 10 11
+3V3

R219
33
U28 R226 U28 U28 U28
XC2V1000-4 33 XC2V1000-4 XC2V1000-4 XC2V1000-4

TCA[0:19]
F BANK 0 BANK 1 BANK 2 BANK 3 TB74 BANK 4 BANK 5 BANK 6 BANK 7

LD[0:15]
RFADD0 B4 F12 POTCS BDIG11 C21 M21 LD0 AB19 AA11 TCA6 BWD5 V5 L2 RFDC10
IO IO/GCLK3P IO IO IO/DOUT IO/GCLK7S IO IO
RFADD1 A4 F13 TGCAB ADIG12 C22 M20 LD1 RFXINIT AA19 Y11 TCA7 BWD6 U5 L3 RFDC11
IO IO/GCLK2S IO IO IO/INIT_B IO/GCLK6P IO IO

RFDC[0:15]
RFADD2 C4 E12 TGCWE E18 M19 LD2 XDATA0 V18 W11 TCA8 BWD7 Y2 L4 RFDC12
RFADD[0:16]

IO IO/GCLK1P IO/VRP2 IO IO/D0 IO/GCLK5S IO/VRN6 IO

RFADD3 C5 D12 POTCK F18 M18 LD3 XDATA1 V17 V11 TCA9 CTRLD0 Y1 L5 RFDC13
IO IO/GCLK0S IO/VRN2 IO IO/D1 IO/GCLK4P IO/VRP6 IO
RFADD4 B5 C12 TGCD0 BDIG12 D21 M17 LD4 XDATA2 W18 U11 TCA10 CTRLD1 V4 K1 RFDC14
IO/VRP0 IO IO IO/VREF3 IO/D2/ALT_VRP4 IO IO IO/VREF7
RFADD5 A5 B12 TGCD1 ADIG13 D22 N17 LD5 XDATA3 Y18 U10 TCA11 CND0 V3 K2 RFDC15
IO/VRN0 IO/VREF1 IO/VREF2 IO IO/D3/ALT_VRN4 IO/VREF5 IO/VREF6 IO

TGCD[0:7]
RFADD6 D6 A13 TGCD2 BDIG13 E19 N22 LD6 IMG7 AA18 AB10 TCA16 CND1 W2 K3 OEMEMC
IO/VREF0 IO IO IO IO/VREF4 IO IO IO
RFADD7 C6 B13 TGCD3 ADIG14 E20 N21 LD7 IMG6 AB18 AA10 TCA17 CND2 W1 K4 WEMEMC
IO IO IO IO IO IO IO IO

CND[0:7]
RFADD8 B6 C13 TGCD4 BDIG14 E21 N20 LD8 IMG5 W17 Y10 TCA18 CND3 U4 L6 RFADC14
IO IO IO IO IO/VRP4 IO IO IO
RFADD9 A6 D13 TGCD5 ADIG15 E22 N19 LD9 IMG4 Y17 W10 TCA19 CND4 U3 K6 RFDB0
IO IO IO IO IO/VRN4 IO IO IO
RFADD10 E7 E13 TGCD6 BDIG15 F19 N18 LD10 IMG3 AA17 V10 TCD0 CND5 V2 K5 RFDB1
IO IO IO IO IO IO IO IO
RFADD11 E8 E14 TGCD7 ADIGREF0 F20 P18 LD11 IMG2 AB17 V9 TCD1 CND6 V1 J5 RFDB2
IO IO/VREF1 IO IO IO IO/VREF5 IO IO
RFADD12 D7 A14 POTEOC BDIGREF0 F21 P22 LD12 IMG1 V16 AB9 TCD2 CND7 U2 J1 RFDB3
IO IO IO IO/VREF3 IO IO IO IO/VREF7
RFADD13 C7 B14 POTADD DDIG0 F22 P21 LD13 IMG0 V15 AA9 TCD3 RFDA0 U1 J2 RFDB4

TCD[0:15]
IO/VREF0 IO IO/VREF2 IO IO IO IO/VREF6 IO
RFADD14 B7 C14 POTDOUT DDIG1 G18 P20 LD14 REAL15 W16 Y9 TCD4 RFDA1 T5 J3 RFDB5
IO IO IO IO IO IO IO IO
E RFADD15 A7 IO IO D14 ADIG0 DDIG2 H18 IO IO P19 LD15 REAL14 Y16 IO/VREF4 IO W9 TCD5 RFDA2 R5 IO IO J4 RFDB6
RFADD16 D8 A15 BDIG0 DDIG3 G19 R22 LSCNT REAL13 AA16 AB8 TCD6 RFDA3 T4 H1 RFDB7
IO IO/VREF1 IO IO IO IO/VREF5 IO IO

RFDB[0:15]
OEMEMD C8 B15 ADIG1 DDIG4 G20 R21 LRW REAL12 AB16 AA8 TCD7 RFDA4 T3 H2 RFDB8
IO IO IO IO IO IO IO IO
WEMEMD B8 C15 BDIG1 DDIG5 G21 R20 RFI0 REAL11 W15 Y8 TCD8 RFDA5 T2 H3 RFDB9
IO IO IO IO IO IO IO IO
CSMEMD A8 D15 ADIG2 DDIG6 G22 R19 RFI1 REAL10 Y15 W8 TCD9 RFDA6 T1 H4 RFDB10
IO IO IO IO IO IO IO IO
RFDD0 E9 F14 BDIG2 DDIG7 H19 R18 RFI2 REAL9 AA15 U9 TCD10 RFDA7 R4 J6 RFDB11
IO IO IO IO/VREF3 IO IO IO IO/VREF7
RFDD1 F9 E15 ADIG3 DDIG8 H20 P17 RFI3 REAL8 AB15 V8 TCD11 RFDA8 R3 H5 RFDB12
IO/VREF0 IO IO/VREF2 IO IO IO

RFDA[0:15]
IO/VREF6 IO
RFDD[0:15]

RFDD2 D9 A16 BDIG3 DDIG9 H21 T22 RFI4 REAL7 U14 AB7 TCD12 RFDA9 R2 G1 RFDB13
IO IO IO IO IO IO IO IO
RFDD3 ADIG4 DDIG10 RFI5 REAL6 TCD13 RFDA10 RFDB14

RFI[0:15]
C9 IO IO B16 H22 IO IO T21 V14 IO/VREF4 IO AA7 R1 IO IO G2
RFDD4 BDIG4 DDIG11 RFI6 REAL5 TCD14 RFDA11 RFDB15

REAL[0:15]
B9 IO IO/VREF1 C16 J17 IO IO T20 W14 IO IO/VREF5 Y7 P6 IO IO G3
RFDD5 A9 D16 ADIG5 DDIG12 J18 T19 RFI7 REAL4 Y14 W7 TCD15 RFDA12 P5 G4 OEMEMB
IO IO IO IO IO IO IO IO
RFDD6 E10 E16 BDIG5 DDIG13 J19 U22 RFI8 REAL3 AA14 AB6 TCWE RFDA13 P4 F1 WEMEMB
IO/VREF0 IO IO IO IO IO IO IO
RFDD7 F10 E17 ADIG6 DDIG14 J20 U21 RFI9 REAL2 AB14 AA6 TCOE RFDA14 P3 F2 RFADB14
IO IO IO IO IO IO IO IO
RFDD8 D10 A17 BDIG6 DDIG15 J21 U20 RFI10 REAL1 U13 Y6 TCSCTRL RFDA15 P2 F3 RFAD0
IO IO IO IO/VREF3 IO/VREF4 IO IO IO/VREF7
RFDD9 C10 B17 ADIG7 DDIG16 J22 U19 RFI11 REAL0 V13 W6 BWD0 OEMEMA P1 F4 RFAD1
IO IO IO/VREF2 IO IO IO IO/VREF6 IO
RFDD10 B10 C17 BDIG7 DDIG17 K17 T18 RFI12 TCA0 W13 V7 BWD1 WEMEMA N6 G5 RFAD2

BWD[0:7]
IO IO IO IO IO IO/VRP5 IO IO

RFAD[0:13]
IMG[0:15]
RFDD11 A10 D17 ADIG8 DDIG18 K18 U18 RFI13 TCA1 Y13 V6 BWD2 RFADA14 N5 F5 RFAD3
IO IO/VREF1 IO IO IO IO/VRN5 IO IO
D RFDD12 E11 A18 BDIG8 DDIG19 K19 V22 RFI14 TCA2 AA13 AB5 BWD3 RFDC0 N4 E1 RFAD4
IO/VREF0 IO/VRP1 IO IO IO IO IO IO

TCA[0:19]
RFDD13 F11 B18 ADIG9 ADIGREF1 K20 V21 RFI15 TCA3 AB13 AA5 BWD4 RFDC1 N3 E2 RFAD5
IO IO/VRN1 IO IO IO IO/VREF5 IO IO
RFDD14 D11 C18 BDIG9 BDIGREF1 K21 V20 IMG15 TCA4 U12 Y5 XDATA4 RFDC2 N2 E3 RFAD6
IO/GCLK7P IO IO IO IO/VREF4 IO/D4/ALT_VRP5 IO IO
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

RFDD15 C11 D18 ADIG10 LA0 K22 V19 IMG14 TCA5 V12 W5 XDATA5 RFDC3 N1 E4 RFAD7
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

IO/GCLK6S IO IO IO IO IO/D5/ALT_VRN5 IO IO

RFDC[0:15]
TB60
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

B11 A19 BDIG10 LA1 L17 W22 IMG13 DPTCLK1 W12 AB4 XDATA6 RFDC4 M6 D1 RFAD8
IO/GCLK5P IO IO IO/VREF3 IO/GCLK3S IO/D6 IO IO/VREF7
TB59 A11 IO/GCLK4S IO B19 ADIG11 LA2 L18 IO/VREF2 IO W21 IMG12 TXS1 Y12 IO/GCLK2P IO/D7 AA4 XDATA7 RFDC5 M5 IO/VREF6 IO D2 RFAD9
LA3 L19 Y22 IMG11 FIROUTCK AA12 Y4 XWE RFDC6 M4 C1 RFAD10
IO IO/VRP3 IO/GLCK1S IO/RDWR_B IO IO/VRN7
LA4 L20 Y21 IMG10 CK40D AB12 AA3 RFCSB RFDC7 M3 C2 RFAD11
IO IO/VRN3 IO/GCLK0P IO/CS_B IO IO/VRP7
ADIG[0:15]
DDIG[0:19]
BDIG[0:15]

L21 W20 IMG9 RFDC8 M2 E5 RFAD12

IO IO IO IO
LA[0:4]

+3V3 +3V3 +3V3

L22 IO IO AA20 IMG8 TB63 +3V3 RFDC9 M1 IO IO E6 RFAD13

G11 VCCOBank0 VCCOBank1 G14 L16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 L7
G10 VCCOBank0 VCCOBank1 G13 K16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 K7
G9 G12 J16 P16 T14 T11 P7 J7 +3V3
VCCOBank0 VCCOBank1 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T10 N7 VCCOBank6 VCCOBank7 H6
F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 M16 T12 VCCOBank4 VCCOBank5 T9 M7 VCCOBank6 VCCOBank7 G6

U20 U26 U25 U29

K6R1016V1D K6R1016V1D K6R1016V1D KM616V4002BT-15
OEMEMA 41 OEMEMB 41 OEMEMC 41 OEMEMD 41
OE OE OE OE
WEMEMA 17 WEMEMB 17 WEMEMC 17 WEMEMD 17
WE WE WE WE
6 6 6 CSMEMD 6
R198 CS R200 CS R199 CS CS
1K00 40 UB 1K00 40 UB 1K00 40 UB 40 UB
39 LB 39 LB 39 LB 39 LB +3V3
RFAD0 44 7 RFDA0 RFAD0 44 7 RFDB0 RFAD0 44 7 RFDC0 RFADD0 5 7 RFDD0
B A0 I/O0 A0 I/O0 A0 I/O0 A0 I/O0
RFAD1 43 8 RFDA1 RFAD1 43 8 RFDB1 RFAD1 43 8 RFDC1 RFADD1 4 8 RFDD1 +3V3
A1 I/O1 A1 I/O1 A1 I/O1 A1 I/O1
RFAD2 42 9 RFDA2 RFAD2 42 9 RFDB2 RFAD2 42 9 RFDC2 RFADD2 3 9 RFDD2
A2 I/O2 A2 I/O2 A2 I/O2 A2 I/O2
RFAD3 27 10 RFDA3 RFAD3 27 10 RFDB3 RFAD3 27 10 RFDC3 RFADD3 2 10 RFDD3
A3 I/O3 A3 I/O3 A3 I/O3 A3 I/O3
RFAD4 26 13 RFDA4 RFAD4 26 13 RFDB4 RFAD4 26 13 RFDC4 RFADD4 1 13 RFDD4
A4 I/O4 A4 I/O4 A4 I/O4 A4 I/O4
RFAD5 25 14 RFDA5 RFAD5 25 14 RFDB5 RFAD5 25 14 RFDC5 RFADD5 44 14 RFDD5 1K00
A5 I/O5 A5 I/O5 A5 I/O5 A5 I/O5
RFAD6 24 15 RFDA6 RFAD6 24 15 RFDB6 RFAD6 24 15 RFDC6 RFADD6 43 15 RFDD6 R231 U28 R210
A6 I/O6 A6 I/O6 A6 I/O6 A6 I/O6 TB73 4K7
RFAD7 21 A7 I/O7 16 RFDA7 RFAD7 21 A7 I/O7 16 RFDB7 RFAD7 21 A7 I/O7 16 RFDC7 RFADD7 42 A7 I/O7 16 RFDD7 XC2V1000-4
RFAD8 20 29 RFDA8 RFAD8 20 29 RFDB8 RFAD8 20 29 RFDC8 RFADD8 27 29 RFDD8 RFXCCLK Y19 C19 XTCK
A8 I/O8 A8 I/O8 A8 I/O8 A8 I/O8 CCLK TCK
RFAD9 19 30 RFDA9 RFAD9 19 30 RFDB9 RFAD9 19 30 RFDC9 RFADD9 26 30 RFDD9 RFXPROG A2 D3 XTD1
A9 I/O9 A9 I/O9 A9 I/O9 A9 I/O9 PROG_B TDI
RFAD10 18 31 RFDA10 RFAD10 18 31 RFDB10 RFAD10 18 31 RFDC10 RFADD10 25 31 RFDD10 RFXDONE AB20 D20 XTD2 J3
A10 I/O10 A10 I/O10 A10 I/O10 A10 I/O10 DONE TDO
RFAD11 5 32 RFDA11 RFAD11 5 32 RFDB11 RFAD11 5 32 RFDC11 RFADD11 24 32 RFDD11 AB2 B20 XTMS
A11 I/O11 A11 I/O11 A11 I/O11 A11 I/O11 M0 TMS 1 2
RFAD12 4 35 RFDA12 RFAD12 4 35 RFDB12 RFAD12 4 35 RFDC12 RFADD12 23 35 RFDD12 W3 D5
A12 I/O12 A12 I/O12 A12 I/O12 A12 I/O12 M1 DXN 3 4
RFAD13 3 36 RFDA13 RFAD13 3 36 RFDB13 RFAD13 3 36 RFDC13 RFADD13 22 36 RFDD13 AB3 A3
A13 I/O13 A13 I/O13 A13 I/O13 A13 I/O13 M2 DXP 5 6
RFADA14 2 37 RFDA14 RFADB14 2 37 RFDB14 RFADC14 2 37 RFDC14 RFADD14 21 37 RFDD14 B3 A21
A14 I/O14 A14 I/O14 A14 I/O14 A14 I/O14 HSWAP_EN VBATT 7 8
1 38 RFDA15 1 38 RFDB15 1 38 RFDC15 RFADD15 20 38 RFDD15 AB21 A20
A15 I/O15 A15 I/O15 A15 I/O15 A15 I/O15 PWRDWN_B RSVD 9 10
22 22 22 RFADD16 19
NC NC NC A16
23 NC 23 NC 23 NC 18 A17
A 28 28 28 1K00
NC NC NC
R208
837 0147 042 Rev.A
FORM:

SHEET DESCRIPTION:
"7350" CONTROL BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 4 11

 1 2 3 4 5 6 7 8 9 10 11

U15 U15 U15 U15 TB35

TB12
XC2S300 XC2S300 XC2S300 XC2S300
TB23
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

DP2D0 A3 A11 CK40E SCCTRL8 C21 L22 CFM2D0 U12 U9 CFM1D0 M1 C1 BW1D0
I/O GCK2,I I/O(DOUT,BUSY) I/O(TRDY) I/O I/O I/O(TRDY) I/O
DP2D1 A4 A12 DP1D0 SCCTRL0 C22 M17 CFMPD22 U13 U10 CFM1D9 M2 C2 AVG_DATA3
I/O I/O(DLL) I/O(DIN,D0) I/O I/O I/O I/O I/O
DP2D2 A5 A13 DP1D1 BWPD7 D20 M18 CFMPD15 U14 U11 SCAN_MODEOUT4 M3 D1 BW1D1
I/O I/O I/O I/O I/O I/O I/O I/O
DP2D3 A6 A14 DP1D2 BW2D7 D21 M19 CFMPD7 V12 V6 LINK10 LD2 M4 D2 AVG_DATA4
I/O I/O I/O(VREFBank2) I/O I/O I/O I/O I/O
DP2D4 A7 A15 DP1D3 BW2D0 D22 M20 CFM2D15 V13 V7 LINK11 LD15 M5 D3 AVG_DATA12
I/O I/O I/O I/O I/O(VREFBank4) I/O I/O I/O
DP2D5 A8 I/O I/O A16 DP1D4 CNPD6 E19 I/O I/O M21 CFM2D8 V14 I/O I/O(VREFBank5) V8 TB30 M6 I/O I/O E1 BW1D2
DP2D6 A9 I/O I/O A17 DP1D5 CNPD0 E20 I/O I/O M22 CFM2D1 TB13 V15 I/O(VREFBank4) I/O V9 CFM1D1 N1 I/O I/O(VREFBank7) E2 AVG_DATA5
E DP2D7 A10 I/O I/O A18 DP1D6 BWPD0 E21 I/O I/O(D4) N17 SCCTRL4 V16 I/O I/O(VREFBank5) V10 TB25 CFM1D10 N2 I/O I/O E3 AVG_DATA13
QM2D0 B3 A19 DP1D7 BW2D1 E22 N18 CFMPD16 V17 V11 SCAN_MODEOUT5 N3 F1 BW1D3
I/O I/O I/O I/O(VREFBank3) I/O I/O I/O(VREFBank6) I/O
QM2D1 B4 A20 XWE SCCTRL10 F18 N19 CFMPD8 DDOTIN W12 W5 LINK8 LD3 N4 F2 AVG_DATA6
I/O I/O(WRITE) I/O I/O I/O I/O I/O I/O(VREFBank7)
QM2D2 B5 B12 QM1D0 CNPD7 F19 N20 CFMPD0 W13 W6 LINK9 LA0 N5 F3 AVG_DATA14
I/O I/O I/O I/O I/O I/O I/O I/O
QM2D3 B6 I/O(VREFBank0) I/O(VREFBank1) B13 QM1D1 CNPD1 F20 I/O I/O N21 CFM2D9 TB20 W14 I/O I/O W7 DLINEIN N6 I/O I/O F4 DL
QM2D4 B7 B14 QM1D2 BWPD1 F21 N22 CFM2D2 W15 W8 CFM1D2 P1 F5 LD9
I/O I/O I/O(VREFBank2) I/O I/O I/O I/O I/O
QM2D5 B8 B15 QM1D3 BW2D2 F22 P17 CFMPD23 W16 W9 CFM1D11 P2 G1 BW1D4
I/O I/O I/O I/O I/O I/O I/O I/O
QM2D6 B9 B16 QM1D4 SCCTRL11 G18 P18 CFMPD17 LINK14 W17 W10 SCAN_MODEOUT6 P3 G2 AVG_DATA7
I/O I/O I/O I/O I/O I/O I/O I/O
QM2D7 B10 B17 QM1D5 SCSTOP G19 P19 CFMPD9 LINK15 W18 W11 LD4 P4 G3 AVG_DATA15
I/O I/O I/O I/O I/O(VREFBank4) I/O I/O I/O
QM2D8 B11 B18 QM1D6 CNPD2 G20 P20 CFMPD1 TXS0 Y12 Y5 DPD0 LA1 P5 G4 SCAUX0
I/O(DLL) I/O(VREFBank1) I/O I/O I/O(DLL) I/O I/O I/O
QM2D9 C4 I/O I/O B19 QM1D7 BWPD2 G21 I/O I/O P21 CFM2D10 DPD7 Y13 I/O I/O Y6 DPD1 TB32 P6 I/O I/O G5 LD10
QM2D10 C5 I/O(VREFBank0) I/O(CS) B20 SCXCS1 BW2D3 G22 I/O I/O(D5) P22 SCCTRL5 TB14 Y14 I/O I/O Y7 DPD2 CFM1D3 R1 I/O I/O H1 BW1D5
QM2D11 C6 C12 RHO_WEIGHT0 SCCTRL12 H18 R18 CFMPD18 DPAUX Y15 Y8 DPD3 CFM1D12 R2 H2 AVG_DATA8
I/O I/O I/O(VREFBank2) I/O(VREFBank3) I/O I/O I/O I/O
THETA_WEIGHT0 C7 C13 RHO_WEIGHT1 SCCTRL1 H19 R19 SCCTRL6 Y16 Y9 DPD4 SCAN_MODE7 R3 H3 SCAN_MODEOUT0
I/O I/O I/O(D1) I/O(D6) I/O I/O I/O(VREFBank6) I/O(VREFBank7)
THETA_WEIGHT1 C8 I/O I/O C14 RHO_WEIGHT2 SCCTRL2 H20 I/O(D2) I/O R20 CFMPD2 TB15 Y17 I/O(VREFBank4) I/O Y10 DPD5 LD5 R4 I/O I/O H4 SCAUX1
THETA_WEIGHT2 C9 C15 RHO_WEIGHT3 BWPD3 H21 R21 CFM2D11 LINK12 Y18 Y11 DPD6 LA2 R5 H5 LD11
I/O I/O I/O I/O I/O I/O I/O I/O
THETA_WEIGHT3 C10 C16 QM1D8 BW2D4 H22 R22 CFM2D3 LINK13 Y19 AA3 BWD0 CFM1D4 T1 J1 BW1D6
I/O I/O I/O I/O I/O I/O I/O I/O
D DPTCLK0 C11 C17 QM1D9 LINK7 J17 T18 CFMPD19 SCCLK1 AA12 AA5 BWD1 CFM1D13 T2 J2 AVG_DATA9
GCK3,I I/O I/O I/O GCK0/I I/O I/O I/O
QM2D12 D5 C18 QM1D10 SCCTRL13 J18 T19 CFMPD10 CND0 AA13 AA6 BWD2 SCAN_MODE8 T3 J3 SCAN_MODEOUT1
I/O I/O I/O I/O I/O I/O I/O I/O
QM2D13 D6 I/O I/O D12 QM1D14 TB4 J19 I/O I/O T20 CFMPD3 CND1 AA14 I/O I/O AA7 BWD3 LD6 T4 I/O I/O J4 ESCANOUT
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

QM2D14 D7 D13 QM1D15 CNPD3 J20 T21 CFM2D12 CND2 AA15 AA8 BWD4 LA3 T5 J5 LD12
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

I/O I/O I/O I/O(VREFBank3) I/O I/O I/O I/O

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

QM2D15 D8 D14 CTRLD0 BWPD4 J21 T22 CFM2D4 CND3 AA16 AA9 BWD5 CFM1D5 U1 J6 LA4
I/O(VREFBank0) I/O I/O I/O I/O I/O I/O(VREFBank6) I/O
QM1D11 D9 D15 CTRLD1 BW2D5 J22 U18 CFMPD20 CND4 AA17 AA10 BWD6 CFM1D14 U2 K1 BW1D7
I/O I/O(VREFBank1) I/O I/O I/O I/O I/O I/O
QM1D12 D10 D16 TCLK0 K17 U19 CFMPD11 CND5 AA18 AA11 BWD7 SCAN_MODE9 U3 K2 AVG_DATA10
I/O(VREFBank0) I/O I/O I/O I/O I/O I/O I/O
QM1D13 D11 D17 CTRLD3 CFMPD13 K18 U20 CFMPD4 CND6 AA19 AB3 CFMD0 LD7 U4 K3 SCAN_MODEOUT2
I/O I/O I/O(VREFBank2) I/O I/O I/O I/O I/O(VREFBank7)
ML E7 D18 IL SCCTRL3 K19 U21 CFM2D13 CND7 AA20 AB4 CFMD1 CFM1D6 V1 K4 LD0
I/O I/O I/O(D3) I/O I/O I/O I/O I/O
MOT0 E8 E12 SCCTRLRW CNPD4 K20 U22 CFM2D5 CFMD9 AB13 AB5 CFMD2 CFM1D15 V2 K5 LD13
I/O I/O I/O I/O I/O I/O(VREFBank5) I/O(VREFBank6) I/O
MOT1 E9 E13 SCCTRLCS BWPD5 K21 V19 CFMPD12 CFMD10 AB14 AB6 CFMD3 MCYCLE_START V3 K6 LSSCAN
I/O I/O I/O I/O I/O I/O I/O I/O
E10 E14 SCCTRL9 BW2D6 K22 V20 CFMPD5 CFMD11 AB15 AB7 CFMD4 LD8 V4 L1 AVG_DATA0
I/O I/O I/O I/O I/O I/O(VREFBank5) I/O I/O
ACFM0 E11 E15 DPTCLK0 CFMPD21 L17 V21 CFM2D14 CFMD12 AB16 AB8 CFMD5 CFM1D7 W1 L2 AVG_DATA11
I/O I/O I/O I/O I/O I/O I/O I/O
LINK1 F9 E16 ACFM1 CFMPD14 L18 V22 CFM2D6 CFMD13 AB17 AB9 CFMD6 AVG_DATA1 W2 L3 SCAN_MODEOUT3
I/O I/O(VREFBank1) I/O I/O(VREFBank3) I/O I/O I/O I/O
LINK2 F10 E17 LINK0 CFMPD6 L19 W21 SCXINIT CFMD14 AB18 AB10 CFMD7 MRESET_DONE W3 L4 LD1
I/O I/O I/O I/O(INIT) I/O I/O I/O I/O
LINK3 F11 F12 LINK4 CNPD5 L20 W22 CFM2D7 CFMD15 AB19 AB11 CFMD8 CFM1D8 Y1 L5 LD14
I/O I/O I/O I/O I/O I/O(DLL) I/O I/O
F13 LINK5 BWPD6 L21 Y22 SCCTRL7 CFMD16 AB20 AB12 SCCLK0 AVG_DATA2 Y2 L6 LRW
I/O I/O(IRDY) I/O(D7) I/O GCK1,I I/O I/O(IRDY)
F14 LINK6 CFMD17 AB21
C I/O I/O
TB5
TB26 F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T9 TB19 N7 VCCOBank6 VCCOBank7 G6
F8 F16 H17 P16 T14 T10 P7 H6
TB29 VCCOBank0 VCCOBank1
TB11 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
G9 G13 J16 R17 U15 U7 R6 J7
TB24 VCCOBank0 VCCOBank1 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
TB31 G10 VCCOBank0 VCCOBank1 G14 TB7 K16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7

TB3
+3V3 +3V3 +3V3 +3V3
+3V3 +3V3 +3V3
+3V3
VICINO PIN U15
R174
TB27 VICINO PIN U15
82

C171
R11 VICINO PIN U15
100P
82

C7
100P
B +3V3

TB10
TB8
U15
TB9
XC2S300
SCXCCLK B22 E6 XTCK
CCLK TCK
SCXPROG Y21 PROGRAM
SCXDONE W20 DONE
AA1 C19 XTD4
M0 TDI
U5 A21 XTDO
M1 TDO
AB2 E4 XTMS
M2 TMS
R196
1K00

A
837 0147 042 Rev.A
FORM:

SHEET DESCRIPTION:
"7350" CONTROL BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 5 11

 1 2 3 4 5 6 7 8 9 10 11

+3V3 +3V3
+3V3
+3V3

R189 R161
33 R186 R162 33 R172 33 R195
R170 R194
F 33
TB16 33 33 33 33
U14 R179
U14
XC2V1000-4 33 U14 U14
SCCLK1 XC2V1000-4
TB28 XC2V1000-4 XC2V1000-4 TB40
VICINO PIN U14
BANK 0 BANK 1
BANK 2 BANK 3
BANK 4 BANK 5 TB42
BANK 6 BANK 7
MICD11 B4 F12 LSSCAN
IO IO/GCLK3P BW2A9 C21 M21 CFM2A7
IO IO
MICD5 A4 F13 ML SCCTRL8 AB19 AA11 DPTCLK0
IO IO/GCLK2S BW2A0 C22 M20 CFM2A15 IO/DOUT IO/GCLK7S LD6 V5 L2 BW1A14
IO IO IO IO
LD13 C4 E12 DL SCXINIT AA19 Y11 TCLK0
IO IO/GCLK1P LINK14 E18 M19 CFMPA3 IO/INIT_B IO/GCLK6P LD5 U5 L3 SCAN_MODEOUT0
IO/VRP2 IO IO IO
LD14 C5 D12 MOT0 SCCTRL0 V18 W11 CTRLD1
IO IO/GCLK0S LINK15 F18 M18 CFMPA10 IO/D0 IO/GCLK5S LINK4 Y2 L4 SCAN_MODE7
IO/VRN2 IO IO/VRN6 IO
LINK11 B5 C12 MICUB SCCTRL1 V17 V11 CTRLD0
IO/VRP0 IO BW2A10 D21 M17 CFMPA16 IO/D1 IO/GCLK4P LINK5 Y1 L5 MRESET_DONE
IO IO/VREF3 IO/VRP6 IO
LINK10 A5 B12 MICA12 SCCTRL2 W18 U11 QM1D12
IO/VRN0 IO/VREF1 BW2A1 D22 N17 CFMPA17 IO/D2/ALT_VRP4 IO XY_ADD8 V4 K1 BW1A6
IO/VREF2 IO IO IO/VREF7
LA0 D6 A13 MICA5 SCCTRL3 Y18 U10 QM1D11
IO/VREF0 IO BWPA4 E19 N22 CFM2A0 IO/D3/ALT_VRN4 IO/VREF5 XY_ADD1 V3 K2 BW1A13
IO IO IO/VREF6 IO
LD15 C6 B13 MICA11 QM1D3 AA18 AB10 DP2D5
IO IO BW2A18 E20 N21 CFM2A8 IO/VREF4 IO CFM1A15 W2 K3 BW1WE
IO IO IO IO
MICD10 B6 C13 MICOE DP1D5 AB18 AA10 QM2D3
IO IO BW2A11 E21 N20 CFM2A16 IO IO CFM1A7 W1 K4 SCAN_MODEOUT6
IO IO IO IO
MICD4 A6 D13 MOT1 LINK3 W17 Y10 THETA_WEIGHT0
IO IO BW2A2 E22 N19 CFMPA4 IO/VRP4 IO XY_ADD7 U4 L6 LD9
IO IO IO IO
LA3 E7 E13 SCSTOP LINK2 Y17 W10 QM2D9
IO IO BWPA5 F19 N18 CFMPA11 IO/VRN4 IO XY_ADD0 U3 K6 LD8
IO IO IO IO
E DPAUX E8 E14 QM1D2 AA17 V10 QM1D8
IO IO/VREF1 BW2OE F20 P18 CFMPA12 IO IO CFM1A14 V2 K5 MCYCLE_START
IO IO IO IO
LA2 D7 A14 MICA4 DP1D4 AB17 V9 QM2D11
IO IO BW2A12 F21 P22 CFM2A1 IO IO/VREF5 CFM1A6 V1 J5 SCAUX1
IO IO/VREF3 IO IO
MICD15 C7 B14 MICA10 QM2D14 V16 AB9 DP2D4
IO/VREF0 IO BW2A3 F22 P21 CFM2A9 IO IO CFM1A13 U2 J1 BW1A5
IO/VREF2 IO IO IO/VREF7
MICD9 B7 C14 MICLB QM2D13 V15 AA9 QM2D2
IO IO BWPA11 G18 P20 CFM2A17 IO IO CFM1A5 U1 J2 BW1A12
IO IO IO/VREF6 IO
MICD3 A7 D14 ACFM1 RHO_WEIGHT3 W16 Y9 QM2D7
IO IO BWPA12 H18 P19 CFMPA5 IO IO LD4 T5 J3 BW1OE
IO IO IO IO
LA4 D8 A15 MICA3 QM1D7 Y16 W9 QM2D8
IO IO/VREF1 BWPA6 G19 R22 CFM2A2 IO/VREF4 IO LD3 R5 J4 SCAN_MODEOUT5
IO IO IO IO
MICD14 C8 B15 MICA9 QM1D1 AA16 AB8 DP2D3
IO IO BW2WE G20 R21 CFM2A10 IO IO/VREF5 XY_ADD6 T4 H1 BW1A4
IO IO IO IO
MICD8 B8 IO IO C15 TB17 BW2A13 G21 R20 CFM2A18
DP1D3 AB16 IO IO AA8 QM2D1
CFM1WE T3 H2 BW1A11
IO IO IO IO
MICD2 A8 D15 CFMPWE RHO_WEIGHT2 W15 Y8 QM2D6
IO IO BW2A4 G22 R19 CFMPA6 IO IO CFM1A12 T2 H3 BW1A18
IO IO IO IO
MICCS E9 F14 SCCTRL9 QM1D6 Y15 W8 THETA_WEIGHT3
IO IO BWPA7 H19 R18 CFMPA13 IO IO CFM1A4 T1 H4 SCAN_MODEOUT4
IO IO/VREF3 IO IO
SCCTRL12 F9 E15 CNPWE QM1D0 AA15 U9 QM2D15
IO/VREF0 IO BWPA0 H20 P17 CFMPA18 IO IO XY_ADD5 R4 J6 LD7
IO/VREF2 IO IO IO/VREF7
LRW D9 A16 MICA2 DP1D2 AB15 V8 QM2D10
IO IO BW2A14 H21 T22 CFM2A3 IO IO CFM1OE R3 H5 SCAUX0
IO IO IO/VREF6 IO
MICD13 C9 B16 MICA8 QM1D15 U14 AB7 DP2D2
IO IO BW2A5 H22 T21 CFM2A11 IO IO CFM1A11 R2 G1 BW1A3
IO IO IO IO
MICD7 B9 C16 MICA15 QM2D12 V14 AA7 QM2D0
IO IO/VREF1 BWPA16 J17 T20 CFM2OE IO/VREF4 IO CFM1A3 R1 G2 BW1A10
IO IO IO IO
MICD1 A9 D16 CNPOE RHO_WEIGHT1 W14 Y7 QM2D5
IO IO BWPA13 J18 T19 CFMPA7 IO IO/VREF5 LD12 P6 G3 BW1A17
IO IO IO IO
SCCTRLRW E10 E16 BWPWE QM1D5 Y14 W7 THETA_WEIGHT2
IO/VREF0 IO BWPA8 J19 U22 CFM2A4 IO IO LD2 P5 G4 SCAN_MODEOUT3
IO IO IO IO
SCCTRL11 F10 E17 CFMPOE DP1D7 AA14 AB6 DP2D1
IO IO BWPA1 J20 U21 CFM2A12 IO IO XY_ADD4 P4 F1 BW1A2
IO IO IO IO
ACFM0 D10 A17 MICA1 DP1D1 AB14 AA6 DP2D7
D IO IO BW2A15 J21 U20 CFM2WE IO IO CFM1A18 P3 F2 BW1A9
IO IO/VREF3 IO IO
MICD12 C10 B17 MICA7 QM1D14 U13 Y6 QM2D4
IO IO BW2A6 J22 U19 CFMPA8 IO/VREF4 IO CFM1A10 P2 F3 BW1A16
IO/VREF2 IO IO IO/VREF7
MICD6 B10 C17 MICA14 QM1D10 V13 W6 THETA_WEIGHT1
IO IO BWPA17 K17 T18 CFMPA14 IO IO CFM1A2 P1 F4 SCAN_MODEOUT2
IO IO IO/VREF6 IO
MICD0 A10 D17 BWPOE RHO_WEIGHT0 W13 V7 LINK1
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

IO IO/VREF1 BWPA14 K18 U18 CFMPA15 IO IO/VRP5 LD11 N6 G5 ESCANOUT

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

IO IO IO IO
SCCTRL13 E11 A18 LINK12 QM1D4 Y13 V6 LINK0
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

IO/VREF0 IO/VRP1 BWPA9 K19 V22 CFM2A5 IO IO/VRN5 LD1 N5 F5 SCAN_MODE9

IO IO IO IO
SCCTRL10 F11 B18 LINK13 DP1D6 AA13 AB5 DP2D0
IO IO/VRN1 BWPA2 K20 V21 CFM2A13 IO IO XY_ADD3 N4 E1 BW1A1
IO IO IO IO
IL D11 C18 MICA13 DP1D0 AB13 AA5 DP2D6
IO/GCLK7P IO BW2A16 K21 V20 CFMPA0 IO IO/VREF5 CFM1A17 N3 E2 BW1A8
IO IO IO IO
SCCTRLCS C11 D18 MICWE QM1D13 U12 Y5 SCCTRL4
IO/GCLK6S IO BW2A7 K22 V19 CFMPA9 IO/VREF4 IO/D4/ALT_VRP5 CFM1A9 N2 E3 BW1A15
IO IO IO IO
TXS0 B11 A19 MICA0 QM1D9 V12 W5 SCCTRL5
IO/GCLK5P IO BWPA18 L17 W22 CFM2A6 IO IO/D5/ALT_VRN5 CFM1A1 N1 E4 SCAN_MODEOUT1
SCCLK0 IO IO/VREF3 IO IO
A11 B19 MICA6 CTRLD3 W12 AB4 SCCTRL6
IO/GCLK4S IO BWPA15 L18 W21 CFM2A14 IO/GCLK3S IO/D6 LD10 M6 D1 BW1A0
IO/VREF2 IO IO IO/VREF7
33 DLINEIN Y12 AA4 SCCTRL7
BWPA10 L19 Y22 LINK7 IO/GCLK2P IO/D7 LD0 M5 D2 BW1A7
IO IO/VRP3 IO/VREF6 IO
DDOTIN AA12 Y4 XWE
VICINOR173
PIN U14 BWPA3 L20 Y21 LINK6 IO/GLCK1S IO/RDWR_B XY_ADD2 M4 C1 LINK8
IO IO/VRN3 IO IO/VRN7
CK40F AB12 AA3 SCXCS0
BW2A17 L21 W20 CFMPA1 IO/GCLK0P IO/CS_B CFM1A16 M3 C2 LINK9
IO IO IO IO/VRP7
BW2A8 L22 AA20 CFMPA2 TB18 CFM1A8 M2 E5 SCAN_MODE8
IO IO
TB22 TB34 IO IO
CFM1A0 M1 E6 LA1
IO IO
G11 VCCOBank0 VCCOBank1 G14
L16 T17 TB21 TB41
VCCOBank2 VCCOBank3
G10 VCCOBank0 VCCOBank1 G13 U16 VCCOBank4 VCCOBank5 U8
K16 VCCOBank2 VCCOBank3 R17 T6 VCCOBank6 VCCOBank7 L7
G9 VCCOBank0 VCCOBank1 G12 U15 VCCOBank4 VCCOBank5 U7
J16 VCCOBank2 VCCOBank3 P16 R6 VCCOBank6 VCCOBank7 K7
C F8 VCCOBank0 VCCOBank1 F16 T14 VCCOBank4 VCCOBank5 T11
H17 VCCOBank2 VCCOBank3 N16 P7 VCCOBank6 VCCOBank7 J7
F7 VCCOBank0 VCCOBank1 F15 T13 VCCOBank4 VCCOBank5 T10
G17 VCCOBank2 VCCOBank3 M16 N7 VCCOBank6 VCCOBank7 H6
T12 VCCOBank4 VCCOBank5 T9
M7 VCCOBank6 VCCOBank7 G6

+3V3 +3V3
+3V3 +3V3
+3V3 +3V3
+3V3 +3V3

33
R171
R169 33
33
R163 33
R164 R188 33
33 R190 33
R197 33
+3V3
+3V3 R192
+3V3
+3V3
B
+3V3 +3V3

R168
1K00 R193
U14 4K7
XC2V1000-4
SCXCCLK Y19 C19 XTCK
CCLK TCK
SCXPROG A2 D3 XTD3
PROG_B TDI
SCXDONE AB20 D20 XTD4 J1
DONE TDO
AB2 B20 XTMS
M0 TMS 1 2
TB6 W3 M1 DXN D5
3 4
AB3 M2 DXP A3
5 6
B3 HSWAP_EN VBATT A21
7 8
AB21 PWRDWN_B RSVD A20
9 10

A
R191
837 0147 042 Rev.A

1K00
FORM:

SHEET DESCRIPTION:
"7350" CONTROL BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 6 11

 1 2 3 4 5 6 7 8 9 10 11

U23 U22
U21 U13
CY7C1049 CY7C1049
CFM1OE 37 CFM1OE 37 CY7C1049 K6R1016V1D
OE OE
F CFM1WE 15 CFM1WE 15
BW1OE 37 OE
MICOE 41 OE
WE WE
BW1WE 15 MICWE 17
8 8 WE WE
CS CS
8 MICCS 6
CS CS
MICUB 40
CFM1A0 3 9 CFM1D0 CFM1A0 3 9 CFM1D8 UB
A0 I/O0 A0 I/O0
BW1A0 3 9 BW1D0 MICLB 39
CFM1A1 4 10 CFM1D1 CFM1A1 4 10 CFM1D9 A0 I/O0 LB
A1 I/O1 A1 I/O1
BW1A1 4 10 BW1D1
CFM1A2 5 13 CFM1D2 CFM1A2 5 13 CFM1D10 A1 I/O1 MICA0 44 7 MICD0
A2 I/O2 A2 I/O2 A0 I/O0
BW1A2 5 13 BW1D2
CFM1A3 6 14 CFM1D3 CFM1A3 6 14 CFM1D11 A2 I/O2 MICA1 43 8 MICD1
A3 I/O3 A3 I/O3 A1 I/O1
BW1A3 6 14 BW1D3
CFM1A4 7 31 CFM1D4 CFM1A4 7 31 CFM1D12 A3 I/O3 MICA2 42 9 MICD2
A4 I/O4 A4 I/O4 A2 I/O2
BW1A4 7 31 BW1D4
CFM1A5 16 32 CFM1D5 CFM1A5 16 32 CFM1D13 A4 I/O4 MICA3 27 10 MICD3
A5 I/O5 A5 I/O5 A3 I/O3
BW1A5 16 32 BW1D5
CFM1A6 17 35 CFM1D6 CFM1A6 17 35 CFM1D14 A5 I/O5 MICA4 26 13 MICD4
A6 I/O6 A6 I/O6 A4 I/O4
BW1A6 17 35 BW1D6
CFM1A7 18 36 CFM1D7 CFM1A7 18 36 CFM1D15 A6 I/O6 MICA5 25 14 MICD5
A7 I/O7 A7 I/O7 A5 I/O5
BW1A7 18 36 BW1D7
CFM1A8 19 CFM1A8 19 A7 I/O7 MICA6 24 15 MICD6
A8 A8 A6 I/O6
BW1A8 19
CFM1A9 20 CFM1D[0:7] CFM1A9 20 CFM1D[8:15] A8 MICA7 21 16 MICD7
A9 A9 A7 I/O7
BW1A9 20
CFM1A10 26 CFM1A10 26 A9 BW1D[0:7] MICA8 20 29 MICD8
A10 A10 A8 I/O8
BW1A10 26
CFM1A11 27 CFM1A11 27 A10 MICA9 19 30 MICD9
A11 A11 A9 I/O9
BW1A11 27
CFM1A12 28 CFM1A12 28 A11 MICA10 18 31 MICD10
A12 A12 A10 I/O10
BW1A12 28
CFM1A13 29 CFM1A13 29 A12 MICA11 5 32 MICD11
A13 A13 A11 I/O11
E BW1A13 29
CFM1A14 30 CFM1A14 30 A13 MICA12 4 35 MICD12
A14 A14 A12 I/O12
BW1A14 30
CFM1A15 38 CFM1A15 38 A14 MICA13 3 36 MICD13
A15 A15 A13 I/O13
BW1A15 38
CFM1A16 39 CFM1A16 39 A15 MICA14 2 37 MICD14
A16 A16 A14 I/O14
BW1A16 39
CFM1A17 40 CFM1A17 40 A16 MICA15 1 38 MICD15
A17 A17 A15 I/O15
BW1A17 40
CFM1A18 41 CFM1A18 41 A17 22
A18 A18 NC
BW1A18 41 A18 23 NC MICD[0:15]
28 NC
CFM1A[0:18]
BW1A[0:18]

MICA[0:15]

U8 U1 U11
U3 U4
CY7C1049 CY7C1049 CY7C1049
CNPOE BWPOE CY7C1049 CY7C1049
D 37 OE 37 OE
CFMPOE CFMPOE
CFMPOE 37 OE
CNPWE BWPWE 37 OE 37 OE
15 WE 15 WE CFMPWE
CFMPWE CFMPWE 15 WE
15 WE 15 WE
8 CS 8 CS 8 CS
8 8
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

CS CS
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

BWPA0 3 9 CNPD0 BWPA0 3 9 BWPD0

A0 I/O0 A0 I/O0 CFMPA0 3 9 CFMPD16
CFMPA0 3 9 CFMPD0 CFMPA0 3 9 CFMPD8 A0 I/O0
BWPA1 4 10 CNPD1 BWPA1 4 10 BWPD1 A0 I/O0 A0 I/O0
A1 I/O1 A1 I/O1 CFMPA1 4 10 CFMPD17
CFMPA1 4 10 CFMPD1 CFMPA1 4 10 CFMPD9 A1 I/O1
BWPA2 5 13 CNPD2 BWPA2 5 13 BWPD2 A1 I/O1 A1 I/O1
A2 I/O2 A2 I/O2 CFMPA2 5 13 CFMPD18
CFMPA2 5 13 CFMPD2 CFMPA2 5 13 CFMPD10 A2 I/O2
BWPA3 6 14 CNPD3 BWPA3 6 14 BWPD3 A2 I/O2 A2 I/O2
A3 I/O3 A3 I/O3 CFMPA3 6 14 CFMPD19
CFMPA3 6 14 CFMPD3 CFMPA3 6 14 CFMPD11 A3 I/O3
BWPA4 7 31 CNPD4 BWPA4 7 31 BWPD4 A3 I/O3 A3 I/O3
A4 I/O4 A4 I/O4 CFMPA4 7 31 CFMPD20
CFMPA4 7 31 CFMPD4 CFMPA4 7 31 CFMPD12 A4 I/O4
BWPA5 16 32 CNPD5 BWPA5 16 32 BWPD5 A4 I/O4 A4 I/O4
A5 I/O5 A5 I/O5 CFMPA5 16 32 CFMPD21
CFMPA5 16 32 CFMPD5 CFMPA5 16 32 CFMPD13 A5 I/O5
BWPA6 17 35 CNPD6 BWPA6 17 35 BWPD6 A5 I/O5 A5 I/O5
A6 I/O6 A6 I/O6 CFMPA6 17 35 CFMPD22
CFMPA6 17 35 CFMPD6 CFMPA6 17 35 CFMPD14 A6 I/O6
BWPA7 18 36 CNPD7 BWPA7 18 36 BWPD7 A6 I/O6 A6 I/O6
A7 I/O7 A7 I/O7 CFMPA7 18 36 CFMPD23
CFMPA7 18 36 CFMPD7 CFMPA7 18 36 CFMPD15 A7 I/O7
BWPA8 19 BWPA8 19 A7 I/O7 A7 I/O7
A8 A8 CFMPA8 19
CFMPA8 19 CFMPA8 19 A8
BWPA9 20 BWPA9 20 A8 A8
A9 A9 CFMPD[0:7] CFMPD[8:15] CFMPA9 20 CFMPD[16:23]
CFMPA9 20 CFMPA9 20 A9
BWPA10 26 CNPD[0:7] BWPA10 26 BWPD[0:7] A9 A9
A10 A10 CFMPA10 26
CFMPA10 26 CFMPA10 26 A10
BWPA11 27 BWPA11 27 A10 A10
A11 A11 CFMPA11 27
CFMPA11 27 CFMPA11 27 A11
BWPA12 28 BWPA12 28 A11 A11
A12 A12 CFMPA12 28
CFMPA12 28 CFMPA12 28 A12
BWPA13 29 BWPA13 29 A12 A12
C A13 A13 CFMPA13 29
CFMPA13 29 CFMPA13 29 A13
BWPA14 30 BWPA14 30 A13 A13
A14 A14 CFMPA14 30
CFMPA14 30 CFMPA14 30 A14
BWPA15 38 BWPA15 38 A14 A14
A15 A15 CFMPA15 38
CFMPA15 38 CFMPA15 38 A15
BWPA16 39 BWPA16 39 A15 A15
A16 A16 CFMPA16 39
CFMPA16 39 CFMPA16 39 A16
BWPA17 40 BWPA17 40 A16 A16
A17 A17 CFMPA17 40
CFMPA17 40 CFMPA17 40 A17
BWPA18 41 BWPA18 41 A17 A17
A18 A18 CFMPA18 41
CFMPA18 41 CFMPA18 41 A18
A18 A18

BWPA[0:18] CFMPA[0:18]
+3V3 U36
74LCX245
19 G
1 T/R
ESCANOUT 2 18 ESCAN
A1 B1
U9 U2 SCAN_MODEOUT0 3 17 SCAN_MODE0
A2 B2
U10 SCAN_MODEOUT1 4 16 SCAN_MODE1
CY7C1049 CY7C1049 A3 B3
CFM2OE 37 CFM2OE 37 CY7C1049 SCAN_MODEOUT2 5 A4 B4 15 SCAN_MODE2
B OE OE
BW2OE 37 SCAN_MODEOUT3 6 14 SCAN_MODE3
CFM2WE 15 CFM2WE 15 OE A5 B5
WE WE
BW2WE 15 SCAN_MODEOUT4 7 13 SCAN_MODE4
8 8 WE A6 B6
CS CS
8 SCAN_MODEOUT5 8 12 SCAN_MODE5
CS A7 B7
SCAN_MODEOUT6 9 11 SCAN_MODE6
CFM2A0 3 9 CFM2D0 CFM2A0 3 9 CFM2D8 A8 B8
A0 I/O0 A0 I/O0
BW2A0 3 9 BW2D0
CFM2A1 4 10 CFM2D1 CFM2A1 4 10 CFM2D9 A0 I/O0
A1 I/O1 A1 I/O1 U49
BW2A1 4 10 BW2D1
CFM2A2 5 13 CFM2D2 CFM2A2 5 13 CFM2D10 A1 I/O1
A2 I/O2 A2 I/O2
CFM2A3 6 14 CFM2D3 CFM2A3 6 14 CFM2D11
BW2A2 5 A2 I/O2 13 BW2D2 74LCX245
A3 I/O3 A3 I/O3
BW2A3 6 14 BW2D3 19
CFM2A4 7 31 CFM2D4 CFM2A4 7 31 CFM2D12 A3 I/O3 G
A4 I/O4 A4 I/O4
BW2A4 7 31 BW2D4 1
CFM2A5 16 32 CFM2D5 CFM2A5 16 32 CFM2D13 A4 I/O4 T/R
A5 I/O5 A5 I/O5
BW2A5 16 32 BW2D5
CFM2A6 17 35 CFM2D6 CFM2A6 17 35 CFM2D14 A5 I/O5 2 18
A6 I/O6 A6 I/O6 A1 B1
BW2A6 17 35 BW2D6
CFM2A7 18 36 CFM2D7 CFM2A7 18 36 CFM2D15 A6 I/O6 3 17
A7 I/O7 A7 I/O7 A2 B2
BW2A7 18 36 BW2D7
CFM2A8 19 CFM2A8 19 A7 I/O7 4 16
A8 A8 A3 B3
CFM2D[0:7] BW2A8 19
CFM2A9 20 CFM2A9 20 CFM2D[8:15] A8 5 15
A9 A9 A4 B4
BW2A9 20
CFM2A10 26 CFM2A10 26 A9 BW2D[0:7] 6 14
A10 A10 A5 B5
BW2A10 26
CFM2A11 27 CFM2A11 27 A10 7 13
A11 A11 A6 B6
BW2A11 27
CFM2A12 28 CFM2A12 28 A11 DDOT 8 12 DDOTIN
A12 A12 A7 B7
BW2A12 28
CFM2A13 29 CFM2A13 29 A12 DLINE 9 11 DLINEIN
A13 A13 A8 B8
A CFM2A14 30 CFM2A14 30
BW2A13 29 A13
A14 A14 47
BW2A14
837 0147 042 Rev.A

CFM2A15 CFM2A15 30 A14 47

38 A15 38 A15
BW2A15 38 R259 R258 R175 R176
CFM2A16 39 A16
CFM2A16 39 A16
A15 R273
FORM:

BW2A16 39 1K00 1K00

CFM2A17 40 CFM2A17 40 A16 1K00
A17 A17 C179 C180
BW2A17 40
CFM2A18 41 CFM2A18 41 A17
A18 A18
BW2A18 41 33P 33P
A18

CFM2A[0:18]
BW2A[0:18]

SHEET DESCRIPTION:
"7350" CONTROL BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 7 11

 1 2 3 4 5 6 7 8 9 10 11

+6V
R99 +5V
10 C399 100N
C48
100N C60
+3V3C R98
R89 +5V
100N R97 +5V
R278 U58
1K00 TP20 R82 1 R280 100N
10
F
3K3 C57 100N 10
1K00
12
+Vs L2726 C395
- 1
8
U40 20
11
15K 2
V+ TLE2062 R72
+

U39 R66
-
1 VCC
3
TGC 39K TP17 CR4
AD7302 +
BAS21
V-
TGCD0 1 15
DB7(MSB) VDD
4 R71 U50 R279 R120
TGCD1 2 8
DB6
TGCD2 3 16
R100 R101 10K V+ LMC662 220 1
DB5 REFin R81 VMOT 2 -
TGCD3 3K3 1K00
4 DB4 2K00 TP21 1 K1
TGCD4 5 19
3
+ CR5
DB3 VoutA
V-
R290 R291 STPS1H100U
5V 2VIE
TGCD5 6 DB2
8
U40 R84 R83 4 TP16 1K00 220 +
TGCD6 7 18
DB1 VoutB TLE2062
TGCD7 8
R80 6
V+ 10K 39K
DB0(LSB) -
2K00 7 DGAIN MPH1
5
+
R105
9 CS AGND 17 V- Connector Y0
TGCWE 10
39K R277 1
U59 100N
WR C55 C56 4 -5V R275 MPH2
TGCAB 11 A/B C42 R90 1K00
12
+Vs L2726 C393
470P 470P - 1
E 12 20 Connector Z0
PD 1U 10 R104 8
U50 11
13 LDAC +

14 20 CR2 10K
6
V+ LMC662
CLR DGND C49 VMOT -
7
LM385BM1.2 100N 5
+
V-
R276 R119
R92 R91 4
220 1 R299 R298
10K 39K 1K00 1K00
+3V3
CR6
R289 R288
U51 STPS1H100U
R74 R77 -5V 1K00 220
+5V
Q1 TLV5620 VCC
R70 10
14 C45 10
BC817 VDD
220 100N -6V
POTREF 100N
MPADCK 7 CLK
C394 C408 C409
R63 R73 MPADDATA 6 DATA DACA 12 47N 47N
+5V
C40 MPADLOAD 8 100N
1K2
0
1K5 LOAD R87
11 C58 +6V
R69 47U DACB 10 100N
D VMOT 2 REFA C400
CR3 3 REFB DACC 10
TP19
TL431AC 4 REFC R76
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

2K2
The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

5 9 39K
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

REFD DACD
R285 U58
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

R68 C44 1 100N

R67 R286
MPADLDAC 13 LDAC R109 R108 R107 R106 R75 U52 1K00 +Vs L2726
10K 100N 8 9 - 1 C398
15K 15K 15K 15K 10K LMC662 2
LM385BM1.2 1 2
V+
10 R300 R301
CR1 GND VMOT -
1
+
1K00 1K00
3
+
V-
R85 R86 4 TP18
+5V 10K 39K R284 R122
R54 220 1
100N R111
10
C33 39K VCC
CR7 K2
R294 R295 STPS1H100U 5V 2VIE
1K00 220
R296 RV2 R297 R110 8
U52 +
C 4K7 1K 4K7 10K V+ LMC662
POTREF VMOT 6 -
7 R283 U59 100N MPH3
TP13 5
1 R281
R56 + 1K00 +Vs L2726 C396 Connector W0
V- 9 1
2K -
2
4 MPH4
L1 R55 8
U31 R93 R94 10
+
R52 Connector X0
TEMP1 33U 10K
2
V+ LMC662 10K 39K
- 1K00
1
3
+
C35 C29 V- C28 -5V R282 R121
R51 R78
100N 100N 1U TP15 100N
150K
4 C46 10
220 1

C27 CR8 R127

R293 R292 STPS1H100U
2K7 MOTORON
1K00 220
1U

R134 -6V Q2
C397 100N
R126
1K00 BC817
B POT0 4K7

R274 RV1 R287 R133

U41 +3V3C
1K00 R88
4K7 1K 4K7 POT1 TLV1543
POTREF 10
1 20 P5
R132 A0 VCC
R61 1K00
2 A1 1 2
2K POT2 3 19 POTEOC C47 PSENSE 3 4 TSENSE
A2 EOC
L2 R59 8
U31 R131 4 A3 I/O CLK 18 POTCK
100N 5 6
R62 5 17 POTADD POFFS VREF
TEMP2 33U 10K
6
V+ LMC662 1K00 A4 ADDRESS 7 8
- 1K00 POT3 6 16 POTDOUT 9 10
7 A5 DATA OUT
5 7 15 POTCS AUX 11 12 VA
+ R130 A6 CS
C34 C31 V- C32 8 A7 REF+ 14 POTREF 13 14
1K00
100N 100N 4 1U POT4 9 13 CTAUX0 15 16 CTAUX4
A8 REF-
11 C59 CTAUX1 17 18 CTAUX5
R129 A9 +3V3C
R60 C73 C71 C69 12 A10 GND 10 100N CTAUX2 19 20 CTAUX6
1K00 +5V
150K POT5 1U 1U 1U CTAUX3 21 22 CTAUX7
23 24 -5V
R128 C72 C70 C68
A C74 25 26
C30 POT[0:6] 1K00 1U 1U 1U
POT6 1U
837 0147 042 Rev.A

27 28
29 30 POTREF
1U
FORM:

R95 R79 C54 C43 31 32

820K 820K 100N 100N 33 34
35 36
37 38
39 40

SHEET DESCRIPTION:
"7350" CONTROL BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 8 11

 1 2 3 4 5 6 7 8 9 10 11

+3V3

R266 +3V3

F U34
4K7
74LCX245
G 19 LSFE
T/R 1 LCRW R270 R269
LC0 18 B1 A1 2 LD0 U48 4K7
4K7
LC1 17 B2 A2 3 LD1 74LCX244
LC2 LD2
R272 R271 R253
16 B3 A3 4 LSFE 1 1G R252
LC3 15 5 LD3 19 4K7 4K7
B4 A4 2G 4K7 4K7
LC4 14 6 LD4
B5 A5 LCA0 2 18 LA0
1A1 1Y1
LC5 13 7 LD5
B6 A6 LCA1 4 16 LA1
1A2 1Y2
LC6 12 8 LD6
B7 A7 LCA2 6 14 LA2
1A3 1Y3
LC7 11 9 LD7
B8 A8 LCA3 8 12 LA3
1A4 1Y4
LCA4 11 9 LA4
2A1 2Y1
U46 LCRW 13 7 LRW
LC[0:15]

2A2 2Y2

LD[0:15]
74LCX245 15 2A3 2Y3 5
G 19 17 2A4 2Y4 3
T/R 1
E
LC8 18 2 LD8
B1 A1
LC9 17 3 LD9
B2 A2
LC10 16 4 LD10
B3 A3
LC11 15 5 LD11
B4 A4
LC12 14 6 LD12
B5 A5
LC13 13 7 LD13
B6 A6
LC14 12 8 LD14
B7 A7
LC15 11 9 LD15
B8 A8

R139
33
+3V3
U65 C20
R116 R38
CY2305 33
82 100P
D CK40A
6 VDD CLKout 8
3 R236 C376
CLK1 R117
U56 D40M 1 REF CLK2 2 82 100P
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

33
The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

CK40B
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

74HC139 CLK3 5
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

LCA0 2 4 CONFOE0 4 7 R216 C305

1A 1Y0 GND CLK4 R115
LCA1 3 5 CONFOE1 82
1B 1Y1 33 100P
CK40C
6 CONFOE2
1Y2
1 7 CONFOE3
1G 1Y3 R118
LCA2 14 12 33
2A 2Y0
CK40D
LCRW 13 11
2B 2Y1
2Y2 10 R114
LSGR 15 9 CONFOECPU
2G 2Y3 33
CK40E

+3V3 R113
+3V3C U64 33
CK40F
CY2305
6 VDD CLKout 8 R136
C
CLK1 3
33 R178 R182 R214
1 2 D40A 82 82 82
REF CLK2
R257 R256 R255 R254 R267 R268 U47 CLK3 5 R137
4 7 C182 C196 C301
4K7 4K7 4K7 4K7 4K7 4K7 74LCX244 GND CLK4 33
D40B 100P 100P 100P
1 1G
19 2G R138
CONF0 2 18 LC0 33
1A1 1Y1 D40C
CONF[0:5]

CONF1 4 16 LC1
1A2 1Y2
CONF2 6 14 LC2
1A3 1Y3
CONF3 8 12 LC3
1A4 1Y4
CONF4 11 9 LC4
2A1 2Y1 +3V3
CONF5 13 7 LC5
2A2 2Y2 LC[0:5] U53
15 2A3 2Y3 5
17 3 74AC161
+3V3 2A4 2Y4
CK40B 2 CLK
1 CLR
9 LOAD
B
10 ENT RCO 15
+3V3 7 ENP
R244 R243 R242 R241 R246 R247 U35 R245
3 A QA 14 R262
100 100 100 100 100 100 74LCX244 470K U33
4 B QB 13
1 74LVT273 33
1G 5 12 D5M
C QC
CONFOE3 19 LSGW 11
2G CLK 6 11
D QD
CONF0 1 RES
2 1A1 1Y1 18
CONF[0:5]
4 16 CONF1 LC12 3 2 TCRESET
1A2 1Y2 1D 1Q
6 14 CONF2 LC13 4 5 FLASH
1A3 1Y3 2D 2Q
8 12 CONF3 LC14 7 6
1A4 1Y4 3D 3Q
11 9 CONF4 LC15 8 9
2A1 2Y1 4D 4Q
13 7 CONF5 13 12
2A2 2Y2 5D 5Q
15 2A3 2Y3 5 C378 14 6D 6Q 15

R240 R239 R238 R237 R248 R249 17 2A4 2Y4 3 470N 17 7D 7Q 16

18 8D 8Q 19
100 100 100 100 100 100

A
837 0147 042 Rev.A
FORM:

SHEET DESCRIPTION:
"7350" CONTROL BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 9 11

 1 2 3 4 5 6 7 8 9 10 11

+2V2
+1V8B +1V5
+2V2 U18
U5
TPS72501 TPS72501
2 IN OUT 4
2 IN OUT 4
-6V
C155 C186 C184 C183 C199 C131
C142 C204 C210 C188 C145 C197 U38 -5V 47N 470N
1 EN FB 5 47N 47N 47N 470N
F 1 EN FB 5 47K 47N 47N 47N 47N 470N 470N UCC384DP-ADJ R20
GND
R3 C5 2 VIN VOUT 5 GND 27K
C15
47U 3 VIN C19 C18 47U
C3 C1 3 6 VIN VOUTS 1 C37 1U
3 C130
1U C203 C151 R64 4U7 4U7 C153 C152 C187 C156 C206
4U7 100K C143 C146 C192 C150 7 VIN 22P 120K
470N
470N
470N 470N 120K C41 47N 47N 47N 47N
R1 47N 47N 47N 47N R19
8 SD/CT GND 4

C38 +1V5B
4U7
22N
R65 +2V2 U16
+2V2 39K
U57 +1V5A C53 TPS72501
TPS72501 2 IN OUT 4
2 IN OUT 4
1 EN FB 5 C299 C335 C297 C300 C349 C357
C328 C294 C295 C292 C351 C280 R22 C11 47N 47N 47N 47N 470N 470N
1 EN FB 5
R96 C50 47N 47N 47N 47N 470N 470N
GND 47U
27K
GND 47U +6V C9 C8
27K
E C62 C52 U54 1U 4U7
3
1U 3 +5V C265 C269
4U7 LP2951-3.1
C350 C281 R23 C296 C338 C334 C337 470N 470N
8 VIN OUTPUT 1
R102 C331 C291 C330 C327 470N 470N
120K 47N 47N 47N 47N
120K 47N 47N 47N 47N
3 SHUTDWN Vtap 6 C61
82K 47N
C63
5 7 4U7
ERROR FB R103
C77
VCC +3V3C
4U7 4 2
GND SENSE U55
+1V8A
+2V2 U24 27K LP2951-3.1
R112 8 1
TPS72501 VIN OUTPUT
2 IN OUT 4
3 SHUTDWN Vtap 6
R123 R124 C75
1 EN FB 5 C352 C372 C289 C353 C377 C285 47N C407 C382 C388 C401 C404 C383
C21 47N 47N 47N 47N 470N 470N
VCC U32 +3V3AUX 5 ERROR FB 7 150K 820K
C65 47N 47N 47N 47N 47N 47N
GND
R45 47U C78
47K LP3964-ADJ 4U7
4U7 4 2
D 2 3 GND SENSE
3 VIN VOUT
R125
C288 C374 1 SD ADJ 4 75K
C22 C23 R44 C314 C290 C315 C373
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

470N 470N 10K R50 C25

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

1U 100K 47N 47N 47N 47N GND C26 C389 C406 C387 C405 C386
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

4U7
R53 18K 82P
33U 47N 47N 47N 47N 47N
5

C36
+2V2
100U
U6 +1V26 R49
TPS72501 10K5
2 IN OUT 4
+3V3AUX
1 EN FB 5 C242 C202 C177 C234 C207 C233 C235 C240
+3V3
R4 47N 47N 47N 47N 47N 47N 470N 470N
GND
3K9
C4 C2 C6
3
C 1U 4U7 47U
C237 C236 C213 C157 C139 C218
R2 C195 C208 C198 C175 C172 470N 470N
120K 47N 47N 47N 470N
47N 47N 47N 47N 47N
C24 C101 C106 C93 C102 C89 C100 C118 C121 C111 C117 C115 C125
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
47U
C263 C272 C229 C126
+3V3
47N 47N 47N 470N

C214 C209 C138 C216 C227 C313 C168 C154 C167 C164 C165 C127 C232 C129 C215 C194 C275 C94 C95 C119 C116 C120 C246 C251 C256 C247 C255 C277 C344 C324
C141 C10 10U 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 10U 47N 47N
470N 47U
C189
C267 C363 C271 TP14
C190 C191 C162 C169 C163 C222 C221 C147 C148 C149 C133 C134 C226 C161 C166 C220 C273
47N 47N 470N
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 47N
47N 470N 470N
C108 C97 C107 C96 C88 C84 C87 C83 C86 C82 C85 C81
B 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N TP8
C219 C306 C135 C369 C321 C341 C310 C258 C307 C311 C319 C136 C283 C284 C39 C128 C354 C303 C370 C274
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 10U 10U 47N 47N 47N 470N
47N 470N 470N TP2

C185 C268 C318 C359 C329 C293 C356 C316 C304 C312 C320 C368 C137 C361 C317 C309 C160 C140 C254 C250 C253 C249 C252 C248 C110 C99 C109 C98
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
C260 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N TP6
47N 470N 470N 47N 47N 10U
470N
C298

C339 C340 C325 C326 C347 C348 C345 C346 C332 C278 TP3
C336 C362 C266 C279 C270 C323 C322 C259 C371
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
47N 470N 470N 470N 47N 47N 47N 470N
470N
C245 C244 C380 C384 C391 C381 C390 C379 C392 C403 C402 C385
TP22
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
C170 C264 C367 C276 C355 C360 C261 C262 C364 C173 C178 C375 C287 C343 C342 C358 C308 C366 C217
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 47N 47N 47N 470N
47N 47N 470N
C144 TP1
A
837 0147 042 Rev.A

C224 C205 C174 C257 C365 C225 C123 C124 C122 C112 C113 C114 C105 C103 C104 C90 C91 C92
C231 C230 C228 C201 C200 C241 C223 C211 C243 C212 C193 C176
FORM:

470N 470N 470N 47N 47N

10U
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N TP9
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N

SHEET DESCRIPTION:
"7350" CONTROL BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 10 11

 1 2 3 4 5 6 7 8 9 10 11

P3 P4
VCC P2
L5 P1 A1 B1
DDIG0 DDIG1 A1 B1
100U A1 B1 A2 B2
A1 B1 DDIG2 DDIG3 A2 B2
FEXPROG1 A2 B2 FEXPROG0 A3 B3
C66 A2 B2 DDIG4 DDIG5 A3 B3
F FEXDONE1 A3 B3 FEXDONE0 A4 B4
47U A3 B3 A4 B4
A4 B4 DDIG6 A5 B5 DDIG7
FEXINIT1 FEXINIT0
A4 B4 DDIG8 DDIG9 A5 B5
FEXCCLK1 A5 B5 FEXCCLK0 A6 B6
A5 B5 DDIG10 DDIG11 A6 B6
D40A A6 B6 D40B A7 B7
A6 B6 DDIG12 DDIG13 A7 B7
D40C A7 B7 D40M A8 B8
A7 B7 DDIG14 DDIG15 A8 B8
BDIG0 A8 B8 ADIG0 A9 B9
A8 B8 DDIG16 DDIG17 A9 B9
BDIG1 A9 B9 ADIG1 A10 B10
A9 B9 DDIG18 DDIG19 A10 B10
BDIG2 A10 B10 ADIG2 A11 B11
TXS A10 B10 SMP A11 B11
BDIG3 A11 B11 ADIG3 A12 B12
DPTCK A11 B11 TCLK A12 B12
BDIG4 A12 B12 ADIG4 A13 B13
A12 B12 A13 B13
BDIG5 A13 B13 ADIG5 MOT0 A14 B14 CONFOE0
CFMON A13 B13 CFMOFF A14 B14
BDIG6 A14 B14 ADIG6 MOT1 A15 B15 CONFOE1
MLN0 A14 B14 MLN1 A15 B15
BDIG7 A15 B15 ADIG7 POS A16 B16 CONFOE2
MLN2 A15 B15 MLN3 A16 B16
BDIG8 A16 B16 ADIG8 ESCAN A17 B17 CONF5
DL A16 B16 ACFM A17 B17
BDIG9 A17 B17 ADIG9 PROBE A18 B18 CONF4
A17 B17 A18 B18
BDIG10 A18 B18 ADIG10 A19 B19 CONF3
CFMD16 A18 B18 CFMD17 A19 B19
BDIG11 A19 B19 ADIG11 A20 B20 CONF2
CFMD14 A19 B19 CFMD15 A20 B20
BDIG12 A20 B20 ADIG12 A21 B21 CONF1
E CFMD12 A20 B20 CFMD13 A21 B21
BDIG13 A21 B21 ADIG13 A22 B22 CONF0
CFMD10 A21 B21 CFMD11 A22 B22
BDIG14 A22 B22 ADIG14 A23 B23
CFMD8 A22 B22 CFMD9 SADD0 SADD1 A23 B23
BDIG15 A23 B23 ADIG15 A24 B24
CFMD6 A23 B23 CFMD7 SADD2 SADD3 A24 B24
BDIGREF0 A24 B24 ADIGREF0 A25 B25
CFMD4 A24 B24 CFMD5 SADD4 SADD5 A25 B25
BDIGREF1 A25 B25 ADIGREF1 A26 B26
CFMD2 A25 B25 CFMD3 A26 B26
L3 -6V
SADD6 A27 B27 SADD7 A26 B26 HWC0
DREADY1 DREADY0
CFMD0 A26 B26 CFMD1 22U SADD8 SADD9 A27 B27 HWC1
A27 B27 A28 B28
DPD6 A27 B27 DPD7 SADD10 SADD11 A28 B28
A28 B28 +6V A29 B29
DPD4 A28 B28 DPD5 L4 SADD12 SADD13 A29 B29 D5M

+VT

+VT
A29 B29 A30 B30
DPD2 A29 B29 DPD3 SADD14 SADD15 A30 B30
A30 B30 22U A31 B31
DPD0 A30 B30 DPD1 SADD16 SADD17 A31 B31
A31 B31 A32 B32
DDOT A31 B31 DLINE SADD18 SADD19 A32 B32
A32 B32 A33 B33
A32 B32 C51 C67 A33 B33
MRESET_DONE A33 B33 A34 B34
A33 B33 47U 47U A34 B34
SCAUX0 SCAUX1 A34 B34 LQ0 A35 B35 PI
AVG_DATA0 A34 B34 AVG_DATA1 LQ1 LQ2 A35 B35 MPH1
R141 A35 B35 A36 B36
AVG_DATA2 A35 B35 AVG_DATA3 FES1 FES0 A36 B36 MPH2
A36 B36 A37 B37
A36 B36 33 A37 B37
AVG_DATA4 AVG_DATA5 A37 B37 FES2 A38 B38 MPH3
LSSCAN
D AVG_DATA6 A37 B37 AVG_DATA7 A38 B38 L6 +3V3 TXFRAME A39 B39 TXSTB A38 B38 MPH4
AVG_DATA8 A38 B38 AVG_DATA9 TXRES RXSTB A39 B39
C80 A39 B39 22U A40 B40
AVG_DATA10 A39 B39 AVG_DATA11 A40 B40 TSENSE
47P A40 B40 A41 B41
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

A40 B40 A41 B41

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

AVG_DATA12 AVG_DATA13 A41 B41 RLB15 A42 B42 RLB14 PSENSE

C410
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

AVG_DATA14 A41 B41 AVG_DATA15 RLB13 RLB12 A42 B42 VA

A42 B42 A43 B43
A42 B42 47U A43 B43
A43 B43 RLB11 A44 B44 RLB10 POFFS
XY_ADD0 A43 B43 XY_ADD1 RLB9 RLB8 A44 B44 VREF
A44 B44 A45 B45
XY_ADD2 A44 B44 XY_ADD3 RLB7 RLB6 A45 B45 AUX
R140 A45 B45 A46 B46
XY_ADD4 A45 B45 XY_ADD5 RLB5 RLB4 A46 B46 TEMP1
33 A46 B46 LSGR A47 B47
XY_ADD6 A46 B46 XY_ADD7 RLB3 RLB2 A47 B47 TEMP2
LSGW A47 B47 A48 B48
XY_ADD8 A47 B47 MCYCLE_START A48 B48 SELPED
LCA0 A48 B48 LCA1 A49 B49
SCAN_MODE0 A48 B48 SCAN_MODE1 A49 B49
C79 A49 B49
A49 B49
47P
A50 B50
RLB1 RLB0 A50 B50
A50 B50 A51 B51
A50 B50 FEPRG FERW A51 B51 SELA/B
LCA2 A51 B51 LCA3 A52 B52
SCAN_MODE2 A51 B51 SCAN_MODE3 R135 A52 B52 SELB/C
LCA4 A52 B52 LCRW A53 B53
SCAN_MODE4 A52 B52 SCAN_MODE5 A53 B53 PBA/B
C LC0 A53 B53 LC1 33 A54 B54
SCAN_MODE6 A53 B53 SCAN_MODE7 LSCNT A54 B54 PBB/C
LC2 A54 B54 LC3 A55 B55
SCAN_MODE8 A54 B54 SCAN_MODE9 A55 B55 PED
LC4 A55 B55 LC5 A56 B56
POT0 A55 B55 POT1 A56 B56 GSEL0
LC6 A56 B56 LC7 C76 A57 B57
POT2 A56 B56 POT3 A57 B57 GSEL1
LC8 A57 B57 LC9 47P A58 B58
POT4 A57 B57 POT5 A58 B58 HF0
LC10 A58 B58 LC11 A59 B59
A58 B58 +2V2 A59 B59
POT6 POTREF A59 B59 A60 B60 HF1
LC12 LC13
A59 B59 DGAIN A60 B60
L7 A60 B60 HF2
LC14 LC15
TGC A60 B60 15U

C64
47U

ALIMENTAZIONI IMPLICITE
-----------------------

NET: +1V5 NET: +3V3 NET: GND

B ALIMENTAZIONI MODIFICATE
--------- --------- --------
------------------------
U14.U17 U13.33 U11.11 U19.26 U28.K14 U15.M12 U14.Y20 U14.C3 U27.P12 U46.10 U47.10
U14.U6 U13.11 UP3.37 U13.34 U28.K13 U15.M11 U14.Y3 U14.B21 U27.P11 U42.10 U33.10
NET: +1V5B NET: +1V8A NET: +3V3AUX NET: +3V3
U14.T16 UP1.32 UP3.9 U13.12 U28.K12 U15.M10 U14.W19 U14.B2 U27.P10 U36.10 U23.34
---------- ---------- ------------ ---------
U14.T15 UP2.32 U7.91 UP1.16 U28.K11 U15.M9 U14.W4 U14.A22 U27.P9 U37.10 U23.12
U28.U17 U30.P14 U28.AB11 U19.27
U14.T8 U20.33 U7.65 UP2.16 U28.K10 U15.M7 U14.P14 U14.A1 U27.N14 U8.34 U22.34
U28.U6 U30.P3 U28.AA22 U53.16 COMPONENTI NON MONTATI:
U14.T7 U20.11 U7.41 U20.34 U28.K9 U15.L16 U14.P13 U30.T16 U27.N13 U8.12 U22.12
U28.T16 U30.N13 U28.AA1 ------------------------
U14.R16 U26.33 U7.15 U20.12 U28.J14 U15.L14 U14.P12 U30.T1 U27.N12 U35.10 U21.34
U28.T15 U30.N4 U28.M22 NET: -6V C171 EQUIP_LEVEL 2 R189 EQUIP_LEVEL 2
U14.R7 U26.11 U49.20 U26.34 U28.J13 U15.L13 U14.P11 U30.R15 U27.N11 U29.34 U21.12
U28.T8 U30.M12 U28.L1 -------- C182 EQUIP_LEVEL 2 R190 EQUIP_LEVEL 2
U14.H16 U25.33 U48.20 U26.12 U28.J12 U15.L12 U14.P10 U30.R2 U27.N10 U29.12 U17.174
U28.T7 U30.M5 U28.B22 U59.17 C196 EQUIP_LEVEL 2 R192 EQUIP_LEVEL 2
U14.H7 U25.11 U47.20 U25.34 U28.J11 U15.L11 U14.P9 U30.L11 U27.N9 U10.34 U17.157
U28.R16 U30.E12 U28.B1 U59.16 C20 EQUIP_LEVEL 2 R194 EQUIP_LEVEL 2
U14.G16 U34.20 U33.20 U25.12 U28.J10 U15.L10 U14.N14 U30.L6 U27.M14 U10.12 U17.153
U28.R7 U30.E5 U28.A12 U59.15 C282 EQUIP_LEVEL 2 R195 EQUIP_LEVEL 2
U14.G15 U46.20 U23.33 U28.AB22 U28.J9 U15.L9 U14.N13 U30.K10 U27.M13 U1.34 U17.144
U28.H16 U30.D13 U14.AB11 U59.14 C286 EQUIP_LEVEL 2 R197 EQUIP_LEVEL 2
U14.G8 U36.20 U23.11 U28.AB1 U28.D19 U15.L7 U14.N12 U30.K9 U27.M12 U1.12 U17.130
U28.H7 U30.D4 U14.AA22 U59.7 C301 EQUIP_LEVEL 2 R209 EQUIP_LEVEL 2
U14.G7 U8.33 U22.33 U28.AA21 U28.D4 U15.K14 U14.N11 U30.K8 U27.M11 U9.34 U17.117
U28.G16 U30.C14 U14.AA1 U59.6 C302 EQUIP_LEVEL 2 R211 EQUIP_LEVEL 2
U14.F17 U8.11 U22.11 U28.AA2 U28.C20 U15.K13 U14.N10 U30.K7 U27.M10 U9.12 U17.109
U28.G15 U30.C3 U14.M22 U59.5 C305 EQUIP_LEVEL 2 R213 EQUIP_LEVEL 2
U14.F6 U29.33 U21.33 U28.Y20 U28.C3 U15.K12 U14.N9 U30.J10 U27.M9 U4.34 U17.97
U28.G8 U14.L1 U59.4 C376 EQUIP_LEVEL 2 R214 EQUIP_LEVEL 2
U29.11 U21.11 U28.Y3 U28.B21 U15.K11 U14.M14 U30.J9 U27.L14 U4.12 U17.91
U28.G7 NET: +1V5A U14.B22 U58.17 C43 EQUIP_LEVEL 2 R215 EQUIP_LEVEL 2
NET: +1V26 U10.33 U17.168 U28.W19 U28.B2 U15.K10 U14.M13 U30.J8 U27.L13 U3.34 U17.83
U28.F17 ---------- U14.B1 U58.16 C54 EQUIP_LEVEL 2 R216 EQUIP_LEVEL 2
---------- U10.11 U17.141 U28.W4 U28.A22 U15.K9 U14.M12 U30.J7 U27.L12 U3.12 U17.73
U28.F6 U27.U17 U14.A12 U58.15 C7 EQUIP_LEVEL 2 R224 EQUIP_LEVEL 2
U17.171 U1.33 U17.124 U28.P14 U28.A1 U15.J14 U14.M11 U30.H10 U27.L11 U2.34 U17.65
U27.U6 U27.AB11 U58.14 J1 EQUIP_LEVEL 2 R236 EQUIP_LEVEL 2
U17.165 U1.11 U17.105 U28.P13 U15.AB22 U15.J13 U14.M10 U30.H9 U27.L10 U2.12 U17.56
NET: +1V8B U27.T16 U27.AA22 U58.7 J2 EQUIP_LEVEL 2 R24 EQUIP_LEVEL 2
U17.148 U9.33 U17.94 U28.P12 U15.AB1 U15.J12 U14.M9 U30.H8 U27.L9 U11.34 U17.47
---------- U27.T15 U27.AA1 U58.6 J3 EQUIP_LEVEL 2 R241 EQUIP_LEVEL 2
U17.121 U9.11 U17.80 U28.P11 U15.AA21 U15.J11 U14.L14 U30.H7 U27.K14 U11.12 U17.39
U15.V18 U27.T8 U27.M22 U58.5 R11 EQUIP_LEVEL 2 R242 EQUIP_LEVEL 2
U17.113 U4.33 U17.53 U28.P10 U15.AA2 U15.J10 U14.L13 U30.G10 U27.K13 UP3.48 U17.29
U15.V5 U27.T7 U27.L1 U58.4 R161 EQUIP_LEVEL 2 R243 EQUIP_LEVEL 2
U17.100 U4.11 U17.36 U28.P9 U15.Y20 U15.J9 U14.L12 U30.G9 U27.K12 UP3.42 U17.16
A U17.77 U3.33 U17.12 U28.N14 U15.Y3 U15.G12 U14.L11 U30.G8 U27.K11 UP3.21 U12.90
U15.U17 U27.R16 U27.B22 R162 EQUIP_LEVEL 2 R240 EQUIP_LEVEL 2
U15.U6 U27.R7 U27.B1 R163 EQUIP_LEVEL 2 R246 EQUIP_LEVEL 2
U17.50 U3.11 U12.91 U28.N13 U15.T12 U15.G11 U14.L10 U30.G7 U27.K10 U7.90 U12.76
837 0147 042 Rev.A

U15.T16 U27.H16 U27.A12 R164 EQUIP_LEVEL 2 R247 EQUIP_LEVEL 2

U17.33 U2.33 U12.65 U28.N12 U15.T11 U15.C20 U14.L9 U30.F11 U27.K9 U7.76 U12.71
U15.T15 U27.H7 R169 EQUIP_LEVEL 2 R250 EQUIP_LEVEL 2
U17.21 U2.11 U12.41 U28.N11 U15.P14 U15.C3 U14.K14 U30.F6 U27.J14 U7.71 U12.67
U15.T8 U27.G16 NET: +3V3C R170 EQUIP_LEVEL 2 R251 EQUIP_LEVEL 2
FORM:

U17.9 U11.33 U12.15 U28.N10 U15.P13 U15.B21 U14.K13 U30.B15 U27.J13 U7.67 U12.60
U15.T7 U27.G15 ---------- R171 EQUIP_LEVEL 2 R38 EQUIP_LEVEL 2
U28.N9 U15.P12 U15.B2 U14.K12 U30.B2 U27.J12 U7.60 U12.55
U15.R16 U27.G8 U45.20 R172 EQUIP_LEVEL 2 R67 EQUIP_LEVEL 2
U28.M14 U15.P11 U15.A22 U14.K11 U30.A16 U27.J11 U7.55 U12.40
U15.R7 U27.G7 U61.20 R174 EQUIP_LEVEL 2 R68 EQUIP_LEVEL 2
U28.M13 U15.P10 U15.A1 U14.K10 U30.A1 U27.J10 U7.40 U12.26
U15.H16 U27.F17 U44.20 R178 EQUIP_LEVEL 2 R79 EQUIP_LEVEL 2
U28.M12 U15.P9 U45.10 U14.K9 U27.AB22 U27.J9 U7.26 U12.21
U15.H7 U27.F6 U63.20 R182 EQUIP_LEVEL 2 R95 EQUIP_LEVEL 2
U28.M11 U15.N14 U61.10 U14.J14 U27.AB1 U27.D19 U7.21 U12.17
U15.G16 U43.20 R184 EQUIP_LEVEL 2 U19 EQUIP_LEVEL 2
U28.M10 U15.N13 U44.10 U14.J13 U27.AA21 U27.D4 U7.17 U12.10
U15.G15 U62.20 R186 EQUIP_LEVEL 2
U28.M9 U15.N12 U63.10 U14.J12 U27.AA2 U27.C20 U7.10 U12.5
U15.G8 U42.20 R188 EQUIP_LEVEL 2
U28.L14 U15.N11 U43.10 U14.J11 U27.Y20 U27.C3 U7.5
U15.G7 U37.20
U28.L13 U15.N10 U62.10 U14.J10 U27.Y3 U27.B21 U60.10
U15.F17 U35.20
SHEET U28.L12 U15.N9 U14.AB22 U14.J9 U27.W19 U27.B2 U56.8 DESCRIPTION:
U15.F6 U60.20 "7350" CONTROL BOARD
A2 U28.L11
U28.L10
U28.L9
U15.M16
U15.M14
U15.M13
U14.AB1
U14.AA21
U14.AA2
U14.D19
U14.D4
U14.C20
U27.W4
U27.P14
U27.P13
U27.A22
U27.A1
U34.10
U53.8
U49.10
U48.10
U15.E18
U15.E5
U56.16
Document Revision: SHEET: OF:

by EpD Number: 950 1216 000 SE C 11 11

 1 2 3 4 5 6 7 8 9 10 11

VCC P2
L2 P1 P3
22U A1 B1
A1 B1 A1 B1
A2 B2 D40B
A2 B2 DDIG0 A2 B2 DDIG1
C50 A3 B3
A3 B3 DDIG2 A3 B3 DDIG3
47U A4 B4
A4 B4 DDIG4 A4 B4 DDIG5
A5 B5
E A5 B5
A6 B6 DDIG6 A5 B5 DDIG7
A6 B6 DDIG8 A6 B6 DDIG9
A7 B7
A7 B7 DDIG10 A7 B7 DDIG11
A8 B8
A8 B8 DDIG12 A8 B8 DDIG13
A9 B9
A9 B9 DDIG14 A9 B9 DDIG15
A10 B10
TXS A10 B10 SMP DDIG16 A10 B10 DDIG17
A11 B11
DPTCLK A11 B11 TCLK DDIG18 A11 B11 DDIG19
A12 B12
A12 B12 A12 B12
A13 B13
CFMON A13 B13 CFMOFF A13 B13
A14 B14
MLN0 A14 B14 MLN1 ADVIN A14 B14
A15 B15
MLN2 A15 B15 MLN3 ADVOUT A15 B15
A16 B16
DL A16 B16 ACFM A16 B16
A17 B17
A17 B17 RECIN A17 B17
A18 B18
CFMD16 A18 B18 CFMD17 RECOUT A18 B18
A19 B19
CFMD14 A19 B19 CFMD15 A19 B19
A20 B20
CFMD12 A20 B20 CFMD13 LINEINADV A20 B20
A21 B21
CFMD10 A21 B21 CFMD11 LINEOUTADV A21 B21
A22 B22
CFMD8 A22 B22 CFMD9 A22 B22
D A23 B23
CFMD6 A23 B23 CFMD7 LINEINREC A23 B23
A24 B24
CFMD4 A24 B24 CFMD5 LINEOUTREC A24 B24
A25 B25
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

A25 B25 A25 B25

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

CFMD2 CFMD3 A26 B26

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

CFMD0 A26 B26 CFMD1 A26 B26

A27 B27
DPD6 A27 B27 DPD7 A27 B27
A28 B28
DPD4 A28 B28 DPD5 A28 B28

+VT

+VT
A29 B29
DPD2 A29 B29 DPD3 +6V A29 B29
A30 B30
DPD0 A30 B30 DPD1
-6V
A31 B31
L4 A30 B30
DDOT A31 B31 DLINE L5 A32 B32
100U A31 B31
A32 B32 100U A32 B32
+3V3 A33 B33
SCAUX0 A33 B33 SCAUX1 R152 A33 B33
A34 B34 C52
A34 B34 47K C53 A35 B35
A34 B34
47U
A35 B35 R182 47U
A36 B36
A35 B35
A36 B36 33 A36 B36
A37 B37
A37 B37 LSDOP +3V3 A37 B37
A38 B38
A38 B38 L3 A38 B38
C62 A39 B39
22U
A39 B39 A39 B39
47P A40 B40
C A40 B40 A40 B40
A41 B41
A41 B41 A41 B41
A42 B42 C51 R150
A42 B42 +3V3 A42 B42
R151 A43 B43 47U
A43 B43 47K A43 B43
A44 B44
A44 B44 47K A44 B44
R181 A45 B45
A45 B45 A45 B45
A46 B46 LSGR
A46 B46 33 A46 B46
LSGW A47 B47
SPKN1 A47 B47 SPKR1 A47 B47
LCA0 A48 B48 LCA1
SPKN2 A48 B48 SPKR2 C61 A49 B49
A48 B48
A49 B49 47P A49 B49

A50 B50
A50 B50 A50 B50
LCA2 A51 B51 LCA3
A51 B51 DSIN A51 B51
LCA4 A52 B52 LCRW
A52 B52 A52 B52
LC0 A53 B53 LC1
A53 B53 DCOS A53 B53
LC2 A54 B54 LC3
A54 B54
LC4 A55 B55 LC5
R159 A54 B54
B A55 B55
LC6 A56 B56 LC7
47K A55 B55
A56 B56 A56 B56
LC8 A57 B57 LC9
A57 B57 A57 B57
LC10 A58 B58 LC11 +2V2
A58 B58 A58 B58
LC12 A59 B59 LC13 L1
A59 B59 A59 B59
LC14 A60 B60 LC15 15U
A60 B60 A60 B60

C47
47U

A
837 0147 042 Rev.A
FORM:

CONNETTORI SCHEDA

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" DOPPLER BOARD
A2 GAMBACCIANI DONNINI ANDREUCCETTI 23/02/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: IND200500080 Number: 950 1217 000 SE C 1 16
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
 1 2 3 4 5 6 7 8 9 10 11

+3V3

+2V2 U24 +1V8A VCC U10 +3V3_DSP R282 U49

TPS72501 TPS72501 470K 74LVT273
C302
2 4 2 4 470N 11
F IN OUT IN OUT LSGW CLK
C23 C5 C2 1 RES
C16 C3 C1
1 EN FB 5 1 EN FB 5
3 2

R75

R34
180K
4U7 1U 4U7 1U LC9 1D 1Q DSP_RESET
R74

56K
47U 47U
GND GND LC10 4 2D 2Q 5 PRGMODE
120K 7 6
R128 LC11 3D 3Q CPUAUX0
3 3 LC15 8 4D 4Q 9 CPUAUX1
10
13 12

R47
5D 5Q FLASH_RESET
R48

22K
14 6D 6Q 15
120K 17 16
7D 7Q
18 8D 8Q 19
+2V2 U17 +1V8B

TPS72501
2 IN OUT 4
C10 C6
C11
1 EN FB 5

R69
4U7 1U
R70

56K
47U
GND
120K
E +3V3 +3V3AUX
3
W1

VCC
U26
LP3964-ADJ W2
+2V2 U18 2 3
+1V8C VIN VOUT
TPS72501 C19 C22

R108
2 IN OUT 4
1 SD ADJ 4 C20

18K
C7 100U 82P
C12 R106 GND 33U
C13 10K
1 EN FB 5
4U7 1U R71 R72 R107 C299 R118
56K
47U +3V3
GND 5 10K5 47N
120K 33
XIL1_40M
3
R117
U43
33
CY2305 XIL2_40M
D 6 VDD CLKout 8 R115
CLK1 3
33
D40B 1 REF CLK2 2 XIL3_40M
+2V2 U19
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

+1V5 5 R120
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

CLK3
TPS72501
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

4 GND CLK4 7
33
2 IN OUT 4 XIL0_40M
C14 C18
C15 R119
1 EN FB 5
R73

4U7 1U 33
R65
27K

47U
DSP_CLK
GND
120K

+2V2 U28 +1V26

C TPS72501
2 IN OUT 4
C21 C24
C25 R153
R109

1 EN FB 5
4U7 1U
R110
3K9

47U 33
GND XIL0_TXS
120K
R162
3
33
XIL1_TXS
U61
R147 R163
1K00
74LCX244
1 33
1G
+6V U45 +5V XIL2_TXS
19 2G
TPS72501 2 18 R184
TXS 1A1 1Y1
2 IN OUT 4
4 1A2 1Y2 16 33
C41 C40 XIL3_TXS
C30 6 1A3 1Y3 14 R183
R124

1 EN FB 5
4U7 1U 8 1A4 1Y4 12
R121
56K

4U7 33
B GND DPTCLK 11 2A1 2Y1 9 XIL2_DPTCLK
18K 13 7
2A2 2Y2
15 5
R161
3 2A3 2Y3
17 3 33
2A4 2Y4
XIL3_DPTCLK

R160
33
XIL1_DPTCLK
-6V U54 -5V
UCC384DP-ADJ R146
2 5 33
VIN VOUT
XIL0_DPTCLK
3
C45 VIN C310 C46
120K
R296

6 VIN VOUTS 1
4U7 22P 4U7
7 VIN R297
39K
8 SD/CT GND 4

C311
A 22N
837 0147 042 Rev.A
FORM:

REGOLATORI DI TENSIONE E TIMING DI BASE

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 2 16

 1 2 3 4 5 6 7 8 9 10 11

R60
0 +3V3_DSP
R81

C17
CLKOUT2/GP2

100P
2
82 2 2
R58 R59
33 4K7

R196
47N
C82
U14 U14

1K00
CLKOUT3
2 P4
F TMS320C6711C TMS320C6711C
R62 A3 E20 TB8 1 2
DSP_CLK CLKIN HD0 R32 ED0 K18 ED0
DSP_TMS DSP_TRST
4K7 D20 TB6 3 4
HD1 1K00 K19 DSP_TDI
ED1 ED1
Y12 CLKOUT2 HD2 D18 TB1 L18 Y6 5 6
ED2 ED2 EA2 EA2
R76 D10 CLKOUT3 HD3 C20 R31 DSP_TDO 7 8
ED3 L19 ED3 EA3 V7 EA3
HD4 C19 9 10
+3V3_DSP 1K00 1K00 ED4 M19 ED4 EA4 W7 EA4
FL1 +3V3_DSP C4 CLKMODE0 HD5 B18 TB12 +3V3_DSP M20 V8 DSP_TCK 11 12
ED5 ED5 EA5 EA5
300MA HD6 C17 TB20 R53 N18 W8 DSP_EMU0 13 14 DSP_EMU1
ED6 ED6 EA6 EA6
C5 PLLHV HD7 A18 TB24 1K00 N19 Y8
C9 ED7 ED7 EA7 EA7

R201

4K7
R197
C8 HD8 B17 +3V3_DSP
ED8 N20 ED8 EA8 V9 EA8

4K7
10U
100N
DSP_EMU0 D9 EMU0 HD9 C16 TB23 P18 Y9
ED9 ED9 EA9 EA9
DSP_EMU1 B9 EMU1 HD10 B16 TB25 R54 P20 V10
ED10 ED10 EA10 EA10
D3 EMU2 HD11 A16 TB28 R19 W13
TB37 B10 C15
1K00 ED11 ED11 EA11 EA11
TB32 EMU3 HD12 +3V3_DSP R20 V14
ED12 ED12 EA12 EA12
C11 EMU4 HD13 A15 TB30 T18 W14
R82 TB31 ED13 ED13 EA13 EA13 +3V3_DSP
B12 EMU5 HD14 C14 TB26 T20 Y14
0 TB29 ED14 ED14 EA14 EA14 R101
HD15 B14 TB27 T19 W15 0
DSP_CLK ED15 ED15 EA15 EA15 PRGMODE
E 2 DSP_RESET A13 RESET
ED16 V4 ED16 EA16 Y15 EA16
+3V3_DSP
R55 DSP_TRST B6 TRST HINT J20 TB15 W4 V16
R218
ED17 ED17 EA17 EA17 0
1K00 HCNTL0 G18 TB5 Y3 Y16
XIL0_PROG
ED18 ED18 EA18 EA18
C13 NMI HCNTL1 G19 TB7 V2 W17 R94
AWE TB21 C2 H20 TB14 ED19 ED19 EA19 EA19 0
DSP_INT0 EXT_INT4 HHWIL V1 Y18 XIL0_CCLK
R63

R100
ED20 ED20 EA20 EA20
TB69 C1 G20 TB13

R95

R98

R89

R99

R88
1K00

1K00

1K00

1K00
AOE DSP_INT1 EXT_INT5 HR/W U2 U18 R216

1K2

1K5
33 ED21 ED21 EA21 EA21
D2 0
XIL0_CCLK TB76 DSP_INT2 EXT_INT6 U1

2
ECLKOUT ED22 ED22 XIL0_DONE
2 DSP_INT3 E3 EXT_INT7 U3 K3
XIL0_DIN TB75 E18 TB2 ED23 ED23 CLKS0
R96
R64 HAS
ED24 T1 ED24 CLKR0 H3 0
DSP_INT0 TB38 4K7
Y11 ECLKIN HCS F20 TB10 T2 G3
XIL0_DIN
ED25 ED25 CLKX0
TB41 Y10 ECLKOUT HDS1 E19 TB3 R3 J1 R219
DSP_INT1 ED26 ED26 DR0 0
V11 ARE/SDCAS/SSADS HDS2 F18 TB4 R2 H2 XIL0_INIT
TB39 TB33 ED27 ED27 DX0
DSP_INT2
R66 AOE W10 AOE/SDRAS/SSOE HRDY H19 TB9 P1 J3
TB40 V12 AWE/SDWE/SSWE
ED28 ED28 FSR0 R215
DSP_INT3 AWE P2 H1 0
4K7 ED29 ED29 FSX0 XIL0_AUX
Y5
CE0 TB68 +3V3_DSP ARDY
ED30 P3 ED30 R83
CE0 V17 CE0 0
N3 E1
CE1 TB19 R77 B7 W18
ED31 ED31 CLKS1 DSP_CLKS1
DSP_TMS TMS CE1 CE1 M1
CLKR1 DSP_CLKR1
CE2 TB22 0 DSP_TDO A8 TDO CE2 W6 CE2
D READY/BUSY
DSP_TOUT0 G1 TOUT0 CLKX1 L3 DSP_CLKX1 R104
A7 V6 0
CE3 TB34 2
DSP_TDI TDI CE3 CE3
DSP_TINP0 G2 TINP0 DR1 M2 DSP_DR1
DSP_TCK A6 TCK BE0 V20 BE0 L2
BE0 TB18 U19
DX1 DSP_DX1
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

R33
The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

BE1 BE1 F1 M3
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

DSP_TOUT1 TOUT1 FSR1 DSP_FSR1

TB17 J18 Y4
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

BE1 HOLDA BE2 BE2 F2 L1

1K00 TB11 J17 V5
DSP_TINP1 TINP1 FSX1 DSP_FSX1
BE2 TB36 +3V3_DSP HOLD BE3 BE3
J19

R103

R105

R102
TB16 BUSREQ C12
TB35 RSV

R86

R87

R85

R97

R84

R90

R91
BE3

1K5

1K5

1K5

1K5

10K

10K

1K5

1K5

1K5

1K5
A5 RSV RSV D7
DSP_DX1 TB42 A12 D12
RSV RSV
B5 RSV RSV N1
B11 RSV RSV N2

+3V3_DSP
R93

R92

R56

R57
10K

10K

10K

10K
TP15
2

+3V3_DSP

+3V3_DSP

+3V3_DSP
C

+3V3 +3V3

UP4 UP5 UP1 U15 U25

29F040-120 29F040-120 AM29LV160 K6R4016V1D K6R4016V1D
R229

R243
1K00

1K00

AOE 24 OE AOE 24 OE EA2 25 A0 DQ0 29 ED0 AOE 41 OE AOE 41 OE

CE1 22 CE CE1 22 CE EA3 24 A1 DQ1 31 ED1 AWE 17 WE AWE 17 WE
31 WE 31 WE EA4 23 A2 DQ2 33 ED2 CE2 6 CS CE2 6 CS
EA5 22 A3 DQ3 35 ED3 BE1 40 UB BE3 40 UB
EA6 21 A4 DQ4 38 ED4 BE0 39 LB BE2 39 LB
EA2 12 A0 O0 13 ED0 EA2 12 A0 O0 13 ED8
EA7 20 A5 DQ5 40 ED5
EA3 11 A1 O1 14 ED1 EA3 11 A1 O1 14 ED9 EA2 1 A0 I/O0 7 ED0 EA2 1 A0 I/O0 7 ED16
EA8 19 A6 DQ6 42 ED6
EA4 10 A2 O2 15 ED2 EA4 10 A2 O2 15 ED10 EA3 2 A1 I/O1 8 ED1 EA3 2 A1 I/O1 8 ED17
EA9 18 A7 DQ7 44 ED7
EA5 9 A3 O3 17 ED3 EA5 9 A3 O3 17 ED11 EA4 3 A2 I/O2 9 ED2 EA4 3 A2 I/O2 9 ED18
EA10 8 A8 DQ8 30 ED8
EA6 8 A4 O4 18 ED4 EA6 8 A4 O4 18 ED12 EA5 4 A3 I/O3 10 ED3 EA5 4 A3 I/O3 10 ED19
EA11 7 A9 DQ9 32 ED9
EA7 7 A5 O5 19 ED5 EA7 7 A5 O5 19 ED13 EA6 5 A4 I/O4 13 ED4 EA6 5 A4 I/O4 13 ED20
EA12 6 A10 DQ10 34 ED10
EA8 6 A6 O6 20 ED6 EA8 6 A6 O6 20 ED14 EA7 18 A5 I/O5 14 ED5 EA7 18 A5 I/O5 14 ED21
B EA13 5 A11 DQ11 36 ED11
EA9 5 A7 O7 21 ED7 EA9 5 A7 O7 21 ED15 EA8 19 A6 I/O6 15 ED6 EA8 19 A6 I/O6 15 ED22
EA14 4 A12 DQ12 39 ED12
EA10 27 A8 EA10 27 A8 EA9 20 A7 I/O7 16 ED7 EA9 20 A7 I/O7 16 ED23
EA15 3 A13 DQ13 41 ED13
EA11 26 A9 EA11 26 A9 EA10 21 A8 I/O8 29 ED8 EA10 21 A8 I/O8 29 ED24
EA16 2 A14 DQ14 43 ED14
EA12 23 A10 EA12 23 A10 EA11 22 A9 I/O9 30 ED9 EA11 22 A9 I/O9 30 ED25
EA17 1 A15 DQ15(A-1) 45 ED15
EA13 25 A11 EA13 25 A11 EA12 23 A10 I/O10 31 ED10 EA12 23 A10 I/O10 31 ED26
EA18 48 A16
EA14 4 A12 EA14 4 A12 EA13 24 A11 I/O11 32 ED11 EA13 24 A11 I/O11 32 ED27
EA19 17 A17 RY/BY 15 READY/BUSY
EA15 28 A13 EA15 28 A13 EA14 25 A12 I/O12 35 ED12 EA14 25 A12 I/O12 35 ED28
EA20 16 A18
EA16 29 A14 EA16 29 A14 EA15 26 A13 I/O13 36 ED13 EA15 26 A13 I/O13 36 ED29
22K
R78
EA21 9 A19
EA17 3 A15 EA17 3 A15 EA16 27 A14 I/O14 37 ED14 EA16 27 A14 I/O14 37 ED30
EA18 2 A16 EA18 2 A16 EA17 42 A15 I/O15 38 ED15 EA17 42 A15 I/O15 38 ED31
CE0 26 CE
EA19 30 A17 EA19 30 A17 EA18 43 A16 EA18 43 A16
AOE 28 OE
EA20 1 A18 EA20 1 A18 EA19 44 A17 EA19 44 A17
AWE 11 WE
+3V3
FLASH_RESET 12 RESET
47 BYTE
R267
1K00

A
837 0147 042 Rev.A
FORM:

+3V3

DSP

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 3 16

 1 2 3 4 5 6 7 8 9 10 11

R240 R239
4K7
4K7

+3V3
XIL_INIT

+3V3
XIL_PROG
R242 R238
1K00 XIL_DONE 4K7

+3V3
2
C292
F 100P
U34 U34 U34 U34
2
XC2S300 XC2S300 XC2S300 XC2S300
R261
BANK 0 BANK 1 82 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
2

SCAUX1 A3 I/O GCK2,I A11 XIL0_40M C21 I/O(DOUT,BUSY) I/O(TRDY) L22 XIL1_CS DOPAUXCTL1 U12 I/O I/O U9 EA2 ED0 M1 I/O(TRDY) I/O C1 XIL1_AUX0
A4 A12
TB74 C22 M17 U13 U10 M2 C2
SCAUX0 I/O I/O(DLL) DDIG0 XIL0_DIN I/O(DIN,D0) I/O XIL2_CS DOPAUXCTL0 I/O I/O EA3 ED1 I/O I/O XIL1_AUX1
DPD4 A5 I/O I/O A13 DDIG1 XIL0_AUX D20 I/O I/O M18 XIL3_CS DOPAUX0 U14 I/O I/O U11 EA4 ED2 M3 I/O I/O D1 XIL1_AUX2
DPD5 A6 I/O I/O A14 DDIG2 CPUAUX0 D21 I/O(VREFBank2) I/O M19 XIL_WRITE DOPAUX1 V12 I/O I/O V6 EA5 ED3 M4 I/O I/O D2 XIL1_AUX3
DPD2 A7 I/O I/O A15 DDIG3 CPUAUX1 D22 I/O I/O M20 XIL_BUSY DOPAUX2 V13 I/O(VREFBank4) I/O V7 EA6 ED4 M5 I/O I/O D3 XIL2_AUX0
DPD3 A8 I/O I/O A16 DDIG4 E19 I/O I/O M21 XIL_CCLK DOPAUX3 V14 I/O I/O(VREFBank5) V8 EA7 ED5 M6 I/O I/O E1 XIL2_AUX1
DPD0 A9 I/O I/O A17 DDIG5 E20 I/O I/O M22 DOPAUX4 V15 I/O(VREFBank4) I/O V9 EA8 ED6 N1 I/O I/O(VREFBank7) E2 XIL2_AUX2
DPD1 A10 I/O I/O A18 DDIG6 SMP E21 I/O I/O(D4) N17 DOPAUX5 V16 I/O I/O(VREFBank5) V10 EA9 ED7 N2 I/O I/O E3 XIL2_AUX3
DPD6 B3 I/O I/O A19 DDIG7 TCLK E22 I/O I/O(VREFBank3) N18 DOPAUX6 V17 I/O I/O V11 EA10 ED8 N3 I/O(VREFBank6) I/O F1 XIL3_AUX0
DPD7 B4 I/O I/O(WRITE) A20 DDIG8 SMPIN F18 I/O I/O N19 XIL_DATA0 DOPAUX7 W12 I/O I/O W5 EA11 ED9 N4 I/O I/O(VREFBank7) F2 XIL3_AUX1
B5 B12 F19 N20 +3V3 W13 W6 N5 F3
TB106 I/O I/O DDIG9 FFTCK I/O I/O XIL_DATA1 DOPAUX8 I/O I/O EA12 ED10 I/O I/O XIL3_AUX2
B6 I/O(VREFBank0) I/O(VREFBank1) B13 DDIG10 DL F20 I/O I/O N21 XIL_DATA2 DOPAUX9 W14 I/O I/O W7 EA13 ED11 N6 I/O I/O F4 XIL3_AUX3
E TB105 B7 I/O I/O B14 DDIG11 SININ F21 I/O(VREFBank2) I/O N22 XIL_DATA3 DOPAUX10 W15 I/O I/O W8 EA14 ED12 P1 I/O I/O F5 VOL_CLK
TB104 B8 B15 F22 P17 W16 W9 P2 G1
TB103 I/O I/O DDIG12 COSIN I/O I/O XIL_DATA4 DOPAUX11 I/O I/O EA15 ED13 I/O I/O VOL_DIN
B9 I/O I/O B16 DDIG13 CFMD16 G18 I/O I/O P18 XIL_DATA5 DOPAUX12 W17 I/O I/O W10 EA16 ED14 P3 I/O I/O G2 VOL_LDSH
B10 I/O I/O B17 DDIG14 CFMD17 G19 I/O I/O P19 XIL_DATA6 DOPAUX13 W18 I/O(VREFBank4) I/O W11 EA17 ED15 P4 I/O I/O G3 SPKOFF
B11 I/O(DLL) I/O(VREFBank1) B18 DDIG15 XIL0_TXS G20 I/O I/O P20 XIL_DATA7 DOPAUX15 Y12 I/O(DLL) I/O Y5 EA18 ED16 P5 I/O I/O G4 ACLKX0
C4 I/O I/O B19 DDIG16 XIL0_DPTCLK G21 I/O I/O P21 DOPAUXCTL3 DOPAUX14 Y13 I/O I/O Y6 EA19 ED17 P6 I/O I/O G5 ADLL
+3V3 C5 B20 G22 P22 Y14 Y7 R1 H1
I/O(VREFBank0) I/O(CS) DDIG17 I/O I/O(D5) DOPAUXCTL2 DSP_INT0 I/O I/O EA20 ED18 I/O I/O ADLR
C6 I/O I/O C12 DDIG18 H18 I/O(VREFBank2) I/O(VREFBank3) R18 DOPAUX21 DSP_INT1 Y15 I/O I/O Y8 EA21 ED19 R2 I/O I/O H2 ADX0
C7 C13 H19 R19 Y16 Y9 R3 H3

4K7
I/O I/O DDIG19 I/O(D1) I/O(D6) DOPAUX20 DSP_INT2 I/O I/O AOE ED20 I/O(VREFBank6) I/O(VREFBank7) VTRAUDIO
C8 C14 H20 R20 Y17 Y10 R4 H4
R114

I/O I/O PRGMODE I/O(D2) I/O DOPAUX19 DSP_INT3 I/O(VREFBank4) I/O AWE ED21 I/O I/O PCAUDIO
2

R225
C9 C15 R253 H21 R21 Y18 Y11 R5 H5
4K7

I/O I/O LA0 CFMON I/O I/O DOPAUX18 DSP_TINP0 I/O I/O CE0 ED22 I/O I/O
C10 I/O I/O C16 LA2 0 CFMOFF H22 I/O I/O R22 DOPAUX16 DSP_TOUT0 Y19 I/O I/O AA3 CE1 ED23 T1 I/O I/O J1
C11 GCK3,I I/O C17 LD0 ACFM J17 I/O I/O T18 DOPAUX25 AA12 GCK0/I I/O AA5 CE2 ED24 T2 I/O I/O J2
LD10 D5 I/O I/O C18 LD3 LD8 J18 I/O I/O T19 DOPAUX24 DSP_TINP1 AA13 I/O I/O AA6 CE3 ED25 T3 I/O I/O J3
DDOT D6 I/O I/O D12 LD15 LD13 J19 I/O I/O T20 DOPAUX23 DSP_TOUT1 AA14 I/O I/O AA7 BE0 ED26 T4 I/O I/O J4
DLINE D7 I/O I/O D13 LNA2 LD9 J20 I/O I/O(VREFBank3) T21 DOPAUX22 READY/BUSY AA15 I/O I/O AA8 BE1 ED27 T5 I/O I/O J5
LD7 D8 I/O(VREFBank0) I/O D14 LNA8 MLN0 J21 I/O I/O T22 DOPAUX26 CLKOUT2/GP2 AA16 I/O I/O AA9 BE2 ED28 U1 I/O(VREFBank6) I/O J6
D LD12 D9 I/O I/O(VREFBank1) D15 LA1 MLN1 J22 I/O I/O U18 DOPAUX31 CLKOUT3 AA17 I/O I/O AA10 BE3 ED29 U2 I/O I/O K1
D10 I/O(VREFBank0) I/O D16 LA3 MLN2 K17 I/O I/O U19 DOPAUX30 AA18 I/O I/O AA11 ED30 U3 I/O I/O K2
D11 I/O I/O D17 LD1 LNA4 K18 I/O(VREFBank2) I/O U20 DOPAUX29 AA19 I/O I/O AB3 ED31 U4 I/O I/O(VREFBank7) K3
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

E7 I/O I/O D18 LD4 LNA0 K19 I/O(D3) I/O U21 DOPAUX28 AA20 I/O I/O AB4 DSP_CLKS1 V1 I/O I/O K4
TB77
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

E8 I/O I/O E12 LD5 LD14 K20 I/O I/O U22 DOPAUX27 AB13 I/O I/O(VREFBank5) AB5 DSP_CLKR1 V2 I/O(VREFBank6) I/O K5
TB78 E9 E13 K21 V19 AB14 AB6 V3 K6
TB80 I/O I/O LD6 LNA5 I/O I/O DOPAUX17 I/O I/O DSP_CLKX1 I/O I/O
E10 I/O I/O E14 LD2 MLN3 K22 I/O I/O V20 AB15 I/O I/O(VREFBank5) AB7 DSP_DR1 V4 I/O I/O L1
TB107 E11 E15 L17 V21 AB16 AB8 W1 L2
TB108 I/O I/O LSDOP LNA10 I/O I/O I/O I/O DSP_DX1 I/O I/O
F9 I/O I/O(VREFBank1) E16 LNA3 LNA7 L18 I/O I/O(VREFBank3) V22 AB17 I/O I/O AB9 DSP_FSR1 W2 I/O I/O L3
TB79 F10 E17 L19 W21 AB18 AB10 W3 L4
TB110 I/O I/O LNA9 LNA6 I/O I/O(INIT) XIL0_INIT I/O I/O DSP_FSX1 I/O I/O
F11 I/O I/O F12 LA4 LNA1 L20 I/O I/O W22 AB19 I/O I/O(DLL) AB11 ECLKOUT Y1 I/O I/O L5
TB109 F13 L21 Y22 AB20 AB12 Y2 L6
I/O LRW LNA11 I/O(IRDY) I/O(D7) I/O GCK1,I I/O I/O(IRDY)
I/O F14 LD11 AB21 I/O

R226
4K7
F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T9 N7 VCCOBank6 VCCOBank7 G6
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T10 P7 VCCOBank6 VCCOBank7 H6
G9 VCCOBank0 VCCOBank1 G13 J16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 J7
C G10 VCCOBank0 VCCOBank1 G14 K16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7
+3V3

U34
+3V3 +3V3 +3V3 +3V3
+3V3 XC2S300

TB102
XIL0_CCLK B22 CCLK TCK E6 XIL_TCK
XIL0_PROG Y21 PROGRAM
W20

R228
XIL0_DONE DONE

1K00
AA1 M0 TDI C19 XIL_TDI
2 U5 A21
M1 TDO XIL0_TDO
AB2 M2 TMS E4 XIL_TMS

TB73

R227

R236

R237
XIL1_CS

1K00

1K00

1K00
XIL2_CS TB61

XIL3_CS TB81
B +3V3
XIL_WRITE TB62 TP6 +3V3

XIL_BUSY TB55
TB56

R113

R112

R111
XIL_CCLK

4K7

4K7

4K7
XIL_DATA0 TB54

XIL_DATA1 TB58 +3V3

J1
1
XIL_DATA2 TB57 XIL_TCK 1 2
C4

+3V3
XIL_TDO 3 4
XIL_DATA3 TB43 47U 5 6
XIL_TMS
TB44 7 8
XIL_DATA4
XIL_TDI 9 10
XIL_DATA5 TB53

XIL_DATA6 TB52

A XIL_DATA7 TB49
837 0147 042 Rev.A
FORM:

FPGA DI CONTROLLO

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 4 16

 1 2 3 4 5 6 7 8 9 10 11

F U33 U33 U33 U33

XIL_INIT
XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4

R235
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

0
CFI0 B4 IO IO/GCLK3P F12 TB70 1J_0 C21 IO IO M21 4J_0 XIL_BUSY AB19 IO/DOUT IO/GCLK7S AA11 DDIG18 V5 IO IO L2 LD5
CFI1 A4 IO IO/GCLK2S F13 TB67 1J_1 C22 IO IO M20 4J_1 AA19 IO/INIT_B IO/GCLK6P Y11 XIL1_TXS DDIG19 U5 IO IO L3 LA0
CFI2 C4 IO IO/GCLK1P E12 TB71 1J_2 E18 IO/VRP2 IO M19 4J_2 XIL_DATA0 V18 IO/D0 IO/GCLK5S W11 DDIG8 Y2 IO/VRN6 IO L4 LA2
CFI3 C5 IO IO/GCLK0S D12 TB72 1J_3 F18 IO/VRN2 IO M18 4J_3 XIL_DATA1 V17 IO/D1 IO/GCLK4P V11 DDIG9 Y1 IO/VRP6 IO L5 LD10
CFI4 B5 IO/VRP0 IO C12 MTI_COR0 1J_4 D21 IO IO/VREF3 M17 4J_4 XIL_DATA2 W18 IO/D2/ALT_VRP4 IO U11 DOPAUX8 DDIG0 V4 IO IO/VREF7 K1 LD2
CFI5 A5 IO/VRN0 IO/VREF1 B12 MTI_COR1 1J_5 D22 IO/VREF2 IO N17 4J_5 XIL_DATA3 Y18 IO/D3/ALT_VRN4 IO/VREF5 U10 DOPAUX17 DDIG1 V3 IO/VREF6 IO K2 LNA8
CFI6 D6 IO/VREF0 IO A13 FIRST/SECOND 1J_6 E19 IO IO N22 4J_6 MTICS AA18 IO/VREF4 IO AB10 DOPAUX22 DDIG10 W2 IO IO K3 LA3
CFI7 C6 IO IO B13 TEST_CLK 1J_7 E20 IO IO N21 4J_7 MTIOE AB18 IO IO AA10 DOPAUX3 DDIG11 W1 IO IO K4 LD6
CFI8 B6 IO IO C13 TESTSIN8 1J_8 E21 IO IO N20 4J_8 MTIWE W17 IO/VRP4 IO Y10 DOPAUX11 DDIG2 U4 IO IO L6 LA4
CFI9 A6 IO IO D13 TESTSIN9 1J_9 E22 IO IO N19 4J_9 ADCK Y17 IO/VRN4 IO W10 DOPAUX10 DDIG3 U3 IO IO K6 LNA5
CFI10 E7 IO IO E13 TESTSIN10 1J_10 F19 IO IO N18 4J_10 ADOFF AA17 IO IO V10 DOPAUX26 DDIG12 V2 IO IO K5 LD1
CFI11 E8 IO IO/VREF1 E14 TESTSIN11 1J_11 F20 IO IO P18 4J_11 DOPAUX31 AB17 IO IO/VREF5 V9 DOPAUX28 DDIG13 V1 IO IO J5 LD4
E CFI12 D7 IO IO A14 TESTSIN12 1J_12 F21 IO IO/VREF3 P22 4J_12 DOPAUXCTL1 V16 IO IO AB9 DOPAUX18 DDIG14 U2 IO IO/VREF7 J1 LD7
CFI13 C7 IO/VREF0 IO B14 TESTSIN13 1J_13 F22 IO/VREF2 IO P21 4J_13 DOPAUXCTL0 V15 IO IO AA9 DOPAUX16 DDIG15 U1 IO/VREF6 IO J2 LA1
CFI14 B7 IO IO C14 TESTSIN14 1J_14 G18 IO IO P20 4J_14 W16 IO IO Y9 DOPAUX13 DDIG4 T5 IO IO J3 LD3
CFI15 A7 IO IO D14 TESTSIN15 1J_15 H18 IO IO P19 4J_15 DOPAUX1 Y16 IO/VREF4 IO W9 DOPAUX12 DDIG7 R5 IO IO J4 LD11
CFQ0 D8 IO IO/VREF1 A15 TESTCOS8 2J_0 G19 IO IO R22 3J_0 DOPAUX29 AA16 IO IO/VREF5 AB8 DOPAUXCTL3 DDIG6 T4 IO IO H1 LD15
CFQ1 C8 IO IO B15 TESTCOS9 2J_1 G20 IO IO R21 3J_1 DOPAUX25 AB16 IO IO AA8 DOPAUXCTL2 DDIG5 T3 IO IO H2 LD12
CFQ2 B8 IO IO C15 TESTCOS10 2J_2 G21 IO IO R20 3J_2 DOPAUX2 W15 IO IO Y8 DOPAUX24 DDIG16 T2 IO IO H3 LD8
CFQ3 A8 IO IO D15 TESTCOS11 2J_3 G22 IO IO R19 3J_3 DOPAUX15 Y15 IO IO W8 DOPAUX30 DDIG17 T1 IO IO H4 LD9
CFQ4 E9 IO IO F14 TESTCOS12 2J_4 H19 IO IO/VREF3 R18 3J_4 DOPAUX9 AA15 IO IO U9 DOPAUX27 CPUAUX0 R4 IO IO/VREF7 J6 MLN0
CFQ5 F9 IO/VREF0 IO E15 TESTCOS13 2J_5 H20 IO/VREF2 IO P17 3J_5 DOPAUX23 AB15 IO IO V8 DOPAUX20 CPUAUX1 R3 IO/VREF6 IO H5 LSDOP
CFQ6 D9 IO IO A16 TESTCOS14 2J_6 H21 IO IO T22 3J_6 DOPAUX4 U14 IO IO AB7 LNA11 R2 IO IO G1 LRW
CFQ7 C9 IO IO B16 TESTCOS15 2J_7 H22 IO IO T21 3J_7 DOPAUX0 V14 IO/VREF4 IO AA7 SCAUX1 R1 IO IO G2 LD0
CFQ8 B9 IO IO/VREF1 C16 XIL1_XIL2_AUX0 2J_8 J17 IO IO T20 3J_8 DOPAUX7 W14 IO IO/VREF5 Y7 P6 IO IO G3 LD13
CFQ9 A9 IO IO D16 XIL1_XIL2_AUX1 2J_9 J18 IO IO T19 3J_9 DOPAUX14 Y14 IO IO W7 P5 IO IO G4 LNA3
CFQ10 E10 IO/VREF0 IO E16 XIL1_XIL3_AUX0 2J_10 J19 IO IO U22 3J_10 DOPAUX19 AA14 IO IO AB6 P4 IO IO F1 LNA2
CFQ11 F10 IO IO E17 XIL1_XIL3_AUX1 2J_11 J20 IO IO U21 3J_11 DOPAUX21 AB14 IO IO AA6 P3 IO IO F2 LNA4
CFQ12 D10 IO IO A17 XIL1_AUX0 2J_12 J21 IO IO/VREF3 U20 3J_12 DOPAUX5 U13 IO/VREF4 IO Y6 P2 IO IO/VREF7 F3 LNA0
D CFQ13 C10 IO IO B17 XIL1_AUX1 2J_13 J22 IO/VREF2 IO U19 3J_13 V13 IO IO W6 P1 IO/VREF6 IO F4 LNA9
CFQ14 B10 IO IO C17 XIL1_AUX2 2J_14 K17 IO IO T18 3J_14 W13 IO IO/VRP5 V7 N6 IO IO G5 LD14
CFQ15 A10 IO IO/VREF1 D17 XIL1_AUX3 2J_15 K18 IO IO U18 3J_15 Y13 IO IO/VRN5 V6 N5 IO IO F5 LNA1
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

E11 A18 K19 V22 AA13 AB5 N4 E1

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

IO/VREF0 IO/VRP1 AA0 IO IO AA15 IO IO IO IO SCAUX0

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

F11 IO IO/VRN1 B18 AA1 K20 IO IO V21 AA14 AB13 IO IO/VREF5 AA5 N3 IO IO E2 LNA10
D11 IO/GCLK7P IO C18 TB66 AA2 K21 IO IO V20 AA13 U12 IO/VREF4 IO/D4/ALT_VRP5 Y5 XIL_DATA4 N2 IO IO E3 LNA6
TB101
C11 IO/GCLK6S IO D18 TB63 AA3 K22 IO IO V19 AA12 DOPAUX6 V12 IO IO/D5/ALT_VRN5 W5 XIL_DATA5 N1 IO IO E4 LNA7
TB100
XIL1_40M B11 IO/GCLK5P IO A19 TB65 AA4 L17 IO IO/VREF3 W22 AA11 W12 IO/GCLK3S IO/D6 AB4 XIL_DATA6 M6 IO IO/VREF7 D1 MLN1
TB94
A11 IO/GCLK4S IO B19 TB64 AA5 L18 IO/VREF2 IO W21 AA10 Y12 IO/GCLK2P IO/D7 AA4 XIL_DATA7 M5 IO/VREF6 IO D2 MLN2
2
L19 Y22 AA12 Y4
TB95 M4 C1
AA6 IO IO/VRP3 AA9 IO/GLCK1S IO/RDWR_B XIL_WRITE TB96 IO IO/VRN7 MLN3
R241 L20 Y21 AB12 AA3 M3 C2
82 AA7 IO IO/VRN3 AA8 XIL1_DPTCLK IO/GCLK0P IO/CS_B XIL1_CS TB97 IO IO/VRP7 ACFM
L21 IO IO W20 M2 IO IO E5 CFMON
L22 AA20
TB99 M1 E6
IO IO TB98 IO IO CFMOFF
2

C231
G11 VCCOBank0 VCCOBank1 G14 L16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 L7
100P
G10 VCCOBank0 VCCOBank1 G13 K16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 K7
G9 VCCOBank0 VCCOBank1 G12 J16 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T11 P7 VCCOBank6 VCCOBank7 J7
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T10 N7 VCCOBank6 VCCOBank7 H6
C
F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 M16 T12 VCCOBank4 VCCOBank5 T9 M7 VCCOBank6 VCCOBank7 G6

XIL_DONE

TB59
U33
+3V3 +3V3 +3V3 +3V3
XC2V1000-4

R234
+3V3 Y19 C19
XIL_CCLK CCLK TCK XIL_TCK

0
XIL_PROG A2 PROG_B TDI D3 XIL0_TDO
AB20 DONE TDO D20 XIL1_TDO
AB2 B20

R249
M0 TMS XIL_TMS

1K00
W3 M1 DXN D5
2 AB3 A3
M2 DXP
B3 HSWAP_EN VBATT A21
AB21 PWRDWN_B RSVD A20

R244

R251

R252

R250
1K00

1K00

1K00

1K00

R233
1K00
B

+3V3 +3V3
TP7

+3V3

C26
47U

A
837 0147 042 Rev.A
FORM:

FPGA RFII E MTI

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 5 16

 1 2 3 4 5 6 7 8 9 10 11

F
U20 U20 U20 U20
XC2S300 XC2S300 XC2S300 XC2S300

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

DPX1 A3 I/O GCK2,I A11 XIL2_DPTCLK XIL_BUSY C21 I/O(DOUT,BUSY) I/O(TRDY) L22 M1X16 M2X0 U12 I/O I/O U9 OCI0 CFI12 M1 I/O(TRDY) I/O C1 MTI_COR0
DPX0 A4 I/O I/O(DLL) A12 DPX9 XIL_DATA0 C22 I/O(DIN,D0) I/O M17 M1X17 M2X1 U13 I/O I/O U10 OCI1 CFI13 M2 I/O I/O C2 CPUAUX0
DPX3 A5 I/O I/O A13 DPX17 DPY3 D20 I/O I/O M18 M1X15 M2X2 U14 I/O I/O U11 OCI2 CFI2 M3 I/O I/O D1 CFQ15
DPX2 A6 I/O I/O A14 DPX19 DPY0 D21 I/O(VREFBank2) I/O M19 M1Y1 M2X3 V12 I/O I/O V6 OCI3 CFI3 M4 I/O I/O D2 CFMOFF
DPX4 A7 I/O I/O A15 DPX20 DPY1 D22 I/O I/O M20 M1X20 M2X4 V13 I/O(VREFBank4) I/O V7 OCI4 CFI4 M5 I/O I/O D3 CFQ9
DPX5 A8 I/O I/O A16 DPX22 RXYCS E19 I/O I/O M21 M1X21 M2X5 V14 I/O I/O(VREFBank5) V8 OCI5 CFI5 M6 I/O I/O E1 CFQ10
DPX7 A9 I/O I/O A17 XIL2_XIL3_AUX0 RXYOE E20 I/O I/O M22 M1X19 M2X6 V15 I/O(VREFBank4) I/O V9 OCI6 CFI6 N1 I/O I/O(VREFBank7) E2 CFQ14
DPX14 A10 I/O I/O A18 DPY19 RXYWE E21 I/O I/O(D4) N17 XIL_DATA4 M2X7 V16 I/O I/O(VREFBank5) V10 OCI7 CFI7 N2 I/O I/O E3 LD2
TY2 B3 I/O I/O A19 DPY17 MEM1CS E22 I/O I/O(VREFBank3) N18 TB45 M2X8 V17 I/O I/O V11 OCI8 CFI8 N3 I/O(VREFBank6) I/O F1 CPUAUX1
TY3 B4 I/O I/O(WRITE) A20 XIL_WRITE MEM1OE F18 I/O I/O N19 M1Y0 M2X9 W12 I/O I/O W5 OCI9 CFI9 N4 I/O I/O(VREFBank7) F2 XIL2_TXS
TY4 B5 I/O I/O B12 PEROE MEM1WE F19 I/O I/O N20 M1X23 M2X10 W13 I/O I/O W6 OCI10 CFI10 N5 I/O I/O F3 LD5
TY5 B6 I/O(VREFBank0) I/O(VREFBank1) B13 DPX16 MEM2CS F20 I/O I/O N21 M1X22 M2X11 W14 I/O I/O W7 OCI11 CFI11 N6 I/O I/O F4 LD6
E
TY6 B7 I/O I/O B14 DPX18 MEM2OE F21 I/O(VREFBank2) I/O N22 M1Y3 M2X12 W15 I/O I/O W8 OCI12 CFI0 P1 I/O I/O F5 LD7
TX1 B8 I/O I/O B15 DPX21 MEM2WE F22 I/O I/O P17 TB48 M2X13 W16 I/O I/O W9 OCI13 CFI1 P2 I/O I/O G1 MTI_COR1
DPX6 B9 I/O I/O B16 DPX23 DPY8 G18 I/O I/O P18 TB47 M2X14 W17 I/O I/O W10 OCI14 CFI14 P3 I/O I/O G2 FIRST/SECOND
DPX15 B10 I/O I/O B17 DPY21 M1X1 G19 I/O I/O P19 TB46 M2X15 W18 I/O(VREFBank4) I/O W11 OCI15 CFI15 P4 I/O I/O G3 LD10
DPX13 B11 I/O(DLL) I/O(VREFBank1) B18 DPY18 XIL1_XIL2_AUX1 G20 I/O I/O P20 M1X18 M2X16 Y12 I/O(DLL) I/O Y5 OCQ0 CFQ0 P5 I/O I/O G4 LD11
CFMAUX2 C4 I/O I/O B19 DPY16 XIL2_XIL3_AUX1 G21 I/O I/O P21 M1Y8 M2X17 Y13 I/O I/O Y6 OCQ1 CFQ1 P6 I/O I/O G5 LD12
C5 B20 G22 P22 +3V3 Y14 Y7 R1 H1
CFMAUX3 I/O(VREFBank0) I/O(CS) XIL2_CS M1X6 I/O I/O(D5) XIL_DATA5 M2X18 I/O I/O OCQ2 LN0 I/O I/O ACFM
CFMAUX5 C6 I/O I/O C12 DPY22 M1X14 H18 I/O(VREFBank2) I/O(VREFBank3) R18 M1Y9 M2X19 Y15 I/O I/O Y8 OCQ3 LN1 R2 I/O I/O H2 CFMON
CFMAUX7 C7 I/O I/O C13 DPY12 XIL_DATA1 H19 I/O(D1) I/O(D6) R19 XIL_DATA6 M2X20 Y16 I/O I/O Y9 OCQ4 CFQ4 R3 I/O(VREFBank6) I/O(VREFBank7) H3 LD15
C8 C14 H20 R20 Y17 Y10 R4 H4

R202
TX3 I/O I/O DPY14 XIL_DATA2 I/O(D2) I/O M1Y10 M2X21 I/O(VREFBank4) I/O OCQ5 CFQ5 I/O I/O LSDOP
C9 C15 H21 R21 Y18 Y11 R5 H5

4K7
TY7 I/O I/O PERWE M1X5 I/O I/O M1Y11 M2X22 I/O I/O OCQ6 CFQ6 I/O I/O LRW
TY8 C10 I/O I/O C16 DPY6 M1X4 H22 I/O I/O R22 M1Y12 M2X23 Y19 I/O I/O AA3 OCQ7 LNA6 T1 I/O I/O J1 CFQ12
XIL2_40M C11 GCK3,I I/O C17 DPY4 M1X0 J17 I/O I/O T18 M1Y13 AA12 GCK0/I I/O AA5 OCQ8 LNA7 T2 I/O I/O J2 CFQ13
CFMAUX1 D5 I/O I/O C18 DPY2 M1X11 J18 I/O I/O T19 M1Y14 AA13 I/O I/O AA6 OCQ9 LA4 T3 I/O I/O J3 LNA2
CFMAUX4 D6 I/O I/O D12 DPY10 M1X13 J19 I/O I/O T20 M1Y15 M2Y0 AA14 I/O I/O AA7 OCQ10 LD1 T4 I/O I/O J4 LNA3
CFMAUX6 D7 I/O I/O D13 DPY13 M1X12 J20 I/O I/O(VREFBank3) T21 M1Y16 M2Y1 AA15 I/O I/O AA8 OCQ11 CFQ11 T5 I/O I/O J5 LNA4
CFMAUX0 D8 I/O(VREFBank0) I/O D14 DPY15 M1Y7 J21 I/O I/O T22 M1Y17 M2Y2 AA16 I/O I/O AA9 OCQ12 LNA0 U1 I/O(VREFBank6) I/O J6 LNA5
D TY0 D9 I/O I/O(VREFBank1) D15 TX8 M1Y6 J22 I/O I/O U18 M1Y18 M2Y3 AA17 I/O I/O AA10 OCQ13 LNA1 U2 I/O I/O K1 LNA8
TY1 D10 I/O(VREFBank0) I/O D16 DPY5 DPY9 K17 I/O I/O U19 M1Y19 M2Y4 AA18 I/O I/O AA11 OCQ14 LD0 U3 I/O I/O K2 CFQ8
DPX12 D11 I/O I/O D17 XIL2_AUX0 M1X7 K18 I/O(VREFBank2) I/O U20 M1Y20 M2Y5 AA19 I/O I/O AB3 OCQ15 LA3 U4 I/O I/O(VREFBank7) K3 CFQ7
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

TX4 E7 I/O I/O D18 XIL2_AUX1 XIL_DATA3 K19 I/O(D3) I/O U21 M1Y21 M2Y6 AA20 I/O I/O AB4 M2Y23 LD13 V1 I/O I/O K4 LNA9
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

TX5 E8 I/O I/O E12 DPY11 M1X10 K20 I/O I/O U22 M1Y22 M2Y7 AB13 I/O I/O(VREFBank5) AB5 M2Y22 LD14 V2 I/O(VREFBank6) I/O K5 LNA10
TX6 E9 I/O I/O E13 DPY23 M1Y5 K21 I/O I/O V19 M1Y23 M2Y8 AB14 I/O I/O AB6 M2Y21 LA2 V3 I/O I/O K6 LNA11
TX0 E10 I/O I/O E14 DPY20 M1Y4 K22 I/O I/O V20 FLAG2 M2Y9 AB15 I/O I/O(VREFBank5) AB7 M2Y20 LA1 V4 I/O I/O L1 CFQ2
DPX10 E11 I/O I/O E15 DPY7 M1X2 L17 I/O I/O V21 TB51 M2Y10 AB16 I/O I/O AB8 M2Y19 LD8 W1 I/O I/O L2 CFQ3
TX7 F9 I/O I/O(VREFBank1) E16 XIL2_AUX2 M1X3 L18 I/O I/O(VREFBank3) V22 M2Y11 AB17 I/O I/O AB9 M2Y18 LD9 W2 I/O I/O L3 LN2
TX2 F10 I/O I/O E17 XIL2_AUX3 M1X9 L19 I/O I/O(INIT) W21 M2Y12 AB18 I/O I/O AB10 M2Y17 LA0 W3 I/O I/O L4 LN3
DPX11 F11 I/O I/O F12 DPX8 M1X8 L20 I/O I/O W22 TB50 M2Y13 AB19 I/O I/O(DLL) AB11 M2Y16 LD3 Y1 I/O I/O L5 SCAUX0
I/O F13 PERCS M1Y2 L21 I/O(IRDY) I/O(D7) Y22 XIL_DATA7 M2Y14 AB20 I/O GCK1,I AB12 LD4 Y2 I/O I/O(IRDY) L6 SCAUX1
I/O F14 XIL1_XIL2_AUX0 M2Y15 AB21 I/O

4K7
R203
R210
F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T9 N7 VCCOBank6 VCCOBank7 G6
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T10 P7 VCCOBank6 VCCOBank7 H6

0
G9 VCCOBank0 VCCOBank1 G13 J16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 J7
C G10 VCCOBank0 VCCOBank1 G14 K16 VCCOBank2 VCCOBank3 T17 XIL_INIT U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7
+3V3

XIL_DONE U20
+3V3 +3V3 +3V3 +3V3 +3V3
XC2S300

R208

TB60
XIL_CCLK B22 CCLK TCK E6 XIL_TCK

0
XIL_PROG Y21 PROGRAM

R204
W20 DONE

1K00
AA1 M0 TDI C19 XIL1_TDO
2 U5 A21
M1 TDO XIL2_TDO
AB2 M2 TMS E4 XIL_TMS

R205

R209

R206
1K00

1K00

1K00
B XIL2_40M +3V3

2
R217
82

2
100P
C162

TP9

A +3V3
837 0147 042 Rev.A

C29
FORM:

47U

FPGA CORRELATOR

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 6 16

 1 2 3 4 5 6 7 8 9 10 11

F
U32 U32 U32 U32
XC2S300 XC2S300 XC2S300 XC2S300

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

CFMD0 A3 I/O GCK2,I A11 XIL3_DPTCLK XIL_BUSY C21 I/O(DOUT,BUSY) I/O(TRDY) L22 OCS TX0 U12 I/O I/O U9 TO1 CFI0 M1 I/O(TRDY) I/O C1 LA0
CFMD2 A4 I/O I/O(DLL) A12 TB85 XIL_DATA0 C22 I/O(DIN,D0) I/O M17 OOE TX1 U13 I/O I/O U10 TO2 CFI1 M2 I/O I/O C2 LA1
CFMD5 A5 I/O I/O A13 TB84 M1O13 D20 I/O I/O M18 OWE TX2 U14 I/O I/O U11 TO3 CFI2 M3 I/O I/O D1 LA2
CFMD9 A6 I/O I/O A14 TB83 M1O14 D21 I/O(VREFBank2) I/O M19 OCLK TX3 V12 I/O I/O V6 TO4 CFI3 M4 I/O I/O D2 LA3
CFMD13 A7 I/O I/O A15 TB82 M1O15 D22 I/O I/O M20 TH1 TX4 V13 I/O(VREFBank4) I/O V7 TO5 CFI4 M5 I/O I/O D3 LA4
CFMD17 A8 I/O I/O A16 M2O0 M1O9 E19 I/O I/O M21 TH2 TX5 V14 I/O I/O(VREFBank5) V8 TO6 CFI5 M6 I/O I/O E1 LD0
A9 I/O I/O A17 M2O1 M1O10 E20 I/O I/O M22 VARIANCE TX6 V15 I/O(VREFBank4) I/O V9 TO7 CFI6 N1 I/O I/O(VREFBank7) E2 LD1
A10 I/O I/O A18 M2O2 M1O11 E21 I/O I/O(D4) N17 XIL_DATA4 TX7 V16 I/O I/O(VREFBank5) V10 TO8 CFI7 N2 I/O I/O E3 LD2
CFMD1 B3 I/O I/O A19 M2O3 M1O12 E22 I/O I/O(VREFBank3) N18 ADP10 TX8 V17 I/O I/O V11 CFMAUX0 CFI8 N3 I/O(VREFBank6) I/O F1 LD3
CFMD3 B4 I/O I/O(WRITE) A20 XIL_WRITE M1O4 F18 I/O I/O N19 ADP11 TY0 W12 I/O I/O W5 CFMAUX1 CFI9 N4 I/O I/O(VREFBank7) F2 LD4
CFMD6 B5 I/O I/O B12 Q0 M1O5 F19 I/O I/O N20 ADP12 TY1 W13 I/O I/O W6 CFMAUX2 CFI10 N5 I/O I/O F3 LD5
CFMD10 B6 I/O(VREFBank0) I/O(VREFBank1) B13 Q1 M1O6 F20 I/O I/O N21 ADP13 TY2 W14 I/O I/O W7 CFMAUX3 CFI11 N6 I/O I/O F4 LD6
E
CFMD14 B7 I/O I/O B14 Q2 M1O7 F21 I/O(VREFBank2) I/O N22 ADP14 TY3 W15 I/O I/O W8 CFMAUX4 CFI12 P1 I/O I/O F5 LD7
XIL3_AUX0 B8 I/O I/O B15 Q3 M1O8 F22 I/O I/O P17 ADP15 TY4 W16 I/O I/O W9 CFMAUX5 CFI13 P2 I/O I/O G1 LD8
XIL3_AUX1 B9 I/O I/O B16 M2O4 M1O0 G18 I/O I/O P18 ADP16 TY5 W17 I/O I/O W10 CFMAUX6 CFI14 P3 I/O I/O G2 LD9
XIL3_AUX2 B10 I/O I/O B17 M2O5 M1O1 G19 I/O I/O P19 ADP17 TY6 W18 I/O(VREFBank4) I/O W11 CFMAUX7 CFI15 P4 I/O I/O G3 LD10
XIL3_AUX3 B11 I/O(DLL) I/O(VREFBank1) B18 M2O6 M1O2 G20 I/O I/O P20 TY7 Y12 I/O(DLL) I/O Y5 VA0 CFQ0 P5 I/O I/O G4 LD11
CFMD4 C4 I/O I/O B19 M2O7 M1O3 G21 I/O I/O P21 TY8 Y13 I/O I/O Y6 VA1 CFQ1 P6 I/O I/O G5 LD12
C5 B20 G22 P22 +3V3 Y14 Y7 R1 H1
CFMD7 I/O(VREFBank0) I/O(CS) XIL3_CS I/O I/O(D5) XIL_DATA5 I/O I/O VA2 CFQ2 I/O I/O LD13
CFMD11 C6 I/O I/O C12 Q4 H18 I/O(VREFBank2) I/O(VREFBank3) R18 Y15 I/O I/O Y8 VA3 CFQ3 R2 I/O I/O H2 LD14
CFMD15 C7 I/O I/O C13 Q5 XIL_DATA1 H19 I/O(D1) I/O(D6) R19 XIL_DATA6 Y16 I/O I/O Y9 VA4 CFQ4 R3 I/O(VREFBank6) I/O(VREFBank7) H3 LD15
C8 C14 H20 R20 Y17 Y10 R4 H4

R220
I/O I/O Q6 XIL_DATA2 I/O(D2) I/O AD0 I/O(VREFBank4) I/O VA5 CFQ5 I/O I/O LSDOP
C9 C15 H21 R21 Y18 Y11 R5 H5

4K7
I/O I/O Q7 ADB10 I/O I/O AD1 I/O I/O VA6 CFQ6 I/O I/O LRW
FLAG2 C10 I/O I/O C16 M2O8 ADB11 H22 I/O I/O R22 AD2 Y19 I/O I/O AA3 VA7 CFQ7 T1 I/O I/O J1 LNA0
XIL3_40M C11 GCK3,I I/O C17 M2O9 ADB12 J17 I/O I/O T18 AD3 AA12 GCK0/I I/O AA5 VE0 CFQ8 T2 I/O I/O J2 LNA1
CFMD8 D5 I/O I/O C18 M2O10 ADB13 J18 I/O I/O T19 AD4 AA13 I/O I/O AA6 VE1 CFQ9 T3 I/O I/O J3 LNA2
CFMD12 D6 I/O I/O D12 Q8 ADB14 J19 I/O I/O T20 AD5 DPO1 AA14 I/O I/O AA7 VE2 CFQ10 T4 I/O I/O J4 LNA3
CFMD16 D7 I/O I/O D13 Q9 ADR10 J20 I/O I/O(VREFBank3) T21 AD6 DPO3 AA15 I/O I/O AA8 VE3 CFQ11 T5 I/O I/O J5 LNA4
XIL1_XIL3_AUX0 D8 I/O(VREFBank0) I/O D14 Q10 ADR11 J21 I/O I/O T22 AD7 DPO11 AA16 I/O I/O AA9 VE4 CFQ12 U1 I/O(VREFBank6) I/O J6 LNA5
D XIL1_XIL3_AUX1 D9 I/O I/O(VREFBank1) D15 Q11 ADR12 J22 I/O I/O U18 AD8 DPO13 AA17 I/O I/O AA10 VE5 CFQ13 U2 I/O I/O K1 LNA6
XIL2_XIL3_AUX0 D10 I/O(VREFBank0) I/O D16 M2O11 ADR13 K17 I/O I/O U19 AD9 DPO14 AA18 I/O I/O AA11 VE6 CFQ14 U3 I/O I/O K2 LNA7
XIL2_XIL3_AUX1 D11 I/O I/O D17 M2O12 ADR14 K18 I/O(VREFBank2) I/O U20 ADA10 DPO15 AA19 I/O I/O AB3 VE7 CFQ15 U4 I/O I/O(VREFBank7) K3 LNA8
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

E7 I/O I/O D18 M2O13 XIL_DATA3 K19 I/O(D3) I/O U21 ADA11 DPO12 AA20 I/O I/O AB4 ACFM V1 I/O I/O K4 LNA9
TB93
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

E8 I/O I/O E12 Q12 ADQ10 K20 I/O I/O U22 ADA12 DPO7 AB13 I/O I/O(VREFBank5) AB5 CFMON V2 I/O(VREFBank6) I/O K5 LNA10
TB92 E9 E13 K21 V19 AB14 AB6 V3 K6
TB91 I/O I/O Q13 ADQ11 I/O I/O ADA13 DPO0 I/O I/O CFMOFF I/O I/O LNA11
E10 I/O I/O E14 Q14 ADQ12 K22 I/O I/O V20 ADA14 DPO2 AB15 I/O I/O(VREFBank5) AB7 MTI_COR0 V4 I/O I/O L1 LN0
TB89 E11 E15 L17 V21 AB16 AB8 W1 L2
TB87 I/O I/O Q15 ADQ13 I/O I/O ADA15 DPO4 I/O I/O MTI_COR1 I/O I/O LN1
F9 I/O I/O(VREFBank1) E16 M2O14 ADQ14 L18 I/O I/O(VREFBank3) V22 DPO5 AB17 I/O I/O AB9 FIRST/SECOND W2 I/O I/O L3 LN2
TB90 F10 E17 L19 W21 AB18 AB10 W3 L4
TB88 I/O I/O M2O15 ADDAUX I/O I/O(INIT) DPO6 I/O I/O CPUAUX0 I/O I/O LN3
F11 I/O I/O F12 L20 I/O I/O W22 DPO10 AB19 I/O I/O(DLL) AB11 CPUAUX1 Y1 I/O I/O L5 SCAUX0
TB86 F13 L21 Y22 AB20 AB12 Y2 L6
I/O I/O(IRDY) I/O(D7) XIL_DATA7 DPO9 I/O GCK1,I XIL3_TXS I/O I/O(IRDY) SCAUX1
I/O F14 DPO8 AB21 I/O

4K7
R221
F7 F15 G17 N16 T13 T9 N7 G6

R230
VCCOBank0 VCCOBank1 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T10 P7 VCCOBank6 VCCOBank7 H6

0
G9 VCCOBank0 VCCOBank1 G13 J16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 J7
C G10 VCCOBank0 VCCOBank1 G14 K16 VCCOBank2 VCCOBank3 T17 XIL_INIT U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7
+3V3

XIL_DONE U32
+3V3 +3V3 +3V3 +3V3
+3V3 XC2S300

R231
XIL_CCLK B22 CCLK TCK E6 XIL_TCK

0
XIL_PROG Y21 PROGRAM
W20 DONE

R223
AA1 C19

1K00
M0 TDI XIL2_TDO
2 U5 M1 TDO A21 XIL_TDO
AB2 M2 TMS E4 XIL_TMS

R224

R232

R222
1K00

1K00

1K00
XIL3_40M

B 2 +3V3
R254
82

2
C279
100P

TP14

+3V3

A
C27
837 0147 042 Rev.A

47U
FORM:

FPGA CORRELATOR

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 7 16

 1 2 3 4 5 6 7 8 9 10 11

U22 U8 U12 U13 U9

74LVT273 K6R1016V1D K6R1016V1D K6R1016V1D K6R1016V1D
ADCK 11 CLK MTIOE 41 OE MTIOE 41 OE MTIOE 41 OE MTIOE 41 OE
F ADOFF 1 RES MTIWE 17 WE MTIWE 17 WE MTIWE 17 WE MTIWE 17 WE
MTICS 6 CS MTICS 6 CS MTICS 6 CS MTICS 6 CS
AA0 3 1D 1Q 2 AD_MTI0
40 UB 40 UB 40 UB 40 UB
AA1 4 2D 2Q 5 AD_MTI1
39 LB 39 LB 39 LB 39 LB
AA2 7 3D 3Q 6 AD_MTI2
AA3 8 4D 4Q 9 AD_MTI3 AD_MTI0 44 A0 I/O0 7 1J_0 AD_MTI0 44 A0 I/O0 7 2J_0 AD_MTI0 44 A0 I/O0 7 3J_0 AD_MTI0 44 A0 I/O0 7 4J_0
AA4 13 5D 5Q 12 AD_MTI4 AD_MTI1 43 A1 I/O1 8 1J_1 AD_MTI1 43 A1 I/O1 8 2J_1 AD_MTI1 43 A1 I/O1 8 3J_1 AD_MTI1 43 A1 I/O1 8 4J_1
AA5 14 6D 6Q 15 AD_MTI5 AD_MTI2 42 A2 I/O2 9 1J_2 AD_MTI2 42 A2 I/O2 9 2J_2 AD_MTI2 42 A2 I/O2 9 3J_2 AD_MTI2 42 A2 I/O2 9 4J_2
AA6 17 7D 7Q 16 AD_MTI6 AD_MTI3 27 A3 I/O3 10 1J_3 AD_MTI3 27 A3 I/O3 10 2J_3 AD_MTI3 27 A3 I/O3 10 3J_3 AD_MTI3 27 A3 I/O3 10 4J_3
AA7 18 8D 8Q 19 AD_MTI7 AD_MTI4 26 A4 I/O4 13 1J_4 AD_MTI4 26 A4 I/O4 13 2J_4 AD_MTI4 26 A4 I/O4 13 3J_4 AD_MTI4 26 A4 I/O4 13 4J_4
AD_MTI5 25 A5 I/O5 14 1J_5 AD_MTI5 25 A5 I/O5 14 2J_5 AD_MTI5 25 A5 I/O5 14 3J_5 AD_MTI5 25 A5 I/O5 14 4J_5
AD_MTI6 24 A6 I/O6 15 1J_6 AD_MTI6 24 A6 I/O6 15 2J_6 AD_MTI6 24 A6 I/O6 15 3J_6 AD_MTI6 24 A6 I/O6 15 4J_6
U21
AD_MTI7 21 A7 I/O7 16 1J_7 AD_MTI7 21 A7 I/O7 16 2J_7 AD_MTI7 21 A7 I/O7 16 3J_7 AD_MTI7 21 A7 I/O7 16 4J_7
74LVT273 20 29 20 29 20 29 20 29
AD_MTI8 A8 I/O8 1J_8 AD_MTI8 A8 I/O8 2J_8 AD_MTI8 A8 I/O8 3J_8 AD_MTI8 A8 I/O8 4J_8
ADCK 11 CLK
AD_MTI9 19 A9 I/O9 30 1J_9 AD_MTI9 19 A9 I/O9 30 2J_9 AD_MTI9 19 A9 I/O9 30 3J_9 AD_MTI9 19 A9 I/O9 30 4J_9
ADOFF 1 RES
AD_MTI10 18 A10 I/O10 31 1J_10 AD_MTI10 18 A10 I/O10 31 2J_10 AD_MTI10 18 A10 I/O10 31 3J_10 AD_MTI10 18 A10 I/O10 31 4J_10
AA8 3 1D 1Q 2 AD_MTI8 LN0 5 A11 I/O11 32 1J_11 LN0 5 A11 I/O11 32 2J_11 LN0 5 A11 I/O11 32 3J_11 LN0 5 A11 I/O11 32 4J_11
AA9 4 2D 2Q 5 AD_MTI9 LN1 4 A12 I/O12 35 1J_12 LN1 4 A12 I/O12 35 2J_12 LN1 4 A12 I/O12 35 3J_12 LN1 4 A12 I/O12 35 4J_12
E AA10 7 3D 3Q 6 AD_MTI10 LN2 3 A13 I/O13 36 1J_13 LN2 3 A13 I/O13 36 2J_13 LN2 3 A13 I/O13 36 3J_13 LN2 3 A13 I/O13 36 4J_13
AA11 8 4D 4Q 9 LN0 LN3 2 A14 I/O14 37 1J_14 LN3 2 A14 I/O14 37 2J_14 LN3 2 A14 I/O14 37 3J_14 LN3 2 A14 I/O14 37 4J_14
AA12 13 5D 5Q 12 LN1 1 A15 I/O15 38 1J_15 1 A15 I/O15 38 2J_15 1 A15 I/O15 38 3J_15 1 A15 I/O15 38 4J_15
AA13 14 6D 6Q 15 LN2 22 NC 22 NC 22 NC 22 NC
AA14 17 7D 7Q 16 LN3 23 NC 23 NC 23 NC 23 NC
AA15 18 8D 8Q 19 28 NC 28 NC 28 NC 28 NC

R198
U7

1K00

TP2

TP1

TP3

TP5

TP4

TP8
7ALCX374
1 OE
TEST_CLK 11 CLK

TESTCOS8 3 D1 Q1 2 TCOS0
D
TESTCOS9 4 D2 Q2 5 TCOS1
TESTCOS10 7 D3 Q3 6 TCOS2
8 9
R30 R26 R212 R79
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

TESTCOS11 D4 Q4 TCOS3
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

13 12 1K2 1K2 82K 82K

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

TESTCOS12 D5 Q5 TCOS4
TCOS7 TSIN7 CFI10 CFQ10
TESTCOS13 14 D6 Q6 15 TCOS5
TESTCOS14 17 D7 Q7 16 TCOS6

R46

R52

R40

R42
18 19 R29 R25 R207 R61

1K2

1K2

1K2

1K2
TESTCOS15 D8 Q8 TCOS7
1K2 1K2 39K 39K
TCOS6 TSIN6 CFI11 CFQ11

R51

R45

R38

R41
R28 R24 R214 R67

1K2

1K2

1K2

1K2
1K2 1K2 22K 22K
TCOS5 TSIN5 CFI12 CFQ12

R195

R50

R44

R39

R36
U6 R27 R23 R213 R68

1K2

1K2

1K2

1K2
1K00
C 7ALCX374 1K2 1K2 10K 10K
1 TCOS4 TSIN4 CFI13 CFQ13
OE
TEST_CLK 11 CLK

R49

R43

R37

R35
3 2 R12 R1 R211 R80

1K2

1K2

1K2

1K2
TESTSIN8 D1 Q1 TSIN0
TESTSIN9 4 D2 Q2 5 TSIN1 1K2 1K2 4K7 4K7
TESTSIN10 7 D3 Q3 6 TSIN2 TCOS3 TSIN3 CFI14 CFQ14
TESTSIN11 8 D4 Q4 9 TSIN3
TESTSIN12 13 D5 Q5 12 TSIN4

R14

R13
R15 R4

1K2

1K2

1K2

1K2
R3

R2
TESTSIN13 14 D6 Q6 15 TSIN5
TESTSIN14 17 D7 Q7 16 TSIN6 1K2 1K2
18 19 TCOS2 TSIN2
TESTSIN15 D8 Q8 TSIN7

R17

R16
R18 R7

1K2

1K2

1K2

1K2
R6

R5
1K2 1K2
TCOS1 TSIN1

R19

R20
B R21 R10

1K2

1K2

1K2

1K2
R8

R9
1K2 1K2
TCOS0 TSIN0
TP11 R22

R11
1K2

1K2
A
837 0147 042 Rev.A
FORM:

MEMORIE MTI E TEST POINT RFII E MTI

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 8 16

 1 2 3 4 5 6 7 8 9 10 11

U58 U40 U47 U31

K6R1016V1D K6R1016V1D K6R1016V1D K6R4016V1D
OOE 41 OE MEM1OE 41 OE MEM2OE 41 OE PEROE 41 OE
F OWE 17 WE MEM1WE 17 WE MEM2WE 17 WE PERWE 17 WE
OCS 6 CS MEM1CS 6 CS MEM2CS 6 CS PERCS 6 CS
40 UB 40 UB 40 UB 40 UB
39 LB 39 LB 39 LB 39 LB

AD0 44 A0 I/O0 7 Q0 AD0 44 A0 I/O0 7 M1O0 AD0 44 A0 I/O0 7 M2O0 AD0 1 A0 I/O0 7 DPO0
AD1 43 A1 I/O1 8 Q1 AD1 43 A1 I/O1 8 M1O1 AD1 43 A1 I/O1 8 M2O1 AD1 2 A1 I/O1 8 DPO1
AD2 42 A2 I/O2 9 Q2 AD2 42 A2 I/O2 9 M1O2 AD2 42 A2 I/O2 9 M2O2 AD2 3 A2 I/O2 9 DPO2
AD3 27 A3 I/O3 10 Q3 AD3 27 A3 I/O3 10 M1O3 AD3 27 A3 I/O3 10 M2O3 AD3 4 A3 I/O3 10 DPO3
AD4 26 A4 I/O4 13 Q4 AD4 26 A4 I/O4 13 M1O4 AD4 26 A4 I/O4 13 M2O4 AD4 5 A4 I/O4 13 DPO4
AD5 25 A5 I/O5 14 Q5 AD5 25 A5 I/O5 14 M1O5 AD5 25 A5 I/O5 14 M2O5 AD5 18 A5 I/O5 14 DPO5
AD6 24 A6 I/O6 15 Q6 AD6 24 A6 I/O6 15 M1O6 AD6 24 A6 I/O6 15 M2O6 AD6 19 A6 I/O6 15 DPO6
AD7 21 A7 I/O7 16 Q7 AD7 21 A7 I/O7 16 M1O7 AD7 21 A7 I/O7 16 M2O7 AD7 20 A7 I/O7 16 DPO7
AD8 20 A8 I/O8 29 Q8 AD8 20 A8 I/O8 29 M1O8 AD8 20 A8 I/O8 29 M2O8 AD8 21 A8 I/O8 29 DPO8
ADDAUX 19 A9 I/O9 30 Q9 AD9 19 A9 I/O9 30 M1O9 AD9 19 A9 I/O9 30 M2O9 AD9 22 A9 I/O9 30 DPO9
ADQ10 18 A10 I/O10 31 Q10 ADA10 18 A10 I/O10 31 M1O10 ADB10 18 A10 I/O10 31 M2O10 ADP10 23 A10 I/O10 31 DPO10
ADQ11 5 A11 I/O11 32 Q11 ADA11 5 A11 I/O11 32 M1O11 ADB11 5 A11 I/O11 32 M2O11 ADP11 24 A11 I/O11 32 DPO11
ADQ12 4 A12 I/O12 35 Q12 ADA12 4 A12 I/O12 35 M1O12 ADB12 4 A12 I/O12 35 M2O12 ADP12 25 A12 I/O12 35 DPO12
E ADQ13 3 A13 I/O13 36 Q13 ADA13 3 A13 I/O13 36 M1O13 ADB13 3 A13 I/O13 36 M2O13 ADP13 26 A13 I/O13 36 DPO13
ADQ14 2 A14 I/O14 37 Q14 ADA14 2 A14 I/O14 37 M1O14 ADB14 2 A14 I/O14 37 M2O14 ADP14 27 A14 I/O14 37 DPO14
1 A15 I/O15 38 Q15 ADA15 1 A15 I/O15 38 M1O15 1 A15 I/O15 38 M2O15 ADP15 42 A15 I/O15 38 DPO15
22 NC 22 NC 22 NC ADP16 43 A16
23 NC 23 NC 23 NC ADP17 44 A17
28 NC 28 NC 28 NC

R191

R190
U2 UP3

1K00

1K00
R199

R189

R188
UP2

1K00

1K00
1K00
7ACT374 29F040-70
D 1 24 U5 27C4096-70 U3
OE R200 OE R194 R192
OCLK 11 CLK 1K00
22 CE 1K00
74LCX244 22 OE 1K00
74LCX244

VCC
31 WE 1 1G 3 CS 1 1G
R0 3 D1 Q1 2 RT0
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

VCC
19 2 19
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

4 5 2G Vpp 2G
R1 D2 Q2 RT1
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

R2 7 D3 Q3 6 RT2 RT0 12 A0 O0 13 2 1A1 1Y1 18 VA0 TY0 24 A0 O0 21 2 1A1 1Y1 18 VE0

R3 8 D4 Q4 9 RT3 RT1 11 A1 O1 14 4 1A2 1Y2 16 VA1 TY1 25 A1 O1 20 4 1A2 1Y2 16 VE1
R4 13 D5 Q5 12 RT4 RT2 10 A2 O2 15 6 1A3 1Y3 14 VA2 TY2 26 A2 O2 19 6 1A3 1Y3 14 VE2
R5 14 D6 Q6 15 RT5 RT3 9 A3 O3 17 8 1A4 1Y4 12 VA3 TY3 27 A3 O3 18 8 1A4 1Y4 12 VE3
R6 17 D7 Q7 16 RT6 RT4 8 A4 O4 18 11 2A1 2Y1 9 VA4 TY4 28 A4 O4 17 11 2A1 2Y1 9 VE4
R7 18 D8 Q8 19 RT7 RT5 7 A5 O5 19 13 2A2 2Y2 7 VA5 TY5 29 A5 O5 16 13 2A2 2Y2 7 VE5
RT6 6 A6 O6 20 15 2A3 2Y3 5 VA6 TY6 30 A6 O6 15 15 2A3 2Y3 5 VE6
RT7 5 A7 O7 21 17 2A4 2Y4 3 VA7 TY7 31 A7 O7 14 17 2A4 2Y4 3 VE7
U4 27 32 11
R193 PO0 A8 TY8 A8 O8 R0
1K00
7ACT374 PO1 26 A9 TX0 35 A9 O9 10 R1
1 OE PO2 23 A10 TX1 36 A10 O10 9 R2
OCLK 11 CLK PO3 25 A11 TX2 37 A11 O11 8 R3
PO4 4 A12 TX3 38 A12 O12 7 R4
TO1 3 D1 Q1 2 PO0
C TO2 4 D2 Q2 5 PO1
PO5 28 A13 TX4 39 A13 O13 6 R5
PO6 29 A14 TX5 40 A14 O14 5 R6
TO3 7 D3 Q3 6 PO2
PO7 3 A15 TX6 41 A15 O15 4 R7
TO4 8 D4 Q4 9 PO3
VARIANCE 2 A16 TX7 42 A16
TO5 13 D5 Q5 12 PO4
TH1 30 A17 TX8 43 A17
TO6 14 D6 Q6 15 PO5
TH2 1 A18
TO7 17 D7 Q7 16 PO6
TO8 18 D8 Q8 19 PO7

TP12

TP13

TP10
R257 R247
100K 100K
CFMD2 CFMD7
R260 R246
B 47K 47K
CFMD3 CFMD12
R248 R255
22K 22K
CFMD4 CFMD13
R256 R258
10K 10K
CFMD5 CFMD14
R259 R245
4K7 4K7
CFMD6 CFMD15

A
837 0147 042 Rev.A
FORM:

MEMORIE E TEST POINT CORRELATOR

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 9 16

 1 2 3 4 5 6 7 8 9 10 11

U11 U1 U38 U35

K6R1016V1D K6R1016V1D K6R1016V1D K6R1016V1D
RXYOE 41 OE RXYOE 41 OE MEM1OE 41 OE MEM1OE 41 OE
F RXYWE 17 WE RXYWE 17 WE MEM1WE 17 WE MEM1WE 17 WE
RXYCS 6 CS RXYCS 6 CS MEM1CS 6 CS MEM1CS 6 CS
40 UB 40 UB 40 UB 40 UB
39 LB 39 LB 39 LB 39 LB

AD0 44 A0 I/O0 7 OCI0 AD0 44 A0 I/O0 7 OCQ0 AD0 44 A0 I/O0 7 M1X0 AD0 44 A0 I/O0 7 M1X16
AD1 43 A1 I/O1 8 OCI1 AD1 43 A1 I/O1 8 OCQ1 AD1 43 A1 I/O1 8 M1X1 AD1 43 A1 I/O1 8 M1X17
AD2 42 A2 I/O2 9 OCI2 AD2 42 A2 I/O2 9 OCQ2 AD2 42 A2 I/O2 9 M1X2 AD2 42 A2 I/O2 9 M1X18
AD3 27 A3 I/O3 10 OCI3 AD3 27 A3 I/O3 10 OCQ3 AD3 27 A3 I/O3 10 M1X3 AD3 27 A3 I/O3 10 M1X19
AD4 26 A4 I/O4 13 OCI4 AD4 26 A4 I/O4 13 OCQ4 AD4 26 A4 I/O4 13 M1X4 AD4 26 A4 I/O4 13 M1X20
AD5 25 A5 I/O5 14 OCI5 AD5 25 A5 I/O5 14 OCQ5 AD5 25 A5 I/O5 14 M1X5 AD5 25 A5 I/O5 14 M1X21
AD6 24 A6 I/O6 15 OCI6 AD6 24 A6 I/O6 15 OCQ6 AD6 24 A6 I/O6 15 M1X6 AD6 24 A6 I/O6 15 M1X22
AD7 21 A7 I/O7 16 OCI7 AD7 21 A7 I/O7 16 OCQ7 AD7 21 A7 I/O7 16 M1X7 AD7 21 A7 I/O7 16 M1X23
AD8 20 A8 I/O8 29 OCI8 AD8 20 A8 I/O8 29 OCQ8 AD8 20 A8 I/O8 29 M1X8 AD8 20 A8 I/O8 29 M1Y0
AD9 19 A9 I/O9 30 OCI9 AD9 19 A9 I/O9 30 OCQ9 AD9 19 A9 I/O9 30 M1X9 AD9 19 A9 I/O9 30 M1Y1
ADR10 18 A10 I/O10 31 OCI10 ADR10 18 A10 I/O10 31 OCQ10 ADA10 18 A10 I/O10 31 M1X10 ADA10 18 A10 I/O10 31 M1Y2
ADR11 5 A11 I/O11 32 OCI11 ADR11 5 A11 I/O11 32 OCQ11 ADA11 5 A11 I/O11 32 M1X11 ADA11 5 A11 I/O11 32 M1Y3
ADR12 4 A12 I/O12 35 OCI12 ADR12 4 A12 I/O12 35 OCQ12 ADA12 4 A12 I/O12 35 M1X12 ADA12 4 A12 I/O12 35 M1Y4
E ADR13 3 A13 I/O13 36 OCI13 ADR13 3 A13 I/O13 36 OCQ13 ADA13 3 A13 I/O13 36 M1X13 ADA13 3 A13 I/O13 36 M1Y5
ADR14 2 A14 I/O14 37 OCI14 ADR14 2 A14 I/O14 37 OCQ14 ADA14 2 A14 I/O14 37 M1X14 ADA14 2 A14 I/O14 37 M1Y6
1 A15 I/O15 38 OCI15 1 A15 I/O15 38 OCQ15 ADA15 1 A15 I/O15 38 M1X15 ADA15 1 A15 I/O15 38 M1Y7
22 NC 22 NC 22 NC 22 NC
23 NC 23 NC 23 NC 23 NC
28 NC 28 NC 28 NC 28 NC

U29 U27 U23 U16

K6R1016V1D K6R1016V1D K6R1016V1D K6R1016V1D
MEM1OE 41 OE MEM2OE 41 OE MEM2OE 41 OE MEM2OE 41 OE
MEM1WE 17 WE MEM2WE 17 WE MEM2WE 17 WE MEM2WE 17 WE
MEM1CS 6 CS MEM2CS 6 CS MEM2CS 6 CS MEM2CS 6 CS
40 UB 40 UB 40 UB 40 UB
39 LB 39 LB 39 LB 39 LB

AD0 44 A0 I/O0 7 M1Y8 AD0 44 A0 I/O0 7 M2X0 AD0 44 A0 I/O0 7 M2X16 AD0 44 A0 I/O0 7 M2Y8
D AD1 43 A1 I/O1 8 M1Y9 AD1 43 A1 I/O1 8 M2X1 AD1 43 A1 I/O1 8 M2X17 AD1 43 A1 I/O1 8 M2Y9
AD2 42 A2 I/O2 9 M1Y10 AD2 42 A2 I/O2 9 M2X2 AD2 42 A2 I/O2 9 M2X18 AD2 42 A2 I/O2 9 M2Y10
AD3 27 A3 I/O3 10 M1Y11 AD3 27 A3 I/O3 10 M2X3 AD3 27 A3 I/O3 10 M2X19 AD3 27 A3 I/O3 10 M2Y11
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

AD4 26 A4 I/O4 13 M1Y12 AD4 26 A4 I/O4 13 M2X4 AD4 26 A4 I/O4 13 M2X20 AD4 26 A4 I/O4 13 M2Y12
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

AD5 25 A5 I/O5 14 M1Y13 AD5 25 A5 I/O5 14 M2X5 AD5 25 A5 I/O5 14 M2X21 AD5 25 A5 I/O5 14 M2Y13
AD6 24 A6 I/O6 15 M1Y14 AD6 24 A6 I/O6 15 M2X6 AD6 24 A6 I/O6 15 M2X22 AD6 24 A6 I/O6 15 M2Y14
AD7 21 A7 I/O7 16 M1Y15 AD7 21 A7 I/O7 16 M2X7 AD7 21 A7 I/O7 16 M2X23 AD7 21 A7 I/O7 16 M2Y15
AD8 20 A8 I/O8 29 M1Y16 AD8 20 A8 I/O8 29 M2X8 AD8 20 A8 I/O8 29 M2Y0 AD8 20 A8 I/O8 29 M2Y16
AD9 19 A9 I/O9 30 M1Y17 AD9 19 A9 I/O9 30 M2X9 AD9 19 A9 I/O9 30 M2Y1 AD9 19 A9 I/O9 30 M2Y17
ADA10 18 A10 I/O10 31 M1Y18 ADB10 18 A10 I/O10 31 M2X10 ADB10 18 A10 I/O10 31 M2Y2 ADB10 18 A10 I/O10 31 M2Y18
ADA11 5 A11 I/O11 32 M1Y19 ADB11 5 A11 I/O11 32 M2X11 ADB11 5 A11 I/O11 32 M2Y3 ADB11 5 A11 I/O11 32 M2Y19
ADA12 4 A12 I/O12 35 M1Y20 ADB12 4 A12 I/O12 35 M2X12 ADB12 4 A12 I/O12 35 M2Y4 ADB12 4 A12 I/O12 35 M2Y20
ADA13 3 A13 I/O13 36 M1Y21 ADB13 3 A13 I/O13 36 M2X13 ADB13 3 A13 I/O13 36 M2Y5 ADB13 3 A13 I/O13 36 M2Y21
ADA14 2 A14 I/O14 37 M1Y22 ADB14 2 A14 I/O14 37 M2X14 ADB14 2 A14 I/O14 37 M2Y6 ADB14 2 A14 I/O14 37 M2Y22
ADA15 1 A15 I/O15 38 M1Y23 1 A15 I/O15 38 M2X15 1 A15 I/O15 38 M2Y7 1 A15 I/O15 38 M2Y23
22 NC 22 NC 22 NC 22 NC
23 NC 23 NC 23 NC 23 NC
C 28 NC 28 NC 28 NC 28 NC

U37
U36 U30
K6R4016V1D
41 K6R4016V1D K6R4016V1D
PEROE OE
PEROE 41 OE PEROE 41 OE
PERWE 17 WE
PERWE 17 WE PERWE 17 WE
PERCS 6 CS
PERCS 6 CS PERCS 6 CS
40 UB
40 UB 40 UB
39 LB
39 LB 39 LB
AD0 1 A0 I/O0 7 DPX0
AD0 1 A0 I/O0 7 DPX16 AD0 1 A0 I/O0 7 DPY8
AD1 2 A1 I/O1 8 DPX1
AD1 2 A1 I/O1 8 DPX17 AD1 2 A1 I/O1 8 DPY9
AD2 3 A2 I/O2 9 DPX2
AD2 3 A2 I/O2 9 DPX18 AD2 3 A2 I/O2 9 DPY10
AD3 4 A3 I/O3 10 DPX3
AD3 4 A3 I/O3 10 DPX19 AD3 4 A3 I/O3 10 DPY11
AD4 5 A4 I/O4 13 DPX4
AD4 5 A4 I/O4 13 DPX20 AD4 5 A4 I/O4 13 DPY12
AD5 18 A5 I/O5 14 DPX5
B AD6 19 A6 I/O6 15 DPX6
AD5 18 A5 I/O5 14 DPX21 AD5 18 A5 I/O5 14 DPY13
AD6 19 A6 I/O6 15 DPX22 AD6 19 A6 I/O6 15 DPY14
AD7 20 A7 I/O7 16 DPX7
AD7 20 A7 I/O7 16 DPX23 AD7 20 A7 I/O7 16 DPY15
AD8 21 A8 I/O8 29 DPX8
AD8 21 A8 I/O8 29 DPY0 AD8 21 A8 I/O8 29 DPY16
AD9 22 A9 I/O9 30 DPX9
AD9 22 A9 I/O9 30 DPY1 AD9 22 A9 I/O9 30 DPY17
ADP10 23 A10 I/O10 31 DPX10
ADP10 23 A10 I/O10 31 DPY2 ADP10 23 A10 I/O10 31 DPY18
ADP11 24 A11 I/O11 32 DPX11
ADP11 24 A11 I/O11 32 DPY3 ADP11 24 A11 I/O11 32 DPY19
ADP12 25 A12 I/O12 35 DPX12
ADP12 25 A12 I/O12 35 DPY4 ADP12 25 A12 I/O12 35 DPY20
ADP13 26 A13 I/O13 36 DPX13
ADP13 26 A13 I/O13 36 DPY5 ADP13 26 A13 I/O13 36 DPY21
ADP14 27 A14 I/O14 37 DPX14
ADP14 27 A14 I/O14 37 DPY6 ADP14 27 A14 I/O14 37 DPY22
ADP15 42 A15 I/O15 38 DPX15
ADP15 42 A15 I/O15 38 DPY7 ADP15 42 A15 I/O15 38 DPY23
ADP16 43 A16
ADP16 43 A16 ADP16 43 A16
ADP17 44 A17
ADP17 44 A17 ADP17 44 A17

A
837 0147 042 Rev.A
FORM:

MEMORIE CORRELATOR

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 10 16

 Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.
FORM:
837 0147 042 Rev.A The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

by EpD
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

SHEET

A2
B
C
F

A
E

D
1
2

47U
C31
CR1 R273
TL431AC
22

DSIN
DCOS

+6V

R274 R122
C71 2K0 2K0 C70
220N 220N
3

18K
18K

R165
R164

5
6
3
2

+
-

4
8

V-
V+
4
8

V-
V+

C56

33
100N C63 C55

7
U62
47P
1

R144
18K
U62
4

47P
18K

R166
R148

LMC662
LMC662

+5V

SMPIN
R268
2K2 TP19 TP18

1
U41
74ACT14
5

2
5
3
2
1
5
3
2
1

C317 C315
100N 100N
6

-IN
-IN

FFTCK

+IN
+IN

Vref
Vref

U56
U55

R269
CS/SHDN
CS/SHDN

2K2
ADS8320
ADS8320

DCLOCK
DCLOCK

DOUT
VCC
DOUT
VCC

GND
GND

4
6
7
8
4
6
7
8

U41
74ACT14

+5V
+5V

C318 C316
100N 100N
7
8

R281 R276
4K7 4K7
VCC
VCC

8
6
4
2

17
15
13
11
1
1
1
1

U46
U46
U46
U46
U46
U46
U46
U46

19
19
19
19

74LCX244
74LCX244
74LCX244
74LCX244
74LCX244
74LCX244
74LCX244
74LCX244

3
5
7
9
12
14
16
18
9

SININ
COSIN

1K

1K
R275

R277

Number:
Document
DESCRIPTION:
10

950 1217 000 SE

"7350" DOPPLER BOARD
Revision:
C
SHEET:
11

INGRESSO DOPPLER CW

11
OF:
16
 1 2 3 4 5 6 7 8 9 10 11

C39
1N2

1500P
C74
R131 R178
5K6 C44
R132 4K7 C68

TP16
100N
100N R176
33
E

+5V
33

+5V
R127 8
U48
R186 4
U66
U41
5K6
2
V+ LF353
-
1
1K
6
V+ TL064
74ACT14 -
VCC 3 7
+ REC
ACLKX0 5 6 V-
5
+ C60
V-
4 220N
+5V

R177
C294
11
R278

100N

4K7
2K2

R134

R133

1K00
R171
U66

12K

12K
4

R271
U41 U42 TL064

C296
V+
13

100N
-

10
74ACT14 14
AD1866 12
RECOUT
+
ADLL 9 8 1 VL VS 9 V-
4 CLK VS 15
11
R279

22K
R158
2K2

2 LL VBL 16
VOL 14
D
3 DL NRL 13
U41
74ACT14 6 8
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

LR VBR
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

11 10 10
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

ADX0 VOR
5 DR NRR 11
R272
2K2

7 12
DGND AGND C59

C49
1N2
C34 C33 1500P
U41 10U 10U
74ACT14

ADLR 13 12 R141 R157

5K6 4K7
R270
2K2

R135 8
U48
R149 4
U66
5K6 V+ LF353
C 6 - 1K V+ TL064
7 2 -
5 1 ADV
+
R143 V-
R140 3
+ C75
12K 33 V-
4 220N
TP17

-5V

R170
11
C48

4K7
R142
100N

1K00
R180
U66

12K
4

9
V+ TL064
-
8 ADVOUT
10
+
V- R179
11 33

22K
R187

-5V
C69
100N

A
837 0147 042 Rev.A
FORM:

USCITA AUDIO PER IL VTR

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 12 16

 1 2 3 4 5 6 7 8 9 10 11

C308
R287

100N
C307
33

+5V
1U
F ADV

R286
10K
U53
74HCT4052

C322
U57 16 VCC

100N
4
R125 TL064 U39

C37
220N
V+ 1 0
2

VCC
-
2K2 1 5 1 COM 3 74ACT14
ADVIN 3
+ 2 2 5 6

C57
10U
C35
V- VOL_CLK

47U
4 3 +5V

R129
11

R265
7

22K
VEE
R116

2K2

C28
100N
6

R136
INH U65
33

R138
10

1K
R173 A TPA0211

-5V
9
U39

33
B 3
10K
74ACT14 R175 VDD

C42
100N
8 R123

C32
GND

100N
9 8 1K8
E VOL_DIN 1 5
IN VO+ SPKR1
R185 4
U63 33

+5V
R266
10K
9
V+ TL064 2 SHTDWN VO- 8 SPKN1

2K2
LINEOUTADV -
8 U57
10 U44 4

C67
+
U39 4 BYPASS SE/BTL 6
LM1972 TL064

1U
V-
9 -
V+
C73
11 74ACT14 13 8
VDD1 7
10 470N GND
VOL_LDSH 11 10 9 CLOCK GND1 3 +
V-
VSS1 18
11

R264
11 DATA-IN

2K2
12 DATA-OUT VDD2 15
U39 19
GND2
74ACT14 10 7
LOAD/SHIFT VSS2
VTRAUDIO 1 2
4 IN1 OUT1 2
R262
2K2

20 IN2 OUT2 17

C323
100N
D 1 GND_AC GND_AC 16

VCC
5 GND_AC GND_AC 14
6 GND_AC GND_LOGIC 8
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

U57
The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

C58
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

R263

U39 4

C66

47U
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

TL064
2K2

1U
V+
74ACT14 6 -
7
PCAUDIO 3 4 5
+
V-
U64
11
TPA0211
R174 3 VDD

C43
100N
1K8
1 5
C313

IN VO+ SPKR2
R145
1U

R155 2 SHTDWN VO- 8 SPKN2

10K

R139
REC
33

33
+5V
4 6
R299

BYPASS SE/BTL
C64 C72
10K

U53 100N 7
470N GND
C
74HCT4052 -5V

4
U57 16 VCC R154 4
U63
R126 TL064 10K TL064
C38
220N

V+ 12 0
V+
13 -
2 -
2K2 14 14 1 COM 13 1 LINEINADV
RECIN 12
+ 15
3
+
U39
2
10U
C36

V- V- 74ACT14
11 3
R130

11 11 13 12
7 SPKOFF
22K

VEE
6 R156
R137

INH
10 10K
1K

A
9 B

R167 8 GND
10K

R168 4
U63
R172 U63
C312

4 R298 10K TL064

100N

V+
10K V+ TL064 13 -
B LINEOUTREC 6 - 33 14 LINEINREC
7 12
-5V

+
5 V-
+
V-
11
11

R169
33

-5V
C65
100N

A
837 0147 042 Rev.A
FORM:

USCITA AUDIO PER GLI ALTOPARLANTI E PC AUDIO IN/OUT

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 13 16

 1 2 3 4 5 6 7 8 9 10 11

F U59
74LCX138
LCA0 1 A Y0 15
LCA1 2 B Y1 14
LCA2 3 C Y2 13
Y3 12
Y4 11
LCRW 6 G1 Y5 10
4 G2A Y6 9
LSGR 5 G2B Y7 7

+3V3

U52
E 74LCX244

R283

R284

R288

R290

R293

R292
100

100

100

100

100

100
1 1G
2 2 2 2 2 2 19 2G
2 1A1 1Y1 18 LC0
4 1A2 1Y2 16 LC1
6 1A3 1Y3 14 LC2
8 1A4 1Y4 12 LC3
11 2A1 2Y1 9 LC4
13 2A2 2Y2 7 LC5
15 2A3 2Y3 5
17 2A4 2Y4 3

R280

R285

R289

R291

R295

R294
100

100

100

100

100

100
D U60
R300
1K00
74LCX244
1 1G
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

19
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

2G
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

LCA0 2 1A1 1Y1 18 LA0

LCA1 4 1A2 1Y2 16 LA1
LCA2 6 1A3 1Y3 14 LA2
LCA3 8 1A4 1Y4 12 LA3
LCA4 11 2A1 2Y1 9 LA4
LCRW 13 2A2 2Y2 7 LRW
15 2A3 2Y3 5
17 2A4 2Y4 3

C
U51
74LCX245
LSDOP 19 G
LCRW 1 T/R

LD0 2 A1 B1 18 LC0
LD1 3 A2 B2 17 LC1
LD2 4 A3 B3 16 LC2
LD3 5 A4 B4 15 LC3
LD4 6 A5 B5 14 LC4
LD5 7 A6 B6 13 LC5
LD6 8 A7 B7 12 LC6
LD7 9 A8 B8 11 LC7

B
U50
74LCX245
LSDOP 19 G
LCRW 1 T/R

LD8 2 A1 B1 18 LC8
LD9 3 A2 B2 17 LC9
LD10 4 A3 B3 16 LC10
LD11 5 A4 B4 15 LC11
LD12 6 A5 B5 14 LC12
LD13 7 A6 B6 13 LC13
LD14 8 A7 B7 12 LC14
LD15 9 A8 B8 11 LC15

A
837 0147 042 Rev.A
FORM:

CONFIGURAZIONE SCHEDA E BUS CPU

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 14 16

 1 2 3 4 5 6 7 8 9 10 11

+1V5 +1V8A +1V8B +1V8C

C247 C249 C245 C246 C219 C222 C217 C221 C263 C261 C254 C255 C234 C236 C227 C229 C149 C151 C145 C148 C129 C125 C153 C123 C239 C242 C213 C240 C210 C212 C206 C208
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
F

CORE VIRTEX2 CORE SPARTAN2 CORE SPARTAN2 CORE SPARTAN2

+1V5 +1V8A +1V8B +1V8C

C179 C197 C224 C284 C189 C257 C266 C182 C169 C164 C101 C94 C280 C271 C194 C174
470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N

CORE VIRTEX2 CORE SPARTAN2 CORE SPARTAN2 CORE SPARTAN2

E +3V3 +3V3 +3V3 +3V3

C175 C233 C171 C173 C165 C166 C157 C167 C262 C260 C272 C267 C273 C235 C250 C228 C241 C286 C243 C215 C282 C211 C200 C198 C209 C214 C154 C218 C150 C152 C147 C146
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

I/O VIRTEX2 I/O SPARTAN2 I/O SPARTAN2 I/O SPARTAN2

+3V3 +3V3 +3V3 +3V3

C264 C288 C237 C256 C251 C253 C248 C290 C230 C177 C196 C183 C185 C277 C291 C238 C220 C232 C223 C207 C204 C195 C187 C188 C124 C144 C122 C143 C278 C97 C95 C96
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
D

I/O VIRTEX2 I/O SPARTAN2 I/O SPARTAN2 I/O SPARTAN2

Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

+3V3 +3V3 +3V3 +3V3

C252 C181 C184 C98 C126 C172 C265 C287 C225 C244 C276 C289 C161 C156 C186 C205
470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N

I/O VIRTEX2 I/O SPARTAN2 I/O SPARTAN2 I/O SPARTAN2

+3V3AUX
C

C281 C226 C178 C176 C285 C216 C180 C283

47N 47N 47N 47N 47N 47N 47N 47N

AUX VIRTEX2

+1V26 +3V3_DSP

C102 C104 C134 C139 C130 C131 C127 C128 C114 C108 C111 C138 C105 C136 C137 C118 C132 C119 C121 C109
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

B
CORE DSP I/O DSP

+1V26 +3V3_DSP

C107 C106 C135 C133 C110 C103 C120 C117

470N 470N 470N 470N 470N 470N 470N 470N

CORE DSP I/O DSP

A
837 0147 042 Rev.A
FORM:

BYPASS FPGA E DSP

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 15 16

 1 2 3 4 5 6 7 8 9 10 11

COMPONENTI NON MONTATI: ALIMENTAZIONI IMPLICITE

---------------------------- ----------------------- ALIMENTAZIONI MODIFICATE
C162 EQUIP_LEVEL 2 ------------------------
C17 EQUIP_LEVEL 2 NET: +1V26
C231 EQUIP_LEVEL 2 ---------- NET: +3V3_DSP
C279 EQUIP_LEVEL 2 U14.W19 U14.K1 -------------
C292 EQUIP_LEVEL 2 U14.W2 U14.F17 U14.Y17
R204 EQUIP_LEVEL 2 U14.V18 U14.F4 U14.Y7
R217 EQUIP_LEVEL 2 U14.V3 U14.D15 U14.W12
R223 EQUIP_LEVEL 2 U14.U15 U14.D14 U14.W9
F R228 EQUIP_LEVEL 2 U14.U14 U14.D11 U14.W3
R238 EQUIP_LEVEL 2 U14.U11 U14.D6 U14.V19
R241 EQUIP_LEVEL 2 U14.U10 U14.D5 U14.V15
R249 EQUIP_LEVEL 2 U14.U6 U14.C18 U14.V13
R253 EQUIP_LEVEL 2 U14.R17 U14.C7 U14.U16
R254 EQUIP_LEVEL 2 U14.R4 U14.C3 U14.U12
R261 EQUIP_LEVEL 2 U14.L20 U14.B19 U14.U7
+3V3 R283 EQUIP_LEVEL 2 U14.L17 U14.B2 U14.U5
R284 EQUIP_LEVEL 2 U14.L4 U14.A10 U14.T3
R288 EQUIP_LEVEL 2 U14.K17 U14.A9 U14.R18
R290 EQUIP_LEVEL 2 U14.K4 U14.A4 U14.R1
R292 EQUIP_LEVEL 2 U14.M18
C113 C140 C115 C78 C155 C93 C201 C193 C190 C76 R293 EQUIP_LEVEL 2 NET: +1V5 U14.J2
R57 EQUIP_LEVEL 2 --------- U14.H18
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N R58 EQUIP_LEVEL 2 U33.U17 U33.H16 U14.F3
R60 EQUIP_LEVEL 2 U33.U6 U33.H7 U14.D19
R63 EQUIP_LEVEL 2 U33.T16 U33.G16 U14.D16
R77 EQUIP_LEVEL 2 U33.T15 U33.G15 U14.D1
R81 EQUIP_LEVEL 2 U33.T8 U33.G8 U14.C10
R82 EQUIP_LEVEL 2 U33.T7 U33.G7 U14.B13
R99 EQUIP_LEVEL 2 U33.R16 U33.F17 U14.B8
R98 EQUIP_LEVEL 2 U33.R7 U33.F6 U14.B3
U14.A17
+3V3 NET: +3V3
--------- NET: +1V8A
U7.20 U49.20 U47.11 U37.11 ----------
E U6.20 U35.33 U9.33 U31.33 U34.V18
U5.20 U35.11 U9.11 U31.11 U34.V5
C202 C270 C293 C85 C269 C297 C141 C99 C90 C83 U3.20 U40.33 U13.33 U1.33 U34.U17
U46.20 U40.11 U13.11 U1.11 U34.U6
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N U52.20 U38.33 U12.33 U11.33 U34.T16
U21.20 U38.11 U12.11 U11.11 U34.T15
U22.20 U29.33 U8.33 U61.20 U34.T8
UP4.32 U29.11 U8.11 U51.20 U34.T7
UP5.32 U27.33 U58.33 U50.20 U34.R16
U15.33 U27.11 U58.11 U60.20 U34.R7
U15.11 U23.33 U30.33 U34.H16
U25.33 U23.11 U30.11 U34.H7
U25.11 U16.33 U36.33 U34.G16
+3V3 UP1.37 U16.11 U36.11 U34.G15
U59.16 U47.33 U37.33 U34.G8
U34.G7
NET: VCC U34.F17
-------- U34.F6
C295 C54 C160 C259 C77 C258 C100 C112 C168 C92 U4.20 U34.E18
U2.20 U34.E5
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N UP3.32
U41.14 NET: +3V3AUX
U39.14 ------------
UP2.44 U33.AB11
U33.AA22
U33.AA1
D NET: GND
U33.M22
--------
U33.L1
U7.10 U14.B15 U34.M10 U33.C3 U20.N11
U33.B22
+3V3 U6.10 U14.B4 U34.M9 U33.B21 U20.N10
U33.B1
U5.10 U14.B1 U34.M7 U33.B2 U20.N9
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

U33.A12
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

U4.10 U14.A20 U34.L16 U33.A22 U20.M16

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

U2.10 U14.A19 U34.L14 U33.A1 U20.M14

NET: +1V8C
UP3.16 U14.A14 U34.L13 U32.AB22 U20.M13
----------
U41.7 U14.A11 U34.L12 U32.AB1 U20.M12
C142 C91 C300 C89 C88 C298 C275 C87 C274 C203 U32.V18
U3.10 U14.A2 U34.L11 U32.AA21 U20.M11
U32.V5
U46.10 U14.A1 U34.L10 U32.AA2 U20.M10
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N U32.U17
U52.10 UP1.46 U34.L9 U32.Y20 U20.M9
U32.U6
U21.10 UP1.27 U34.L7 U32.Y3 U20.M7
U32.T16
U22.10 U59.8 U34.K14 U32.T12 U20.L16
U32.T15
UP4.16 U49.10 U34.K13 U32.T11 U20.L14
U32.T8
UP5.16 U35.34 U34.K12 U32.P14 U20.L13
U32.T7
U15.34 U35.12 U34.K11 U32.P13 U20.L12
U32.R16
U15.12 U40.34 U34.K10 U32.P12 U20.L11
U32.R7
U25.34 U40.12 U34.K9 U32.P11 U20.L10
U32.H16
+3V3 U25.12 U38.34 U34.J14 U32.P10 U20.L9
U32.H7
U14.Y20 U38.12 U34.J13 U32.P9 U20.L7
U32.G16
U14.Y19 U29.34 U34.J12 U32.N14 U20.K14
U32.G15
U14.Y13 U29.12 U34.J11 U32.N13 U20.K13
U32.G8
U14.Y2 U27.34 U34.J10 U32.N12 U20.K12
U32.G7
U14.Y1 U27.12 U34.J9 U32.N11 U20.K11
C199 C305 C268 C304 C192 C303 C309 C159 C301 C158 U32.F17
U14.W20 U23.34 U34.G12 U32.N10 U20.K10
U32.F6
C U14.W16 U23.12 U34.G11 U32.N9 U20.K9
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N U32.E18
U14.W11 U16.34 U34.C20 U32.M16 U20.J14
U32.E5
U14.W5 U16.12 U34.C3 U32.M14 U20.J13
U14.W1 U47.34 U34.B21 U32.M13 U20.J12
NET: +1V8B
U14.U20 U47.12 U34.B2 U32.M12 U20.J11
----------
U14.U17 U9.34 U34.A22 U32.M11 U20.J10
U20.V18
U14.U13 U9.12 U34.A1 U32.M10 U20.J9
U20.V5
U14.U9 U13.34 U33.AB22 U32.M9 U20.G12
U20.U17
U14.U8 U13.12 U33.AB1 U32.M7 U20.G11
U20.U6
+3V3 U14.U4 U12.34 U33.AA21 U32.L16 U20.C20
U20.T16
U14.T17 U12.12 U33.AA2 U32.L14 U20.C3
U20.T15
U14.T4 U8.34 U33.Y20 U32.L13 U20.B21
U20.T8
U14.P19 U8.12 U33.Y3 U32.L12 U20.B2
U20.T7
U14.P17 U58.34 U33.W19 U32.L11 U20.A22
U20.R16
U14.P4 U58.12 U33.W4 U32.L10 U20.A1
C306 C314 C170 C321 C320 C163 C191 C116 C319 U20.R7
U14.N17 U30.34 U33.P14 U32.L9 U51.10
U20.H16
U14.N4 U30.12 U33.P13 U32.L7 U50.10
47N 47N 47N 47N 47N 47N 47N 47N 47N U20.H7
U14.M17 U36.34 U33.P12 U32.K14 U60.10
U20.G16
U14.M12 U36.12 U33.P11 U32.K13 UP2.34
U20.G15
U14.M11 U37.34 U33.P10 U32.K12 UP2.12
U20.G8
U14.M10 U37.12 U33.P9 U32.K11
U20.G7
U14.M9 U31.34 U33.N14 U32.K10
U20.F17
U14.M4 U31.12 U33.N13 U32.K9
U20.F6
U14.L12 U1.34 U33.N12 U32.J14
U20.E18
U14.L11 U1.12 U33.N11 U32.J13
VCC U20.E5
U14.L10 U11.34 U33.N10 U32.J12
B U14.L9 U11.12 U33.N9 U32.J11
U14.K20 U61.10 U33.M14 U32.J10
U14.K12 U39.7 U33.M13 U32.J9
U14.K11 U34.AB22 U33.M12 U32.G12
C84 C86 C79 C80 C81 U14.K10 U34.AB1 U33.M11 U32.G11
U14.K9 U34.AA21 U33.M10 U32.C20
47N 47N 47N 47N 47N U14.K2 U34.AA2 U33.M9 U32.C3
U14.J12 U34.Y20 U33.L14 U32.B21
U14.J11 U34.Y3 U33.L13 U32.B2
U14.J10 U34.T12 U33.L12 U32.A22
U14.J9 U34.T11 U33.L11 U32.A1
U14.J4 U34.P14 U33.L10 U20.AB22
U14.H17 U34.P13 U33.L9 U20.AB1
U14.H4 U34.P12 U33.K14 U20.AA21
U14.G17 U34.P11 U33.K13 U20.AA2
U14.G4 U34.P10 U33.K12 U20.Y20
U14.F19 U34.P9 U33.K11 U20.Y3
U14.E17 U34.N14 U33.K10 U20.T12
U14.E4 U34.N13 U33.K9 U20.T11
U14.E2 U34.N12 U33.J14 U20.P14
U14.D17 U34.N11 U33.J13 U20.P13
U14.D13 U34.N10 U33.J12 U20.P12
U14.D8 U34.N9 U33.J11 U20.P11
U14.D4 U34.M16 U33.J10 U20.P10
U14.C9 U34.M14 U33.J9 U20.P9
U14.C8 U34.M13 U33.D19 U20.N14
A U14.C6 U34.M12 U33.D4 U20.N13
U14.B20 U34.M11 U33.C20 U20.N12
837 0147 042 Rev.A
FORM:

BYPASS COMPONENTI DIGITALI

SHEET DESCRIPTION:
"7350" DOPPLER BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1217 000 SE C 16 16

 1 2 3 4 5 6 7 8 9 10 11

VCC P1 P2 P3 22K P4
L2

+3V3
R200
15U A1 B1 A1 B1 R138 A1 B1
A1 B1 R201
22
C256 A2 B2
A2 B2 A2 B2 DSP_SAFE PCI_INTB R202 A2 B2
A3 B3 A3 B3 22 A3 B3
47U A3 B3 VMA6 VMA7 AUXIN_0 EXTDEV PCI_INTA
A4 B4 A4 B4 22 A4 B4
F A4 B4 VMA8 VMA9 +3V3 REMOTE KB_CLK PCI_INTC
VMA10 A5 B5 VMA11 FSWITCH A5 B5 KB_DAT PCI_RST R203 A5 B5
A5 B5
A6 B6 Y2 A6 B6 A6 B6
A6 B6 VMA12 VMA13 4 AUXIN_1 MS_CLK R196 R189
A7 B7 40MHZ A7 B7 22 A7 B7
A7 B7 VMA14 VMA15 EXTECG MS_DAT PCI_AD31 R197 R190
A8 B8 A8 B8 22 A8 B8 22
A8 B8 VMA16 VMA17 VCC PCI_AD29 R198 R191 PCI_AD30
+12V +12V A9 B9 1 3 A9 B9 22 A9 B9 22
A9 B9 VMA18 VMA19 OE OSC PC_RESET USB_OVCR PCI_AD28 R199 PCI_AD27
A10 B10 A10 B10 22 A10 B10 22
A10 B10 VMA20 VMA21
GND
PCI_AD25 R192 PCI_AD26
A11 B11 A11 B11 22 A11 B11
A11 B11 VMA22 VMA23 PCI_CBE3 R193 R188
A12 B12 A12 B12 22 A12 B12
A12 B12 VMA24 VMA25 PCI_AD24 R194 R170

B
2
A13 B13 A13 B13 22 A13 B13 22
A13 B13 VMA26 VMA27 PCI_AD21 R195 R171 PCI_AD23

A
A14 B14 A14 B14 22 A14 B14 22
A14 B14 VMA28 VMA29 TXD1 CPU_TXD PCI_AD20 R185 R172 PCI_AD22
A15 B15 W54 A15 B15 22 A15 B15 22
A15 B15 DTR1 CPU_DTR PCI_AD19 PCI_AD18
A16 B16 A16 B16 22 A16 B16 22
A16 B16 RTS1 CPU_RTS PCI_AD16 R186 PCI_AD17
A17 B17 RXD1 A17 B17 CPU_RXD R187 A17 B17
A17 B17 +3V3
A18 B18 A18 B18 22 A18 B18
A18 B18 VMD0 VMD1 CTS1 CPU_CTS PCI_CBE2 R182
A19 B19 A19 B19 22 A19 B19
A19 B19 VMD2 VMD3 DSR1 CPU_DSR PCI_FRAME R183
A20 B20 A20 B20 22 A20 B20
A20 B20 VMD4 VMD5 R132 5 DCD1 CPU_DCD PCI_STOP R184
A21 B21 4 2 A21 B21 22 A21 B21
E BUZZER A21 B21 PANPOS
VMD6 VMD7 D40M VCC CPU_RI PCI_IRDY R179
A22 B22 A22 B22 22 A22 B22
TRKXA A22 B22 TRKXB
VMD8 VMD9 33 PCI_TRDY R180
A23 B23 U98 A23 B23 22 A23 B23
TRKYA A23 B23 TRKYB
VMD10 VMD11
74LVC1GU04
VID_HSYNC VID_VBLANK PCI_DEVSEL R181
A24 B24 A24 B24 22 A24 B24
ENCRA A24 B24 ENCRB
VMD12 VMD13 PCI_PME R176
A25 B25 A25 B25 22 A25 B25
ENCLA A25 B25 ENCLB
VMD14 VMD15 TBASE PCI_PERR R177
A26 B26 A26 B26 22 A26 B26
ROW0 A26 B26 ROW1
ECG MOT0 PCI_SERR R178
A27 B27 A27 B27 22 A27 B27
A27 B27 POS MOT1 PCI_PAR
ROW2 ROW3 22
A28 B28 A28 B28 TIMING PCI_CBE1 R175 A28 B28 R173
ROW4 A28 B28 ROW5

+VT

+VT
A29 B29 ESCAN A29 B29 PROBE R174 A29 B29 R167
ROW6 A29 B29 ROW7
A30 B30 A30 B30 22 A30 B30 22
ROW8 A30 B30 ROW9
PCI_AD15 R164 R168 PCI_AD14
A31 B31 A31 B31 22 A31 B31 22
ROW10 A31 B31 ROW11
PCI_AD13 R163 R169 PCI_AD12
A32 B32 A32 B32 22 A32 B32 22
ROW12 A32 B32 ROW13
GRA0 GRA1 PCI_AD11 R162 PCI_AD10
A33 B33 A33 B33 22 A33 B33 22

-6V

-6V
ROW14 A33 B33 ROW15
GRA2 GRA3 PCI_AD9 R161 PCI_AD8
A34 B34 A34 B34 22 A34 B34
COL0 A34 B34 COL1
GRA4 GRA5 PCI_AD7 R160 R166
A35 B35 A35 B35 22 A35 B35
COL2 A35 B35 COL3
GRA6 GRA7 PCI_CBE0 R159 R165
A36 B36 A36 B36 22 A36 B36 22
COL4 A36 B36 COL5
GRA8 GRA9 PCI_AD5 R158 R153 PCI_AD6
22 22
+6V

A37 B37

+6V
GRA10 A37 B37 GRA11 PCI_AD3 R154 A37 B37 PCI_AD4
COL6 A37 B37 COL7
A38 B38 +3V3 A38 B38 22 A38 B38 22
COL8 A38 B38 COL9 L3 GRA12 GRA13 PCI_AD2 PCI_AD1
D A39 B39 A39 B39 22 A39 B39
COL10 A39 B39 COL11 22U GRA14 GRA15 PCI_AD0 R155
A40 B40 A40 B40 A40 B40
COL12 A40 B40 COL13
A41 B41 A41 B41 22 A41 B41
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

R156
The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

A41 B41 PCI_REQ0

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

COL14 COL15 C245

A42 B42 A42 B42 A42 B42
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

A42 B42 PCI_GNT0

47U 22
LSECG A43 B43 VMAUX0 A43 B43 PCI_REQ1 R157 A43 B43
A43 B43
LSVID A44 B44 VMAS A44 B44 VMDS PCI_GNT1 A44 B44
A44 B44
A45 B45 A45 B45 22 A45 B45
A45 B45 LSPS LSSCAN VMBH VMBL PCI_REQ2
LSDOP A46 B46 LSGR A46 B46 PCI_GNT2 A46 B46
A46 B46
LSGW A47 B47 LSCNT VMRW A47 B47 VMACK A47 B47
A47 B47
LCA0 A48 B48 LCA1 VMMODE A48 B48 TCLK A48 B48
A48 B48
A49 B49 A49 B49 A49 B49
A49 B49

A50 B50 A50 B50 A50 B50

A50 B50
LCA2 A51 B51 LCA3 VMA0 A51 B51 VMA1 PCI_CLK1 A51 B51
A51 B51
LCA4 A52 B52 LCRW VMA2 A52 B52 VMA3 PCI_CLKO A52 B52
A52 B52
LC0 A53 B53 LC1 VMA4 A53 B53 VMA5 PCI_CLK2 A53 B53
A53 B53
C A54 B54 LC2 A54 B54 LC3 A54 B54 A54 B54
LC4 A55 B55 LC5 A55 B55 A55 B55
A55 B55
LC6 A56 B56 LC7 A56 B56 A56 B56
A56 B56
LC8 A57 B57 LC9 A57 B57 A57 B57
A57 B57
A58 B58 A58 B58 +2V2 A58 B58
A58 B58 LC10 LC11 L4 MM_SO MM_CS
LC12 A59 B59 LC13 A59 B59 MM_HOLD A59 B59 MM_WP
A59 B59 15U
LC14 A60 B60 LC15 A60 B60 MM_SI A60 B60 MM_SCK
A60 B60

C247
47U

+3V3
+3V3 +3V3 +3V3
3
4
2
1

7
5
6
8

8
7
5
6

3
4
2
1
B
U80 U79 U78 U77
10K 10K 10K 10K

U86 U85 U84 U83

6
5
7
8

2
4
3
1

1
2
4
3

6
5
7
8
100 100 100 100
COL0 8 1 ICOL0 COL4 8 1 ICOL4 COL8 8 1 ICOL8 COL12 8 1 ICOL12
COL1 7 2 ICOL1 COL5 7 2 ICOL5 COL9 7 2 ICOL9 COL13 7 2 ICOL13
COL2 6 3 ICOL2 COL6 6 3 ICOL6 COL10 6 3 ICOL10 COL14 6 3 ICOL14

+3V3
COL3 5 4 ICOL3 COL7 5 4 ICOL7 COL11 5 4 ICOL11 COL15 5 4 ICOL15

5
6
7
8
C236 C237 C238 C240 C232 C233 C234 C235 C228 C229 C230 C231 C224 C225 C226 C227
U17
1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 4K7 C46 C61 C60 C45
10N 10N 10N 10N
U95 U94 U93 U92
100 100 100 100

4
3
2
1
IROW0 1 8 ROW0 IROW4 1 8 ROW4 IROW8 1 8 ROW8 IROW12 1 8 ROW12 ENCLA IENCLA
4 5
2 7 2 7 2 7 2 7
A IROW1 ROW1 IROW5 ROW5 IROW9 ROW9 IROW13 ROW13 ENCLB 3 6 IENCLB
IROW2 3 6 ROW2 IROW6 3 6 ROW6 IROW10 3 6 ROW10 IROW14 3 6 ROW14 ENCRA IENCRA
837 0147 042 Rev.A

2 7
IROW3 4 5 ROW3 IROW7 4 5 ROW7 IROW11 4 5 ROW11 IROW15 4 5 ROW15 ENCRB IENCRB
1 8
FORM:

C281 C282 C283 C284 C277 C278 C279 C280 C273 C274 C275 C276 C269 C270 C271 C272 10K
U25
1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

"7350" PROCESSORS BOARD
A2 ANDREUCCETTI DONNINI ANDREUCCETTI 20/12/04
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1218 000 SE C 1 10
DOCUMENTO FIRMATO ELETTRONICAMENTE - DOCUMENT ELECTRONICALLY SIGNED
 Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.
FORM:
837 0147 042 Rev.A The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

by EpD
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

SHEET

A2
B
C
F

A
E

D
1
2
3
4

PCI_RST

PCI_CLK2
PCI_CLK1

PCI_GNT2
PCI_GNT1
PCI_GNT0
PCI_CLKO
5

+3V3

560
560

R145
R152

560
560

R143
R150

560
560

R144
R151
6

560
560

R142
R149

560
560

R140
R147

560
560

R141
R148

560
560

R139
R146
7

47N
C328
8
9

Number:
Document
DESCRIPTION:
10

950 1218 000 SE

Revision:
"7350" PROCESSORS BOARD
C
SHEET:
11

2
OF:
10
 1 2 3 4 5 6 7 8 9 10 11

U61 U61 U61 U61

XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4

BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

BANK 0 BANK 1

F C21 M21 AB19 AA11 V5 L2

PCI_IRDY
VMA25 B4 IO IO/GCLK3P F12 CPU_CLKOUT
DBG_SA9 IO IO CPU_D9 EA14 IO/DOUT IO/GCLK7S DTRA VMAS IO IO R94 PCI_FRAME
A4 F13 DBG_SA7 C22 IO IO M20 CPU_D15 FPGA_INIT AA19 IO/INIT_B IO/GCLK6P Y11 TB44 VMDS U5 IO IO L3
33
VMA26 IO IO/GCLK2S EA2
E18 M19 ED0 V18 W11 Y2 L4
C4 E12 EA12 IO/VRP2 IO CPU_D10 IO/D0 IO/GCLK5S DSRA EA19 IO/VRN6 IO PCI_AD21
VMA27 IO IO/GCLK1P AWE
F18 M18 ED1 V17 V11 Y1 L5
C5 D12 DBG_SD4 IO/VRN2 IO CPU_D5 IO/D1 IO/GCLK4P MNYIRQ EA20 IO/VRP6 IO PCI_PAR
VMA28 IO IO/GCLK0S EA3 ED[0:31]
D21 M17 ED2 W18 U11 V4 K1
B5 C12 DBG_SA6 IO IO/VREF3 CPU_D4 IO/D2/ALT_VRP4 IO DCDA VMBH IO IO/VREF7 PCI_GNT2
VMA29 IO/VRP0 IO LCRW
D22 N17 ED3 Y18 U10 V3 K2
A5 B12 DBG_SA5 IO/VREF2 IO CPU_D12 IO/D3/ALT_VRN4 IO/VREF5 RIA VMBL IO/VREF6 IO PCI_REQ2
VMD0 IO/VRN0 IO/VREF1 LC0
DBG_SA8 E19 IO IO N22 CPU_D8 EA15 AA18 IO/VREF4 IO AB10 DSP_EINT4 VMA0 W2 IO IO K3 PCI_CBE2
VMD1 D6 IO/VREF0 IO A13 LC1
C6 B13 TB53 E20 IO IO N21 CPU_A1 LINK0 AB18 IO IO AA10 DSP_EINT5 VMA1 W1 IO IO K4 PCI_CBE3
VMD2 IO IO LC2
E21 N20 W17 Y10 U4 L6 PCI_AD16
B6 C13 DBG_SA4 IO IO CPU_D14 LINK1 IO/VRP4 IO ARDY VMA2 IO IO
VMD3 IO IO LC3
E22 N19 Y17 W10 U3 K6 PCI_AD17
A6 D13 DBG_SA3 IO IO CPU_D2 LINK2 IO/VRN4 IO ED27 VMA3 IO IO
VMD4 IO IO LC4
F19 N18 AA17 V10 V2 K5 PCI_AD18
E7 E13 DBG_SD1 IO IO CPU_D11 LINK3 IO IO ED8 VMA4 IO IO
VMD5 IO IO LC5
F20 P18 AB17 V9 V1 J5 PCI_AD19
E8 E14 DBG_SD8 IO IO CPU_D6 CPU_RW IO IO/VREF5 ED9 VMA5 IO IO
VMD6 IO IO/VREF1 LC6
F21 P22 V16 AB9 U2 J1 PCI_AD20
D7 A14 DBG_SA2 IO IO/VREF3 CPU_A2 CPU_SIZ0 IO IO ED10 VMA6 IO IO/VREF7
VMD7 IO IO LC7
F22 P21 V15 AA9 U1 J2 PCI_AD21
C7 B14 DBG_SA1 IO/VREF2 IO CPU_A19 DCDB IO IO ED11 VMA7 IO/VREF6 IO
VMD8 IO/VREF0 IO LC8
B7 C14 TB54 G18 IO IO P20 CPU_D13 CPU_FC0 W16 IO IO Y9 ED12 VMA8 T5 IO IO J3 PCI_AD22
VMD9 IO IO LC9

PCI_AD[0:31]
H18 P19 Y16 W9 R5 J4 PCI_AD23
A7 D14 DBG_SD3 IO IO CPU_A17 CPU_FC1 IO/VREF4 IO ED13 VMA9 IO IO
VMD10 IO IO LC10
G19 R22 AA16 AB8 T4 H1 PCI_AD24
D8 A15 DBG_SD9 IO IO CPU_A18 CPU_FC2 IO IO/VREF5 ED21 VMA10 IO IO
E VMD11 IO IO/VREF1 LC11
G20 R21 AB16 AA8 T3 H2 PCI_AD25
C8 B15 DBG_SD10 IO IO CPU_A3 CPU_FC3 IO IO ED24 VMA11 IO IO
VMD12 IO IO LC12
G21 R20 W15 Y8 PCI_AD0 T2 H3 PCI_AD26
B8 C15 DBG_SA0 IO IO CPU_A15 CPU_DSACK0 IO IO ED16 IO IO
VMD13 IO IO LC13
G22 R19 Y15 W8 PCI_AD1 T1 H4 PCI_AD27
A8 D15 DBG_LA23 IO IO CPU_A16 CPU_DSACK1 IO IO ED31 IO IO
VMD14 IO IO LC14
H19 R18 AA15 U9 PCI_AD2 R4 J6 PCI_AD28
E9 F14 DBG_SD11 IO IO/VREF3 CPU_D7 LINK4 IO IO ED14 IO IO/VREF7
VMD15 IO IO LC15
H20 P17 AB15 V8 PCI_AD3 R3 H5 PCI_AD29
F9 E15 DBG_SD12 IO/VREF2 IO CPU_D1 LINK5 IO IO ED15 IO/VREF6 IO
LSGR IO/VREF0 IO EA4
H21 T22 U14 AB7 PCI_AD4 R2 G1 PCI_AD30
D9 A16 DBG_LA22 IO IO CPU_A4 DTRB IO IO ED20 IO IO
LSGW IO IO EA5
H22 T21 V14 AA7 PCI_AD5 R1 G2 PCI_AD31
C9 B16 DBG_LA21 IO IO CPU_A5 DSRB IO/VREF4 IO ED23 IO IO
LSCNT IO IO EA6
J17 T20 W14 Y7 PCI_AD6 P6 G3
B9 C16 DBG_SD6 IO IO CPU_D3 LINK6 IO IO/VREF5 ED17 IO IO PCI_RST
LSDOP IO IO/VREF1 EA7
J18 T19 Y14 W7 PCI_AD7 P5 G4

PCI_AD[0:31]
A9 D16 DBG_SD5 IO IO CPU_A6 LINK7 IO IO ED30 IO IO VMACK
LSSCAN IO IO EA8
J19 U22 AA14 AB6 PCI_AD8 P4 F1
E10 E16 DBG_SD13 IO IO CPU_D0 ARE IO IO ED22 IO IO VMMODE
LSPS IO/VREF0 IO EA9
J20 U21 AB14 AA6 PCI_AD9 P3 F2
F10 E17 DBG_LA18 IO IO CPU_A12 AOE IO IO ED28 IO IO VMA12
LSECG IO IO EA10
J21 U20 U13 Y6 PCI_AD10 P2 F3
D10 A17 DBG_LA20 IO IO/VREF3 CPU_A13 AUXIN_0 IO/VREF4 IO ED18 IO IO/VREF7 VMA13
LSVID IO IO EA11
J22 U19 V13 W6 PCI_AD11 P1 F4
C10 B17 DBG_LA19 IO/VREF2 IO CPU_A8 AUXIN_1 IO IO EA18 IO/VREF6 IO VMA14
LCA0 IO IO DBG_SA16
K17 T18 W13 V7 PCI_AD12 N6 G5
B10 C17 DBG_SD7 IO IO CPU_A14 BE0 IO IO/VRP5 ED29 IO IO VMA15
LCA1 IO IO DBG_SD0
K18 U18 Y13 V6 PCI_AD13 N5 F5
A10 D17 DBG_SD14 IO IO CPU_A20 BE1 IO IO/VRN5 ED19 IO IO VMA16
LCA2 IO IO/VREF1 DBG_SD2
K19 V22 AA13 AB5 PCI_AD14 N4 E1
E11 A18 DBG_MEMR IO IO CPU_A7 BE2 IO IO ED26 IO IO VMA17
LCA3 IO/VREF0 IO/VRP1 DBG_SA15
K20 V21 AB13 AA5 PCI_AD15 N3 E2
F11 B18 DBG_MEMW IO IO CPU_A9 BE3 IO IO/VREF5 ED25 IO IO VMA18
LCA4 IO IO/VRN1 DBG_SA14
D K21 V20 U12 Y5 PCI_CBE0 N2 E3
D11 C18 DBG_IOR IO IO CPU_A11 REMOTE IO/VREF4 IO/D4/ALT_VRP5 ED4 IO IO VMA19
PCI_CLK2 IO/GCLK7P IO DBG_SA12
K22 V19 V12 W5 PCI_CBE1 N1 E4
C11 D18 DBG_IOW IO IO CPU_A22 EA16 IO IO/D5/ALT_VRN5 ED5 IO IO VMA20
TB39 IO/GCLK6S IO DBG_SA10
L17 W22 W12 AB4 M6 D1
B11 A19 DBG_SBHE IO IO/VREF3 CPU_A21 EA17 IO/GCLK3S IO/D6 ED6 IO IO/VREF7 VMA21
TCLK IO/GCLK5P IO DBG_SA13
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

L18 W21 Y12 AA4 PCI_SERR M5 D2

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

USB_OVCR A11 IO/GCLK4S IO B19

TB52 TB51 IO/VREF2 IO CPU_A0 DSPIOCLK IO/GCLK2P IO/D7 ED7 IO/VREF6 IO VMA22
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

L19 Y22 AA12 Y4 PCI_PERR M4 C1

DBG_SD15 IO IO/VRP3 CPU_A23 VMAUX0 IO/GLCK1S IO/RDWR_B FPGA_WR IO IO/VRN7 EA21
L20 Y21 AB12 AA3 PCI_STOP M3 C2
EA13 IO IO/VRN3 CPU_A10 MNY_CLK IO/GCLK0P IO/CS_B MANNYCS IO IO/VRP7 VMRW
L21 W20 PCI_DEVSEL M2 E5
TB49 IO IO CPU_AS IO IO VMA23
L22 AA20 PCI_TRDY M1 E6
TB50 IO IO CPU_DS IO IO VMA24
+3V3

+3V3

+3V3

+3V3

+3V3

+3V3
L16 T17 U16 U8 T6 L7
+3V3

+3V3

G11 G14 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7

VCCOBank0 VCCOBank1
K16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 K7
G10 VCCOBank0 VCCOBank1 G13
J16 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T11 P7 VCCOBank6 VCCOBank7 J7
G9 VCCOBank0 VCCOBank1 G12
H17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T10 N7 VCCOBank6 VCCOBank7 H6
F8 VCCOBank0 VCCOBank1 F16
G17 VCCOBank2 VCCOBank3 M16 T12 VCCOBank4 VCCOBank5 T9 M7 VCCOBank6 VCCOBank7 G6
F7 VCCOBank0 VCCOBank1 F15

U101 U99
100 100
MOT0 8 1 IMOT0 ECG 4 5 IECG
C
MOT1 7 2 IMOT1 POS 3 6 IPOS A B

6 3 2 7 PCI_INTC
TIMING ITIMING TBASE ITBASE
PROBE 5 4 IPROBE ESCAN 1 8 IESCAN W49 A B

C265 C266 C267 C268 C261 C262 C263 C264 PCI_INTB

W48
100P 100P 100P 100P 100P 100P 100P 100P
PCI_INTA

+3V3
R65 +3V3
10K +3V3 UP7
CY2071A
U54 U54 7
10 4 VDD

1
3
4
2
74LCX74 74LCX74
B XTALOUT 4
12 S 9 2 S 5 3
R69
D Q D Q XTALIN
CPU_CLK U62
11 CK 3 CK 33 10K
Q 8 Q 6 8 OE CLKA 1 R46
R R
R67 CLKB 5 DSP_CLK U61

8
6
5
7
2 6 33
10K 13 1 GND CLKC XC2V1000-4 P5
R68 Y19 C19 1 2
+3V3
AWE CCLK TCK
XDSP_CLK +3V3
FPGA_PROG A2 PROG_B TDI D3 3 4
33
MONTARE GIA` PROGRAMMATA FPGA_DONE AB20 DONE TDO D20 5 6 C184
R104 AB2 B20 7 8
47N
U67 M0 TMS
+3V3 33 R113 W3 D5 9 10
M1 DXN
CY2305 R106 10K AB3 A3
33 M2 DXP
6 VDD CLKout 8
B3 HSWAP_EN VBATT A21
3 MNY_CLK
CLK1 AB21 A20
PWRDWN_B RSVD
D40M 1 REF CLK2 2
5
R100 A B A B A B
C201 CLK3 33
47N 4 7
GND CLK4
SID_CLK
A W47 W50 W46
837 0147 042 Rev.A
FORM:

SHEET DESCRIPTION:
"7350" PROCESSORS BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1218 000 SE C 3 10

 1 2 3 4 5 6 7 8 9 10 11

+3V3 +3V3
U55 R70
+3V3 FL2 CY2305 33
300MA SDCLK_0
6 VDD CLKout 8
R71

+3V3
CLK1 3
33
F U42 U37 1 REF CLK2 2 SDCLK_1
C114
MT48LCM16A2 MT48LCM16A2 10U 100N +3V3 C142 CLK3 5 R47 +3V3
1 VDD VDDQ 3
1 VDD VDDQ 3 C115 47N 4 GND CLK4 7 33
14 9 TB38 DSPIOCLK
VDD VDDQ 14 9
VDD VDDQ
27 VDD VDDQ 43
27 VDD VDDQ 43 R50 R40
VDDQ 49
49 U47 W3
22K R39
38
VDDQ C97 22K
22K
SDCLK_0 CLK
SDCLK_1 38 CLK TMS320C6205 TCK_RET P10
J3 E17 TMS 1 2
TB33 DSP_CLK CLKIN TMS
37 CKE TB30 37 CKE
27N T19 CLKOUT2 TDO D19 TDO 3 4
2 ED0
DQ0
DQ0 2 ED16 R38 C111 L3 CLKMODE0 TDI D18 TDI 5 6 R57
EA2 23 4 ED1 4.7 560P
A0 DQ1 EA2 23 4 ED17 K5 D17 TCK 7 8 22K
A0 DQ1 PLLV TCK
EA3 24 5 ED2
A1 DQ2 EA3 24 5 ED18 L2 C19 TRST 9 10
A1 DQ2 PLLG TRST
EA4 25 7 ED3
A2 DQ3 EA4 25 7 ED19 L1 F15 EMU0 11 12
A2 DQ3 PLLF EMU0
EA5 26 8 ED4
A3 DQ4 EA5 26 A3 DQ4 8 ED20 W39 EMU1 E18 EMU1 13 14
EA6 29 A4 DQ5 10 ED5
EA6 29 10 ED21 R43 C3
ED[0:31] A4 DQ5 56 DSP_RESET RESET +3V3
EA7 30 11 ED6 ED[0:31]
EA[2:21]
A5 DQ6 EA7 30 A5 DQ6 11 ED22 A8 NMI RSV0 C8 R51 22K
EA8 31 13 ED7
A6 DQ7 EA8 31 A6 DQ7 13 ED23 R35 1K00
B15 EXT_INT7 RSV1 A4 R53 22K
E EA9 32 42 ED8 22K
A7 DQ8 EA9 32 42 ED24 C15 K3
A7 DQ8 XDSPREQ EXT_INT6 RSV2
EA10 33 44 ED9
A8 DQ9 EA10 33 44 ED25 A16 L5
EA11 34 45 ED10
A8 DQ9
DSP_EINT5
EXT_INT5 RSV3 R44
A9 DQ10 EA[2:21] EA11 34 45 ED26 B16 T18 UP1
A9 DQ10 EXT_INT4 RSV4
22 47 ED11 DSP_EINT4
A10 DQ11 22 A10 DQ11 47 ED27 A15 IACK RSV5 A3 AM29LV160
EA13 35 48 ED12
A11 DQ12 EA13 35 48 ED28 B3
A11 DQ12 RSV6 EA2 25 29 ED0
36 50 ED13 A0 DQ0
NC/(A12) DQ13 36 50 ED29 C14 B4
NC/(A12) DQ13 INUM0 RSV7 EA3 24 31 ED1
EA15 21 51 ED14 A1 DQ1
BA1 DQ14 EA14 21 51 ED30 B14 C4
BA1 DQ14 INUM1 RSV8 EA4 23 33 ED2
EA14 20 53 ED15 A2 DQ2
BA0 DQ15 EA15 20 53 ED31 A14 K2
BA0 DQ15 INUM2 RSV9 EA5 22 35 ED3
A3 DQ3
SDA10 F12 J17
SDA10 INUM3 RSV10 EA6 21 38 ED4
18 39 A4 DQ4
SDRAS RAS DQMH BE1 18 39 N18
SDRAS RAS DQMH BE3 RSV11 EA7 20 40 ED5
17 15 A5 DQ5
SDCAS CAS DQML BE0 17 15 A18
SDCAS CAS DQML BE2 DMAC0 EA8 19 42 ED6
16 A6 DQ6
SDWE WE
SDWE 16 WE
+3V3 C16 DMAC1 TOUT0 E5 TB41 EA9 18 44 ED7
19 A7 DQ7

ED[0:31]
SDCS1 CS 19 B17 C5

EA[2:21]
SDCS1 CS DMAC2 TINP0 EA10 8 30 ED8
6 A8 DQ8
VSSQ 6 A17
VSSQ DMAC3 EA11 7 32 ED9
28 12 A9 DQ9
VSS VSSQ 28 12 A5 R56 10K
VSS VSSQ TOUT1 EA12 6 34 ED10
41 VSS VSSQ 46
41 46 R75 R72 B18 B5
A10 DQ10
VSS VSSQ PD TINP1 EA13 5 36 ED11
54 52 DSPREQ 10K 1K00 A11 DQ11
VSS VSSQ 54 52
VSS VSSQ R54 EA14 4 39 ED12
A12 DQ12
D 1K00
C9 CLKX0 CLKX1 E6 CLKX0R1 EA15 3 A13 DQ13 41 ED13
DSP_SAFE A9 FSX0 FSX1 A6 FSX0R1 EA16 ED14
2 A14 DQ14 43
FPGA_WR B10 DX0 DX1 B7 DX0R1 EA17 ED15
1 A15 DQ15(A-1) 45
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

B9 B6
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

FPGA_PROG CLKR0 CLKR1 CLKX1R0 EA18 48 A16

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

FPGA_INIT E10 FSR0 FSR1 C7 FSX1R0 EA19 17 A17 RY/BY 15

FPGA_DONE A10 DR0 DR1 A7 DX1R0 EA20 16 A18
+3V3 BOOTMODE0
EA21 9 A19
A12 CLKS0 CLKS1 C6
B A
W41 A B
FLASHCS 26 CE

+3V3
DSP_MODE
TB47 TB46 TB45 CR3 AOE 28 OE
W37 BOOTMODE1 1K00 R74 BAT54 AWE 11 WE
12 RESET
B A U52 U47
ED[0:31] 47 BYTE
TMS320C6205 22K
22K
5 4 ED0 ED0 R17 V13 EA2 R73
W38 BOOTMODE2 ED0 EA2

+3V3
6 3 ED1 ED1 R18 ED1 EA3 W13 EA3 R76
B A 7 2 ED2 ED2 R19 ED2 EA4 R12 EA4 U47 +3V3 4K7 R48
8 1 ED3 ED3 P17 ED3 EA5 U12 EA5 TMS320C6205 22K
C U46 ED4 EA6 W42
W36 BOOTMODE3 P18 ED4 EA6 W12 PCI_CLKO W5 PCLK VIOP U3
22K ED5 N15 R11 EA7 P3 +3V3 +12V CR4
ED5 EA7 VIOP
5 4 ED4 C78 C130
B A ED6 P19 U11 EA8 PCI_AD0 U7 G1 BAT54
ED6 EA8 AD0 VIOP 47N 47N U56
6 3 ED5
ED7 N19 V11 EA9 PCI_AD1 W6
ED7 EA9 AD1
7 2 ED6
ED8 M17 W11 EA10 PCI_AD2 V3 V4 R77 LP2951-3.1
W33 BOOTMODE4
8 1 ED7
ED8 EA10 AD2 PCBE0 PCI_CBE0
8 1
ED9 M18 U10 EA11 PCI_AD3 V6 T2 10K VIN OUTPUT
U45 ED9 EA11 AD3 PCBE1 PCI_CBE1
EA[2:21]

B A ED10 M19 V10 EA12 PCI_AD4 U6 M3

22K ED10 EA12 AD4 PCBE2 PCI_CBE2
ED11 EA13 PCI_AD5 3 SHUTDWN Vtap 6
1 8 ED8 L19 ED11 EA13 W10 V5 AD5 PCBE3 G2 PCI_CBE3 470K C157
W35 EES0
2 7 ED9
ED12 L18 ED12 EA14 U9 EA14 PCI_AD6 U5 AD6
W18 R66 470N
ED13 EA15 PCI_AD7 5 ERROR FB 7
ED10 L17 ED13 EA15 V9 W4 AD7 PREQ F2 PCI_REQ0 PCI_AD19
3 6
B A ED14 K19 W9 EA16 PCI_AD8 U4 D1
4 5 ED11 ED14 EA16 AD8 PGNT R25
PCI_GNT0 B A
4 2
U51 ED15 K18 ED15 EA17 W8 EA17 PCI_AD9 V1 AD9
GND SENSE
EES1 33 PCI_INTC
ED16 K17 V8 EA18 PCI_AD10 W2 H5
W29 22K ED16 EA18 AD10 PIDSEL
R58 R59
1 8 ED12 ED17 K15 U8 EA19 PCI_AD11 W3 R2 W25
ED17 EA19 AD11 PDEVSEL PCI_DEVSEL

B
B A 2 7 ED13 ED18 J19 W7 EA20 PCI_AD12 U1 N5 PCI_INTB 47K 7K5
ED18 EA20 AD12 PFRAME PCI_FRAME

A
3 6 ED14 ED19 J18 V7 EA21 PCI_AD13 U2 C1
ED19 EA21 AD13 PINTA

B
W30 EES2 4 5 ED15 ED20 H19 ED20 TB35 PCI_AD14 V2 AD14 PPAR T3 PCI_PAR
B U44 ED21 PCI_AD15
W24
H18 W16 T1 C2

A
ED21 BE0 BE0 AD15 PRST PCI_RST
B A 22K ED22 H17 V16 PCI_AD16 N1 P1
ED22 BE1 BE1 AD16 PIRDY PCI_IRDY
1 8 ED16 PCI_INTA
ED23 G19 W17 PCI_AD17 N2 R1
ED23 BE2 BE2 AD17 PSTOP PCI_STOP
2 7 ED17
ED24 G18 U16 PCI_AD18 M1 N3 2 UP5
W28 LENDIAN
3 6 ED18
ED24 BE3 BE3 AD18 PTRDY PCI_TRDY SCLK
ED25 G17 ED25
PCI_AD19 M2 AD19 93C56W
4 5 ED19
B A ED26 F19 V17 PCI_AD20 H1 B19 3 4
U43 ED26 CE0 SDCS1 AD20 XSP_DO DI DO
ED27 F18 W18 PCI_AD21 J1 C11
22K ED27 CE1 FLASHCS AD21 XSP_CS
ED28 G15 U17 PCI_AD22 H2 C17 6
W27 EEA1 1 8 ED20 ED28 CE2 MANNYCS AD22 XSP_CLK ORG
ED29 F17 V18 PCI_AD23 H3 C18 7
2 7 ED21 ED29 CE3 AD23 XSP_DI DU
B A ED30 E19 PCI_AD24 G3 1
3 6 ED22 ED30 R37 AD24 CS
+3V3

ED31 F14 P14 PCI_AD25 F1 D3

4 5 ED23 ED31 HOLD AD25 PME PCI_PME
W32 PLL_CNF0 U41 HOLDA V15 10K PCI_AD26 F5 AD26 3.3VauxDET B1
22K R45
22K U14 PCI_AD27 F3 A2
ARE ARE AD27 PWR_WKP R49
B A 1 8 ED24 W14 PCI_AD28 E1 B2 22K
AOE AOE AD28 3.3Vaux R55 22K

+3V3
2 7 ED25 V14 U18 PCI_AD29 E2
AWE AWE SDRAS/SSOE SDRAS AD29
3 6 ED26 W15 V19 PCI_AD30 E3 P5 C145
W26 PLL_CNF1 ARDY ARDY SDCAS/SSADS SDCAS AD30 PSERR PCI_SERR
4 5 ED27 U19 T17 PCI_AD31 D2 P2 47N
SDA10 SDA10 SDWE/SSWE SDWE AD31 PPERR PCI_PERR
A B A
U50
PCI_AD[0:31]
22K
837 0147 042 Rev.A

+3V3

1 8 ED28
W31 PLL_CNF2
ED29
FORM:

2 7 R34
3 6 ED30 10K
B A
4 5 ED31

W34

SHEET DESCRIPTION:
"7350" PROCESSORS BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1218 000 SE C 4 10

 1 2 3 4 5 6 7 8 9 10 11

U72
U73 CPU_CKO R114
R125 1K00 74LCX244
MC68340PV-16VE
C243 33 1 1G
33P 90 VDDSYN CLKOUT 95 CPU_CLKOUT 19 2G
U71 CPULA0 CPULA0 CPU_A0
CPU_CLK 91 EXTAL A0 113 2 1A1 1Y1 18
F 74LCX245 89 37 CPULA1 CPULA1 4 16 CPU_A1
CPU_XTAL XTAL A1 1A2 1Y2
CPU_FC3 19 G CPULA2 CPULA2 CPU_A2
CPU_XFC 93 XFC A2 38 6 1A3 1Y3 14
CPU_RW 1 T/R CPULA3 CPULA3 CPU_A3
A3 39 8 1A4 1Y4 12
CPU_D0 7 13 CPULD0 CPULD0 144 42 CPULA4 CPULA4 11 9 CPU_A4
A1 B1 D0 A4 2A1 2Y1
CPU_D1 6 14 CPULD1 CPULD1 143 43 CPULA5 CPULA5 13 7 CPU_A5
A2 B2 D1 A5 2A2 2Y2 UP3 UP2
CPU_D2 9 11 CPULD2 CPULD2 142 44 CPULA6 CPULA6 15 5 CPU_A6
A3 B3 D2 A6 2A3 2Y3
CPU_D3 8 12 CPULD3 CPULD3 141 45 CPULA7 CPULA7 17 3 CPU_A7 AM29LV160 AM29LV160
A4 B4 D3 A7 2A4 2Y4
CPU_A1 25 29 CPU_D0 CPU_A1 25 29 CPU_D0
CPU_D4 5 15 CPULD4 CPULD4 138 46 CPULA8 A0 DQ0 A0 DQ0
A5 B5 D4 A8
CPU_A2 24 31 CPU_D1 CPU_A2 24 31 CPU_D1
CPU_D5 3 17 CPULD5 CPULD5 137 47 CPULA9 U82 A1 DQ1 A1 DQ1
A6 B6 D5 A9 CPULA[0:23] CPU_A[0:23]
CPU_A3 23 33 CPU_D2 CPU_A3 23 33 CPU_D2
CPU_D6 4 16 CPULD6 CPULD6 136 48 CPULA10 A2 DQ2 A2 DQ2
A7 B7 D6 A10
R121 74LCX244 CPU_A4 22 35 CPU_D3 CPU_A4 22 35 CPU_D3
CPU_D7 2 18 CPULD7 CPULD7 135 51 CPULA11 A3 DQ3 A3 DQ3
A8 B8 D7 A11 1 1G CPU_A5 21 38 CPU_D4 CPU_A5 21 38 CPU_D4
CPULD8 134 52 CPULA12 A4 DQ4 A4 DQ4
D8 A12 1K00 19 2G CPU_A6 20 40 CPU_D5 CPU_A6 20 40 CPU_D5
CPULD9 133 53 CPULA13 A5 DQ5 A5 DQ5
U75 D9 A13

CPULD[0:15]
CPULA8 CPU_A8 CPU_A7 CPU_D6 CPU_A7 CPU_D6
CPU_D[0:15]

CPULD10 CPULA14 2 1A1 1Y1 18 19 A6 DQ6 42 19 A6 DQ6 42

132 D10 A14 55
74LCX245 CPULA9 CPU_A9 CPU_A8 CPU_D7 CPU_A8 CPU_D7

CPU_D[0:15]
CPULD11 CPULA15 4 1A2 1Y2 16 18 A7 DQ7 44 18 A7 DQ7 44
131 D11 A15 56

CPU_D[0:15]
CPULA10 CPU_A10 CPU_A9 CPU_D8 CPU_A9 CPU_D8

CPU_A[0:23]
19 G CPULD12 CPULA16 6 1A3 1Y3 14 8 A8 DQ8 30 8 A8 DQ8 30
128 D12 A16 57

CPU_A[0:23]
1 CPULA11 8 12 CPU_A11 CPU_A10 7 32 CPU_D9 CPU_A10 7 32 CPU_D9
T/R CPULD13 126 60 CPULA17 1A4 1Y4 A9 DQ9 A9 DQ9
D13 A17
E CPULA12 11 9 CPU_A12 CPU_A11 6 34 CPU_D10 CPU_A11 6 34 CPU_D10
CPU_D8 9 11 CPULD8 CPULD14 125 61 CPULA18 2A1 2Y1 A10 DQ10 A10 DQ10
A1 B1 D14 A18
CPULA13 13 7 CPU_A13 CPU_A12 5 36 CPU_D11 CPU_A12 5 36 CPU_D11
CPU_D9 8 12 CPULD9 CPULD15 124 62 CPULA19 2A2 2Y2 A11 DQ11 A11 DQ11
A2 B2 D15 A19
CPULA14 15 5 CPU_A14 CPU_A13 4 39 CPU_D12 CPU_A13 4 39 CPU_D12
CPU_D10 5 15 CPULD10 63 CPULA20 2A3 2Y3 A12 DQ12 A12 DQ12
A3 B3 A20
CPULA15 17 3 CPU_A15 CPU_A14 3 41 CPU_D13 CPU_A14 3 41 CPU_D13
CPU_D11 6 14 CPULD11 69 64 CPULA21 2A4 2Y4 A13 DQ13 A13 DQ13
A4 B4 CPU_FC0 FC0 A21
CPU_A15 2 43 CPU_D14 CPU_A15 2 43 CPU_D14
CPU_D12 7 13 CPULD12 70 65 CPULA22 A14 DQ14 A14 DQ14
A5 B5 CPU_FC1 FC1 A22
U96 CPU_A16 1 45 CPU_D15 CPU_A16 1 45 CPU_D15
CPU_D13 4 16 CPULD13 71 66 CPULA23 A15 DQ15(A-1) A15 DQ15(A-1)
A6 B6 CPU_FC2 FC2 A23
CPU_A17 48 CPU_A17 48
CPU_D14 3 A7 B7 17 CPULD14
CPU_FC3 72 FC3 A24/PA0 123
R129 74LCX244 A16 A16
CPU_A18 17 15 CPU_A18 17 15
CPU_D15 2 18 CPULD15 122 19 A17 RY/BY A17 RY/BY
A8 B8 A25/PA1/IACK1 DSP_RST 1G
CPU_A19 16 CPU_A19 16
97 121 1K00 1 A18 A18
RESET A26/PA2/IACK2 DSP_MODE 2G
CPU_A20 9 CPU_A20 9
A B 99 120 A19 A19
CPU_BERR BERR A27/PA3/IACK3 XDSP_RST CPULA16 11 9 CPU_A16
1A1 1Y1
CPU_RESET 98 117
CPU_HALT HALT A28/PA4/IACK4 XDSP_MODE CPULA17 13 7 CPU_A17
1A2 1Y2 26 26
103 116 FLASH0 CE FLASH1 CE
W52 +3V3 CPU_AS AS A29/PA5/IACK5 PRTPWRON CPULA18 15 1A3 1Y3 5 CPU_A18
28 28
104 115 OE OE
CPU_DS DS A30/PA6/IACK6 LINK0 CPULA19 17 3 CPU_A19
1A4 1Y4 11 11
107 114 WE WE
CPU_RW R/W A31/PA7/IACK7 LINK1 CPULA20 4 16 CPU_A20
2A1 2Y1 12 12
105 RESET RESET
CPU_SIZ0 SIZ0 CPULA21 8 12 CPU_A21
R120

R122

2A2 2Y2 47 47
106 87 BYTE BYTE
CPU_SIZ1 SIZ1 MODCK/PB0 CPU_MCKPB0 CPULA22 6 14 CPU_A22
4K7

4K7

2A3 2Y3
CS0/AVEC 1 CPU_CS0AVEC CPULA23 CPU_A23
2 2A4 2Y4 18

+3V3

+3V3
D CPU_DSACK0 112 DSACK0 CS1/IRQ1/PB1 2 INT1
111 3
CR5
CPU_DSACK1 DSACK1 CS2/IRQ2/PB2 INT2
PC_RESET R103 R102
IRQ3/PB3 4 INT3 R126 BAT54
22K 22K
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

100 5 CPU_RESET
4K7 Q1
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

CPU_BR BR CS3/IRQ4/PB4 INT4

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

CPU_BG 101 BG IRQ5/PB5 8 INT5 BC817

CPU_BGACK 102 BGACK IRQ6/PB6 9 INT6
108 10 W45 U91
CPU_RMC RMC IRQ7/PB7 INT7 R110 13
CPU_DS
4K7 11
16 29 PC_RST 12
CPU_DREQ1_X DREQ1 RTSA/OP0 CPU_RTSA +3V3 +12V U91
15 23 74LCX00 10
CPU_DACK1_X DACK1 RTSB/OP1 CPU_RTSB CR6 8
CPU_DONE1_X 14 DONE1 TxRDYA/OP6 26 CPU_TXRDYA U68 BAT54 9
27
U91
RxRDYA/FFULLA/OP4 CPU_RXRDYA R108 LP2951-3.1 1 74LCX00 +3V3
CPU_DREQ2_X 13 DREQ2 3
10K 8 VIN OUTPUT 1
2 U91
CPU_DACK2_X 12 DACK2 SCLK 21 CPU_SCLK_X
11 17 R107 C202 C206 74LCX00 4
R111
CPU_DONE2_X DONE2 X1 CPU_X1_X 3 6 6
PRTPWRON SHUTDWN Vtap 470K 100N 470N
X2 20 CPU_X2_X CPU_RW 5
10K
CPU_TGATE1_X 79 TGATE1 74LCX00 U69
5 ERROR FB 7
CPU_TIN1_X 81 TIN1 RxDA 33 CPU_RXDA U69 11
C 13
CPU_TOUT1_X 80 TOUT1 TxDA 32 CPU_TXDA CPU_A20 5
4 GND SENSE 2 12
4
CTSA 28 CPU_CTSA
RAM 6 74LCX02
CPU_TGATE2_X 36 TGATE2 R105 U66
34 25
R101 74LCX02 U66 13
CPU_TIN2_X TIN2 RxDB CPU_RXDB 47K 7K5 10 11
CPU_SIZ0
CPU_TOUT2_X 35 TOUT2 TxDB 24 CPU_TXDB 8 12
CPU_A0 9
CTSB 22 CPU_CTSB 74LCX00
78 74LCX00
CPU_TCK_X TCK
CPU_TMS_X 77 TMS BKPT/DSCLK 83 CPU_BKPT U69 U66
82
U66 1
FREEZE CPU_FREEZE +3V3 74LCX02 5 3
CPU_TDI_X 76 TDI IPIPE/DSO 85 CPU_DSO 8 6 2
10 4
CPU_TDO_X 75 TDO IFETCH/DSI 84 CPU_DSI 74LCX00
9
74LCX00
R109 R112
10K 10K

TB5
U60 U59
U70 CY7C1049 CY7C1049
B
DSP_RST 1 74LCX11 37 OE 37 OE
2 12 DSP_RESET 15 WE 15 WE
+3V3 8 CS 8 CS
+3V3 13
TB6
CPU_A1 3 9 CPU_D0 CPU_A1 3 9 CPU_D8
U70 A0 I/O0 A0 I/O0
R134 CPU_A2 4 A1 I/O1 10 CPU_D1 CPU_A2 4 A1 I/O1 10 CPU_D9
R97 XDSP_RST 9 74LCX11
CPU_A3 CPU_D2 CPU_A3 CPU_D10
5K6 5 A2 I/O2 13 5 A2 I/O2 13
10K

CPU_D[0:15]
10 8 XDSP_RESET CPU_A4 CPU_D3 CPU_A4 CPU_D11

CPU_D[0:15]
6 A3 I/O3 14 6 A3 I/O3 14
U64 CPU_A5 CPU_D4 CPU_A5 CPU_D12
11 7 A4 I/O4 31 7 A4 I/O4 31
74LCX138 R137 R135 CPU_A6 CPU_D5 CPU_A6 CPU_D13
U97 +3V3
16 A5 I/O5 32 16 A5 I/O5 32
CPU_A21 1 A Y0 15 FLASH0 100K 33K CPU_A7 CPU_D6 CPU_A7 CPU_D14
17 35 17 35
2 14 TLC7701 +3V3 A6 I/O6 A6 I/O6
CPU_A22 B Y1 FLASH1 CPU_A8 18 36 CPU_D7 CPU_A8 18 36 CPU_D15
3 13
7 SENSE VDD 8 U69 A7 I/O7 A7 I/O7
CPU_A23 C Y2 RAM 2 CPU_A9 19 CPU_A9 19
A8 A8

CPU_A[0:23]

CPU_A[0:23]
12 1
U70 Y3
2 6 3 R127 CPU_A10 20 A9
CPU_A10 20 A9
11 RESIN RESET
Y4 4K7 CPU_A11 26 CPU_A11 26
5 74LCX11 74LCX02 A10 A10
CPU_FC0 6 G1 Y5 10 R131 CPU_A12 27 CPU_A12 27
C257 3 5 A11 A11
3 6 4 9 22K CT RESET CPU_RESET
CPU_FC1 G2A Y6 CPU_A13 28 CPU_A13 28
A 5 7 W53 C259 A12 A12
CPU_FC2 4 G2B Y7 CR7 CPU_A14 29 A13
CPU_A14 29 A13
837 0147 042 Rev.A

47N 470N 1 CNTRL GND 4

BAT54 CPU_A15 30 CPU_A15 30
A14 A14
CPU_AS CPU_A16 CPU_A16
FORM:

38 A15 38 A15
CPU_A17 39 CPU_A17 39
A16 A16
CPU_A18 40 CPU_A18 40
A17 A17
CPU_A19 41 CPU_A19 41
A18 A18

SHEET DESCRIPTION:
"7350" PROCESSORS BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1218 000 SE C 5 10

 1 2 3 4 5 6 7 8 9 10 11

U74
MC68340
N8 VDDSYN CLKOUT P10 CPU_CKO
F
CPU_CLK Q9 EXTAL A0 M14 CPULA0
CPU_XTAL P8 XTAL A1 B1 CPULA1
Q10 C2 CPULA2
CPU_XFC XFC A2
C1 CPULA3 U81
A3 +3V3
CPULD0 B14 D0 A4 D1 CPULA4 100N C221 75C3243
CPULD1 C13 D1 A5 E3 CPULA5 28 C1+
C220
100N
CPULD2 A15 E2 CPULA6 24 26
D2 A6 C1- VCC
J1 J2 C219
CPULD3 B15 E1 CPULA7 1
D3 A7 C2+ 100N
CPULD4 CPULA8 1 DBG_SA0 1 DBG_SD0
C15 D4 A8 F3 100N C248 2 C2- V+ 27
CPULD5 D14 F2 CPULA9 2 DBG_SA1 2 DBG_SD1
D5 A9
CPULD6 D15 F1 CPULA10 3 DBG_SA2 3 DBG_SD2 14 9
D6 A10 CPU_TXDB DIN1 DOUT1 TXD1
CPULD7 E13 G1 CPULA11 4 DBG_SA3 4 DBG_SD3 13 10
D7 A11 CPU_RTSB DIN2 DOUT2 RTS1
CPULD[0:15] CPULA[0:23] 5 5
CPULD8 E14 H1 CPULA12 DBG_SA4 DBG_SD4 12 11
D8 A12 DTRB DIN3 DOUT3 DTR1
6 6
CPULD9 E15 D9 A13 H2 CPULA13 DBG_SA5 DBG_SD5 VTR
CPULD10 F15 J1 CPULA14 7 DBG_SA6 7 DBG_SD6 19 4
D10 A14 CPU_RXDB ROUT1 RIN1 RXD1 (to Connectors board)
CPULD11 F14 J2 CPULA15 8 DBG_SA7 8 DBG_SD7 18 5
D11 A15 CPU_CTSB ROUT2 RIN2 CTS1
CPULD12 CPULA16 9 DBG_SA8 9 DBG_SD8
E G14 D12 A16 K1 20 ROUT2B
CPULD13 G15 K2 CPULA17 10 DBG_SA9 10 DBG_SD9 17 6
D13 A17 DSRB ROUT3 RIN3 DSR1
CPULD14 H14 L1 CPULA18 11 DBG_SA10 11 DBG_SD10 16 7
D14 A18 DCDB ROUT4 RIN4 DCD1
CPULD15 H15 L2 CPULA19 12 12 DBG_SD11 15 8
D15 A19 ROUT5 RIN5
M1 CPULA20 13 DBG_SA12 13 DBG_SD12
A20
CPU_FC0 N2 FC0 A21 L3 CPULA21 14 DBG_SA13 14 DBG_SD13 R117 23 3
15 15 10K FORCEON V-
Q1 N1 CPULA22 DBG_SA14 DBG_SD14 C249

+3V3
CPU_FC1 FC1 A22 +3V3 22
16 16 FORCEOFF
P2 P1 CPULA23 DBG_SA15 DBG_SD15 100N
CPU_FC2 FC2 A23 21 25
17 17 INVALID GND
Q2 J14 DBG_SA16
CPU_FC3 FC3 A24/PA0 PC_RST B A
J13 18 18 DBG_MEMW
A25/PA1/IACK1 DSP_RESET
19 19 DBG_MEMR
CPU_RESET Q11 RESET A26/PA2/IACK2 J15 DSP_MODE R118 R119 W51
Q12 K15 20 20 DBG_IOW
CPU_BERR BERR A27/PA3/IACK3 XDSP_RESET 10K 10K
P11 L15 21 21 DBG_IOR
CPU_HALT HALT A28/PA4/IACK4 XDSP_MODE
CPU_AS Q14 AS A29/PA5/IACK5 L14 PRTPWRON
22 22 C253 U100
23 23 100N +3V3
P13 M15 DBG_LA18
CPU_DS DS A30/PA6/IACK6 LINK0
24 24
75C3243 C252
P14 L13 DBG_LA19 DBG_SBHE 100N
CPU_RW R/W A31/PA7/IACK7 LINK1 28
25 25 C1+
N12 DBG_LA20
CPU_SIZ0 SIZ0 24 26
26 26 C1- VCC
Q15 Q8 DBG_LA21
D CPU_SIZ1 SIZ1 MODCK/PB0 CPU_MCKPB0 1
27 27 C2+ C251
A14 DBG_LA22
CS0/AVEC CPU_CS0AVEC C286 2 27
28 28 C2- V+
N15 B13 DBG_LA23
CPU_DSACK0 DSACK0 CS1/IRQ1/PB1 INT1 100N
N14 C12 29 29 100N
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

CPU_DSACK1 DSACK1 CS2/IRQ2/PB2 INT2 14 9

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

30 30 CPU_TXDA DIN1 DOUT1 CPU_TXD

A13
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

IRQ3/PB3 INT3 13 10
31 31 CPU_RTSA DIN2 DOUT2 CPU_RTS
CPU_BR Q13 BR CS3/IRQ4/PB4 B12 INT4
DTRA 12 DIN3 DOUT3 11 CPU_DTR
N11 A12 32 32
CPU_BG BG IRQ5/PB5 INT5

VCC +3V3

VCC +3V3
P12 A11 33 33
CPU_BGACK BGACK IRQ6/PB6 INT6 19 4
CPU_RMC P15 RMC IRQ7/PB7 C10 INT7
34 34 CPU_RXDA
18
ROUT1 RIN1
5
CPU_RXD RS-232 (Debug)
35 35 CPU_CTSA ROUT2 RIN2 CPU_CTS
(to PC board)
20 ROUT2B
A8 B4 36 36
CPU_DREQ1_X DREQ1 RTSA/OP0 CPU_RTSA 17 6
37 37 DSRA ROUT3 RIN3 CPU_DSR
CPU_DACK1_X C9 DACK1 RTSB/OP1 B6 CPU_RTSB
DCDA 16 ROUT4 RIN4 7 CPU_DCD
B9 A4 38 38
CPU_DONE1_X DONE1 TxRDYA/OP6 CPU_TXRDYA C200 RIA 15 ROUT5 RIN5 8 CPU_RI
B5 10P 39 39
RxRDYA/FFULLA/OP4 CPU_RXRDYA
A9 40 40
CPU_DREQ2_X DREQ2 R128 23 3
A10 A7 CPU_X1_X 10K FORCEON V- C287
CPU_DACK2_X DACK2 SCLK CPU_SCLK_X

+3V3
22 FORCEOFF
CPU_DONE2_X B10 DONE2 X1 B8
R99 Y1 100N
21 INVALID GND 25
X2 B7 3.686400MHZ
1M
C CPU_TGATE1_X N5 TGATE1
B A

Q5 A2 CPU_X2_X
CPU_TIN1_X TIN1 RxDA CPU_RXDA
CPU_TOUT1_X P5 TOUT1 TxDA B3 CPU_TXDA W55
A3
R98 C186
CTSA CPU_CTSA 470 10P
CPU_TGATE2_X C3 TGATE2
CPU_TIN2_X A1 TIN2 RxDB A5 CPU_RXDB
CPU_TOUT2_X B2 TOUT2 TxDB C6 CPU_TXDB
CTSB A6 CPU_CTSB
CPU_TCK_X Q4 TCK
CPU_TMS_X P4 TMS BKPT/DSCLK P6 CPU_BKPT
FREEZE Q6 CPU_FREEZE
CPU_TDI_X Q3 TDI IPIPE/DSO Q7 CPU_DSO
CPU_TDO_X P3 TDO IFETCH/DSI N6 CPU_DSI

U87 U88
B +3V3
10K +3V3
10K
CPU_BERR 8 1
CPU_TGATE1_X 2 7
CPU_TCK_X 5 4
CPU_TIN1_X 3 6
CPU_TMS_X 6 3
CPU_TGATE2_X 4 5
CPU_TDI_X 7 2
CPU_TIN2_X 1 8

U65 U89
+3V3 +3V3 +3V3
10K 10K P14
CPU_DREQ1_X 1 8 CPU_SCLK_X 2 7
CPU_DS 1 2 CPU_BERR
CPU_DONE1_X 2 7 1 8
3 4 CPU_BKPT
CPU_DREQ2_X 3 6 CPU_BKPT 4 5
5 6 CPU_FREEZE
CPU_DONE2_X 4 5 CPU_DSI 3 6
CPU_RESET 7 8 CPU_DSI
9 10 CPU_DSO
U90
+3V3 BDM
10K
CPU_BR 1 8
A 2 7
R124
CPU_BGACK
837 0147 042 Rev.A

3 6 4K7
CPU_HALT
CPU_MCKPB0
CPU_CS0AVEC 4 5
FORM:

SHEET DESCRIPTION:
"7350" PROCESSORS BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1218 000 SE C 6 10

 1 2 3 4 5 6 7 8 9 10 11

W2

DM_CLKFB

U38
MT48LCM16A2
U32 33 1 VDD VDDQ 3
+3V3
DM_CLK 1 8 14 VDD VDDQ 9
F 2 7 27 43
DM_CKE VDD VDDQ
DM_A0 3 6 VDDQ 49

DM_A1 4 5 38 CLK

U29 33 37
U36 CKE
DM_A2 1 8
DQ0 2 U36
XC2V1000-4 DM_A3 2 7
23 4 R204
3 6
A0 DQ1 XC2V1000-4 1K00
DM_A4 24 5
A1 DQ2
BANK 0 BANK 1 4 5
DM_A5 25 7
A2 DQ3 BANK 4 BANK 5
U30 26 A3 DQ4 8 TB29
B4 F12 33
CRT_GREEN0 IO IO/GCLK3P SID_CLK 29 10
4 5 A4 DQ5 AB19 AA11
CRT_GREEN1 A4 IO IO/GCLK2S F13 TB24 DM_A6
30 11
EXTDEV IO/DOUT IO/GCLK7S TB16
3 6 A5 DQ6 AA19 Y11
CRT_RED3 C4 IO IO/GCLK1P E12 DM_CLKFB
DM_A7
31 13
XFPGA_INIT IO/INIT_B IO/GCLK6P TB9
2 7 A6 DQ7 V18 W11
CRT_RED1 C5 IO IO/GCLK0S D12 DM_CLK
DM_A8
32 42
XED0 IO/D0 IO/GCLK5S TB10
1 8 A7 DQ8 V17 V11
CRT_BLUE6 B5 IO/VRP0 IO C12 DM_CAS
DM_A9
33 44
XED1 IO/D1 IO/GCLK4P TB12
A8 DQ9 W18 U11 TB14
A5 B12 XED2 IO/D2/ALT_VRP4 IO
CRT_GREEN3 IO/VRN0 IO/VREF1 DM_DQ7 U33 33 34 A9 DQ10 45
Y18 U10
D6 A13 XED3 IO/D3/ALT_VRN4 IO/VREF5 MS_DAT
CRT_RED5 IO/VREF0 IO DM_DQ8 4 5 22 47
DM_A10 A10 DQ11 AA18 AB10
E C6 B13 XEA17 IO/VREF4 IO ICOL0
CRT_GREEN2 IO IO DM_DQMH 2 7 35 48
DM_A11 A11 DQ12 AB18 AA10
B6 C13 XAOE IO IO ICOL1
CRT_GREEN4 IO IO DM_BA0 1 8 36 50
DM_A12 NC/(A12) DQ13 W17 Y10
A6 D13 XEA6 IO/VRP4 IO IROW1
CRT_BLUE2 IO IO DM_RAS 3 6 21 51
BA1 DQ14 Y17 W10
E7 E13 XEA9 IO/VRN4 IO KB_DAT
CRT_RED2 IO IO DM_DQ5 20 53
BA0 DQ15 AA17 V10
E8 E14 XEA10 IO IO MS_CLK
CRT_RED4 IO IO/VREF1 DM_DQ6
ICOL11 AB17 IO IO/VREF5 V9 LINK0
CRT_RED7 D7 IO IO A14 DM_CS 18 RAS DQMH 39
IROW10 V16 IO IO AB9 XAWE
CRT_GREEN5 C7 IO/VREF0 IO B14 DM_DQML 17 CAS DQML 15
U34 IROW8 V15 IO IO AA9 XARE
CRT_GREEN7 B7 IO IO C14 DM_CKE 33 16 WE
XEA7 W16 IO IO Y9 LINK7
CRT_GREEN6 A7 IO IO D14 DM_BA1 DM_BA1 4 5
19 CS
XEA11 Y16 IO/VREF4 IO W9 LINK6
CRT_RED6 D8 IO IO/VREF1 A15 DM_WE DM_BA0 3 6
VSSQ 6
XEA18 AA16 IO IO/VREF5 AB8 VID_HSYNC
CRT_BLUE3 C8 IO IO B15 DM_A12 DM_RAS 2 7
28 VSS VSSQ 12
ICOL14 AB16 IO IO AA8 VID_VBLANK
CRT_BLUE1 B8 IO IO C15 DM_A1 DM_CAS 1 8
41 VSS VSSQ 46
XEA13 W15 IO IO Y8 GRA0
CRT_BLUE0 A8 IO IO D15 DM_A0 54 VSS VSSQ 52 Y15 W8
E9 F14 U35 33 GRA7 IO IO LINK1
CRT_BLUE4 IO IO DM_A6
AA15 U9 R63 R64
F9 E15 4 5 ICOL2 IO IO KB_CLK
CRT_RED0 IO/VREF0 IO DM_A4 DM_WE 470
ICOL15 AB15 IO IO V8 LINK2 470
CRT_BLUE7 D9 IO IO A16 DM_A11 DM_CS 2 7
IROW14 U14 IO IO AB7 GRA4
CRT_BLUE5 C9 IO IO B16 DM_A10 DM_DQML 3 6
GRA1 V14 IO/VREF4 IO AA7 GRA5
DM_DQ11 B9 IO IO/VREF1 C16 DM_A3 DM_DQMH 1 8
D GRA2 W14 IO IO/VREF5 Y7 GRA6
DM_DQ15 A9 IO IO D16 DM_A2
U49 GRA3 Y14 IO IO W7 LINK5
DM_DQ1 E10 IO/VREF0 IO E16 DM_A5 33
ICOL10 AA14 IO IO AB6 GRA8
F10 E17 1 8
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

DM_DQ0 IO IO DM_A7 DM_DQ15

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

ICOL12 AB14 IO IO AA6 GRA9

D10 A17 2 7
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

DM_DQ2 IO IO DM_A9 DM_DQ14

ICOL5 U13 IO/VREF4 IO Y6 GRA10
DM_DQ14 C10 IO IO B17 DM_A8 DM_DQ13 3 6
ICOL7 V13 IO IO W6 GRA13
DM_DQ9 B10 IO IO C17 MM_CS DM_DQ12 4 5
ICOL8 W13 IO IO/VRP5 V7 LINK3
DM_DQ10 A10 IO IO/VREF1 D17 MM_WP
ICOL13 Y13 IO IO/VRN5 V6 LINK4
DM_DQ13 E11 IO/VREF0 IO/VRP1 A18 MM_HOLD U40 33 AA13 AB5
F11 B18 ICOL6 IO IO GRA14
DM_DQ12 IO IO/VRN1 MM_SCK 1 8
DM_DQ11 AB13 AA5
D11 C18 ICOL4 IO IO/VREF5 GRA15
DM_DQ3 IO/GCLK7P IO MM_SI 2 7
DM_DQ10 U12 Y5
C11 D18 ICOL3 IO/VREF4 IO/D4/ALT_VRP5 XED4
DM_DQ4 IO/GCLK6S IO MM_SO 3 6
DM_DQ9 V12 W5
B11 A19 ICOL9 IO IO/D5/ALT_VRN5 XED5
TB11 IO/GCLK5P IO XDM_CLK
DM_DQ8 4 5
W12 AB4
TB13 A11 IO/GCLK4S IO B19 TB22 TB15 IO/GCLK3S IO/D6 XED6
Y12 AA4
U39 33
TB23 IO/GCLK2P IO/D7 XED7
AA12 Y4
4 5 TB21 IO/GLCK1S IO/RDWR_B XFPGA_WR
DM_DQ7 AB12 AA3
XDSPIOCLK IO/GCLK0P IO/CS_B SIDCS
DM_DQ6 3 6
DM_DQ5 2 7
C
DM_DQ4 1 8
+3V3

+3V3

G11 VCCOBank0 VCCOBank1 G14

+3V3

+3V3
U16 VCCOBank4 VCCOBank5 U8
G10 VCCOBank0 VCCOBank1 G13 U48 33 U15 U7
G9 G12 VCCOBank4 VCCOBank5
VCCOBank0 VCCOBank1 4 5
DM_DQ3 T14 T11
F8 F16 VCCOBank4 VCCOBank5
VCCOBank0 VCCOBank1 3 6
DM_DQ2 T13 T10
F7 F15 VCCOBank4 VCCOBank5
VCCOBank0 VCCOBank1 2 7
DM_DQ1 T12 T9
VCCOBank4 VCCOBank5
DM_DQ0 1 8

+3V3

1
2
3
4
U11
10K

U36

8
7
6
5
XC2V1000-4 P15
+3V3
XAWE Y19 CCLK TCK C19 1 2
+3V3 A2 D3 3 4
XFPGA_PROG PROG_B TDI
XFPGA_DONE AB20 DONE TDO D20 5 6 C43
AB2 B20 7 8 47N
M0 TMS
R79 W3 D5 9 10
M1 DXN
10K AB3 A3
M2 DXP
B3 HSWAP_EN VBATT A21
AB21 PWRDWN_B RSVD A20

A B A B A B

A W43 W44 W40

837 0147 042 Rev.A
FORM:

SHEET DESCRIPTION:
"7350" PROCESSORS BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1218 000 SE C 7 10

 1 2 3 4 5 6 7 8 9 10 11

+2V2 U58 +1V5X

+1V5X
TPS72501
+3V3
2 IN OUT 4

R80
1 EN FB 5
27K
C160 GND C107 C86 C133 C136 C308 C296 C297 C311 C102 C71 C59 C63 C131 C138 C57 C64 C25
F R78 C139 C1 C27 C2 C24 C26 C4 C250 C258 C260
1U C172 47U 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N
470N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
4U7 3 120K

+2V2 U63 +1V5

TPS72501 +1V5 +1V5DSP +1V5XDSP
2 IN OUT 4

R83
1 EN FB 5
27K C326 C316 C327 C317 C303 C313 C312 C305 C291 C290 C294 C292
GND C195 C191 C147 C151 C168 C183 C180 C162 C146 C152 C190 C196
C158 47N 47N 47N 47N
C171 R82 47N 47N 47N 47N 47N 47N 47N 47N
C159 47U 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
1U 3 120K
4U7

+2V2 U53 +1V5DSP

+2V2 U27 +1V5XDSP
TPS72501 TPS72501
2 IN OUT 4
2 IN OUT 4
R42 R8
1 EN FB 5
1 EN FB 5
27K
GND 27K
C98 C83 C96 C125 C93 C77 C94 C110 C80 C129 C75 C124 GND C21 C17 C36 C7 C18 C51 C54 C10 C50 C5
C84 R41 C23 C12
1U 3
47U 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N C20 R7 47U 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
4U7 120K 1U 3
4U7 120K

+3V3

D Virtex (XC2V1000) -M-

TP5 TP3 TP2 TP1 TP4

C323 C48 C324 C325 C318 C321 C31 C319 C322 C15 C30 C320 C194 C179 C166 C192 C148 C150 C181 C169 C156
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

47U

+3V3 +3V3AUX

Virtex (XC2V1000) -S-

C85 C134 C88 C58 C307 C306 C309 C300 C310 C298 C299 C301 C56 C117 C118 C72 C13 C135 C62 C101 C103 C65 C55 C137 C132
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N 47U 47N 47N 47N 47N 47N 47N 47N 47N

C +3V3

TMS320C6205

U76 +3V3AUX
C109 C113 C127 C76 C126 C304 C29 C315 C314 C302 C79 C128 C92 C120 C95 C81 VCC
LP3964-ADJ
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
47U 2 3
VIN VOUT
R123 R116 C217
1 SD ADJ 4 82P
18K
10K
GND C222 C182 C167 C154 C193 C149 C185 C170 C155
470N 47N 470N 47N 47N 470N 47N 470N
+3V3 C246 33U

100U 5
TMS320C6205 (extra) R115
10K5

C289 C295 C9 C288 C6 C52 C293 C34 C53 C38 C47 C16 C41 C35 C19 C11
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
47U
B

+3V3

Miscellanea

C204 C211 C208 C215 C254 C239 C218 C209 C212 C255 C203 C241 C223 C105 C122 C3 C104 C32 C14 C28 C91 C108 C33 C216 C74 C49 C106 C89 C214 C66 C44
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
47U 47U 47U

+3V3

Miscellanea

C189 C143 C285 C87 C188 C70 C213 C112 C165 C210 C242 C144 C121 C205 C164 C100 C163 C198 C116 C161 C244 C207 C99 C199 C90 C123 C119 C73 C197 C67 C187
A
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
47U 47U 47U
837 0147 042 Rev.A
FORM:

SHEET DESCRIPTION:
"7350" PROCESSORS BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1218 000 SE C 8 10

 1 2 3 4 5 6 7 8 9 10 11

+3V3
+3V3 +3V3
U31 R15
FL1 CY2305 33
300MA XSDCLK_0
6 VDD CLKout 8
R33

+3V3
CLK1 3
F U6 U3
33
1 REF CLK2 2 XSDCLK_1
MT48LCM16A2 MT48LCM16A2 C40 C39 5
1 3
+3V3 C68 CLK3 R12 +3V3
VDD VDDQ 1 3 100N 47N 4 7 33
VDD VDDQ 10U GND CLK4
14 VDD VDDQ 9 XDSPIOCLK
14 VDD VDDQ 9 TB36 R20
27 VDD VDDQ 43
27 VDD VDDQ 43 22K
VDDQ 49 R3
VDDQ 49
TB32 U8 W1
22K R2
XSDCLK_0 38 CLK 38
C22 P16 22K
XSDCLK_1 CLK TMS320C6205 XTCK_RET

TB34 J3 E17 XTMS 1 2

37 TB31 XDSP_CLK CLKIN TMS
CKE 37 CKE 27N T19 D19 XTDO 3 4
2 XED0 CLKOUT2 TDO
DQ0 2 XED16 R5
DQ0 L3 D18 XTDI 5 6 R27
XEA2 23 A0 DQ1 4 XED1
XEA2 23 4 XED17 4.7
C37 CLKMODE0 TDI
A0 DQ1 560P K5 D17 XTCK 7 8 22K
XEA3 24 5 XED2 PLLV TCK
A1 DQ2 XEA3 24 5 XED18
A1 DQ2 L2 C19 XTRST 9 10
XEA4 25 A2 DQ3 7 XED3
XEA4 25 7 XED19 R9 PLLG TRST
A2 DQ3 L1 F15 XEMU0 11 12
XEA5 26 8 XED4 PLLF EMU0
A3 DQ4 XEA5 26 8 XED20
XEA6 29 10 XED5
A3 DQ4 56 W19 EMU1 E18 XEMU1 13 14
A4 DQ5 XEA6 29 10 XED21
A4 DQ5 C3
XEA7 30 11 XED6 XDSP_RESET RESET +3V3
A5 DQ6 XEA7 XED22
XEA[2:21]

XED[0:31]
30 A5 DQ6 11 R21 22K
XEA8 XED7 A8 NMI RSV0 C8

XED[0:31]
31 A6 DQ7 13 XEA8 XED23
31 A6 DQ7 13 R23 22K
XEA9 XED8 R52 B15 EXT_INT7 RSV1 A4
E 32 A7 DQ8 42 XEA9 32 42 XED24
XEA10 XED9
A7 DQ8
DSPREQ C15 EXT_INT6 RSV2 K3 R10 22K

XEA[2:21]
33 A8 DQ9 44 XEA10 XED25
33 A8 DQ9 44 1K00
XEA11 34 A9 DQ10 45 XED10
XEA11 XED26
XDSP_EINT5 A16 EXT_INT5 RSV3 L5 UP4
34 A9 DQ10 45
B16 T18
22 A10 DQ11 47 XED11
22 47 XED27
XDSP_EINT4 EXT_INT4 RSV4 AM29LV160
A10 DQ11 A15 A3
XEA13 35 48 XED12 IACK RSV5 XEA2 25 29 XED0
A11 DQ12 XEA13 35 48 XED28 A0 DQ0
A11 DQ12 B3
36 50 XED13 RSV6 XEA3 24 31 XED1
NC/(A12) DQ13 36 50 XED29 A1 DQ1
NC/(A12) DQ13 C14 B4
XEA15 21 51 XED14 INUM0 RSV7 XEA4 23 33 XED2
BA1 DQ14 XEA14 21 51 XED30 A2 DQ2
BA1 DQ14 B14 C4
XEA14 20 53 XED15 INUM1 RSV8 XEA5 22 35 XED3
BA0 DQ15 XEA15 20 53 XED31 A3 DQ3
BA0 DQ15 A14 K2
INUM2 RSV9 XEA6 21 38 XED4
XSDA10 A4 DQ4
XSDA10 F12 J17
18 39 INUM3 RSV10 XEA7 20 40 XED5
XSDRAS RAS DQMH XBE1 18 39 A5 DQ5
XSDRAS RAS DQMH XBE3 N18
17 15 RSV11 XEA8 19 42 XED6
XSDCAS CAS DQML XBE0 17 15 A6 DQ6
XSDCAS CAS DQML XBE2 A18
16 DMAC0 XEA9 18 44 XED7
XSDWE WE 16 A7 DQ7
XSDWE WE +3V3 TB43

XED[0:31]
C16 DMAC1 TOUT0 E5 XEA10 XED8
XSDCS1 19 CS 8 A8 DQ8 30
XSDCS1 19 CS B17 DMAC2 TINP0 C5 XEA11 XED9

XEA[2:21]
VSSQ 6 7 A9 DQ9 32
VSSQ 6
A17 DMAC3 XEA12 XED10
28 VSS VSSQ 12 R26 DSP1T1 6 A10 DQ10 34
28 12
VSS VSSQ R14 TOUT1 A5 TB55 XEA13 XED11
41 VSS VSSQ 46
41 46 R13 1K00
5 A11 DQ11 36

+3V3
VSS VSSQ B18 B5
54 52 XDSPREQ 10K PD TINP1 XEA14 4 39 XED12
VSS VSSQ 54 52 A12 DQ12
VSS VSSQ 10K
R36 XEA15 3 41 XED13
D A13 DQ13
C9 CLKX0 CLKX1 E6 CLKX1R0 XEA16 XED14
1K00 2 A14 DQ14 43
DSP_SAFE A9 FSX0 FSX1 A6 FSX1R0 XEA17 XED15
1 A15 DQ15(A-1) 45
XFPGA_WR B10 DX0 DX1 B7 DX1R0 XEA18 48
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

A16
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

XFPGA_PROG B9 CLKR0 CLKR1 B6 CLKX0R1 XEA19 17 15

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

A17 RY/BY
XFPGA_INIT E10 FSR0 FSR1 C7 FSX0R1 XEA20 16 A18
XFPGA_DONE A10 DR0 DR1 A7 DX0R1 XEA21
+3V3 XBOOTMODE0 9 A19

A12 CLKS0 CLKS1 C6

B A XFLASHCS 26 CE
W17 A B R17 CR1 28

+3V3
XAOE OE
XDSP_MODE
TB48 TB42 TB40 BAT54 XAWE 11 WE
W15 XBOOTMODE1 1K00
12 RESET
B A U8 47 BYTE
XED[0:31] 22K
U10 22K TMS320C6205 R19
R28

+3V3
5 4 XED0 XED0 R17 V13 XEA2
W16 XBOOTMODE2 ED0 EA2
6 3 XED1 XED1 R18 ED1 EA3 W13 XEA3 4K7 R16
XED2 XED2 XEA4 W21 22K
B A 7 2 R19 ED2 EA4 R12 U8 +3V3
8 1 XED3 XED3 P17 U12 XEA5
C ED3 EA5 TMS320C6205
XED4 P18 W12 XEA6
W10 XBOOTMODE3
U7 ED4 EA6
PCI_CLK1 W5 PCLK VIOP U3 +3V3 +12V
22K XED5 N15 R11 XEA7
5 4 XED4
ED5 EA7
VIOP P3 CR2
B A XED6 P19 ED6 EA8 U11 XEA8
PCI_AD0 U7 G1 C8 C42 U28 BAT54
6 3 XED5 AD0 VIOP 47N 47N
XED7 N19 V11 XEA9
XED6
ED7 EA9 PCI_AD1 W6 AD1 LP2951-3.1
7 2 XED8 M17 W11 XEA10 R32
W14 XBOOTMODE4
8 1 XED7
ED8 EA10 PCI_AD2 V3 AD2 PCBE0 V4 PCI_CBE0 8 VIN OUTPUT 1
XED9 XEA11 10K
XEA[2:21]

M18 ED9 EA11 U10 PCI_AD3 V6 AD3 PCBE1 T2 PCI_CBE1

B A XED10 M19 V10 XEA12
U5 22K ED10 EA12 PCI_AD4 U6 AD4 PCBE2 M3 PCI_CBE2 3 SHUTDWN Vtap 6 R31
XED8
XED11 L19 ED11 EA13 W10 XEA13
PCI_AD5
C82
1 8 V5 AD5 PCBE3 G2 PCI_CBE3 470K
XED12 L18 U9 XEA14 470N
W11 XEES0 2 7 XED9 ED12 EA14 PCI_AD6 U5 AD6 5 ERROR FB 7
XED13 L17 V9 XEA15 W20
3 6 XED10 ED13 EA15 PCI_AD7 W4 F2
AD7 PREQ PCI_REQ1
B A XED14 K19 W9 XEA16
4 5 XED11 ED14 EA16 PCI_AD8 U4 D1 PCI_AD20 4 2
XED15 K18 W8 XEA17
AD8 PGNT R6
PCI_GNT1 GND SENSE
ED15 EA17 PCI_AD9 V1 B A
AD9
W7 XEES1 U26 22K XED16 K17 ED16 EA18 V8 XEA18
PCI_AD10 W2 H5
33 PCI_INTC
AD10 PIDSEL
1 8 XED12 XED17 K15 U8 XEA19
ED17 EA19 PCI_AD11 W3 R2
AD11 PDEVSEL PCI_DEVSEL R29 R30

B
B A 2 7 XED13 XED18 J19 W7 XEA20 W23
ED18 EA20 PCI_AD12 U1 N5 PCI_INTB
AD12 PFRAME PCI_FRAME
3 6 XED14 XED19 J18 V7 XEA21

A
ED19 EA21 PCI_AD13 U2 C1 47K 7K5
AD13 PINTA
4 5 XED15 XED20 H19

B
W8 XEES2 ED20 TB37 PCI_AD14 V2 AD14 PPAR T3 PCI_PAR
B XED21 H18 ED21 BE0 W16 XBE0 PCI_AD15
W22
T1 C2

A
B A
U9 22K XED22 H17 V16
AD15 PRST PCI_RST
ED22 BE1 XBE1 PCI_AD16 N1 P1
1 8 XED16 AD16 PIRDY PCI_IRDY
XED23 G19 W17 UP6 PCI_INTA
ED23 BE2 XBE2 PCI_AD17 N2 R1
2 7 XED17 AD17 PSTOP PCI_STOP
XED24 G18 U16
W6 XLENDIAN
3 6 XED18
ED24 BE3 XBE3 PCI_AD18 M1 AD18 PTRDY N3 PCI_TRDY 2 SCLK
XED25 G17 ED25 PCI_AD19 M2 93C56W
4 5 XED19 AD19
B A XED26 F19 V17
ED26 CE0 XSDCS1 PCI_AD20 H1 B19 3 4
AD20 XSP_DO DI DO
XED27 F18 W18
U4 22K ED27 CE1 XFLASHCS PCI_AD21 J1 AD21 XSP_CS C11
XED28 G15 U17
W5 XEEA1 1 8 XED20 ED28 CE2 SIDCS PCI_AD22 H2 AD22 XSP_CLK C17 6 ORG
XED29 F17 V18
2 7 XED21 ED29 CE3 R4 PCI_AD23 H3 AD23 XSP_DI C18 7 DU
B A XED30 E19
3 6 XED22 ED30 PCI_AD24 G3 1
AD24 CS
+3V3

XED31 F14 P14

4 5 XED23 ED31 HOLD PCI_AD25 F1 D3
AD25 PME PCI_PME
W13 XPLL_CNF0 HOLDA V15 10K PCI_AD26 F5 AD26 3.3VauxDET B1
U2 22K XARE U14 ARE PCI_AD27 F3 A2
22K R22
AD27 PWR_WKP R18
B A 1 8 XED24 W14
XAOE AOE PCI_AD28 E1 B2 22K
AD28 3.3Vaux R24 22K

+3V3
2 7 XED25 V14 U18
XAWE AWE SDRAS/SSOE XSDRAS PCI_AD29 E2 AD29
3 6 XED26 W15 V19
W4 XPLL_CNF1 XARDY ARDY SDCAS/SSADS XSDCAS PCI_AD30 E3 AD30 PSERR P5 PCI_SERR C69
4 5 XED27 U19 T17
XSDA10 SDA10 SDWE/SSWE XSDWE PCI_AD31 D2 P2 47N
AD31 PPERR PCI_PERR
A B A
U19 22K PCI_AD[0:31]
837 0147 042 Rev.A

1 8 XED28
W9 XPLL_CNF2
XED29 R1
FORM:

2 7
10K
+3V3

3 6 XED30
B A
4 5 XED31

W12

SHEET DESCRIPTION:
"7350" PROCESSORS BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1218 000 SE C 9 10

 1 2 3 4 5 6 7 8 9 10 11

U36 U36
XC2V1000-4 XC2V1000-4
U1
BANK 2 BANK 3 BANK 6 BANK 7
MT48LCM16A2
U22 33 1 VDD VDDQ 3
C21 M21 +3V3 V5 L2
XDM_DQ0 IO IO XEA4 1 8 14 9 EXTECG IO IO CPU_A1
XDM_CLK VDD VDDQ
XDM_DQ2 C22 IO IO M20 IROW11 IMOT1 U5 IO IO L3 CPU_A14
F XDM_CKE 2 7 27 VDD VDDQ 43
XDM_DQ15 E18 IO/VRP2 IO M19 XEA8 CPU_D8 Y2 IO/VRN6 IO L4 CPU_A13
XDM_A0 3 6 VDDQ 49
XDM_DQ14 F18 IO/VRN2 IO M18 IROW2 CPU_D10 Y1 IO/VRP6 IO L5 CPU_D14
XDM_A1 4 5 38 CLK
XDM_DQ3 D21 IO IO/VREF3 M17 IROW0 IESCAN V4 IO IO/VREF7 K1 CPU_D2
XDM_DQ4 D22 IO/VREF2 IO N17 IROW4 U16 33 37 IPROBE V3 IO/VREF6 IO K2 CPU_D5
CKE
XDM_DQ13 E19 IO IO N22 XARDY XDM_A2 1 8 ITIMING W2 IO IO K3 CPU_A23
DQ0 2
XDM_DQ1 E20 IO IO N21 IROW3 XDM_A3 2 7 CPU_A6 W1 IO IO K4 CPU_D12
23 A0 DQ1 4
XDM_DQ5 E21 IO IO N20 XED8 XDM_A4 4 5 IECG U4 IO IO L6 CPU_D4
24 A1 DQ2 5
E22 N19 3 6 U3 K6
XDM_DQ6 IO IO XED9 XDM_A5 25 A2 DQ3 7 CPU_A7 IO IO TB1
F19 N18 V2 K5
XDM_DQ12 IO IO XED10
U24 33
26 A3 DQ4 8 CPU_A10 IO IO TB2
F20 P18 V1 J5
XDM_DQ11 IO IO XED11
4 5 29 A4 DQ5 10 CPU_D11 IO IO TB3
F21 P22 XDM_A6 U2 J1
XDM_DQ7 IO IO/VREF3 XEA12
3 6 30 A5 DQ6 11 CPU_SIZ0 IO IO/VREF7 TB4
F22 P21 XDM_A7 U1 J2
XDM_DQML IO/VREF2 IO XEA3 31 13 CPU_A8 IO/VREF6 IO CPU_D7
2 7 A6 DQ7
G18 P20 XDM_A8 T5 J3
XDM_DQ10 IO IO XEA19 32 42 INT7 IO IO CPU_A4
1 8 A7 DQ8
H18 P19 XDM_A9 R5 J4
XDM_A11 IO IO 33 44 ITBASE IO IO CPU_A5
A8 DQ9
XDM_DQ8 G19 IO IO R22 IENCLA U23 IPOS T4 IO IO H1 CRT_CLK
33 34 A9 DQ10 45
XDM_DQ9 G20 IO IO R21 IENCLB CPU_A9 T3 IO IO H2 CPU_D0
XDM_A10 1 8 22 A10 DQ11 47
XDM_WE G21 IO IO R20 XEA16 CPU_D9 T2 IO IO H3 CPU_D6
XDM_A11 3 6 35 A11 DQ12 48
E XDM_DQMH G22 IO IO R19 XEA5 INT6 T1 IO IO H4 CPU_FC2
XDM_A12 2 7 36 NC/(A12) DQ13 50
XDM_A0 H19 IO IO/VREF3 R18 FSWITCH R4 IO IO/VREF7 J6 CPU_A12
4 5 21 BA1 DQ14 51
XDM_CKE H20 IO/VREF2 IO P17 IROW6 IMOT0 R3 IO/VREF6 IO H5 CPU_A17
20 BA0 DQ15 53
XDM_CS H21 IO IO T22 IENCRA CPU_A0 R2 IO IO G1 INT5
XDM_CAS H22 IO IO T21 IENCRB CPU_RW R1 IO IO G2 INT4
18 RAS DQMH 39
XDM_A6 J17 IO IO T20 XED12 CPU_DSACK0 P6 IO IO G3 INT1
17 CAS DQML 15
XDM_A8 J18 IO IO T19 GRA12 U15 33 16 CPU_FC0 P5 IO IO G4 INT3
WE
XDM_A10 J19 IO IO U22 XED13 XDM_BA1 4 5 CPU_A21 P4 IO IO F1 CRT_BLANK
19 CS
XDM_A1 J20 IO IO U21 GRA11 XDM_BA0 3 6 CPU_A22 P3 IO IO F2 CPU_SIZ1
VSSQ 6
XDM_RAS J21 IO IO/VREF3 U20 XEA14
TB27 XDM_RAS 2 7 CPU_DS P2 IO IO/VREF7 F3 CPU_FC3
28 VSS VSSQ 12
XDM_BA0 J22 IO/VREF2 IO U19 XEA15 XDM_CAS 1 8 CPU_D1 P1 IO/VREF6 IO F4 INT2
41 VSS VSSQ 46
XDM_A5 K17 IO IO T18 XDSP_EINT4 CPU_DSACK1 N6 IO IO G5 CPU_FC1
54 VSS VSSQ 52
XDM_A7 K18 IO IO U18 IROW7 U14 33 CPU_A20 N5 IO IO F5 CPU_A19
XDM_A9 K19 IO IO V22 IROW5 XDM_WE 2 7 CPU_D3 N4 IO IO E1
XDM_A12 K20 IO IO V21 XED14 XDM_CS 4 5 CPU_D13 N3 IO IO E2
XDM_BA1 K21 IO IO V20 XED15
TB28 XDM_DQML 1 8 CPU_A18 N2 IO IO E3 MNYIRQ
XDM_A2 K22 IO IO V19 XDM_DQMH 3 6 CPU_D15 N1 IO IO E4 BRDREV4
D XDM_A4 L17 IO IO/VREF3 W22 XDSP_EINT5 CPU_AS M6 IO IO/VREF7 D1 BRDREV0
XDM_A3 L18 IO/VREF2 IO W21 IROW15 U20 33 CPU_A16 M5 IO/VREF6 IO D2 BRDREV1
XEA2 L19 IO IO/VRP3 Y22 IROW13 XDM_DQ15 1 8 CPU_A15 M4 IO IO/VRN7 C1 BRDREV2
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

L20 Y21 2 7 M3 C2
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

IROW12 IO IO/VRN3 XEA20 XDM_DQ14 CPU_A11 IO IO/VRP7 BRDREV3

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

L21 IO IO W20 XDM_DQ13 3 6 CPU_A2 M2 IO IO E5 BRDREV5

IROW9 L22 IO IO AA20 XEA21 XDM_DQ12 4 5 CPU_A3 M1 IO IO E6 PANPOS
TRKYB
TRKYA
+3V3

+3V3

+3V3

+3V3
L16 VCCOBank2 VCCOBank3 T17 U21 T6 VCCOBank6 VCCOBank7 L7
TRKXB 33
K16 VCCOBank2 VCCOBank3 R17 R6 VCCOBank6 VCCOBank7 K7
TRKXA XDM_DQ11 1 8
J16 VCCOBank2 VCCOBank3 P16 P7 VCCOBank6 VCCOBank7 J7
XDM_DQ10 2 7
H17 N16 N7 H6
6
5
7
8

VCCOBank2 VCCOBank3 3 6 VCCOBank6 VCCOBank7

XDM_DQ9
G17 VCCOBank2 VCCOBank3 M16 U18 XDM_DQ8 4 5
M7 VCCOBank6 VCCOBank7 G6

R11 10K
+3V3
U13 33
BUZZER 4 5
XDM_DQ7
1K00 XDM_DQ6 3 6
3
4
2
1

2 7 R90 R84 R88 R95 R92 R86

XDM_DQ5
22K 22K 22K 22K 22K 22K
C ALIMENTAZIONI IMPLICITE XDM_DQ4 1 8
----------------------- +3V3
NET: +1V5 U12 33
BRDREV0
--------- 4 5
XDM_DQ3
U61.U17 U61.T8 U61.H16 U61.G8 BRDREV1
U61.U6 U61.T7 U61.H7 U61.G7 XDM_DQ2 3 6
BRDREV2
U61.T16 U61.R16 U61.G16 U61.F17 2 7
XDM_DQ1
U61.T15 U61.R7 U61.G15 U61.F6 BRDREV3
XDM_DQ0 1 8
BRDREV4
NET: +3V3
--------- BRDREV5
U96.20 UP5.8 U47.R8 U47.E13 U73.86 U8.R14 U8.K14 R91 R85 R89 R96 R93 R87
U72.20 U91.14 U47.R7 U47.E11 U73.74 U8.R13 U8.J6
U82.20 UP3.37 U47.R6 U47.E9 U73.68 U8.R10 U8.H14 22K 22K 22K 22K 22K 22K +3V3
U66.14 UP2.37 U47.R3 U47.E8 U73.59 U8.R9 U8.F6
U75.20 UP1.37 U47.P15 U47.E7 U73.50 U8.R8 U8.E13
ALIMENTAZIONI MODIFICATE Componenti NON MONTATI
U71.20 U64.16 U47.M14 U47.B8 U73.41 U8.R7 U8.E11
------------------------ -----------------------
U54.14 U69.14 U47.L15 U73.140 U73.31 U8.R6 U8.E9
U59.33 U47.U15 U47.L6 U73.130 U73.19 U8.R3 U8.E8
NET: +1V5DSP
C140 EQUIP_LEVEL "2" C324 EQUIP_LEVEL "2" L1
U59.11 U47.R14 U47.K14 U73.119 U73.7 U8.P15 U8.E7
------------
C141 EQUIP_LEVEL "2" C325 EQUIP_LEVEL "2" U57 Board Revision 100U
U60.33 U47.R13 U47.J6 U73.110 U70.14 U8.M14 U8.B8
U47.U13 U47.N17 U47.J5 U47.F10
C153 EQUIP_LEVEL "2" C326 EQUIP_LEVEL "2" ADV7125-140
U60.11 U47.R10 U47.H14 U73.94 UP4.37 U8.L15 C173 EQUIP_LEVEL "2" C327 EQUIP_LEVEL "2"
U47.P12 U47.M15 U47.J2 U47.F9
UP6.8 U47.R9 U47.F6 U73.92 U8.U15 U8.L6 C174 EQUIP_LEVEL "2" J1 EQUIP_LEVEL "2" 24 13
U47.P9 U47.M5 U47.H15 U47.E14 CRT_CLK CLK VAA
C175 EQUIP_LEVEL "2" J2 EQUIP_LEVEL "2"
U47.P6 U47.J15 U47.G5 U47.B12 29
C176 EQUIP_LEVEL "2" L1 EQUIP_LEVEL "2" 11 VAA C140 C178 C174 C173 C153 C141 C175 C176
B NET: GND CRT_BLANK BLANK C177
C177 EQUIP_LEVEL "2" P14 EQUIP_LEVEL "2" 30
-------- NET: +3V3 12 VAA
U96.10 U47.M9 U47.B13 U61.J13 U73.18 U36.J14 U8.K1 ---------
C178 EQUIP_LEVEL "2" P17 EQUIP_LEVEL "2" SYNC R81 100N 100N 10N 10N 10N 100N 100N 100N 10U
C202 EQUIP_LEVEL "2" R130 EQUIP_LEVEL "2" 560
U72.10 U47.M8 U47.B11 U61.J12 U73.6 U36.J13 U8.J13 U74.P9 U74.M13 U74.G3 U74.C7
C243 EQUIP_LEVEL "2" R133 EQUIP_LEVEL "2" 37
U82.10 U47.M7 U47.A13 U61.J11 U70.7 U36.J12 U8.J12 U74.P7 U74.M3 U74.F13 U74.C4 1K00 41 Rset
C257 EQUIP_LEVEL "2" R136 EQUIP_LEVEL "2" CRT_RED0 R0
U66.7 U47.L13 U47.A11 U61.J10 UP4.46 U36.J11 U8.J11 U74.N9 U74.K14 U74.D2 U74.B11 36
C288 EQUIP_LEVEL "2" R60 EQUIP_LEVEL "2" 42 Vref
U75.10 U47.L12 U61.AB22 U61.J9 UP4.27 U36.J10 U8.J10 U74.N4 U74.K3 U74.C14 CRT_RED1 R1
C289 EQUIP_LEVEL "2" R61 EQUIP_LEVEL "2" 35
U71.10 U47.L11 U61.AB1 U61.D19 U36.AB22 U36.J9 U8.J9
C290 EQUIP_LEVEL "2" R62 EQUIP_LEVEL "2" R60 CRT_RED2 43 R2
COMP
U54.7 U47.L10 U61.AA21 U61.D4 U36.AB1 U36.D19 U8.J8 NET: +1V5X
C291 EQUIP_LEVEL "2" R81 EQUIP_LEVEL "2" 44
U59.34 U47.L9 U61.AA2 U61.C20 U36.AA21 U36.D4 U8.J7 ---------- CRT_RED3 R3
C292 EQUIP_LEVEL "2" R84 EQUIP_LEVEL "2"
U59.12 U47.L8 U61.Y20 U61.C3 U36.AA2 U36.C20 U8.H13 U36.U17 U36.T8 U36.H16 U36.G8 45
C293 EQUIP_LEVEL "2" R87 EQUIP_LEVEL "2" CRT_RED4 R4
U60.34 U47.L7 U61.Y3 U61.B21 U36.Y20 U36.C3 U8.H12 U36.U6 U36.T7 U36.H7 U36.G7
C294 EQUIP_LEVEL "2" R88 EQUIP_LEVEL "2" 46
U60.12 U47.K13 U61.W19 U61.B2 U36.Y3 U36.B21 U8.H11 U36.T16 U36.R16 U36.G16 U36.F17
C295 EQUIP_LEVEL "2" R90 EQUIP_LEVEL "2"
CRT_RED5 R5
P17 R62
UP6.5 U47.K12 U61.W4 U61.A22 U36.W19 U36.B2 U8.H10 U36.T15 U36.R7 U36.G15 U36.F6 47 IOR 34 75
C296 EQUIP_LEVEL "2" R92 EQUIP_LEVEL "2" CRT_RED6 R6
UP5.5 U47.K11 U61.P14 U61.A1 U36.W4 U36.A22 U8.H9 1 2
C297 EQUIP_LEVEL "2" R95 EQUIP_LEVEL "2" 48
U98.3 U47.K10 U61.P13 U74.N13 U36.P14 U36.A1 U8.H8 NET: +3V3AUX CRT_RED7 R7
C298 EQUIP_LEVEL "2" U57 EQUIP_LEVEL "2" 33 3 4
U91.7 U47.K9 U61.P12 U74.N10 U36.P13 U8.V12 ------------ IOR
U8.H7 C299 EQUIP_LEVEL "2" U74 EQUIP_LEVEL "2"
U57.40 U47.K8 U61.P11 U74.N7 U36.P12 U8.N13 U61.AB11 U61.L1 U36.AB11 U36.L1 5 6
U57.39 U47.K7 U61.P10 U74.N3 U36.P11 U8.N12
U8.G13
U61.AA22 U61.B22 U36.AA22 U36.B22
C300 EQUIP_LEVEL "2" UP5 EQUIP_LEVEL "2"
CRT_GREEN0 3 75 R61
U8.G12 C301 EQUIP_LEVEL "2" UP6 EQUIP_LEVEL "2" G0 7 8
U57.26 U47.K1 U61.P9 U74.M2 U36.P10 U8.N11 U61.AA1 U61.B1 U36.AA1 U36.B1 4 R130 75
U8.G11 C302 EQUIP_LEVEL "2" Y2 EQUIP_LEVEL "2" CRT_GREEN1 G1
U57.25 U47.J13 U61.N14 U74.K13 U36.P9 U8.N10 U61.M22 U61.A12 U36.M22 U36.A12 32 9 10
U8.G10 C303 EQUIP_LEVEL "2" 5 IOG
U57.15 U47.J12 U61.N13 U74.J3 U36.N14 U8.N9 CRT_GREEN2 G2
U8.G9 C304 EQUIP_LEVEL "2"
U57.14 U47.J11 U61.N12 U74.H13 U36.N13 U8.N8 NET: +1V5XDSP 6
U8.G8 C305 EQUIP_LEVEL "2" CRT_GREEN3 G3
U57.2 U47.J10 U61.N11 U74.H3 U36.N12 U8.N7 ------------- 31
U8.G7 C306 EQUIP_LEVEL "2" 7 IOG
U57.1 U47.J9 U61.N10 U74.G13 U36.N11 U8.M13 U8.U13 U8.N17 U8.J5 U8.F10 CRT_GREEN4
TB17
TB18
TB19
TB20
TB25
TB26

U8.E12 C307 EQUIP_LEVEL "2" G4

TB7
TB8

UP3.46 U47.J8 U61.N9 U74.G2 U36.N10 U8.M12 U8.P12 U8.M15 U8.J2 U8.F9 8 75
U8.C13 C308 EQUIP_LEVEL "2" CRT_GREEN5 G5
A UP3.27 U47.J7 U61.M14 U74.D13 U36.N9 U8.M11
U8.C12
U8.P9 U8.M5 U8.H15 U8.E14
C309 EQUIP_LEVEL "2" 9 R133
UP2.46 U47.H13 U61.M13 U74.D3 U36.M14 U8.M10 U8.P6 U8.J15 U8.G5 U8.B12 CRT_GREEN6 G6
U8.C10 C310 EQUIP_LEVEL "2"
837 0147 042 Rev.A

UP2.27 U47.H12 U61.M12 U74.C11 U36.M13 U8.M9 10 IOB 28

U8.B13 C311 EQUIP_LEVEL "2" CRT_GREEN7 G7
UP1.46 U47.H11 U61.M11 U74.C8 U36.M12 U8.M8
U8.B11 C312 EQUIP_LEVEL "2"
UP1.27 U47.H10 U61.M10 U74.C5 U36.M11 U8.M7
FORM:

U8.A13 C313 EQUIP_LEVEL "2" 27

U64.8 U47.H9 U61.M9 U73.139 U36.M10 U8.L13 16 IOB
U8.A11 C314 EQUIP_LEVEL "2" CRT_BLUE0 B0
U69.7 U47.H8 U61.L14 U73.129 U36.M9 U8.L12 75
C315 EQUIP_LEVEL "2" 17
U47.V12 U47.H7 U61.L13 U73.127 U36.L14 U8.L11 CRT_BLUE1 B1
C316 EQUIP_LEVEL "2"
U47.N13 U47.G13 U61.L12 U73.118 U36.L13 U8.L10
C317 EQUIP_LEVEL "2" CRT_BLUE2 18 B2 R136
U47.N12 U47.G12 U61.L11 U73.109 U36.L12 U8.L9
C318 EQUIP_LEVEL "2" 19
U47.N11 U47.G11 U61.L10 U73.96 U36.L11 U8.L8 CRT_BLUE3 B3
C319 EQUIP_LEVEL "2"
U47.N10 U47.G10 U61.L9 U73.88 U36.L10 U8.L7 20
C320 EQUIP_LEVEL "2" CRT_BLUE4 B4
U47.N9 U47.G9 U61.K14 U73.73 U36.L9 U8.K13
C321 EQUIP_LEVEL "2" 21
U47.N8 U47.G8 U61.K13 U73.67 U36.K14 U8.K12 CRT_BLUE5 B5 +3V3
C322 EQUIP_LEVEL "2"
U47.N7 U47.G7 U61.K12 U73.58 U36.K13 U8.K11 22
SHEET C323 EQUIP_LEVEL "2" CRT_BLUE6 B6 DESCRIPTION:
U47.M13 U47.E12 U61.K11 U73.54 U36.K12 U8.K10 "7350" PROCESSORS BOARD
A2 U47.M12
U47.M11
U47.C13
U47.C12
U61.K10
U61.K9
U73.49
U73.40
U36.K11
U36.K10
U8.K9
U8.K8
CRT_BLUE7 23 B7 PSAVE 38
Document Revision: SHEET: OF:

by EpD
U47.M10 U47.C10 U61.J14 U73.30 U36.K9 U8.K7
Number: 950 1218 000 SE C 10 10
 1 2 3 4 5 6 7 8 9 10 11
+3V3 +3V3
+3V3

R176
330U
L8
U18

R209

4K7
U7

4K7
TMS320VC5502 U16
74LCX00
60 PVDD PSENSE 61 CY7C1327 EMIFCE3 1
F EMIFCLK2 3 UP3
C242 C241 89 CLK VDDQ 4 EMIFA19 2 U7
CLK40A 63 152 EMIFD0 11 29F040-120
470N 47N X2/CLKIN D0/HPID0/EMIFD0 VDDQ 74LCX00 EAOE/ESOE 24
151 EMIFD1 83 20 4 OE
D1/HPID1/EMIFD1 ADV VDDQ
EMIFD2 6 22 CE
R251 62 X1 D2/HPID2/EMIFD2 150 84 ADSP VDDQ 27
5
EMIFD3 EARE/ESADS 31 WE
D3/HPID3/EMIFD3 149 85 ADSC VDDQ 54
33
TMSCLK 54 147 EMIFD4 61
CLKOUT D4/HPID4/EMIFD4 VDDQ
146 EMIFD5 EMIFA0 37 70 EMIFA0 12 13 EMIFD0

2
D5/HPID5/EMIFD5 A0 VDDQ A0 O0
EMIFA0 112 145 EMIFD6 EMIFA1 36 77 EMIFA1 11 14 EMIFD1
R227 A2/HPIA0/EMIFA2 D6/HPID6/EMIFD6 A1 VDDQ A1 O1
47 EMIFA1 111 143 EMIFD7 EMIFA2 35 EMIFA2 10 15 EMIFD2
A3/HPIA1/EMIFA3 D7/HPID7/EMIFD7 A2 A2 O2
C186 EMIFA2 110 142 EMIFD8 EMIFA3 34 EMIFA3 9 17 EMIFD3
A4/HPIA2/EMIFA4 D8/HPID8/EMIFD8 A3 +3V3 A3 O3
EMIFA3 108 140 EMIFD9 EMIFA4 33 EMIFA4 8 18 EMIFD4
47P A5/HPIA3/EMIFA5 D9/HPID9/EMIFD9 A4 A4 O4
EMIFA4 107 139 EMIFD10 EMIFA5 32 EMIFA5 7 19 EMIFD5
2 A6/HPIA4/EMIFA6 D10/HPID10/EMIFD10 A5 A5 O5
EMIFA5 106 138 EMIFD11 EMIFA6 100 EMIFA6 6 20 EMIFD6

R184
A7/HPIA5/EMIFA7 D11/HPID11/EMIFD11 A6 A6 O6

1K00
+3V3 EMIFA6 104 137 EMIFD12 EMIFA7 99 EMIFA7 5 21 EMIFD7
A8/HPIA6/EMIFA8 D12/HPID12/EMIFD12 A7
EMIFD0 R16 A7 O7
EMIFA7 103 136 EMIFD13 EMIFA8 82 58 EMIFA8 27
A9/HPIA7/EMIFA9 D13/HPID13/EMIFD13 A8 DQ0 0 A8
EMIFD1
EMIFA8 102 135 EMIFD14 EMIFA9 81 59 EMIFA9 26
A10/HPIA8/EMIFA10 D14/HPID14/EMIFD14 A9 DQ1 A9
R216 EMIFA9 101 134 EMIFD15 EMIFA10 80 62
EMIFD2
EMIFA10 23
A11/HPIA9/EMIFA11 D15/HPID15/EMIFD15 A10 DQ2 A10
E 4K7 EMIFA10 99 133 EMIFD16 EMIFA11 44 63
EMIFD3 R17 EMIFA11 25
A12/HPIA10/EMIFA12 D16/PGPIO4/EMIFD16 A11 DQ3 A11
EMIFD4 0
EMIFA11 98 132 EMIFD17 EMIFA12 45 68 (*) EMIFA12 4
A13/HPIA11/EMIFA13 D17/PGPIO5/EMIFD17 A12 DQ4 A12
EMIFD5
EMIFA12 96 131 EMIFD18 EMIFA13 46 69 EMIFA13 28
R218 A14/HPIA12/EMIFA14 D18/PGPIO6/EMIFD18 A13 DQ5
EMIFD6
A13
EMIFA13 95 129 EMIFD19 EMIFA14 47 72 EMIFA14 29
4K7 A15/HPIA13/EMIFA15 D19/PGPIO7/EMIFD19 A14 DQ6 A14
EMIFD7 EMIFA18
EMIFA14 93 128 EMIFD20 EMIFA15 48 73 EMIFA15 3
A16/HPIA14/EMIFA16 D20/PGPIO8/EMIFD20 A15 DQ7 A15
EMIFD8
EMIFA15 92 127 EMIFD21 EMIFA16 49 8 EMIFA16 2
R219 A17/HPIA15/EMIFA17 D21/PGPIO9/EMIFD21 A16 DQ8
EMIFD9
+3V3 R14 A16
EMIFA16 90 126 EMIFD22 EMIFA17 50 9 EMIFA17 30
A18/PGPIO0/EMIFA18 D22/PGPIO10/EMIFD22 A17 DQ9 0 A17
4K7 EMIFD10
EMIFA17 89 125 EMIFD23 43 12 1
A19/PGPIO1/EMIFA19 D23/PGPIO11/EMIFD23 NC(A18) DQ10 A18
EMIFD11

R183
EMIFA18 88 123 EMIFD24 88 13
A20/PGPIO2/EMIFA20 D24/PGPIO12/EMIFD24 GW DQ11

1K00
EMIFD12
EMIFA19 87 A21/PGPIO3/EMIFA21 D25/PGPIO13/EMIFD25 122 EMIFD25
DQ12 18 R15
R220 EMIFA[0:19] 120 EMIFD26 EAWE/ESWE 87 19
EMIFD13 UP2
D26/PGPIO14/EMIFD26 BWE DQ13 0
4K7 EMIFD14 (*)
TMSINT0 8 INT0 D27/PGPIO15/EMIFD27 119 EMIFD27 EMIFBE0 93 BWS0 DQ14 22 29F040-120
EMIFD15
TMSINT1 10 118 EMIFD28 EMIFBE1 94 23 24
INT1 D28/PGPIO16/EMIFD28 +3V3 BWS1 DQ15 OE
R221 TMSINT2 11 INT2 D29/PGPIO17/EMIFD29 116 EMIFD29 22 CE
4K7 TMSINT3 13 115 EMIFD30 31 31
INT3 D30/PGPIO18/EMIFD30 MODE WE
TMSINT[0:3]
TMSNMI 14 114 EMIFD31
NMI/WDTOUT D31/PGPIO19/EMIFD31 (*) = Non montare
EMIFD[0:31]
TMSIACK 15 EMIFCE0 98 74
R217 IACK CE1 DP0 EMIFA0 12 A0 O0 13 EMIFD8
D RESET 162 RESET C0/PGPIO20/ARE 86 EARE/ESADS R246 97 CE2 DP1 24 EMIFA1 11 14 EMIFD9
4K7 A1 O1
85 EAOE/ESOE 4K7 92
C1/PGPIO21/AOE CE3 EMIFA2 10 15 EMIFD10
A2 O2
5 84 EAWE/ESWE
GPIO0 C2/PGPIO22/AWE EMIFA3 9 17 EMIFD11
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

R213
The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

R215

R197
EAOE/ESOE 86 A3 O3
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

4 82 EARDY OE

1K00

1K00
GPIO1 C3/PGPIO23/ARDY EMIFA4 8 18 EMIFD12
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

FREADY A4 O4

R83
1K00

1K00
3 81 EMIFCE0
GPIO2 C4/PGPIO24/CE0 EMIFA5 7 19 EMIFD13
2 0 64 A5 O5
2 79 EMIFCE1 ZZ
GPIO4 C5/PGPIO25/CE1 EMIFA6 6 20 EMIFD14
A6 O6
R212 1 GPIO6 C6/PGPIO26/CE2 78 EMIFCE2 R245 EMIFA7 5 21 EMIFD15
A7 O7
1K00 R252 176 GPIO7 C7/PGPIO27/CE3 72 EMIFCE3
EMIFA8 27
EMIFCE[0:3] A8
XCCLK 55 71 EMIFBE0 EMIFD[0:15]
XF C8/PGPIO28/BE0 EMIFA9 26 A9
70 EMIFBE1
R199 33 C9/PGPIO29/BE1 EMIFA10 23 A10
SCLKR0 17 69 EMIFBE2
1K00 CLKR0 C10/PGPIO30/BE2 EMIFA11 25 A11
SDR0 18 68 EMIFBE3
DR0 C11/PGPIO31/BE3 U19 EMIFA12 4
EMIFBE[0:3] A12
SFSR0 19 67
R232 FSR0 C12/PGPIO32/SDCKE
CY7C1327 EMIFA13 28 A13
SCLKX0 20 66
4K7 CLKX0 C13/PGPIO33/SOE EMIFA14 29
89 4 A14
SDX0 22 58 TMSHOLD 4K7 CLK VDDQ
DX0 C14/PGPIO34/HOLD EMIFA15 3
11 A15
SFSX0 23 57 TMSHOLDA VDDQ
R229 FSX0 C15/PGPIO35/HOLDA R253 83 20
EMIFA16 2 A16
SCLKR1 24 ADV VDDQ
CLKR1 EMIFA17 30
4K7 84 27 A17
SDR1 25 74 ADSP VDDQ
C DR1 ECLKIN 1
85 54 A18
SFSR1 26 FSR1 ECLKOUT1 76 TB31 ADSC VDDQ
R234 SCLKX1 EMIFCLK2 VDDQ 61 EMIFA[0:18]
28 CLKX1 ECLKOUT2 75
EMIFA0 37 70
1K00 SDX1 27 64 A0 VDDQ
DX1 EMIFCLKS
R198
EMIFA1 36 77
SFSX1 30 A1 VDDQ
FSX1
EMIFA2 35
47

XDONE 31 175 HD0 A2

DR2 HD0/PGPIO36
R231 XPROG 32 173 HD1
EMIFA3 34 A3
DX2 HD1/PGPIO37
4K7 C130 EMIFA4 33
172 HD2 A4
HD2/PGPIO38 UP1
EMIFA5 32
FLASH 38 170 HD3 33P A5
SP0/GPIO3/CLKX2 HD3/PGPIO39
SP1 37 169 HD4
EMIFA6 100 A6 AM29LV160
SP1/UARTTX/CLKR2 HD4/PGPIO40
EMIFA7 99 EMIFA0 25 29 EMIFD0
XINIT 35 167 HD5 A7 A0 DQ0
R233 SP2/GPIO5/FSX2 HD5/PGPIO41
EMIFA8 82 58
EMIFD16
EMIFA1 24 31 EMIFD1
SP3 34 166 HD6 A8 DQ0 A1 DQ1
4K7 SP3/UARTRX/FSR2 HD6/PGPIO42 EMIFD17
EMIFA9 81 59 EMIFA2 23 33 EMIFD2
40 164 HD7 A9 DQ1 A2 DQ2
SCL HD7/PGPIO43 EMIFD18
EMIFA10 80 62 EMIFA3 22 35 EMIFD3
41 HD[0:7] A10 DQ2 A3 DQ3
SDA EMIFD19
R238 43 HAS
EMIFA11 44 A11 DQ3 63 EMIFA4 21 A4 DQ4 38 EMIFD4
HC0/PGPIO44/HAS EMIFD20
1K00 EMIFA12 45 68 EMIFA5 20 40 EMIFD5
160 42 XBUSY A12 DQ4 A5 DQ5
TCK HC1/PGPIO45/HBIL EMIFD21
EMIFA13 46 69 EMIFA6 19 42 EMIFD6
158 A13 DQ5 A6 DQ6
TDI EMIFD22
R242 156 46 HCNTL0 4K7
EMIFA14 47 A14 DQ6 72 EMIFA7 18 A7 DQ7 44 EMIFD7
TDO HCNTL0 EMIFD23
B 1K00 EMIFA15 48 73 EMIFA8 8 30 EMIFD8
161 45 HCNTL1 A15 DQ7 A8 DQ8
TMS HCNTL1 R249 EMIFA16 49 8
EMIFD24
EMIFA9 7 32 EMIFD9
159 44 XCS A16 DQ8 A9 DQ9
TRST HCS EMIFD25
R211 155 48 XWR
EMIFA17 50 A17 DQ9 9 EMIFA10 6 A10 DQ10 34 EMIFD10
EMU0 HR/W EMIFD26
4K7 43 12 EMIFA11 5 36 EMIFD11
154 51 HDS1 NC(A18) DQ10 A11 DQ11
EMU1 HDS1 EMIFD27
88 13 EMIFA12 4 39 EMIFD12
49 HDS2 EMIFA[0:17] GW DQ11 A12 DQ12
HDS2 EMIFD28
18 EMIFA13 3 41 EMIFD13
HRDY 52 HRDY R256 DQ12
EMIFD29
A13 DQ13
87 19 EMIFA14 2 43 EMIFD14
TIMER0 7 59 HINT 4K7 BWE DQ13 A14 DQ14
4K7 TIM0 HINT EMIFD30
EMIFBE2 93 22 EMIFA15 1 45 EMIFD15
TIMER1 6 163 BWS0 DQ14 A15 DQ15(A-1)
TIM1 HPIENA EMIFD31
R210 EMIFBE3 94 BWS1 DQ15 23 EMIFA16 48 A16
EMIFD[0:15]
+3V3 1K00 EMIFBE[0:3] EMIFA17 17 15 FREADY
EMIFD[0:31] A17 RY/BY
31 EMIFA18 16
R206 MODE A18
EMIFA19 9
R243

R244

R248

A19
1K00

1K00

98 74 EMIFA[0:19]
4K7

CE1 DP0
R196

R186

R185
2

2 97 24 EMIFCE1 26
CE2 DP1 CE
4K7

4K7
R230

U7
47

92 EAOE/ESOE 28
CE3 OE
4K7

C104 J8
R200 R173 EAWE/ESWE 11 WE 74LCX00
86 OE RESET 13
47P 4K7 4K7 12 RESET 11

R266

R237
2 1
47 12

1K00

1K00
A 2 BYTE

+3V3
64
R85

4 3
1K00

ZZ
837 0147 042 Rev.A

6 5 U7
8 7 74LCX00
FORM:

4K7 10
10 9 8
R444 12 11
R180 9
47 14 13

VICINO PIN U18

C448
33P
SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:
"7350" VIDEO BOARD
A2 GAMBACCIANI DONNINI ANDREUCCETTI 30/03/05
Document Revision: SHEET: OF:

by EpD
Nr. O.V.:
E.O.C. EVENT: IND200500163 Number: 950 1219 000 SE C 1 10
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
 1 2 3 4 5 6 7 8 9 10 11
+3V3

R205

R208

R195

R194

R204
1K00

1K00
4K7

4K7

4K7
TB19

F TMSINT[0:3]

TB1
VXD[0:7]

TB7
VMD[0:15]
LA[0:4]
U15 U15 U15 U15
XC2S300 XC2S300 XC2S300 XC2S300
MADD[0:12]
MDAT[0:15]
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
MBADD[0:1] R193
33
MDAT0 A3 A11 MCLK XBUSY C21 L22 EMIFD15 VMA14 U12 U9 VMA28 VXD0 M1 C1 ECGSCLK
I/O GCK2,I I/O(DOUT,BUSY) I/O(TRDY) I/O I/O I/O(TRDY) I/O
MDAT1 A4 A12 MCS HD0 C22 M17 EMIFBE3 VMA8 U13 U10 VMA22 VXD4 M2 C2 PANPOS
I/O I/O(DLL) I/O(DIN,D0) I/O I/O I/O I/O I/O
MDAT2 A5 A13 MBADD0 SFSR1 D20 M18 EAWE/ESWE VMA2 U14 U11 VMA17 VXINIT1 M3 D1 ECGCONV
I/O I/O I/O I/O I/O I/O I/O I/O
MDAT3 A6 I/O I/O A14 MBADD1 EMIFD6 D21 I/O(VREFBank2) I/O M19 EMIFA12 VMA15 V12 I/O I/O V6 LD3 TB8 M4 I/O I/O D2
MDAT4 A7 A15 MADD10 EMIFD4 D22 M20 EMIFD23 VMA9 V13 V7 LA4 BRD0 M5 D3
I/O I/O I/O I/O I/O(VREFBank4) I/O I/O I/O
MDAT5 A8 A16 MADD0 SP3 E19 M21 EMIFD19 VMA3 V14 V8 LDEN BRD1 M6 E1 ECGDATA
E I/O I/O I/O I/O I/O I/O(VREFBank5) I/O I/O
MDAT6 A9 A17 MADD1 SFSX1 E20 M22 EMIFD18 VMD13 V15 V9 VMA29 VXD1 N1 E2
I/O I/O I/O I/O I/O(VREFBank4) I/O I/O I/O(VREFBank7)
MDAT7 A10 A18 MADD2 EMIFD3 E21 N17 HD4 VMD8 V16 V10 VMA23 VXD5 N2 E3
I/O I/O I/O I/O(D4) I/O I/O(VREFBank5) I/O I/O
MDAT15 B3 A19 MADD3 EMIFD1 E22 N18 HINT VMD3 V17 V11 VMA18 VXINIT0 N3 F1
I/O I/O I/O I/O(VREFBank3) I/O I/O I/O(VREFBank6) I/O
MDAT14 B4 A20 XWR HAS F18 N19 EMIFA0 VMA16 W12 W5 LD7 VXBUSY N4 F2
I/O I/O(WRITE) I/O I/O I/O I/O I/O I/O(VREFBank7)

R192
2
MDAT13 B5 B12 MCKE SP1 F19 N20 EMIFA13 VMA10 W13 W6 LD2 BRWR N5 F3
I/O I/O I/O I/O I/O I/O I/O I/O

47
MDAT12 B6 B13 MADD11 EMIFCE3 F20 N21 EMIFD16 VMA4 W14 W7 LA3 BRCS N6 F4
I/O(VREFBank0) I/O(VREFBank1) I/O I/O I/O I/O I/O I/O
MDAT11 B7 B14 MADD9 EMIFD2 F21 N22 EMIFD17 VMD14 W15 W8 LSECG VXD2 P1 F5 C102
I/O I/O I/O(VREFBank2) I/O I/O I/O I/O I/O
MDAT10 B8 B15 MADD8 EMIFD5 F22 P17 TMSHOLDA VMD9 W16 W9 VMRW VXD6 P2 G1
I/O I/O I/O I/O I/O I/O I/O I/O 47P
MDAT9 B9 B16 MADD7 EMIFA10 G18 P18 HCNTL0 VMD4 W17 W10 VMA24 VXCS1 P3 G2
I/O I/O I/O I/O I/O I/O I/O I/O 2
MDAT8 B10 B17 MADD6 HDS1 G19 P19 EMIFA2 VMAUX1 W18 W11 VMA19 VXDONE1 P4 G3
I/O I/O I/O I/O I/O(VREFBank4) I/O I/O I/O
MCLK B11 I/O(DLL) I/O(VREFBank1) B18 MADD5 HDS2 G20 I/O I/O P20 EMIFA1 TB22 Y12 I/O(DLL) I/O Y5 LD6 P5 I/O I/O G4
0 C4 B19 MADD4 EMIFD7 G21 P21 EMIFD20 VMA11 Y13 Y6 LD1 LCDSLEEP P6 G5
I/O I/O I/O I/O I/O I/O I/O I/O
C5 B20 XCS EMIFD0 G22 P22 HD5 VMA5 Y14 Y7 LA2 VXD3 R1 H1
R69 I/O(VREFBank0) I/O(CS) I/O I/O(D5) I/O I/O I/O I/O
C6 C12 MCAS EAOE/ESOE H18 R18 HRDY VMD15 Y15 Y8 LSVIDEO VXD7 R2 H2
I/O I/O I/O(VREFBank2) I/O(VREFBank3) I/O I/O I/O I/O
C7 C13 MRAS HD1 H19 R19 HD6 VMD10 Y16 Y9 VMAS VXWRITE R3 H3
I/O I/O I/O(D1) I/O(D6) I/O I/O I/O(VREFBank6) I/O(VREFBank7)
C8 C14 MDQMH HD2 H20 R20 EMIFA3 VMD5 Y17 Y10 VMA25 VXDONE0 R4 H4
I/O I/O I/O(D2) I/O I/O(VREFBank4) I/O I/O I/O
MDQML C9 C15 SCLKX0 EMIFD8 H21 R21 EMIFD22 VMD0 Y18 Y11 VMA20 TIMING R5 H5
I/O I/O I/O I/O I/O I/O VXCCLK I/O I/O
D MWE C10 I/O I/O C16 TMSIACK EMIFD10 H22 I/O I/O R22 EMIFD21 PSTDO Y19 I/O I/O AA3 LD12 T1 I/O I/O J1 ECG_AUX2
C11 C17 SDR0 FREADY J17 T18 EMIFBE2 TMSCLK AA12 AA5 LD5 0 TRACE1 T2 J2
GCK3,I I/O I/O I/O GCK0/I I/O I/O I/O
D5 C18 SCLKX1 EMIFCE2 J18 T19 EMIFA4 VMA12 AA13 AA6 LD0 VXCS0 T3 J3
I/O I/O I/O I/O I/O I/O R82 I/O I/O
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

D6 I/O I/O D12 MADD12 EMIFA9 J19 I/O I/O T20 EMIFA5 VMA6 AA14 I/O I/O AA7 LA1 VXPROG T4 I/O I/O J4 TB6
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

TB2 D7 I/O I/O D13 TIMER0 EMIFA8 J20 I/O I/O(VREFBank3) T21 EMIFD24 VMA0 AA15 I/O I/O AA8 TCLKI ECG T5 I/O I/O J5 BRD6
D8 D14 EMIFBE0 EMIFD9 J21 T22 EMIFD25 VMD11 AA16 AA9 VMDS VID_HSYNC U1 J6 BRD7
I/O(VREFBank0) I/O I/O I/O I/O I/O I/O(VREFBank6) I/O
D9 D15 SFSX0 EMIFD11 J22 U18 EMIFD29 VMD6 AA17 AA10 VMA26 TRACE0 U2 K1 ECG_AUX1
I/O I/O(VREFBank1) I/O I/O I/O I/O I/O I/O
D10 I/O(VREFBank0) I/O D16 SCLKR1 HCNTL1 K17 I/O I/O U19 EMIFA7 VMD1 AA18 I/O I/O AA11 VMA21 LD15 U3 I/O I/O K2 TB5
D11 D17 SDR1 EMIFA14 K18 U20 EMIFA6 AA19 AB3 LD11 LD10 U4 K3
I/O I/O I/O(VREFBank2) I/O I/O I/O I/O I/O(VREFBank7)
E7 D18 SDX1 HD3 K19 U21 EMIFD26 PSTDI AA20 AB4 LD8 MCYCLE_STARTV1 K4
I/O I/O I/O(D3) I/O I/O I/O I/O I/O
E8 E12 TMSINT3 EMIFA15 K20 U22 EMIFD27 VMA13 AB13 AB5 LD4 V2 K5 BRD4
I/O I/O I/O I/O I/O I/O(VREFBank5) I/O(VREFBank6) I/O
E9 E13 SDX0 EMIFD14 K21 V19 EMIFA19 VMA7 AB14 AB6 LRW LD14 V3 K6 BRD5
I/O I/O I/O I/O I/O I/O I/O I/O
TIMER1 E10 E14 TMSNMI EMIFD12 K22 V20 EMIFA18 VMA1 AB15 AB7 LA0 LD9 V4 L1 ECG_AUX0
I/O I/O I/O I/O I/O I/O(VREFBank5) I/O I/O
TMSINT1 E11 E15 TMSINT0 EMIFBE1 L17 V21 EMIFD30 VMD12 AB16 AB8 VMBL TBASE W1 L2
I/O I/O I/O I/O I/O I/O I/O I/O
EARE/ESADS F9
I/O I/O(VREFBank1) E16 TB3 EMIFA17 L18 I/O I/O(VREFBank3) V22 EMIFD28 VMD7 AB17 I/O I/O AB9 VMBH PHCONV W2 I/O I/O L3
TMSINT2 F10 I/O I/O E17 SCLKR0 EMIFA11 L19 I/O I/O(INIT) W21 XINIT VMD2 AB18 I/O I/O AB10 VMA27 LD13 W3 I/O I/O L4 TB9
F11 I/O I/O F12 TB4 EMIFA16 L20 I/O I/O W22 EMIFD31 VMAUX0 AB19
I/O I/O(DLL) AB11 TMSCLK VID_VSYNC Y1 I/O I/O L5 BRD2
C F13 SFSR0 EMIFD13 L21 Y22 HD7 PSTMS AB20 AB12 CLK40B PHDATA Y2 L6 BRD3
I/O I/O(IRDY) I/O(D7) I/O GCK1,I I/O I/O(IRDY)
F14 TMSHOLD +3V3 +3V3 PSPROG AB21 +3V3
+3V3 I/O I/O +3V3

F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T9 N7 VCCOBank6 VCCOBank7 G6
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T10 P7 VCCOBank6 VCCOBank7 H6
G9 VCCOBank0 VCCOBank1 G13 J16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 J7
G10 VCCOBank0 VCCOBank1 G14 K16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7

TB21
HD[0:7]
TB20 +3V3
R175

EMIFD[0:31]
R181
2
47

47

EMIFA[0:19] VMA[0:29]
C87 C95
33P
33P LD[0:15]
2 R228
33
TB17 PSTCK U48
B R214
33
AD7302
BRD7 1 15
PHSCLK DB7(MSB) VDD
BRD6 2 DB6

R432
2
2 BRD5 3 16

R380
+3V3 DB5 REFin

47
BRD4 4

R84
TB10 DB4

4K7
47
C442 BRD3 5 19 LCDBRITE
DB3 VoutA
+3V3
47P
C337 BRD2 6 DB2
+3V3 TB18 56P BRD1 7 18 C443
2 DB1 VoutB
R179

R178

R177
BRD0 8 47N
U15 DB0(LSB)
R447
4K7

4K7

4K7

XC2S300 J1
0 TB16 BRCS 9 17
2

CS AGND
R430

XCCLK B22 E6 XTCK 1 2

R434

R433

CCLK TCK 10 WR
4K7

XPROG Y21 XVTDO 3 4

R446 R203
4K7

4K7

PROGRAM 11
J7 A/B
XDONE W20 5 6
0 DONE 33 12 PD
PSTCK 1 2 AA1 C19 XTDI 7 8
M0 TDI BRWR 13 LDAC
PSTDO 3 4 U5 A21 XVTDI 9 10
M1 TDO 14 20
CLR DGND

R415
PSTMS 5 6 AB2 E4 XTMS

2
M2 TMS
A 7 8

47
R223

PSTDI
837 0147 042 Rev.A

9 10
C439
1K00

47P
FORM:

SHEET DESCRIPTION:
"7350" VIDEO BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1219 000 SE C 2 10

 1 2 3 4 5 6 7 8 9 10 11

U23 U23 U23 U23

XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

DECODER_Y[0:7]
SDR_DATA56 B4 F12 VMAUX2 XCOM35 C21 M21 DECODER_Y3 VXBUSY AB19 AA11 VMA17 VMD1 V5 L2 SDR_WE
IO IO/GCLK3P IO IO IO/DOUT IO/GCLK7S IO IO
F SDR_DATA57 A4 F13 C22 M20 DEC_VERTSYNC VXINIT1 AA19 Y11 VMA16 VMMODE U5 L3 SDR_DATA36
IO IO/GCLK2S IO IO IO/INIT_B IO/GCLK6P IO IO
SDR_DATA24 C4 E12 TCLKI XCOM22 E18 M19 XCOM2 VXD0 V18 W11 VMA20 Y2 L4 SDR_DATA11
IO IO/GCLK1P IO/VRP2 IO IO/D0 IO/GCLK5S TB26 IO/VRN6 IO
SDR_DATA25 C5 D12 XY_ADD1 XCOM23 F18 M18 XCOM4 VXD1 V17 V11 VMA12 Y1 L5 SDR_ADD3
IO IO/GCLK0S IO/VRN2 IO IO/D1 IO/GCLK4P TB25 IO/VRP6 IO
SDR_DATA26 B5 C12 AVG_DATA1 XCOM42 D21 M17 XCOM5 VXD2 W18 U11 VMA27 VMD4 V4 K1 SDR_ADD13
IO/VRP0 IO IO IO/VREF3 IO/D2/ALT_VRP4 IO IO IO/VREF7
SDR_DATA58 A5 B12 AVG_DATA0 XCOM37 D22 N17 I2C_RESET1 VXD3 Y18 U10 VMA13 VMD0 V3 K2 SDR_S0
IO/VRN0 IO/VREF1 IO/VREF2 IO IO/D3/ALT_VRN4 IO/VREF5 IO/VREF6 IO
SDR_ADD7 D6 A13 AVG_DATA2 XCOM26 E19 N22 DECODER_UV5 LD10 AA18 AB10 VMA14 W2 K3 SDR_DATA43
IO/VREF0 IO IO IO IO/VREF4 IO TB28 IO IO
SDR_BA0 C6 B13 AVG_DATA3 XCOM31 E20 N21 DECODER_Y2 LD14 AB18 AA10 VMA18 W1 K4 SDR_DATA12
IO IO IO IO IO IO TB27 IO IO
SDR_DATA27 B6 C13 XY_ADD2 XCOM39 E21 N20 DEC_HORSYNC LD0 W17 Y10 VMA10 VMACK U4 L6 SDR_DATA8
IO IO IO IO IO/VRP4 IO IO IO
SDR_DATA59 A6 D13 XY_ADD3 XCOM36 E22 N19 DEC_TREADY LD5 Y17 W10 VMA11 CLK_20M U3 K6 SDR_DATA9
IO IO IO IO IO/VRN4 IO IO IO
SDR_ADD8 E7 E13 SCAN_MODE4 XCOM27 F19 N18 DEC_I2CCLK LD7 AA17 V10 VMA6 V2 K5 SDR_ADD4
SDR_ADD[7:11]

IO IO IO IO IO IO TB30 IO IO
SDR_DATA54 E8 E14 SCAN_MODE6 XCOM32 F20 P18 DEC_RTSTAT0 LD9 AB17 V9 VMA1 V1 J5 SDR_ADD5
IO IO/VREF1 IO IO IO IO/VREF5 TB29 IO IO
SDR_ADD9 D7 A14 AVG_DATA4 XCOM38 F21 P22 DECODER_Y1 LD11 V16 AB9 VMA15 SDR_DATA37 U2 J1 SDR_CK1
IO IO IO IO/VREF3 IO IO IO IO/VREF7
SDR_BA1 C7 B14 AVG_DATA5 XCOM40 F22 P21 DECODER_UV4 LD8 V15 AA9 VMA8 SDR_DATA5 U1 J2 SDR_S1

AVG_DATA[0:15]

SCAN_MODE[0:9]
IO/VREF0 IO IO/VREF2 IO IO IO IO/VREF6 IO
SDR_DATA28 B7 C14 XY_ADD4 XCOM24 G18 P20 DECODER_Y7 LA1 W16 Y9 VMA4 T5 J3 SDR_DATA44
IO IO IO IO IO IO IO IO
SDR_DATA60 A7 D14 XY_ADD5 XCOM29 H18 P19 LD1 Y16 W9 VMA5 R5 J4 SDR_DATA13

DECODER_UV[0:7]
IO IO IO IO IO/VREF4 IO IO IO
SDR_ADD10 D8 A15 AVG_DATA6 XCOM28 G19 R22 DECODER_Y0 LD3 AA16 AB8 VMA2 SDR_DATA0 T4 H1 SDR_DATA48
IO IO/VREF1 IO IO IO IO/VREF5 IO IO
SDR_ADD11 C8 B15 AVG_DATA7 XCOM33 G20 R21 DECODER_UV3 LD6 AB16 AA8 VMA9 T3 H2 SDR_DATA16
IO IO IO IO IO IO IO IO
E SDR_DATA29 B8
IO IO C15 XY_ADD6 XCOM20 G21 IO IO R20 DECODER_Y6 VMBL W15 IO IO Y8 VMD15 SDR_DATA38 T2 IO IO H3 SDR_DATA45
SDR_DATA61 A8 D15 XY_ADD7 XCOM41 G22 R19 DEC_DQUAL LA2 Y15 W8 VMA0 SDR_DATA39 T1 H4 SDR_DATA14
IO IO IO IO IO IO IO IO
SDR_DATA55 E9 F14 XCOM18 H19 R18 DEC_RTSTAT1 LA4 AA15 U9 VMA7 SDR_DATA1 R4 J6 SDR_DATA10
IO IO IO IO/VREF3 IO IO IO IO/VREF7
SDR_I2CCLK F9 E15 SCAN_MODE8 XCOM34 H20 P17 DEC_I2CDAT LD2 AB15 V8 VMD12 SDR_DATA32 R3 H5 SDR_DATA40
IO/VREF0 IO IO/VREF2 IO IO IO IO/VREF6 IO
SDR_DQMB2 D9 A16 AVG_DATA8 XCOM16 H21 T22 DECODER_UV7 VMBH U14 AB7 VMA3 SDR_DATA6 R2 G1 SDR_DATA49
IO IO IO IO IO IO IO IO
SDR_DQMB6 C9 B16 AVG_DATA9 XCOM19 H22 T21 DECODER_UV2 LA0 V14 AA7 VMD13 SDR_DATA7 R1 G2 SDR_DATA17
IO IO IO IO IO/VREF4 IO IO IO

LA[0:4]
SDR_DATA30 B9 C16 XY_ADD8 XCOM25 J17 T20 DECODER_Y5 LSVIDEO W14 Y7 VMD10 SDR_ADD0 P6 G3 SDR_DATA46
IO IO/VREF1 IO IO IO IO/VREF5 IO IO
SDR_DATA62 A9 D16 SCAN_MODE1 XCOM30 J18 T19 DECODER_Y4 VMRW Y14 W7 VMD11 P5 G4 SDR_DATA15
IO IO IO IO IO IO IO IO
SDR_DATA22 E10 E16 SCAN_MODE7 XCOM13 J19 U22 DECODER_UV6 LRW AA14 AB6 VMD8 SDR_DATA2 P4 F1 SDR_DATA50
IO/VREF0 IO IO IO IO IO IO IO
SDR_I2CDAT F10 E17 SCAN_MODE9 XCOM17 J20 U21 DECODER_UV1 LA3 AB14 AA6 VMD14 SDR_DATA33 P3 F2 SDR_DATA18
IO IO IO IO IO IO IO IO
SDR_DQMB3 D10 A17 AVG_DATA10 XCOM11 J21 U20 DECODER_UV0 VMDS U13 Y6 VMD5 SDR_DQMB4 P2 F3 SDR_DATA47
IO IO IO IO/VREF3 IO/VREF4 IO IO IO/VREF7
SDR_DQMB7 C10 B17 AVG_DATA11 XCOM1 J22 U19 VID_VSYNC VMA26 V13 W6 VMD6 SDR_DQMB5 P1 F4 SDR_CK0
IO IO IO/VREF2 IO IO IO IO/VREF6 IO
SDR_DATA31 B10 C17 SCAN_MODE0 XCOM15 K17 T18 DEC_GENPUR VMAS W13 V7 VMD7 SDR_ADD1 N6 G5 SDR_DATA41
IO IO IO IO IO IO/VRP5 IO IO
SDR_DATA63 A10 D17 SCAN_MODE3 XCOM14 K18 U18 MRESET_DONE VMA24 Y13 V6 VMD2 N5 F5 SDR_DATA42
IO IO/VREF1 IO IO IO IO/VRN5 IO IO
SDR_DATA23 E11 A18 AVG_DATA12 XCOM8 K19 V22 ECG_AUX0 VMA29 AA13 AB5 VMD9 SDR_DATA3 N4 E1 SDR_DATA51
IO/VREF0 IO/VRP1 IO IO IO IO IO IO

ECG_AUX[0:2]
F11 IO IO/VRN1 B18 AVG_DATA13 XCOM12 K20 IO IO V21 TBASE VMA28 AB13
IO IO/VREF5 AA5 VMD3 SDR_DATA34 N3 IO IO E2 SDR_DATA19
XY_ADD0 D11 C18 SCAN_MODE2 XCOM6 K21 V20 MCYCLE_START VMA21 U12 Y5 VXD4 SDR_DQMB0 N2 E3 SDR_CKE0
IO/GCLK7P IO IO IO IO/VREF4 IO/D4/ALT_VRP5 IO IO
D XCOM21 C11 D18 SCAN_MODE5 XCOM0 K22 V19 VID_HSYNC VMA25 V12 W5 VXD5 SDR_DQMB1 N1 E4 SDR_CAS
IO/GCLK6S IO IO IO IO IO/D5/ALT_VRN5 IO IO
B11 IO/GCLK5P IO A19 AVG_DATA14 XCOM10 L17 IO IO/VREF3 W22 ECG_AUX1 VMA19 W12
IO/GCLK3S IO/D6 AB4 VXD6 SDR_ADD2 M6 IO IO/VREF7 D1 SDR_DATA52
CLK40D A11 B19 AVG_DATA15 XCOM9 L18 W21 LD12 VMA23 Y12 AA4 VXD7 M5 D2 SDR_DATA20
IO/GCLK4S IO IO/VREF2 IO IO/GCLK2P IO/D7 IO/VREF6 IO
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

XCOM3 L19 Y22 ECG_AUX2 VMA22 AA12 Y4 VXWRITE SDR_DATA4 M4 C1 SDR_DATA53

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

IO IO/VRP3 IO/GLCK1S IO/RDWR_B IO IO/VRN7

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

XCOM7 L20 Y21 LD13 DEC_PIXCLKA AB12 AA3 VXCS1 SDR_DATA35 M3 C2 SDR_DATA21
IO IO/VRN3 IO/GCLK0P IO/CS_B IO IO/VRP7
L21 W20 LD4 SDR_CKE1 M2 E5 SDR_RAS
IO IO IO IO
L22 IO IO AA20 LD15 SDR_ADD12 M1 IO IO E6 SDR_ADD6

G11 VCCOBank0 VCCOBank1 G14 L16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 L7
+3V3 G10 G13 +3V3 +3V3 K16 R17 +3V3 +3V3 U15 U7 +3V3 +3V3 R6 K7 +3V3
VCCOBank0 VCCOBank1 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
G9 VCCOBank0 VCCOBank1 G12 J16 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T11 P7 VCCOBank6 VCCOBank7 J7
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T10 N7 VCCOBank6 VCCOBank7 H6
F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 M16 T12 VCCOBank4 VCCOBank5 T9 M7 VCCOBank6 VCCOBank7 G6

C VXINIT1
TB23
TB38 VXCS1

TB35
U35 TB24 U23
ADV7123-140 XC2V1000-4
CRT_CLOCKA 24 13 CRTDAC_VCC VXCCLK Y19 C19 XTCK
CLK VAA TB42 CCLK TCK
R400
CRT_BLANK 11 VAA 29 R12 VXPROG A2 PROG_B TDI D3 VTDI/TDO
47N TB46
C1
1K00 BLANK +5VB
30 VXDONE1 AB20 D20 XVTDO
12 SYNC
VAA R405 10 TB45 DONE TDO
C420 C419 AB2 M0 TMS B20 XTMS
536 TB43
CRT_RED0 39 Rset 37 100N 100N R2 W3 M1 DXN D5
R0
36 VXD0 AB3 A3
CRT_RED1 40 Vref 82 M2 DXP
R1
35 VXD1 B3 A21
CRT_RED2 41 COMP HSWAP_EN VBATT
R2
CRT_RED3 42 R3 4
U1 VXD2 1K00 AB21 PWRDWN_B RSVD A20
R3
VXD3 +3V3
CRT_RED4 43 R4
68 V+ LMH6644 R96
9 -
CRT_RED5 44 8 SVGA_RED
R5
B CRT_RED6 45 R6 IOR 34 10
+
CRT_RED7 V- +3V3
46 R7
CRT_RED8 47 33 R13 11
47N
C2

R8 IOR -5VB
CRT_RED9 48 75 75 10
R9
R413 R9
CRT_GREEN0 1 IOG 32 TB54
G0
TB53 +3V3 +3V3
CRT_GREEN1 2 G1 R5 R133 R134 R378 R379
CRT_GREEN2 3 IOG 31 TB52
G2 82
CRT_GREEN3 4
75 75 TB51 4K7 4K7 4K7 4K7
G3
CRT_GREEN4 5 G4
R411 R10 R4 U1 VXD4
28 4 SDR_I2CDAT ENC0_I2CDAT
CRT_GREEN5 6 IOB VXD5
G5 68 V+ LMH6644
CRT_GREEN6 7 13 VXD6 SDR_I2CCLK ENC0_I2CCLK
G6 -
SVGA_GREEN
27 14
CRT_GREEN7 8 IOB VXD7
G7 12
75 75 + +3V3 +3V3
CRT_GREEN8 9 G8 V-
R263 R272 R140 R382
CRT_GREEN9 10 R408 R11 11
G9 4K7 4K7 4K7 4K7

CRT_BLUE0 14 B0
A CRT_BLUE1 15
+3V3 R7 DEC_I2CDAT ENC1_I2CDAT
B1
837 0147 042 Rev.A

CRT_BLUE2 16 82 DEC_I2CCLK ENC1_I2CCLK

B2
CRT_BLUE3 17 PSAVE 38
B3 U1
FORM:

CRT_BLUE4 18 R6 4
U1 4
B4
CRT_BLUE5 19 68 V+
R8 6
V+
B5 2 -
CRT_BLUE6 - 75 7
20 B6 1 SVGA_BLUE 5
3 +
CRT_BLUE7 21 +
B7 V-
V-
CRT_BLUE8 22 B8 11
CRT_BLUE9 11
23 B9
SHEET DESCRIPTION:
"7350" VIDEO BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1219 000 SE C 3 10

 1 2 3 4 5 6 7 8 9 10 11

U31 U31 U31 U31

XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

FMEM_GW B4 F12 GRA1 LCD_GODD5 C21 M21 CRT_RED8 VXBUSY AB19 AA11 XCOM3 V5 L2 FMEM_D2
IO IO/GCLK3P IO IO IO/DOUT IO/GCLK7S IO IO
F FMEM_OE A4
IO IO/GCLK2S F13 GRA0 LCD_GODD4 C22 IO IO M20 CRT_BLUE3 VXINIT0 AA19
IO/INIT_B IO/GCLK6P Y11 XCOM19 U5
IO IO L3 FMEM_D1
FMEM_A13 C4 E12 GRA3 LCD_BEVEN7 E18 M19 CRT_BLUE8 VXD0 V18 W11 XCOM4 Y2 L4 FMEM_D0
IO IO/GCLK1P IO/VRP2 IO IO/D0 IO/GCLK5S IO/VRN6 IO
XCOM8

VXD[0:3]
FMEM_A14 C5 D12 GRA5 LCD_BEVEN6 F18 M18 CRT_GREEN5 VXD1 V17 V11 Y1 L5 FMEM_D6
IO IO/GCLK0S IO/VRN2 IO IO/D1 IO/GCLK4P IO/VRP6 IO
XCOM17 V4

GRA[0:7]
FMEM_AS B5 C12 GRA7 LCD_BODD3 D21 M17 CRT_GREEN9 VXD2 W18 U11 K1 FMEM_A3
IO/VRP0 IO IO IO/VREF3 IO/D2/ALT_VRP4 IO IO IO/VREF7
FMEM_A17 A5 B12 LCD_BODD2 D22 N17 CRT_BLANK VXD3 Y18 U10 XCOM5 V3 K2 FMEM_A18
IO/VRN0 IO/VREF1 IO/VREF2 IO IO/D3/ALT_VRN4 IO/VREF5 IO/VREF6 IO
LA1 D6 A13 VGA_LVN1 LCD_BEVEN2 E19 N22 CRT_RED5 AA18 AB10 XCOM9 W2 K3 FMEM_D10
IO/VREF0 IO IO IO IO/VREF4 IO IO IO
FMEM_A15 C6 B13 VGA_LVP1 LCD_GEVEN6 E20 N21 CRT_RED4 CRT_RED0 AB18 AA10 XCOM10 W1 K4 FMEM_D15
IO IO IO IO IO IO IO IO
FMEM_A16 B6 C13 GRA6 LCD_REVEN4 E21 N20 CRT_BLUE4 W17 Y10 XCOM12 U4 L6 FMEM_D11
IO IO IO IO IO/VRP4 IO IO IO
LRW A6 D13 GRA4 LCD_REVEN5 E22 N19 CRT_BLUE9 Y17 W10 XCOM13 U3 K6 FMEM_CK0
IO IO IO IO IO/VRN4 IO IO IO
LA0 E7 E13 GRA2 LCD_BEVEN1 F19 N18 CRT_VSYNC AA17 V10 XCOM18 V2 K5 FMEM_A1
IO IO IO IO IO IO IO IO
LD8 E8 E14 LCD_VSYNC LCD_GEVEN5 F20 P18 CRT_BLUE5 CRT_RED1 AB17 V9 XCOM15 V1 J5 FMEM_A0
IO IO/VREF1 IO IO IO IO/VREF5 IO IO
LD9 D7 A14 VGA_LVN2 LCD_REVEN3 F21 P22 CRT_RED7 V16 AB9 XCOM14 U2 J1 FMEM_D3
LA[0:4]

IO IO IO IO/VREF3 IO IO IO IO/VREF7
LA2 C7 B14 VGA_LVP2 LVDS_TXPD F22 P21 CRT_RED3 V15 AA9 XCOM20 U1 J2 FMEM_D14
IO/VREF0 IO IO/VREF2 IO IO IO IO/VREF6 IO
LSVID B7 C14 LCD_GODD3 LCD_BEVEN5 G18 P20 PRN_CNT2 W16 Y9 XCOM42 T5 J3 FMEM_A2
IO IO IO IO IO IO IO IO
V_HSYNC A7 D14 LCD_HSYNC LCD_BEVEN4 H18 P19 CRT_CLOCK Y16 W9 XCOM40 R5 J4 FMEM_D7
IO IO IO IO IO/VREF4 IO IO IO
LD14 D8 A15 VGA_LVN0 LCD_BEVEN0 G19 R22 PRN_CNT0 AA16 AB8 XCOM41 T4 H1 FMEM_D13
IO IO/VREF1 IO IO IO IO/VREF5 IO IO
LD10 C8 B15 VGA_LVP0 LCD_GEVEN4 G20 R21 CRT_RED2 CRT_GREEN0 AB16 AA8 XCOM38 T3 H2 FMEM_D9
IO IO IO IO IO IO IO IO
E LA3 B8 C15 LCD_GODD2 LCD_TXCK G21 R20 ENC_DATAREQ W15 Y8 XCOM30 T2 H3 FMEM_D16
IO IO IO IO IO IO IO IO
LA4 A8 D15 LCD_RODD6 LCD_REVEN6 G22 R19 PRN_CNT3 Y15 W8 XCOM25 T1 H4 FMEM_D20
IO IO IO IO IO IO IO IO
LD13 E9 F14 LCD_DRDY LCD_GEVEN7 H19 R18 ENC_HORSYNC AA15 U9 XCOM34 R4 J6 FMEM_CK1
IO IO IO IO/VREF3 IO IO IO IO/VREF7
LD12 F9 E15 LCD_RODD2 LCD_GEVEN3 H20 P17 CRT_HSYNC CRT_GREEN1 AB15 V8 XCOM37 R3 H5 FMEM_A11
IO/VREF0 IO IO/VREF2 IO IO IO IO/VREF6 IO
LD2 D9 A16 LCD_BODD7 LVDS_TXDUAL H21 T22 ENC_SYNCRES U14 AB7 TRACE0 XCOM29 R2 G1 FMEM_D26
IO IO IO IO IO IO IO IO
LD[0:15]

LD15 C9 B16 LCD_BODD1 LCD_REVEN7 H22 T21 PRN_CNT1 V14 AA7 TRACE1 XCOM36 R1 G2 FMEM_D8
IO IO IO IO IO/VREF4 IO IO IO
LD11 B9 C16 LCD_GODD1 CRT_GREEN6 J17 T20 I2C_RESET0 W14 Y7 FMEM_A5 P6 G3 FMEM_D21
IO IO/VREF1 IO IO IO IO/VREF5 IO IO

LCD_RODD[7:0]
V_VSYNC A9 D16 LCD_RODD5 CRT_GREEN2 J18 T19 ENCODER_CYC1 Y14 W7 XCOM39 P5 G4 FMEM_D12
IO IO IO IO IO IO IO IO
LD1 E10 E16 LCD_RODD1 LCD_BEVEN3 J19 U22 ENCODER_CYC4 AA14 AB6 XCOM0 XCOM24 P4 F1 FMEM_D17
IO/VREF0 IO IO IO IO IO IO IO
LD0 F10 E17 LCD_RODD0 LCD_GEVEN2 J20 U21 ENC1_I2CCLK CRT_BLUE0 AB14 AA6 XCOM1 XCOM33 P3 F2 FMEM_D31
IO IO IO IO IO IO IO IO
LD6 D10 A17 LCD_BODD6 LCD_REVEN1 J21 U20 ENC_PIXCLK U13 Y6 XCOM16 XCOM32 P2 F3 FMEM_D18
IO IO IO IO/VREF3 IO/VREF4 IO IO IO/VREF7
LD3 C10 B17 LCD_BODD0 LCD_REVEN2 J22 U19 ENCODER_CYC2 V13 W6 XCOM11 XCOM35 P1 F4 FMEM_D22
IO IO IO/VREF2 IO IO IO IO/VREF6 IO

ENCODER_CYC[0:7]
VGA_LVN4 B10 C17 LCD_GODD0 CRT_GREEN7 K17 T18 ENCODER_CYC0 W13 V7 FMEM_A6 N6 G5 FMEM_A12
IO IO IO IO IO IO/VRP5 IO IO
VGA_LVP4 A10 D17 LCD_RODD4 CRT_GREEN3 K18 U18 Y13 V6 XCOM6 FMEM_D5 N5 F5 FMEM_A8
IO IO/VREF1 IO IO IO IO/VRN5 IO IO
LD5 E11 IO/VREF0 IO/VRP1 A18 LCD_BODD5 CRT_BLUE6 K19 IO IO V22 ENCODER_CYC5 AA13 IO IO AB5 XCOM2 XCOM31 N4
IO IO E1 FMEM_D24
LD4 F11 B18 LCD_GODD7 LCD_GEVEN1 K20 V21 ENC0_I2CCLK CRT_BLUE1 AB13 AA5 XCOM7 XCOM28 N3 E2 FMEM_D27
IO IO/VRN1 IO IO IO IO/VREF5 IO IO
CLK40C D11 C18 LCD_RODD7 CRT_RED6 K21 V20 ENC_PIXCLK U12 Y5 VXD4 XCOM23 N2 E3 FMEM_D23

VXD[4:7]
IO/GCLK7P IO IO IO IO/VREF4 IO/D4/ALT_VRP5 IO IO
LD7 C11 D18 LCD_RODD3 LCD_REVEN0 K22 V19 ENCODER_CYC3 V12 W5 VXD5 XCOM27 N1 E4 FMEM_D28
D IO/GCLK6S IO IO IO IO IO/D5/ALT_VRN5 IO IO
VGA_LVN3 B11 A19 LCD_BODD4 CRT_GREEN8 L17 W22 ENCODER_CYC6 W12 AB4 VXD6 FMEM_A7 M6 D1 FMEM_D29
IO/GCLK5P IO IO IO/VREF3 IO/GCLK3S IO/D6 IO IO/VREF7
VGA_LVP3 A11 B19 LCD_GODD6 CRT_GREEN4 L18 W21 ENC1_I2CDAT Y12 AA4 VXD7 FMEM_A4 M5 D2 FMEM_D25
IO/GCLK4S IO IO/VREF2 IO IO/GCLK2P IO/D7 IO/VREF6 IO
CRT_BLUE7 L19 Y22 ENCODER_CYC7 ENC_CLKOUTA AA12 Y4 VXWRITE FMEM_D4 M4 C1 FMEM_D19
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

IO IO/VRP3 IO/GLCK1S IO/RDWR_B IO IO/VRN7

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

CRT_BLUE2 L20 Y21 ENC0_I2CDAT AB12 AA3 VXCS0 XCOM22 M3 C2 FMEM_D30

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

IO IO/VRN3 IO/GCLK0P IO/CS_B IO IO/VRP7

LCD_GEVEN0 L21 W20 ENC_VERTSYNC XCOM26 M2 E5 FMEM_A9
IO IO IO IO
CRT_RED9 L22 AA20 XCLK_27M XCOM21 M1 E6 FMEM_A10
IO IO IO IO

G11 VCCOBank0 VCCOBank1 G14 L16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 L7
+3V3 G10 G13 +3V3 +3V3 K16 R17 +3V3 +3V3 U15 U7 +3V3 +3V3 R6 K7 +3V3
VCCOBank0 VCCOBank1 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
G9 VCCOBank0 VCCOBank1 G12 J16 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T11 P7 VCCOBank6 VCCOBank7 J7
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T10 N7 VCCOBank6 VCCOBank7 H6
F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 M16 T12 VCCOBank4 VCCOBank5 T9 M7 VCCOBank6 VCCOBank7 G6

U27 +3V3 U28 +3V3 U33 +3V3 U34 +3V3

TB47 VXINIT0
CY7C1327 (RAM) CY7C1327 (RAM) CY7C1327 (RAM) CY7C1327 (RAM) VXCS0
C +3V3
FMEM_CKA0
+3V3
FMEM_CKA0
+3V3
FMEM_CKA1 89
+3V3
FMEM_CKA1 89
TB50
89 4 89 4 4 4
CLK VDDQ CLK VDDQ CLK VDDQ CLK VDDQ TB101
VDDQ 11 VDDQ 11 VDDQ 11 VDDQ 11 TB44 U31
83 20 83 20 83 20 83 20 TB100
ADV VDDQ ADV VDDQ ADV VDDQ ADV VDDQ XC2V1000-4
84 ADSP VDDQ 27 84 ADSP VDDQ 27 84 ADSP VDDQ 27 84 ADSP VDDQ 27 VXCCLK XTCK
Y19 CCLK TCK C19
FMEM_AS 85 54 FMEM_AS 85 54 FMEM_AS 85 54 FMEM_AS 85 54
ADSC VDDQ ADSC VDDQ ADSC VDDQ ADSC VDDQ VXPROG A2 D3 XVTDI
PROG_B TDI
VDDQ 61 VDDQ 61 VDDQ 61 VDDQ 61 VXDONE0 VTDI/TDO
AB20 DONE TDO D20
FMEM_A0 37 70 FMEM_A0 37 70 FMEM_A0 37 70 FMEM_A0 37 70
A0 VDDQ A0 VDDQ A0 VDDQ A0 VDDQ AB2 B20 XTMS
M0 TMS
FMEM_A1 36 77 FMEM_A1 36 77 FMEM_A1 36 77 FMEM_A1 36 77
A1 VDDQ A1 VDDQ A1 VDDQ A1 VDDQ W3 D5
M1 DXN
FMEM_A2 35 FMEM_A2 35 FMEM_A2 35 FMEM_A2 35
A2 A2 A2 A2 AB3 A3
M2 DXP
FMEM_A3 34 FMEM_A3 34 FMEM_A3 34 FMEM_A3 34

R4452
A3 A3 A3 A3 B3 A21
HSWAP_EN VBATT
FMEM_A4 33 FMEM_A4 33 FMEM_A4 33 FMEM_A4 33
A4 A4 A4 A4 1K00 AB21 A20

47
PWRDWN_B RSVD
FMEM_A5 32 FMEM_A5 32 FMEM_A5 32 FMEM_A5 32
A5 A5 A5 A5 +3V3
FMEM_A6 100 FMEM_A6 100 FMEM_A6 100 FMEM_A6 100
R395 C449
A6 A6 A6 A6
FMEM_A7 99 FMEM_A7 99 FMEM_A7 99 FMEM_A7 99 33P
A7 A7 A7 A7
FMEM_A[0:17]

FMEM_A[0:17]

FMEM_A[0:17]

FMEM_A[0:17]
FMEM_A8 82 58 FMEM_D0 FMEM_A8 82 58 FMEM_D0 FMEM_A8 82 58 FMEM_D16 FMEM_A8 82 58 FMEM_D16
A8 DQ0 A8 DQ0 A8 DQ0 A8 DQ0 +3V3 2
FMEM_A9 81 59 FMEM_D1 FMEM_A9 81 59 FMEM_D1 FMEM_A9 81 59 FMEM_D17 FMEM_A9 81 59 FMEM_D17
A9 DQ1 A9 DQ1 A9 DQ1 A9 DQ1
FMEM_A10 80 62 FMEM_D2 FMEM_A10 80 62 FMEM_D2 FMEM_A10 80 62 FMEM_D18 FMEM_A10 80 62 FMEM_D18
A10 DQ2 A10 DQ2 A10 DQ2 A10 DQ2
B FMEM_A11 44 A11 DQ3 63 FMEM_D3 FMEM_A11 44 A11 DQ3 63 FMEM_D3 FMEM_A11 44 A11 DQ3 63 FMEM_D19 FMEM_A11 44 A11 DQ3 63 FMEM_D19

FMEM_D[16:31]

FMEM_D[16:31]
FMEM_A12 45 68 FMEM_D4 FMEM_A12 45 68 FMEM_D4 FMEM_A12 45 68 FMEM_D20 FMEM_A12 45 68 FMEM_D20
A12 DQ4 A12 DQ4 A12 DQ4 A12 DQ4 VGA_LVP2
FMEM_D[0:15]

FMEM_D[0:15]

FMEM_A13 46 69 FMEM_D5 FMEM_A13 46 69 FMEM_D5 FMEM_A13 46 69 FMEM_D21 FMEM_A13 46 69 FMEM_D21

A13 DQ5 A13 DQ5 A13 DQ5 A13 DQ5

R144
FMEM_A14 47 72 FMEM_D6 FMEM_A14 47 72 FMEM_D6 FMEM_A14 47 72 FMEM_D22 FMEM_A14 47 72 FMEM_D22
A14 DQ6 A14 DQ6 A14 DQ6 A14 DQ6
FMEM_A15 FMEM_D7 FMEM_A15 FMEM_D7 FMEM_A15 FMEM_D23 FMEM_A15 FMEM_D23

100
48 A15 DQ7 73 48 A15 DQ7 73 48 A15 DQ7 73 48 A15 DQ7 73
FMEM_A16 49 8 FMEM_D8 FMEM_A16 49 8 FMEM_D8 FMEM_A16 49 8 FMEM_D24 FMEM_A16 49 8 FMEM_D24
A16 DQ8 A16 DQ8 A16 DQ8 A16 DQ8 VGA_LVP0
FMEM_A17 FMEM_D9 FMEM_A17 FMEM_D9 FMEM_A17 FMEM_D25 FMEM_A17 FMEM_D25 VGA_LVN2
+3V3 50 A17 DQ9 9 50 A17 DQ9 9 +3V3 50 A17 DQ9 9 50 A17 DQ9 9

R143
43 12 FMEM_D10 43 12 FMEM_D10 43 12 FMEM_D26 43 12 FMEM_D26
NC(A18) DQ10 NC(A18) DQ10 NC(A18) DQ10 NC(A18) DQ10
FMEM_GW FMEM_D11 +3V3 FMEM_GW FMEM_D11 FMEM_GW FMEM_D27 FMEM_GW FMEM_D27

100
88 GW DQ11 13 88 GW DQ11 13 88 GW DQ11 13 +3V3 88 GW DQ11 13
18 FMEM_D12 18 FMEM_D12 18 FMEM_D28 18 FMEM_D28 VGA_LVP3
DQ12 DQ12 DQ12 DQ12
FMEM_D13 FMEM_D13 FMEM_D29 FMEM_D29 VGA_LVN0
87 BWE DQ13 19 87 BWE DQ13 19 87 BWE DQ13 19 87 BWE DQ13 19

R402
93 22 FMEM_D14 93 22 FMEM_D14 93 22 FMEM_D30 93 22 FMEM_D30
BWS0 DQ14 BWS0 DQ14 BWS0 DQ14 BWS0 DQ14

100
94 23 FMEM_D15 94 23 FMEM_D15 94 23 FMEM_D31 94 23 FMEM_D31
BWS1 DQ15 BWS1 DQ15 BWS1 DQ15 BWS1 DQ15
VGA_LVP1
VGA_LVN3
31 R345 31 R389 31 R403 31 R344
R136

R141

R401
MODE MODE MODE MODE
1K00

1K00

100
1K00 1K00 1K00 1K00
98 CE1 DP0 74 98 CE1 DP0 74 98 CE1 DP0 74 98 CE1 DP0 74
VGA_LVP4
A 97 CE2 DP1 24 FMEM_A18 97 CE2 DP1 24 97 CE2 DP1 24 FMEM_A18 97 CE2 DP1 24 VGA_LVN1

R145
FMEM_A18 FMEM_A18
837 0147 042 Rev.A

92 CE3 1K00 92 CE3 1K00 92 CE3 1K00 92 CE3 1K00

100
R365 1K00 R404 R388 1K00 R364
FMEM_OE FMEM_OE FMEM_OE FMEM_OE
FORM:

86 OE 86 OE 86 OE 86 OE
R137 R142 VGA_LVN4
64 ZZ 64 ZZ 64 ZZ 64 ZZ

SHEET DESCRIPTION:
"7350" VIDEO BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1219 000 SE C 4 10

 1 2 3 4 5 6 7 8 9 10 11

U41 +3V3 U17

DS90C387 (LVDS TX) SAA7115 (DECODER)
LCD_TXCKA 11 30 LVDS_VCC 1 23 DEC_VCC
CLKIN LVDSVCC VDDE VDDA0
40 25 VDDE VDDA1 17
LVDSVCC
F LCD_REVEN0 10 R10 48 51 VDDE VDDA2 11
LVDSVCC
LCD_REVEN1 9 75 33
R11 VDDE VDDI +3V3
LCD_REVEN2 8 12 LVDSPLL_VCC 8 43

LCD_REVEN[0:7]
R12 PLLVCC VXDD VDDI
LCD_REVEN3 7 18 58 Y1
R13 PLLVCC VDDI +3V3
LCD_REVEN4 6 7 68
R14 CLK_24.576MHZ XTALI VDDI
LCD_REVEN5 5 49 LCD_EVENP0 83 C150 4 24.576MHZ
R15 TxA0+ VDDI
LCD_REVEN6 4 50 LCD_EVENN0 6 93 47N R207
R16 TxA0- XTALO VDDI VCC
LCD_REVEN7 3 1K00
R17 1 3
OE OSC CLK_24.576MHZ
LCD_GEVEN0 2 46 LCD_EVENP1 4 37
G10 TxA1+ XTOUT AMCLK
LCD_GEVEN1 1 47 LCD_EVENN1 39 GND
G11 TxA1- ASCLK
LCD_GEVEN2 100 5 40
LCD_GEVEN[0:7]

G12 VXSS ALRCLK

LCD_GEVEN3 99 44 LCD_EVENP2 41 2
G13 TxA2+ AMXCLK
LCD_GEVEN4 96 45 LCD_EVENN2 10
G14 TxA2- AI24

C166
LCD_GEVEN5 95 12 45 DEC_PIXCLK
G15 AI23 ICLK

47N
LCD_GEVEN6 94 38 LCD_EVENP3 14 46 DEC_DQUAL
G16 TxA3+ AI22 IDQ
LCD_GEVEN7 93 39 LCD_EVENN3 VTR_CHROMIN 16 47
G17 TxA3- AI21 ITRI
LCD_BEVEN0 92 13 48 DEC_GENPUR

C172
B10 AI2D IGP0
UP4

47N
E LCD_BEVEN1 91 36 LCD_ODDP0 18 49
B11 TxA4+ AI12 IGP1
LCD_BEVEN2 90 37 LCD_ODDN0 20 52 DEC_VERTSYNC CY2071A
LCD_BEVEN[0:7]

B12 TxA4- VTR_COMPIN AI11 IGPV

LCD_BEVEN3 89 19 53 DEC_HORSYNC 7
B13 AI1D IGPH VDD

C173
LCD_BEVEN4 88 33 LCD_ODDP1 4
B14 TxA5+ XTALOUT

47N
LCD_BEVEN5 87 34 LCD_ODDN1 28 CLK_20M 3
B15 TxA5- LCC XTALIN
LCD_BEVEN6 86 VTR_LUMIN 29 42 DEC_TREADY
B16 LCC2 ITRDY
LCD_BEVEN7 85 31 LCD_ODDP2 8 1
B17 TxA6+ OE CLKA
LCD_RODD0 84 32 LCD_ODDN2 30 62 DECODER_Y0 5
R20 TxA6- RESON IPD0 CLKB

DECODER_Y[0:7]
LCD_RODD1 81 61 DECODER_Y1 2 6
R21 IPD1 GND CLKC

R250

R239

R235
LCD_RODD2 80 28 LCD_ODDP3 44 60 DECODER_Y2
LCD_RODD[0:7]

R22 TxA7+ 47N 47N TEST0 IPD2

LCD_RODD3 79 29 LCD_ODDN3 73 59 DECODER_Y3

56

56

56
R23 TxA7- TEST1 IPD3
LCD_RODD4 78 C174 C176 74 57 DECODER_Y4 Non montare
R24 TEST2 IPD4
LCD_RODD5 77 77 56 DECODER_Y5
R25 TEST3 IPD5
LCD_RODD6 76 41 LCD_EVENPCK 78 55 DECODER_Y6
R26 TxCLK1+ TEST4 IPD6
LCD_RODD7 75 42 LCD_EVENNCK 79 54 DECODER_Y7
R27 TxCLK1- TEST5 IPD7
LCD_GODD0 74 G20
LCD_GODD1 73 26 LCD_ODDPCK 92 22
G21 TxCLK2+ XRH AOUT
LCD_GODD2 72 27 LCD_ODDNCK 91
LCD_GODD[0:7]

D G22 TxCLK2- XRV

LCD_GODD3 71 +3V3 96 31 DEC_I2CCLK
G23 XRDY SCL
LCD_GODD4 70 95 32 DEC_I2CDAT
G24 XDQ SDA
LCD_GODD5 69 15 94
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

G25 PLLSEL XCLK

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

LCD_GODD6 66 23 LVDS_TXDUAL 80 72 DECODER_UV0

Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

G26 DUAL XTRI HPD0

DECODER_UV[0:7]
LCD_GODD7 65 14 71 DECODER_UV1
G27 PRE HPD1
LCD_BODD0 64 24 90 70 DECODER_UV2
B20 BAL XPD0 HPD2
LCD_BODD1 63 20 89 69 DECODER_UV3
B21 R_FB XPD1 HPD3
LCD_BODD2 62 21 87 67 DECODER_UV4
LCD_BODD[0:7]

B22 R_FDE XPD2 HPD4

LCD_BODD3 61 22 LVDS_TXPD 86 66 DECODER_UV5
B23 PD XPD3 HPD5
LCD_BODD4 60 85 65 DECODER_UV6
B24 XPD4 HPD6
LCD_BODD5 59 25 84 64 DECODER_UV7
B25 LVDSGND XPD5 HPD7
LCD_BODD6 58 35 82
B26 LVDSGND XPD6
LCD_BODD7 57 43 81 34 DEC_RTSTAT0
B27 LVDSGND XPD7 RTS0
51 35 DEC_RTSTAT1
LVDSGND RTS1
I2C_RESET1 27 36
CE RTCO
LCD_HSYNC 54 HSYNC PLLGND 16 TB15 97 TRSTN
LCD_VSYNC 55 VSYNC PLLGND 17 TDI 3 TB11
C LCD_DRDY 56 DRDY(DE) PLLGND 19 26 VSSE TDO 2 TB12
50 VSSE TMS 99 TB13
76 VSSE TCK 98 TB14
100 VSSE
VSSA0 24
38 VSSI VSSA1 15
63 VSSI VSSA2 9
88 VSSI AGND 21

I2C ADDRESS
L18 +3V3 WRITE = 42H
100U READ = 43H
CRTDAC_VCC
C386 C382 C381 C385 C384 C383 C61
10N 10N 10N 100N 100N 100N
10U

R260 R394
B L1 +3V3 33 33
100U ENC_CLKOUT ENC_CLKOUTA LCD_TXCK LCD_TXCKA
DEC_VCC
R377 R383
C162 C149 C144 C32 33 33
100N 100N 100N ENC_PIXCLK ENC_PIXCLKA CRT_CLOCK CRT_CLOCKA
10U
R139 R240
33 33
L20 +3V3 L19 +3V3 ENC_PIXCLK ENC_PIXCLKA DEC_PIXCLK DEC_PIXCLKA

LVDS_VCC
100U
LVDSPLL_VCC
100U R384 R442
33 33
C424 C425 C426 C64 C421 C422 C423 C63 FMEM_CK0 FMEM_CKA0 V_HSYNC VID_HSYNC
1N 10N 100N 1N 10N 100N
10U 10U R396 R443
33 33
FMEM_CK1 FMEM_CKA1 V_VSYNC VID_VSYNC

L7 +3V3 L11 +3V3 R1

82
R376

82
R138

82
R386

82
R387

100U 100U 33
ENC0_VCC ENC1_VCC XCLK_27M XCLK_27MA

A C248 C247 C230 C259 C40 C293 C292 C283 C282 C46
100N 100N 100N 100N 100N 100N 100N 100N C315 C53 C366 C368
837 0147 042 Rev.A

10U 10U
100P 100P 100P 100P
FORM:

SHEET DESCRIPTION:
"7350" VIDEO BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1219 000 SE C 5 10

 1 2 3 4 5 6 7 8 9 10 11
R86 R264
33 33
SDR_DATA32 SDR_DATA0
R283 R87 R273 R95
33
SDR_DQMB4 33 33 33
SDR_DATA33 SDR_DATA1 SDR_DQMB0
R98 R88 R274 R295
33
SDR_DQMB5 33 33 33
SDR_DATA34 SDR_DATA2 SDR_DQMB1
F R124 R90 R275 R303
33
SDR_ADD3 33 33 33
SDR_DATA35 SDR_DATA3 SDR_ADD0
R127 R92 +3V3 R277 R120
+3V3
33
SDR_ADD4 33 33 33
SDR_DATA36 J4 SDR_DATA4 SDR_ADD1
R129 R89 R265 R323
2 1
33
SDR_ADD5 33 4 3 33 33
SDR_DATA37 SDR_DATA5 SDR_ADD2
R276 6 5 R91
8 7
33 33
SDR_DATA38 10 9 SDR_DATA6
R93 12 11 R279
R329 14 13
R122
33 33
33 SDR_DATA39 SDR_DATA7 33
SDR_DATA40 16 15 SDR_DATA8
R330 18 17 R325
20 19
33 33
SDR_DATA41 22 21 SDR_DATA9
E R118 24 23 R327
33 26 25 33
SDR_DATA42 SDR_DATA10
28 27
R94 30 29
R282
33 32 31 33
SDR_DATA43 SDR_DATA11
R97 34 33 R294
36 35
33 33
SDR_DATA44 38 37 SDR_DATA12
R99 40 39 R297
33 42 41 33
SDR_DATA45 SDR_DATA13
44 43
R105 46 45
R299
33 48 47 33
SDR_DATA46 SDR_DATA14
R117 50 49 R316
52 51
33 33
SDR_DATA47 54 53 SDR_DATA15
R318
56 55
33
SDR_CKE0 58 57 R317
D
R321 +3V3 60 59 33
SDR_CK0
33
SDR_CAS +3V3 R340
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

R298
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

62 61 33
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

SDR_RAS
33 64 63
SDR_CKE1 R100
R101 66 65
33
68 67 SDR_WE
33
SDR_ADD12 70 69 R300
R341 72 71 33
SDR_S0
33 74 73
SDR_ADD13
76 75
R102
R301 78 77 33
SDR_S1
+3V3 +3V3
R106 33 80 79 R302
SDR_CK1
82 81
33 33
SDR_DATA48 84 83 SDR_DATA16
R320 86 85 R119
33 88 87 33
C SDR_DATA49 SDR_DATA17
90 89
R121 92 91
R322
33 94 93 33
SDR_DATA50 SDR_DATA18
R324 96 95 R123
98 97
33 33
SDR_DATA51 100 99 SDR_DATA19
R125 102 101 R326
33 104 103 33
SDR_DATA52 SDR_DATA20
106 105
R128 108 107 R328
33 110 109
SDR_DATA53 33
SDR_DATA21
R338 112 111 R336
114 113
33 33
SDR_DATA54 116 115 SDR_DATA22
R337 118 117 R335
33 120 119 33
SDR_DATA55 SDR_DATA23
122 121
B 124 123
126 125
128 127
R339 130 129
R315 132 131
R116 R135
33
SDR_ADD7 33 33 33
SDR_DATA56 134 133 SDR_DATA24 SDR_ADD6
R313 136 135
R319 R115 R113
33 138 137
SDR_BA0 33 33 33
SDR_DATA57 140 139 SDR_DATA25 SDR_ADD8
R311
R314 SDR_I2CCLK 142 141 SDR_I2CDAT R114 R111
33
SDR_BA1 33 144 143 33 33
SDR_DATA58 SDR_DATA26 SDR_ADD9
R334 R312 R112 R132
33
SDR_ADD11 33 +3V3 33 33
SDR_DATA59 +3V3 SDR_DATA27 SDR_ADD10
R333 R309 R110 R131
33
SDR_DQMB6 33 33 33
SDR_DATA60 SDR_DATA28 SDR_DQMB2

A R332 R310 R109 R130

33 33 33 33
837 0147 042 Rev.A

SDR_DQMB7 SDR_DATA61 SDR_DATA29 SDR_DQMB3

R308 SDRAM SOCKET R108
FORM:

33 33
SDR_DATA62 SDR_DATA30
R307 R107
33 33
SDR_DATA63 SDR_DATA31

SHEET DESCRIPTION:
"7350" VIDEO BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1219 000 SE C 6 11

 1 2 3 4 5 6 7 8 9 10 11

C244
R281

47N
+5VB
10 VTR_5P

R269
75

C226
U21

120P
F R267 4
U22
SAA7104 (ENCODER)
CLK_27M 51 43 ENC0_VCC L3 75
2
V+ LMH6644
XTALI VDDA1 -
2U7 1 VTR_FCHROMOUT
VDDA2 44 L5 3
+
50 XTALO VDDA3 52 V-
2U7

C245
VDDA4 53 R287 11

47N
ENC_PIXCLKA 20 6 C224 C223 -5VB

75
R257
PIXCLKI VDDD1 +3V3 10

R258
ENC_PIXCLKA 19 12
PIXCLKI VDDD2 390P 560P
VTR_5N

75
ENC_CLKOUT 27 25
PIXCLKO VDDD3
36 VDDD4 58
LLC
R285
ENCODER_CYC0 24 41 VTR_CHROMOUT 75
PD0 RED_CR_C_CVBS
ENCODER_CYC1 23 42 VTR_LUMOUT

C228
PD1 GREEN_VBS_CVBS

ENCODER_CYC[7:0]

120P
ENCODER_CYC2 22 PD2 BLUE_CB_CVBS 45 VTR_COMPOUT R284 4
U22
ENCODER_CYC3 21 LMH6644
PD3 L4 75
6
V+
ENCODER_CYC4 61 40 -
PD4 HSM_CSYNC 2U7 7 VTR_FLUMOUT
ENCODER_CYC5 62 PD5 VSM 39 L6 5
+
ENCODER_CYC6 63 54 2U7 V-
E PD6 TVD
ENCODER_CYC7 64 11
PD7
TB34 C243 C225

75
R259
2 9

R271
PD8 TMS
3 PD9 TCLK 11 TB32 390P 560P

75
4 PD10 TDI 56 TB37
5 PD11 TDO 10 TB33 R289
TRST 55 TB36 75
17 FSVGC R291

C275
4K7 ENC_VERTSYNC 18 VSVGC R290 U22

120P
1K00 4
ENC_DATAREQ 28 46
R262 CBO RSET
L9 75 V+
ENC_HORSYNC 29 47 9
HSVGC RDUMP -
2U7 8 VTR_FCOMPOUT
38 SRES TTXRQ_XCLKO2 59 12 L10 10
+
60 ENC_SYNCRES 1K00
+3V3 R261 TTX_SRES R292 2U7 V-
37 RTCI R293
1K00 11
35 48 C276 C274

75
R296
OUT_EN VSSA1

R304
VSSA2 49 390P 560P

75
VSSD1 7
ENC0_I2CDAT 15 13
SDA VSSD2
D ENC0_I2CCLK 14 SCL VSSD3 26 U22
4
I2C_RESET0 8 57
U25 RESET VSSD4 R270 13
V+
-
14
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

I2C ADDRESS 75
The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

74LCX244
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

12
WRITE = 88H +
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

19 G V-
READ = 89H
11 A1 Y1 9 11
13 A2 Y2 7
15 A3 Y3 5
17 A4 Y4 3
R352
75

C309
R126

120P
R350 U29
1K00

U25 4 R351
74LCX244 L12 75
2
V+ LMH6644
- 75
1 G 2U7 1 PRN_FRED
L13 3
2 A1 Y1 18 U30 +
V-
2U7
4 A2 Y2 16 CLK_27M SAA7104 (ENCODER)
C ENC1_VCC
11
6 14 51 43 C308 C307

75
R353
A3 Y3 XTALI VDDA1

R348
XCLK_27MA 8 A4 Y4 12 VDDA2 44 390P 560P

75
50 XTALO VDDA3 52
VDDA4 53
ENC_PIXCLKA 20 PIXCLKI VDDD1 6 R357
+3V3
ENC_PIXCLKA 19 12 75
PIXCLKI VDDD2
27 25

C345
PIXCLKO VDDD3

120P
36 LLC VDDD4 58 R358 4
U29
R355
L15 75
13
V+ LMH6644
ENCODER_CYC0 24 41 PRN_RED - 75
PD0 RED_CR_C_CVBS 2U7 14 PRN_FGREEN
ENCODER_CYC1 23 PD1 GREEN_VBS_CVBS 42 PRN_GREEN L17 12
+
ENCODER_CYC[7:0]

ENCODER_CYC2 22 45 PRN_BLUE 2U7 V-

PD2 BLUE_CB_CVBS
ENCODER_CYC3 21 11
PD3
C348 C342

75
R381
ENCODER_CYC4 61 40 PRN_SYNC

R392
PD4 HSM_CSYNC
ENCODER_CYC5 62 39 390P 560P
PD5 VSM

75
ENCODER_CYC6 63 54
PD6 TVD
ENCODER_CYC7 64 PD7 R369
B 2 PD8 TMS 9 TB41 75
3 PD9 TCLK 11 TB39

C344
4 PD10 TDI 56 TB49 R370 U29

120P
4
R375 5 PD11 TDO 10 TB40 R367
L14 75 V+ LMH6644
4K7 TRST 55 TB48 9 - 75
2U7 8 PRN_FBLUE
17 FSVGC R372 L16 10
+
ENC_VERTSYNC 18 VSVGC 1K00 2U7 V-
28 CBO RSET 46
11
4K7 ENC_HORSYNC 29 47 C343 C341

75
R368
HSVGC RDUMP

C322
R371

R452 38 59 12 R354

47N
SRES TTXRQ_XCLKO2 390P 560P
75

60 ENC_SYNCRES 1K00
TTX_SRES R373 10 PRN_5P

+5VB
+3V3
37 RTCI R374
35 OUT_EN VSSA1 48
1K00 VSSA2 49

R359 VSSD1 7
4
U29
ENC1_I2CDAT 15 13
R366
SDA VSSD2
6
V+ LMH6644
ENC1_I2CCLK 14 26 - 75
SCL VSSD3 7 PRN_FSYNC
A I2C_RESET0 8 RESET VSSD4 57 5
+
837 0147 042 Rev.A

V-

C323
I2C ADDRESS
75
R360

R356 11

47N
WRITE = 88H
FORM:

10
READ = 89H

-5VB
PRN_5N

SHEET DESCRIPTION:
"7350" VIDEO BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1219 000 SE C 7 11

 1 2 3 4 5 6 7 8 9 10 11

R161 R164 R163 R162

C77
47N
4K7 1K5 82
10

+5VB

+5VB
EQUIP_LEVEL=2 : Non montare R152
EQUIP_LEVEL=3 : Gestione LCD (sviluppi futuri) +3V3 33
CLK40D

330U
L21
R155
TL431AC
U42 33
CLK40C
R169 CR5 R170 CY2305

C80
470P
1K00 1K00 6 VDD CLKout 8 R151
D40C CLK1 3
33
1 2 CLK40B
REF CLK2
-5VB +5VB R157 R168 C436 C437 CLK3 5 CLK40A
220K 47N 4 7 33
33K 470N GND CLK4
R156
1 U49

2
BAV99W
CR4
U47 AD7896
8 R160 U47
TLC2262 8 PHSCLK 4 2
R165 R166 2
V+ SCLK VDD
- 120K V+ TLC2262
3

1K00 10K 1 6 -
PHYSIO 3 7 1 5 PHDATA

R254

R226

R385

R306
+ VIN SDATA

2
V-
5
+
C81

R171

47

47

47

47
V-
4 PHCONV 7 8
E CONVST BUSY

4K7
4 10U C218 C184 C367 C285
R158

R159

3 6 47P 47P 47P 47P

3M3

12K

AGND DGND
2 2 2 2

R167
C82
47N

10
-5VB

+3V3

R189
33
R431

R407

+3V3 MCKE
47K

47K

D
R410 R73
1K00 33
U45 MADD0 R61
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

R409
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

R416

74LVT273 U37 33
R74

22K
470K
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

MDAT0
LSGW 11 CLK 74LCX245 1K00 +3V3
1 19 MADD1
33 R62
RES G
1
R406 33
LC3 3 2 RESET T/R MDAT1
C438 1D 1Q
LC4 4 5 FLASH
LCA[0:4]
LCA0 18 2 LA0
LA[0:4] R75
470N
2D 2Q B1 A1 R63
LC5 7 6 LCA1 17 3 LA1 33
3D 3Q B2 A2 MADD2 U4 33
8 9 LCA2 16 4 LA2 MDAT2
4D 4Q B3 A3
13 12 LCA3 15 5 LA3 MT48LCM16A2
5D 5Q B4 A4 R76 1 3
R64
14 15 LCA4 14 6 LA4 VDD VDDQ
6D 6Q B5 A5 33 33
LCRW LRW MADD3 14 VDD VDDQ 9 MDAT3
17 7D 7Q 16 13 B6 A6 7
TCLK TCLKI 27 VDD VDDQ 43
18 8D 8Q 19 12 B7 A7 8
LSVID LSVIDEO R53 VDDQ 49 R65
11 B8 A8 9
33 MCLK 38 CLK 33
MADD4

R225
MDAT4

R224
C U38 37
R52 R66

47
CKE

47
2
74LCX138 C183 33 DQ0 33
C182 MADD5 23 4 MDAT5
LCA0 1 15 A0 DQ1
A Y0 33P
LCA1 33P 24 A1 DQ2 5 R67
2 B Y1 14 R51
LCA2 25 A2 DQ3 7
3 C Y2 13 33
33 26 8 MDAT6
12 MADD6 A3 DQ4
Y3
29 A4 DQ5 10 R68
Y4 11
LCRW R50 30 A5 DQ6 11
6 G1 Y5 10 33
31 13 MDAT7
LSGR 4 9 33 A6 DQ7
G2A Y6
5 7
R425 MADD7 32 A7 DQ8 42 MDAT8
G2B Y7
4K7 MADD8 33 44 33
A8 DQ9

+3V3
U44 33 34 45
A9 DQ10 R44
74LCX245 R49 22 A10 DQ11 47 MDAT9
19 LDEN 35 48 33
G MADD9 A11 DQ12
+3V3 1 LCRW 36 50
T/R 33 NC/(A12) DQ13 R43
21 51 MDAT10
LC0 18 2 LD0 BA1 DQ14
B1 A1 R48 20 53 33
LC1 17 3 LD1 MADD10 BA0 DQ15
B2 A2
B LC2 16 B3 A3 4 LD2 33 R42
18 39 MDAT11
LC3 15 5 LD3 RAS DQMH
B4 A4
MADD11 R72 17 15 33
LC4 14 6 LD4 CAS DQML
B5 A5
LC5 LD5 33 16 WE R41
13 B6 A6 7
R47 19
R418

R417

R419

R421

R423

R424

U46 LC6 12 8 LD6 CS MDAT12

B7 A7
MADD12 6
LC7 LD7 VSSQ
100

100

100

100

100

100

11 9 33
74LCX244 B8 A8 MADD[0:12]
33 28 12
VSS VSSQ
1G 1 2 2 2 2 2 41 46
R40
19
R182 VSS VSSQ
MDAT13
2G MBADD1 54 52
VSS VSSQ
LC0 18 2 33
1Y1 1A1 33
LC1 16 4 U36 R39
1Y2 1A2 R71
LC2 14 1Y3 1A3 6 74LCX245 MBADD0 MDAT14
LC3 12 8 19 33 33
1Y4 1A4 G
MBADD[0:1]
LC4 9 11 1
2Y1 2A1 T/R R70 R38
LC5 7 13 MDAT15
2Y2 2A2 LC8 18 2 LD8 MRAS
B1 A1
LC6 5 15 33
2Y3 2A3 LC9 17 3 LD9 33 MDAT[0:15]
B2 A2
LC7 3 17
2Y4 2A4 LC10 16 B3 A3 4 LD10
R191 R60
LC[0:7] MDQMH
A
R422

R420

R426

R427

R428

R429

LC11 15 5 LD11 MCAS

B4 A4
LC12 LD12 33
100

100

100

100

100

100
837 0147 042 Rev.A

14 B5 A5 6 33
LC13 13 B6 A6 7 LD13
R190 R46
MDQML
FORM:

LC14 12 8 LD14 MWE

B7 A7
LC15 11 9 LD15 33
B8 A8 33
LC[0:15] LD[0:15]
R187 R45
MCS
33
R188
SHEET DESCRIPTION:
"7350" VIDEO BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1219 000 SE C 8 11

 1 2 3 4 5 6 7 8 9 10 11

+2V2 C3 C5
+2V2
U24 +1V26 U26 +1V5
1U 1U
TPS72501 TPS72501
2 IN OUT 4 2 IN OUT 4

C45 C42 C294 C51

R104

R343
1 EN FB 5 1 EN FB 5
1U 1U

3K9

27K
4U7 4U7
F GND C141 C169 C163 C164 C142 C158 C216 C219 GND C349 C389 C336 C387 C318 C338
C37 C50
470N 470N 47N 47N 47N 47N 47N 47N 470N 470N 47N 47N 47N 47N
47U 47U
3 3

R103

R342
120K

120K
C170 C220 C137 C140 C194 C192 C161 C388 C353 C403 C316 C390 C404
470N 470N 47N 47N 47N 47N 47N 470N 470N 47N 47N 47N 47N

C4 +2V2 C7 +1V5B
+2V2 U3 +1V8A
U14 1U
1U
TPS72501 TPS72501
2 IN OUT 4
2 IN OUT 4

R201
C125 1 5

R174
E C89 1 5 C29 EN FB
C13 EN FB

27K
47K
1U C213 C265 C273 C212 C206 C233
1U C126 C180 C134 C185 C100 C111 4U7 GND C30
4U7 GND C6 470N 470N 47N 47N 47N 47N
470N 470N 47N 47N 47N 47N 47U
47U 3
3

R202
R172

120K
100K

C135 C98 C110 C147 C107 C103 C268 C284 C207 C234 C272 C281
470N 470N 47N 47N 47N 47N
470N 470N 47N 47N 47N 47N

+3V3AUX

D
C47 C210 C59 C62 C395 C406 C60 C57 C56 C55 C58 C54 C48 C325 C38 C36 C44 C41 C34 C43 C49 C35
10U 470N 470N 47N 47N 47N 47N 47N 47N 47N 47N 10U 470N 470N 47N 47N 47N 47N 47N 47N 47N 47N
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
document may be reproduced, copied distributed or in any way exploited.All rights reserved.

+3V3
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

C76 C31 C113 C378 C400 C375 C376 C377 C413 C412 C399 C416 C415 C414
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
47U 47U

TP3
C39 C25 C153 C131 C187 C156 C155 C154 C114 C115 C116 C117 C136 C157
10U 47U 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

C52 C139 C191 C215 C240 C188 C189 C190 C236 C214 C295 C239 C238 C237 C432 C435 C159
C 10U 470N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

TP4
C222 C193 C299 C312 C330 C296 C297 C298 C326 C311 C300 C329 C328 C327 C138 C143 C171 C160 C217 C221 C204 C203
470N 470N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

C148 C357 C304 C314 C335 C301 C302 C303 C331 C313 C369 C334 C333 C332 C127 C211 C119 C270 C209 C128 C120 C123
47N 47N 47N 47N 47N 47N
470N 470N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

TP2
C372 C398 C411 C370 C371 C373 C407 C397 C374 C410 C409 C408 C261 C235 C208 C99 C256 C255 C251 C105
C365 C364 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
470N 470N

C350 C132 C90 C91 C86 C92 C93 C94 C85 C96 C97 C430 C289 C429 C108 C118 C112 C264 C266 C263 C109 C121
470N 470N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

B
TP6
C129 C122 C447 C440 C267 C277 C229 C246 C324 C347 C346 C310 C427 C431 C252 C253 C254 C269 C133 C124 C181 C232
470N 470N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

C257 C106 C355 C362 C360 C359

470N 470N 47N 47N 47N 47N

TP1
C262 C271 C258 C88 C195 C175 C196 C197 C165 C145 C146 C151 C152 C167 C177 C361 C405 C319 C356 C317 C352
470N 470N 470N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

C418 C402 C393 C380 C340 C321 C306 C417 C401 C392 C379 C339 C396 C351 C358 C354 C363 C391
47N 47N 47N 47N 47N 47N
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
A
837 0147 042 Rev.A

TP5
FORM:

C286 C290 C305 C320 C287 C291 C441 C428 C83 C394
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N

SHEET DESCRIPTION:
"7350" VIDEO BOARD
A2 Document Revision: SHEET: OF:

by EpD Number: 950 1219 000 SE C 9 10

 1 2 3 4 5 6 7 8 9 10 11

VCC P1 P2 P3 ALIMENTAZIONI IMPLICITE

L23 -----------------------
100U
A1 B1 A1 B1 A1 B1 NET: +1V26 NET: +1V5
D40C
C75 ---------- -------------
A2 B2 A2 B2 A2 B2 VGA_LVN4
PRN_CNT0 U18.171 U31.U17 U31.G15
47U A3 B3 A3 B3 A3 B3 VGA_LVP4 U18.165 U31.U6 U31.G8
VMA6 VMA7 PRN_CNT1
U18.148 U31.T16 U31.G7
F A4 B4 VMA8 A4 B4 VMA9 PRN_CNT2 A4 B4 VGA_LVN3
U18.121 U31.T15 U31.F17
A5 B5 A5 B5 A5 B5 VGA_LVP3 U18.113 U31.T8 U31.F6
VMA10 VMA11 PRN_CNT3
U18.100 U31.T7
A6 B6 A6 B6 A6 B6 VGA_LVN2
VMA12 VMA13 U18.77 U31.R16
A7 B7 A7 B7 A7 B7 VGA_LVP2 U18.50 U31.R7
VMA14 VMA15
U18.33 U31.H16
A8 B8 A8 B8 A8 B8 VGA_LVN1
VMA16 VMA17 U18.21 U31.H7
A9 B9 A9 B9 A9 B9 VGA_LVP1 U18.9 U31.G16
VMA18 VMA19
A10 B10 A10 B10 A10 B10 VGA_LVN0
VMA20 VMA21
PSPROG A11 B11 A11 B11 A11 B11 VGA_LVP0
VMA22 VMA23
A12 B12 VMA24 A12 B12 VMA25 A12 B12
PSTDI A13 B13 PSTMS A13 B13 A13 B13
VMA26 VMA27
PSTDO A14 B14 PSTCK A14 B14 VTR_LUMIN A14 B14 NET: +3V3
VMA28 VMA29 VTR_FLUMOUT
---------------------------------
A15 B15 A15 B15 VTR_CHROMIN A15 B15 VTR_FCHROMOUT U46.20 U34.65 U18.80 U19.65
LCD_EVENN0 A16 B16 LCD_ODDN0 A16 B16 VTR_COMPIN A16 B16 U16.91 U34.41 U18.53 U19.41
VTR_FCOMPOUT
U16.65 U34.15 U18.36 U19.15
LCD_EVENP0 A17 B17 LCD_ODDP0 A17 B17 A17 B17 U16.41 U33.91 U18.12 U25.20
A18 B18 A18 B18 A18 B18 U16.15 U33.65 U45.20 UP2.32
VMD0 VMD1 PRN_FRED SVGA_RED
U27.91 U33.41 U38.16 UP3.32
LCD_EVENN1 A19 B19 LCD_ODDN1 A19 B19 A19 B19
VMD2 VMD3 PRN_FGREEN SVGA_GREEN U27.65 U33.15 U36.20
LCD_EVENP1 A20 B20 LCD_ODDP1 A20 B20 A20 B20 U27.41 U44.20 U37.20
VMD4 VMD5 PRN_FBLUE SVGA_BLUE
L26 -6V U27.15 UP1.37 U41.97
E A21 B21 VMD6 A21 B21 VMD7 PRN_FSYNC A21 B21 U28.91 U18.168 U41.82
LCD_EVENN2 A22 B22 LCD_ODDN2 A22 B22 22U A22 B22 U28.65 U18.141 U41.67
VMD8 VMD9 CRT_HSYNC CRT_VSYNC
U28.41 U18.124 U41.53
LCD_EVENP2 A23 B23 LCD_ODDP2 A23 B23 A23 B23
VMD10 VMD11 VID_HSYNC VID_VSYNC U28.15 U18.105 U7.14
A24 B24 A24 B24 A24 B24 U34.91 U18.94 U19.91
VMD12 VMD13 C73
LCD_EVENNCK A25 B25 LCD_ODDN3 A25 B25 47U A25 B25
VMD14 VMD15 PHYSIO TBASE
LCD_EVENPCK A26 B26 LCD_ODDP3 A26 B26 A26 B26 NET: GND
ECG
--------
A27 B27 A27 B27 ECGSCLK A27 B27 U46.10 U33.17 U23.L9 U15.K13 U31.N9
LCD_EVENN3 A28 B28 LCD_ODDNCK A28 B28 A28 B28 U16.90 U33.10 U23.K14 U15.K12 U31.M14
ECGCONV TIMING
U16.76 U33.5 U23.K13 U15.K11 U31.M13
LCD_EVENP3 LCD_ODDPCK

+VT

+VT
A29 B29 A29 B29 ECGDATA A29 B29 U16.71 U44.10 U23.K12 U15.K10 U31.M12
A30 B30 A30 B30 A30 B30 U16.67 UP1.46 U23.K11 U15.K9 U31.M11
+6V U16.60 UP1.27 U23.K10 U15.J14 U31.M10
LCDBRITE A31 B31 LCDSLEEP A31 B31 A31 B31
L25 U16.55 U18.174 U23.K9 U15.J13 U31.M9
A32 B32 A32 B32 A32 B32 U16.40 U18.157 U23.J14 U15.J12 U31.L14
MRESET_DONE 22U GRA0 GRA1
U16.26 U18.153 U23.J13 U15.J11 U31.L13
A33 B33 A33 B33 GRA2 A33 B33 GRA3 U16.21 U18.144 U23.J12 U15.J10 U31.L12
A34 B34 A34 B34 A34 B34 U16.17 U18.130 U23.J11 U15.J9 U31.L11
AVG_DATA0 AVG_DATA1 GRA4 GRA5
C72 U16.10 U18.117 U23.J10 U15.G12 U31.L10
AVG_DATA2 A35 B35 AVG_DATA3 A35 B35 GRA6 A35 B35 GRA7 U16.5 U18.109 U23.J9 U15.G11 U31.L9
A36 B36 A36 B36 47U A36 B36 U27.90 U18.97 U23.D19 U15.C20 U31.K14
AVG_DATA4 AVG_DATA5
U27.76 U18.91 U23.D4 U15.C3 U31.K13
AVG_DATA6 A37 B37 AVG_DATA7 A37 B37 A37 B37 U27.71 U18.83 U23.C20 U15.B21 U31.K12
AVG_DATA8 A38 B38 AVG_DATA9 R437 A38 B38 L24 +3V3 A38 B38 U27.67 U18.73 U23.C3 U15.B2 U31.K11
D U27.60 U18.65 U23.B21 U15.A22 U31.K10
AVG_DATA10 A39 B39 AVG_DATA11 33 A39 B39 A39 B39 U27.55 U18.56 U23.B2 U15.A1 U31.K9
22U
A40 B40 LSVID A40 B40 A40 B40 U27.40 U18.47 U23.A22 U41.98 U31.J14
AVG_DATA12 AVG_DATA13
C446 U27.26 U18.39 U23.A1 U41.83 U31.J13
A41 B41 A41 B41 A41 B41
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;

The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this

AVG_DATA14 AVG_DATA15 U27.21 U18.29 U15.AB22 U41.68 U31.J12

document may be reproduced, copied distributed or in any way exploited.All rights reserved.

A42 B42 47P A42 B42 C71 A42 B42 U27.17 U18.16 U15.AB1 U41.52 U31.J11
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.

VMAUX1
U27.10 U45.10 U15.AA21 U41.13 U31.J10
A43 B43 A43 B43 47U A43 B43
XY_ADD0 XY_ADD1 VMAUX0 VMAUX2 U27.5 U38.8 U15.AA2 U7.7 U31.J9
A44 B44 A44 B44 A44 B44 U28.90 U36.10 U15.Y20 U19.90 U31.D19
XY_ADD2 XY_ADD3 VMAS VMDS
U28.76 U37.10 U15.Y3 U19.76 U31.D4
XY_ADD4 A45 B45 XY_ADD5 R435 A45 B45 VMBH A45 B45 VMBL U28.71 U23.AB22 U15.T12 U19.71 U31.C20
A46 B46 A46 B46 A46 B46 U28.67 U23.AB1 U15.T11 U19.67 U31.C3
XY_ADD6 XY_ADD7 33 LSGR
U28.60 U23.AA21 U15.P14 U19.60 U31.B21
XY_ADD8 A47 B47 MCYCLE_START LSGW A47 B47 R436 VMRW A47 B47 VMACK U28.55 U23.AA2 U15.P13 U19.55 U31.B2
A48 B48 C444 A48 B48 A48 B48 U28.40 U23.Y20 U15.P12 U19.40 U31.A22
SCAN_MODE0 SCAN_MODE1 LCA0 LCA1 33 VMMODE TCLK
U28.26 U23.Y3 U15.P11 U19.26 U31.A1
A49 B49 47P A49 B49 LSECG A49 B49 U28.21 U23.W19 U15.P10 U19.21 U25.10
U28.17 U23.W4 U15.P9 U19.17 UP2.16
U28.10 U23.P14 U15.N14 U19.10 UP3.16
C445 U28.5 U23.P13 U15.N13 U19.5
A50 B50 A50 B50 A50 B50 U34.90 U23.P12 U15.N12 U35.26
47P
U34.76 U23.P11 U15.N11 U35.25
SCAN_MODE2 A51 B51 SCAN_MODE3 LCA2 A51 B51 LCA3 VMA0 A51 B51 VMA1 U34.71 U23.P10 U15.N10 U31.AB22
+3V3 A52 B52 A52 B52 A52 B52 U34.67 U23.P9 U15.N9 U31.AB1
SCAN_MODE4 SCAN_MODE5 LCA4 LCRW VMA2 VMA3
U34.60 U23.N14 U15.M16 U31.AA21
SCAN_MODE6 A53 B53 SCAN_MODE7 LC0 A53 B53 LC1 VMA4 A53 B53 VMA5 U34.55 U23.N13 U15.M14 U31.AA2
C SCAN_MODE8 A54 B54 SCAN_MODE9 LC2 A54 B54 LC3 A54 B54 U34.40 U23.N12 U15.M13 U31.Y20
U34.26 U23.N11 U15.M12 U31.Y3
A55 B55 A55 B55 A55 B55
1K00
R438

LC4 LC5 U34.21 U23.N10 U15.M11 U31.W19

A56 B56 A56 B56 A56 B56 U34.17 U23.N9 U15.M10 U31.W4
LC6 LC7
U34.10 U23.M14 U15.M9 U31.P14
A57 B57 LC8 A57 B57 LC9 A57 B57 U34.5 U23.M13 U15.M7 U31.P13
A58 B58 A58 B58 A58 B58 +2V2 U33.90 U23.M12 U15.L16 U31.P12
LC10 LC11 L22 U33.76 U23.M11 U15.L14 U31.P11
PANPOS A59 B59 LC12 A59 B59 LC13 A59 B59 U33.71 U23.M10 U15.L13 U31.P10
15U
A60 B60 A60 B60 A60 B60 U33.67 U23.M9 U15.L12 U31.P9
LC14 LC15
U33.60 U23.L14 U15.L11 U31.N14
U33.55 U23.L13 U15.L10 U31.N13
C74 U33.40 U23.L12 U15.L9 U31.N12
U33.26 U23.L11 U15.L7 U31.N11
47U
U33.21 U23.L10 U15.K14 U31.N10

ALIMENTAZIONI MODIFICATE
------------------------

NET: +1V5B NET: +1V8A

COMPONENTI NON MONTATI: ---------- ----------
------------------------- U23.U17 U15.V18
C102 EQUIP_LEVEL 2 U23.U6 U15.V5
B C104 EQUIP_LEVEL 2 U23.T16 U15.U17
C184 EQUIP_LEVEL 2 U23.T15 U15.U6
C186 EQUIP_LEVEL 2 U23.T8 U15.T16
C218 EQUIP_LEVEL 2 U23.T7 U15.T15
C285 EQUIP_LEVEL 2 U23.R16 U15.T8
C367 EQUIP_LEVEL 2 U23.R7 U15.T7
C439 EQUIP_LEVEL 2 U23.H16 U15.R16
C442 EQUIP_LEVEL 2 U23.H7 U15.R7
C449 EQUIP_LEVEL 2 U23.G16 U15.H16
C87 EQUIP_LEVEL 2 U23.G15 U15.H7
R15 EQUIP_LEVEL 2 U23.G8 U15.G16
R17 EQUIP_LEVEL 2 U23.G7 U15.G15
R175 EQUIP_LEVEL 2 U23.F17 U15.G8
R192 EQUIP_LEVEL 2 U23.F6 U15.G7
+6V U40 -5VB R196 EQUIP_LEVEL 2 U15.F17
ALLAGARE MIN O25 SQ IN +5VB -6V R226 EQUIP_LEVEL 2 U15.F6
VCC U50 +3V3AUX LP3964-ADJ U43 R227 EQUIP_LEVEL 2
NET: +3V3AUX
U15.E18
R230 EQUIP_LEVEL 2 U15.E5
2 3 ------------
LP3964-ADJ VIN VOUT UCC384DP-ADJ R245 EQUIP_LEVEL 2
U23.AB11
R254 EQUIP_LEVEL 2
2 3 2 5 U23.AA22
R150

VIN VOUT VIN VOUT R306 EQUIP_LEVEL 2

1 4 U23.AA1
SD ADJ 3 C434 R385 EQUIP_LEVEL 2
27K

C65 VIN U23.M22

R147