ADC0820 8-Bit High Speed mP Compatible A/D Converter with Track/Hold Function

February 1995

ADC0820 8-Bit High Speed mP Compatible

A/D Converter with Track/Hold Function
General Description Features
By using a half-flash conversion technique, the 8-bit Y Built-in track-and-hold function
ADC0820 CMOS A/D offers a 1.5 ms conversion time and Y No missing codes
dissipates only 75 mW of power. The half-flash technique Y No external clocking
consists of 32 comparators, a most significant 4-bit ADC Y Single supplyÐ5 VDC
and a least significant 4-bit ADC. Y Easy interface to all microprocessors, or operates
The input to the ADC0820 is tracked and held by the input stand-alone
sampling circuitry eliminating the need for an external sam- Y Latched TRI-STATEÉ output
ple-and-hold for signals moving at less than 100 mV/ms. Y Logic inputs and outputs meet both MOS and T2L volt-
For ease of interface to microprocessors, the ADC0820 has age level specifications
been designed to appear as a memory location or I/O port Y Operates ratiometrically or with any reference value
without the need for external interfacing logic. equal to or less than VCC
Y 0V to 5V analog input voltage range with single 5V
Key Specifications supply
Y Resolution 8 Bits Y No zero or full-scale adjust required
Y Conversion Time 2.5 ms Max (RD Mode) Y Overflow output available for cascading
1.5 ms Max (WR-RD Mode) Y 0.3× standard width 20-pin DIP
Y Input signals with slew rate of 100 mV/ms converted Y 20-pin molded chip carrier package
without external sample-and-hold to 8 bits Y 20-pin small outline package
Y Low Power 75 mW Max Y 20-pin shrink small outline package (SSOP)
Y Total Unadjusted Error g (/2 LSB and g 1 LSB

Connection and Functional Diagrams

Dual-In-Line, Small Outline and
SSOP Packages

TL/H/5501–1
Top View

Molded Chip Carrier

Package

TL/H/5501 – 2
FIGURE 1

TL/H/5501–33
See Ordering Information
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation TL/H/5501 RRD-B30M115/Printed in U. S. A.

 Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required, Lead Temp. (Soldering, 10 sec.)
please contact the National Semiconductor Sales Dual-In-Line Package (plastic) 260§ C
Office/Distributors for availability and specifications. Dual-In-Line Package (ceramic) 300§ C
Supply Voltage (VCC) 10V Surface Mount Package
Vapor Phase (60 sec.) 215§ C
Logic Control Inputs b 0.2V to VCC a 0.2V
Infrared (15 sec.) 220§ C
Voltage at Other Inputs and Output b 0.2V to VCC a 0.2V
Storage Temperature Range b 65§ C to a 150§ C Operating Ratings (Notes 1 & 2)
Package Dissipation at TA e 25§ C 875 mW Temperature Range TMINsTAsTMAX
Input Current at Any Pin (Note 5) 1 mA ADC0820CCJ b 40§ C s TA s a 85§ C
Package Input Current (Note 5) 4 mA ADC0820CIWM b 40§ C s TA s a 85§ C
ADC0820BCN, ADC0820CCN 0§ CsTAs70§ C
ESD Susceptability (Note 9) 1200V
ADC0820BCV, ADC0820CCV 0§ CsTAs70§ C
ADC0820BCWM, ADC0820CCWM 0§ CsTAs70§ C
ADC0820CCMSA 0§ CsTAs70§ C
VCC Range 4.5V to 8V

Converter Characteristics The following specifications apply for RD mode (pin 7 e 0), VCC e 5V, VREF( a ) e 5V,
and VREF(b) e GND unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e Tj e 25§ C.

ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820CCV
ADC0820CCJ
ADC0820BCWM, ADC0820CCWM
Limit
Parameter Conditions ADC0820CCMSA, ADC0820CIWM
Units
Tested Design Tested Design
Typ Typ
Limit Limit Limit Limit
(Note 6) (Note 6)
(Note 7) (Note 8) (Note 7) (Note 8)
Resolution 8 8 8 Bits
Total Unadjusted ADC0820BCN, BCWM g (/2 g (/2 LSB
Error ADC0820CCJ g1 LSB
(Note 3) ADC0820CCN, CCWM, CIWM, g1 g1 LSB
ADC0820CCMSA g1 g1 LSB
Minimum Reference 2.3 1.00 2.3 1.2 kX
Resistance
Maximum Reference 2.3 6 2.3 5.3 6 kX
Resistance
Maximum VREF( a ) VCC VCC VCC V
Input Voltage
Minimum VREF(b) GND GND GND V
Input Voltage
Minimum VREF( a ) VREF(b) VREF(b) VREF(b) V
Input Voltage
Maximum VREF(b) VREF( a ) VREF( a ) VREF( a ) V
Input Voltage
Maximum VIN Input VCC a 0.1 VCC a 0.1 VCC a 0.1 V
Voltage
Minimum VIN Input GNDb0.1 GNDb0.1 GNDb0.1 V
Voltage
Maximum Analog CS e VCC
Input Leakage VIN e VCC 3 0.3 3 mA
Current VIN e GND b3 b 0.3 b3 mA
Power Supply VCC e 5V g 5% g (/16 g (/4 g (/16 g (/4 g (/4 LSB
Sensitivity

2
 DC Electrical Characteristics The following specifications apply for VCC e 5V, unless otherwise specified.
Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C.

ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820CCV
ADC0820CCJ
ADC0820BCWM, ADC0820CCWM
Limit
Parameter Conditions ADC0820CCMSA, ADC0820CIWM
Units
Tested Design Tested Design
Typ Typ
Limit Limit Limit Limit
(Note 6) (Note 6)
(Note 7) (Note 8) (Note 7) (Note 8)
VIN(1), Logical ‘‘1’’ VCC e 5.25V CS, WR, RD 2.0 2.0 2.0 V
Input Voltage Mode 3.5 3.5 3.5 V
VIN(0), Logical ‘‘0’’ VCC e 4.75V CS, WR, RD 0.8 0.8 0.8 V
Input Voltage Mode 1.5 1.5 1.5 V
IIN(1), Logical ‘‘1’’ VIN(1) e 5V; CS, RD 0.005 1 0.005 1 mA
Input Current VIN(1) e 5V; WR 0.1 3 0.1 0.3 3 mA
VIN(1) e 5V; Mode 50 200 50 170 200 mA
IIN(0), Logical ‘‘0’’ VIN(0) e 0V; CS, RD, WR, b 0.005 b1 b 0.005 b1 mA
Input Current Mode
VOUT(1), Logical ‘‘1’’ VCC e 4.75V, IOUT eb360 mA; 2.4 2.8 2.4 V
Output Voltage DB0–DB7, OFL, INT
VCC e 4.75V, IOUT eb10 mA; 4.5 4.6 4.5 V
DB0–DB7, OFL, INT
VOUT(0), Logical ‘‘0’’ VCC e 4.75V, IOUT e 1.6 mA; 0.4 0.34 0.4 V
Output Voltage DB0–DB7, OFL, INT, RDY
IOUT, TRI-STATE VOUT e 5V; DB0–DB7, RDY 0.1 3 0.1 0.3 3 mA
Output Current VOUT e 0V; DB0–DB7, RDY b 0.1 b3 b 0.1 b 0.3 b3 mA
ISOURCE, Output VOUT e 0V; DB0–DB7, OFL b 12 b6 b 12 b 7.2 b6 mA
Source Current INT b9 b 4.0 b9 b 5.3 b 4.0 mA
ISINK, Output Sink VOUT e 5V; DB0–DB7, OFL, 14 7 14 8.4 7 mA
Current INT, RDY
ICC, Supply Current CS e WR e RD e 0 7.5 15 7.5 13 15 mA

AC Electrical Characteristics The following specifications apply for VCC e 5V, tr e tf e 20 ns, VREF( a ) e 5V,
VREF(b) e 0V and TA e 25§ C unless otherwise specified.

Tested Design
Typ
Parameter Conditions Limit Limit Units
(Note 6)
(Note 7) (Note 8)
tCRD, Conversion Time for RD Mode Pin 7 e 0, (Figure 2) 1.6 2.5 ms
tACC0, Access Time (Delay from Pin 7 e 0, (Figure 2) tCRD a 20 tCRD a 50 ns
Falling Edge of RD to Output Valid)
tCWR-RD, Conversion Time for Pin 7 e VCC; tWR e 600 ns, 1.52 ms
WR-RD Mode tRD e 600 ns; (Figures 3a and 3b)
tWR, Write Time Min Pin 7 e VCC; (Figures 3a and 3b) 600 ns
Max (Note 4) See Graph 50 ms
tRD, Read Time Min Pin 7 e VCC; (Figures 3a and 3b) 600 ns
(Note 4) See Graph
tACC1, Access Time (Delay from Pin 7 e VCC, tRDktI; (Figure 3a)
Falling Edge of RD to Output Valid) CL e 15 pF 190 280 ns
CL e 100 pF 210 320 ns
tACC2, Access Time (Delay from Pin 7 e VCC, tRDltI; (Figure 3b)
Falling Edge of RD to Output Valid) CL e 15 pF 70 120 ns
CL e 100 pF 90 150 ns
tACC3, Access Time (Delay from Rising RPULLUP e 1k and CL e 15 pF 30 ns
Edge of RDY to Output Valid)

3
AC Electrical Characteristics (Continued) The following specifications apply for VCC e 5V, tr e tf e 20 ns,
VREF( a ) e 5V, VREF(b) e 0V and TA e 25§ C unless otherwise specified.
Tested Design
Typ
Parameter Conditions Limit Limit Units
(Note 6)
(Note 7) (Note 8)
tI, Internal Comparison Time Pin 7 e VCC; (Figures 3b and 4) 800 1300 ns
CL e 50 pF
t1H, t0H, TRI-STATE Control RL e 1k, CL e 10 pF 100 200 ns
(Delay from Rising Edge of RD to
Hi-Z State)
tINTL, Delay from Rising Edge of Pin 7 e VCC, CL e 50 pF
WR to Falling Edge of INT tRDltI; (Figure 3b) tI ns
tRDktI; (Figure 3a) tRD a 200 tRD a 290 ns
tINTH, Delay from Rising Edge of (Figures 2, 3a and 3b) 125 225 ns
RD to Rising Edge of INT CL e 50 pF
tINTHWR, Delay from Rising Edge of (Figure 4) , CL e 50 pF 175 270 ns
WR to Rising Edge of INT
tRDY, Delay from CS to RDY (Figure 2) , CL e 50 pF, Pin 7 e 0 50 100 ns
tID, Delay from INT to Output Valid (Figure 4) 20 50 ns
tRI, Delay from RD to INT Pin 7 e VCC, tRDktI 200 290 ns
(Figure 3a)
tP, Delay from End of Conversion (Figures 2, 3a, 3b and 4) 500 ns
to Next Conversion (Note 4) See Graph
Slew Rate, Tracking 0.1 V/ms
CVIN, Analog Input Capacitance 45 pF
COUT, Logic Output Capacitance 5 pF
CIN, Logic Input Capacitance 5 pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4: Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Accuracy vs tWR and Accuracy vs tRD graphs.
Note 5: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l V a ) the absolute value of current at that pin should be limited
to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four.
Note 6: Typicals are at 25§ C and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: Human body model, 100 pF discharaged through a 1.5 kX resistor.

TRI-STATE Test Circuits and Waveforms

t1H

TL/H/5501–3
TL/H/5501 – 4

t0H

tr e 20 ns TL/H/5501 – 6
TL/H/5501–5

4
Timing Diagrams

Note: On power-up the state of INT can be high or low. TL/H/5501 – 7

FIGURE 2. RD Mode (Pin 7 is Low)

TL/H/5501 – 8

FIGURE 3a. WR-RD Mode (Pin 7 is High and tRDktI)

TL/H/5501 – 10

FIGURE 4. WR-RD Mode (Pin 7 is High)

Stand-Alone Operation

TL/H/5501 – 9
FIGURE 3b. WR-RD Mode (Pin 7 is High and tRDltI)

5
Typical Performance Characteristics
Power Supply Current vs
Logic Input Threshold Conversion Time (RD Mode) Temperature (not including
Voltage vs Supply Voltage vs Temperature reference ladder)

Accuracy vs tWR Accuracy vs tRD Accuracy vs tp

Accuracy vs VREF tI, Internal Time Delay vs Output Current vs

[VREF e VREF ( a )bVREF (b)] Temperature Temperature

VREF TL/H/5501 – 11
*1 LSB e
256

6
Description of Pin Functions
Pin Name Function Pin Name Function
1 VIN Analog input; range e GNDsVINsVCC 9 INT WR-RD Mode
2 DB0 TRI-STATE data outputÐbit 0 (LSB) INT going low indicates that the conver-
3 DB1 TRI-STATE data outputÐbit 1 sion is completed and the data result is in
4 DB2 TRI-STATE data outputÐbit 2 the output latch. INT will go low, E 800 ns
5 DB3 TRI-STATE data outputÐbit 3 (the preset internal time out, tI) after the
6 WR/RDY WR-RD Mode rising edge of WR (see Figure 3b ); or INT
WR: With CS low, the conversion is start- will go low after the falling edge of RD, if
ed on the falling edge of WR. Approxi- RD goes low prior to the 800 ns time out
mately 800 ns (the preset internal time (see Figure 3a ). INT is reset by the rising
out, tI) after the WR rising edge, the result edge of RD or CS (see Figures 3a and
of the conversion will be strobed into the 3b ).
output latch, provided that RD does not RD Mode
occur prior to this time out (see Figures INT going low indicates that the conver-
3a and 3b ). sion is completed and the data result is in
RD Mode the output latch. INT is reset by the rising
RDY: This is an open drain output (no in- edge of RD or CS (see Figure 2 ).
ternal pull-up device). RDY will go low af- 10 GND Ground
ter the falling edge of CS; RDY will go 11 VREF(b) The bottom of resistor ladder, voltage
TRI-STATE when the result of the conver- range: GNDsVREF(b)sVREF( a ) (Note
sion is strobed into the output latch. It is 5)
used to simplify the interface to a micro- 12 VREF( a ) The top of resistor ladder, voltage range:
processor system (see Figure 2 ). VREF(b)sVREF( a )sVCC (Note 5)
7 Mode Mode: Mode selection inputÐit is inter- 13 CS CS must be low in order for the RD or WR
nally tied to GND through a 50 mA current to be recognized by the converter.
source. 14 DB4 TRI-STATE data outputÐbit 4
RD Mode: When mode is low 15 DB5 TRI-STATE data outputÐbit 5
WR-RD Mode: When mode is high 16 DB6 TRI-STATE data outputÐbit 6
8 RD WR-RD Mode 17 DB7 TRI-STATE data outputÐbit 7 (MSB)
With CS low, the TRI-STATE data outputs 18 OFL Overflow outputÐIf the analog input is
(DB0-DB7) will be activated when RD higher than the VREF( a ), OFL will be low
goes low (see Figure 4 ). RD can also be at the end of conversion. It can be used to
used to increase the speed of the con- cascade 2 or more devices to have more
verter by reading data prior to the preset resolution (9, 10-bit). This output is always
internal time out (tI, E 800 ns). If this is active and does not go into TRI-STATE
done, the data result transferred to output as DB0 – DB7 do.
latch is latched after the falling edge of 19 NC No connection
the RD (see Figures 3a and 3b ). 20 VCC Power supply voltage
RD Mode
With CS low, the conversion will start with
RD going low, also RD will enable the
TRI-STATE data outputs at the comple-
tion of the conversion. RDY going TRI-
STATE and INT going low indicates the
completion of the conversion (see Figure
2 ).

1.0 Functional Description

1.1 GENERAL OPERATION
The internal DAC is actually a subsection of the MS flash
The ADC0820 uses two 4-bit flash A/D converters to make converter. This is accomplished by using the same resistor
an 8-bit measurement (Figure 1 ). Each flash ADC is made ladder for the A/D as well as for generating the DAC signal.
up of 15 comparators which compare the unknown input to The DAC output is actually the tap on the resistor ladder
a reference ladder to get a 4-bit result. To take a full 8-bit which most closely approximates the analog input. In addi-
reading, one flash conversion is done to provide the 4 most tion, the ‘’sampled-data’’ comparators used in the ADC0820
significant data bits (via the MS flash ADC). Driven by the 4 provide the ability to compare the magnitudes of several
MSBs, an internal DAC recreates an analog approximation analog signals simultaneously, without using input summing
of the input voltage. This analog signal is then subtracted amplifiers. This is especially useful in the LS flash ADC,
from the input, and the difference voltage is converted by a where the signal to be converted is an analog difference.
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.

7
1.0 Functional Description (Continued)
1.2 THE SAMPLED-DATA COMPARATOR The actual circuitry used in the ADC0820 is a simple but
Each comparator in the ADC0820 consists of a CMOS in- important expansion of the basic comparator described
verter with a capacitively coupled input (Figure 5 ). Analog above. By adding a second capacitor and another set of
switches connect the two comparator inputs to the input switches to the input (Figure 6 ), the scheme can be expand-
capacitor (C) and also connect the inverter’s input and out- ed to make dual differential comparisons. In this circuit, the
put. This device in effect now has one differential input pair. feedback switch and one input switch on each capacitor (Z
A comparison requires two cycles, one for zeroing the com- switches) are closed in the zeroing cycle. A comparison is
parator, and another for making the comparison. then made by connecting the second input on each capaci-
tor and opening all of the other switches (S switches). The
In the first cycle, one input switch and the inverter’s feed-
change in voltage at the inverter’s input, as a result of the
back switch (Figure 5a ) are closed. In this interval, C is
change in charge on each input capacitor, will now depend
charged to the connected input (V1) less the inverter’s bias
on both input signal differences.
voltage (VB, approximately 1.2V). In the second cycle (Fig-
ure 5b ), these two switches are opened and the other (V2) 1.3 ARCHITECTURE
input’s switch is closed. The input capacitor now subtracts In the ADC0820, one bank of 15 comparators is used in
its stored voltage from the second input and the difference each 4-bit flash A/D converter (Figure 7 ). The MS (most
is amplified by the inverter’s open loop gain. The inverter’s significant) flash ADC also has one additional comparator to
input (VBÊ ) becomes detect input overrange. These two sets of comparators op-
C erate alternately, with one group in its zeroing cycle while
VBb(V1bV2)
C a CS the other is comparing.
and the output will go high or low depending on the sign of
VBÊ bVB.

TL/H/5501 – 13

TL/H/5501–12
C
# VO e VB # VBÊ b VB e (V2 b V1)
C a CS
# V on C e V1 b VB bA
# CS e stray input # VOÊ e [CV2 b CV1]
C a CS
node capacitor
# VOÊ is dependent on V2 b V1
# VB e inverter input
bias voltage

FIGURE 5b. Compare Phase

FIGURE 5a. Zeroing Phase
FIGURE 5. Sampled-Data Comparator

bA
VO e [C1(V2 b V1) a C2(V4 b V3)]
C1 a C2 a CS
bA
e [DQC1 a DQC2]
C1 a C2 a CS

TL/H/5501 – 14

FIGURE 6. ADC0820 Comparator (from MS Flash ADC)

8
Detailed Block Diagram

TL/H/5501 – 15

FIGURE 7

9
1.0 Functional Description (Continued)
When a typical conversion is started, the WR line is brought WR then RD Mode
low. At this instant the MS comparators go from zeroing to
With the MODE pin tied high, the A/D will be set up for the
comparison mode (Figure 8 ). When WR is returned high af-
WR-RD mode. Here, a conversion is started with the WR
ter at least 600 ns, the output from the first set of compara-
input; however, there are two options for reading the output
tors (the first flash) is decoded and latched. At this point the
data which relate to interface timing. If an interrupt driven
two 4-bit converters change modes and the LS (least signifi-
scheme is desired, the user can wait for INT to go low be-
cant) flash ADC enters its compare cycle. No less than 600
fore reading the conversion result (Figure B ). INT will typi-
ns later, the RD line may be pulled low to latch the lower 4
cally go low 800 ns after WR’s rising edge. However, if a
data bits and finish the 8-bit conversion. When RD goes low,
shorter conversion time is desired, the processor need not
the flash A/Ds change state once again in preparation for
wait for INT and can exercise a read after only 600 ns (Fig-
the next conversion.
ure A ). If this is done, INT will immediately go low and data
Figure 8 also outlines how the converter’s interface timing will appear at the outputs.
relates to its analog input (VIN). In WR-RD mode, VIN is
measured while WR is low. In RD mode, sampling occurs
during the first 800 ns of RD. Because of the input connec-
tions to the ADC0820’s LS and MS comparators, the con-
verter has the ability to sample VIN at one instant (Section
2.4), despite the fact that two separate 4-bit conversions are
being done. More specifically, when WR is low the MS flash
is in compare mode (connected to VIN), and the LS flash is
in zero mode (also connected to VIN). Therefore both flash
ADCs sample VIN at the same time.
1.4 DIGITAL INTERFACE
The ADC0820 has two basic interface modes which are se-
lected by strapping the MODE pin high or low.
TL/H/5501 – 17
RD Mode FIGURE A. WR-RD Mode (Pin 7 is High and tRDktI)
With the MODE pin grounded, the converter is set to Read
mode. In this configuration, a complete conversion is done
by pulling RD low until output data appears. An INT line is
provided which goes low at the end of the conversion as
well as a RDY output which can be used to signal a proces-
sor that the converter is busy or can also serve as a system
Transfer Acknowledge signal.

RD Mode (Pin 7 is Low)

TL/H/5501 – 18
FIGURE B. WR-RD Mode (Pin 7 is High and tRDltI)
Stand-Alone
For stand-alone operation in WR-RD mode, CS and RD can
be tied low and a conversion can be started with WR. Data
will be valid approximately 800 ns following WR’s rising
edge.

TL/H/5501–16 WR-RD Mode (Pin 7 is High) Stand-Alone Operation

When in RD mode, the comparator phases are internally

triggered. At the falling edge of RD, the MS flash converter
goes from zero to compare mode and the LS ADC’s com-
parators enter their zero cycle. After 800 ns, data from the
MS flash is latched and the LS flash ADC enters compare
mode. Following another 800 ns, the lower 4 bits are recov-
ered.

TL/H/5501 – 19

10
1.0 Functional Description (Continued)

TL/H/5501 – 20
Note: MS means most significant
LS means least significant
FIGURE 8. Operating Sequence (WR-RD Mode)

OTHER INTERFACE CONSIDERATIONS 2.2 INPUT CURRENT

In order to maintain conversion accuracy, WR has a maxi- Due to the unique conversion techniques employed by the
mum width spec of 50 ms. When the MS flash ADC’s sam- ADC0820, the analog input behaves somewhat differently
pled-data comparators (Section 1.2) are in comparison than in conventional devices. The A/D’s sampled-data com-
mode (WR is low), the input capacitors (C, Figure 6 ) must parators take varying amounts of input current depending
hold their charge. Switch leakage and inverter bias current on which cycle the conversion is in.
can cause errors if the comparator is left in this phase for The equivalent input circuit of the ADC0820 is shown in
too long. Figure 10a . When a conversion starts (WR low, WR-RD
Since the MS flash ADC enters its zeroing phase at the end mode), all input switches close, connecting VIN to thirty-one
of a conversion (Section 1.3), a new conversion cannot be 1 pF capacitors. Although the two 4-bit flash circuits are not
started until this phase is complete. The minimum spec for both in their compare cycle at the same time, VIN still sees
this time (tP, Figures 2, 3a, 3b, and 4 ) is 500 ns. all input capacitors at once. This is because the MS flash
converter is connected to the input during its compare inter-
2.0 Analog Considerations val and the LS flash is connected to the input during its
zeroing phase (Section 1.3). In other words, the LS ADC
2.1 REFERENCE AND INPUT uses VIN as its zero-phase input.
The two VREF inputs of the ADC0820 are fully differential The input capacitors must charge to the input voltage
and define the zero to full-scale input range of the A to D through the on resistance of the analog switches (about 5
converter. This allows the designer to easily vary the span kX to 10 kX). In addition, about 12 pF of input stray capaci-
of the analog input since this range will be equivalent to the tance must also be charged. For large source resistances,
voltage difference between VIN( a ) and VIN(b). By reducing the analog input can be modeled as an RC network as
VREF(VREF e VREF( a )bVREF(b)) to less than 5V, the sen- shown in Figure 10b . As RS increases, it will take longer for
sitivity of the converter can be increased (i.e., if VREF e 2V the input capacitance to charge.
then 1 LSB e 7.8 mV). The input/reference arrangement
In RD mode, the input switches are closed for approximately
also facilitates ratiometric operation and in many cases the
800 ns at the start of the conversion. In WR-RD mode, the
chip power supply can be used for transducer power as well
time that the switches are closed to allow this charging is
as the VREF source.
the time that WR is low. Since other factors force this time
This reference flexibility lets the input span not only be var- to be at least 600 ns, input time constants of 100 ns can be
ied but also offset from zero. The voltage at VREF(b) sets accommodated without special consideration. Typical total
the input level which produces a digital output of all zeroes. input capacitance values of 45 pF allow RS to be 1.5 kX
Though VIN is not itself differential, the reference design without lengthening WR to give VIN more time to settle.
affords nearly differential-input capability for most measure-
ment applications. Figure 9 shows some of the configura-
tions that are possible.

11
2.0 Analog Considerations (Continued)
External Reference 2.5V Full-Scale Power Supply as Reference Input Not Referred to GND

TL/H/5501–21 TL/H/5501 – 22

TL/H/5501 – 23
FIGURE 9. Analog Input Options

TL/H/5501 – 25

TL/H/5501–24
FIGURE 10a FIGURE 10b

2.3 INPUT FILTERING Sampled-data comparators, by nature of their input switch-

It should be made clear that transients in the analog input ing, already accomplish this function to a large degree (Sec-
signal, caused by charging current flowing into VIN, will not tion 1.2). Although the conversion time for the ADC0820 is
degrade the A/D’s performance in most cases. In effect the 1.5 ms, the time through which VIN must be 1/2 LSB stable
ADC0820 does not ‘‘look’’ at the input when these tran- is much smaller. Since the MS flash ADC uses VIN as its
sients occur. The comparators’ outputs are not latched ‘‘compare’’ input and the LS ADC uses VIN as its ‘‘zero’’
while WR is low, so at least 600 ns will be provided to input, the ADC0820 only ‘‘samples’’ VIN when WR is low
charge the ADC’s input capacitance. It is therefore not nec- (Sections 1.3 and 2.2). Even though the two flashes are not
essary to filter out these transients by putting an external done simultaneously, the analog signal is measured at one
cap on the VIN terminal. instant. The value of VIN approximately 100 ns after the
rising edge of WR (100 ns due to internal logic prop delay)
2.4 INHERENT SAMPLE-HOLD will be the measured value.
Another benefit of the ADC0820’s input mechanism is its Input signals with slew rates typically below 100 mV/ms can
ability to measure a variety of high speed signals without the be converted without error. However, because of the input
help of an external sample-and-hold. In a conventional SAR time constants, and charge injection through the opened
type converter, regardless of its speed, the input must re- comparator input switches, faster signals may cause errors.
main at least (/2 LSB stable throughout the conversion pro- Still, the ADC0820’s loss in accuracy for a given increase in
cess if full accuracy is to be maintained. Consequently, for signal slope is far less than what would be witnessed in a
many high speed signals, this signal must be externally conventional successive approximation device. An SAR
sampled, and held stationary during the conversion. type converter with a conversion time as fast as 1 ms would
still not be able to measure a 5V 1 kHz sine wave without
the aid of an external sample-and-hold. The ADC0820, with
no such help, can typically measure 5V, 7 kHz waveforms.

12
3.0 Typical Applications
8-Bit Resolution Configuration

TL/H/5501 – 26
9-Bit Resolution Configuration

TL/H/5501 – 27
Telecom A/D Converter Multiple Input Channels

# VIN e 3 kHz max g 4VP

# No track-and-hold needed
# Low power consumption TL/H/5501 – 28

TL/H/5501 – 29

13
3.0 Typical Applications (Continued)
8-Bit 2-Quadrant Analog Multiplier

TL/H/5501 – 30

Fast Infinite Sample-and-Hold

TL/H/5501 – 31

14
 Digital Waveform Recorder
3.0 Typical Applications (Continued)

15
TL/H/5501 – 32
Ordering Information
Total Temperature
Part Number Package
Unadjusted Error Range
ADC0820BCV V20AÐMolded Chip 0§ C to a 70§ C
Carrier
ADC0820BCWM g (/2 LSB M20BÐWide Body Small 0§ C to a 70§ C
Outline
ADC0820BCN N20AÐMolded DIP 0§ C to a 70§ C
ADC0820CCJ J20AÐCerdip b 40§ C to a 85§ C
ADC0820CCMSA MSA20Ð Shrink Small 0§ C to a 70§ C
Outline
Package
ADC0820CCV g 1 LSB V20AÐMolded Chip 0§ C to a 70§ C
Carrier
ADC0820CCWM M20BÐWide Body Small 0§ C to a 70§ C
Outline
ADC0820CIWM M20BÐWide Body Small b 40§ C to a 85§ C
Outline
ADC0820CCN N20AÐMolded DIP 0§ C to a 70§ C

16
17
Physical Dimensions inches (millimeters)

Hermetic Dual-In-Line Package (J)

Order Number ADC0820CCJ
NS Package Number J20A

SO Package (M)
Order Number ADC0820BCWM, ADC0820CCWM or ADC0820CIWM
NS Package Number M20B

18
Physical Dimensions inches (millimeters) (Continued)

Shrink Small Outline Package (SSOP)

Order Number ADC0820CCMSA
NS Package Number MSA20

Molded Dual-In-Line Package (N)

Order Number ADC0820BCN or ADC0820CCN
NS Package Number N20A

19
ADC0820 8-Bit High Speed mP Compatible A/D Converter with Track/Hold Function
Physical Dimensions inches (millimeters) (Continued)

Molded Chip Carrier Package (V)

Order Number ADC0820BCV or ADC0820CCV
NS Package Number V20A

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