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FABRICATION AND CHARACTERIATION OF

P-N JUNCTION DIODE.

INTRODUCTION

Most semiconductor devices contain at least one junction

between P type and N type. Material (sometimes metal
semiconductor). This P-N junctions are the fundamental to
the performance of function such as rectification and
switching in electronic circuits. Here the discussion is about
how the P-N junction diodes are made. The technology of
junction fabrication is a broad subject which includes the
accumulated knowledge and experience of many research
and manufacturing groups forming junctions and making
contacts to them in mountings suitable for device.

Impurities of one type may be introduced into regions of a

crystal which was grown by doping of the opposite type. In
this case the doping is changed at the junction there are no
gross changes in the latice structure itself. Dependind upon
the manufacturing process There are many types of
junctions such as i) gross junction ii) alloyed junction iii)
diffused junctions. Among these junctions we made only
diffused junction. The junction is formed by different
technology such as (i) diffusion (ii) ion implantation (iii)
chemical vapor deposition (CVD) (iv) Molecular beam
epitaxy. Among these techniques we have used only
diffusion technology.

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BASIC MATERIALS, CHEMICALS AND EQUIPMENTS FOR THE PROCESS :-

a) Silicon Wafer :appropriately designed silicon wafers have been procured from
abroad. Wafers of 4 inch diameter and 350 µm thickness with resistivity 0.5
Ωcm orientation <100> is given for Semiconductor Diode Fabrication.

b) The TemPress diffusion Furnace: The diffusion furnace has been fitted with
quartz tubes in the stacks. The temperature rise and fall upto 1200 OC have been
tested using the microprocessor based temperature controller.

c) Oxygen and Nitrogen Gas :Highly pure oxygen and nitrogen gas together with
cylinders, valves and gas flow control have been used.

d) Bubbler : A water bubbler attach with the gas lines for wet gas delivery is used.

e) Boron Nitride cakes : Boron Nitride cakes has been required for P- type
dopent.

f) De–ionized water plant : De–ionized water plant has been required for
production of 18 MΩ water using doubled distilled water as the input.

g) Chemicals :Other necessary electronic grade chemicals is required.

h) A diamond cutter : A Diamond cutter is required for chip seperation.

i) Masks : Masks is required to maintain appropriate size of the device.

j) Ultra-Sonic vibrator : The ultra-sonic vibratior is required for cleaning

purpose.

k) The vaccume coating unit : The vaccume coating unit with 5 X 10-6 mm of Hg
Pr. vaccume with electron beam evaporation facility is used.

l) Dryer : A dryer is required.

m) Mask Aligner , Photoresist Spinner & Baking furnace : A mask aligner and
photoresist spinner and baking furnace is required for photo-lithography.

n) Temperature controlled heater :A chemical bench temperature controlled

heater is required

o) Voltmeter and Ammeter : voltmeter and ammeter is required for device

performance measurement.

p) Others essential items : Some other general purpose things is requires such as
tweezer, Safety Goggles, Covering dress for lab etc.

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THE VARIOUS PROCESS STEPS FOR REALIZATION

OF P-N JUNCTION DIODES ARE GIVEN BELOW :-

A) Testing of dopant by hot probe method.

B) Etching and polishing of Silicon wafer.
C) Cleaning of silicon wafer.
D) Oxidation.
E) Photo-lithography.
F) Etching of SiO2 Layer
G) Activation of Boron Nitride
Predeposition.
Oxidation
Removal of Borosilicate glass.
H) Metalization.
I) Photolithography
J) Device separation
K) Soldering or bonding for lead contact

DETAILS STEPS FOR THE FABRICATION OF THE P-N JUNCTION DIODE.

A ) Testing the type of dopant by hot probe methode.

At first the probes of the voltmeter is touched on the silicon surface. Then the
positive terminal of the voltmeter is heated (with a soldering iron) and the
reading is checked. If the reading is positive then the wafer is of n type and if the
voltage is negative then the wafer is P type.

In our case the voltmeter shows positive reading and so it is concluded that the
silicon wafer is of N-type.

Fig. 1 : (Hot probe testing to determine the wafer is P type or N type)

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B) Chemical Etching or Polishing

The given n type silicon wafer is a unpolished one. So polishing is required and is
done by 20 % NAOH solution at temperature 85O C for 3 to 5 minutes.

C) Wafer Cleaning

Wafer cleaning is a very important step in device fabrication process because of

the variety of organic and inorganic contaminants of unknown origin, which are
present on the semiconductor surface which detoriate the performance of the
device. The cleaning process is done by i) Acid cleaning process and ii) dry
plasma cleaning process. Here we have done the acid cleaning process.

i) Acid cleaning process.

1)Removing Dust Particle: The wafer is kept in a clean beaker containing hot
(85 OC ) Tri-Chloro-Ethelyn (TCE) and boiled for 5 minutes followed by 3
minute ultrasonic cleaning to remove dust particle.
2)Removing Oil and Grease:The wafer is then transferred to a beaker
containing hot (85 OC ) Acetone and again boiled for 5 minutes and followed by
ultrasonic cleaning for 3 minute.
3)Removing inorganic compound :The wafer is then transferred in a beaker
containing solution of H2SO4 : H2O2 at ratio 1:1 and is heated at 85 OC till the
reaction stop then cleaned into DI water to remove inorganic compounds.
4)Removing Silicon Di Oxide Layer : Then the wafer is dipped into 10% HF
solution for for 2 to 3 minutes and again cleaned into DI water to remove SiO 2
layer.
5)Removing Acidic Organic Compound :The wafer is then immersed in a
beaker containing solution of H2O : H2O2 : NH4OH at ratio 5:1:1 and is heated at
70OC for 10 minutes and then passed into cold DI water to remove acidic
organic compound.
6)Removing Alkaline Organic Compound :The wafer is then immersed in a
beaker containing solution of H2O : H2O2 : HCl at ratio 6:1:1 and heated at
70OC for 10 minute and then cleaned into DI water to remove alkaline organic
compound.
7)Rinsing and Drying :The wafer is rinsed in running DI water. The wafer is
then dried with a wafer dryer. Now the wafer is ready to oxidation.

D) Oxidation

The cleaned silicon wafer then placed in a quartz boat between two wafer
zone. The quartz boat with silicon wafer is then pushed very gently into the middle
zone of the pre-heated (1000 OC ) nitrogen ambient furnace. The oxidation process
is carried out by three step oxidation first dry oxidation then Wet oxidation and
then again dry oxidation.

The furnace is maintained at a temp of 1000 OC in O2 ambient with gas flow

rate 1 Lit/Minute for dry oxidation. For wet oxidation the bubbler temp is
maintained at 90 OC.
The process followed by 15 min dry oxidation then 30 minute wet oxidation
and again 15 minute dry oxidation.

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Temperature Controller, (3 Zone)

Heating Coils

Flue Gas

Wafer on Quartz Boat

Oxygen Gas
Bubbler

Fig . 2 Three Zone Furnace used for Oxidation and Deposition.

E) Photolithography

Photolithography is a process by which we get the proper structure of the device on

the wafer. We use negative photoresist. So for formation of diffusion area we used a
bright field mask. Photolithography process is done by some process steps as
follows.
(i) Coating of Photoresist by spining process : Vaccume holds the wafer on
spinner and a few drops of negative photoresist given on the wafer. Speed of
the Spinner is maintained at 4000 RPM for formation of very thin layer (5μm )
of photoresist for uniform coating and better adhetion.
(ii) Prebaking : The wafer coated with photoresist is then baked for 20 minute at
90 OC for better adhesion of the photoresist with wafer surface.
(iii) UV Expose : The wafer is exposed by UV source with the help of mask aligner
for 8 sec with appropriate mask.
(iv) Development of Photoresist : After exposure the wafer is developed and the
image of the device is obtained.
(v) Post Baking : After development the photoresist baked at 120 OC for 20 minute
for better adhesion of the resist.
(vi) Hard Photoresist removal : Hard photoresist is removed by acetone.

F) Etching of SiO2 layer

The wafer is then dipped in 10% HF solution for 3 minute and the exposed SiO 2
layer is etched away.

G) Diffusion :

As the given wafer is N type so we need to diffuse P type impurity into the wafer to
create P-N junction and we take Boron (P type) impurity for diffusion. The entire
diffusion is consisting the following process.

i) Activation : Solid source of boron i. e. boron nitride (BN) is placed on a quartz

boat and is very slowly pushed to the middle region of the furnace. The BN
wafer is activated in oxygen (flow rate 1 lit/min ambient at 1000 OC) for 30
minutes. During activation a skin of B2O3 is formed on the surface of BN wafer
according to the following reaction.
4 BN + 3O2 = 2 B2O3 + 2 N2

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ii) Pre deposition of Boron : The photolithographic silicon wafer and the activated
BN are then placed in quartz boat side by side within a spacing of 2 mm in
between them. The quartz boat and the silicon wafer is then pushed very gently
into the middle zone of the furnace, maintained at a temperature of 1000 OC in
N2 ambient. Pre-deposition of boron was carried out for 1 hour. Boron was
transported to the silicon surface by the inert carrier gas (here nitrogen) at the
diffusion temperature. Diffusion of boron was performed according to a reaction
between B2O3 and silicon is
2B2O3+ 3 Si = 3 SiO2 + 4B

iii) Oxidation : The furnace maintained at a temperature of 700 OC in the O2 ambient

with gas flow rate 1 lit/min with bubbler temp 90 OC . The diffused silicon wafer
pushed into the furnace for 10 to 15 minutes.

iv) Borosilicate Glass Removal : During predeposition and oxidation process at

temp 1000 OC the Boro-Silicate-Glass (BSG) becomes very hard and acts as
insulating layer. Presence of this layer prevents proper metalic contact with the
chips.

In oxidation step the wafer is placed on a quartz boat inside a quartz tube at
temperature 700 OC and wet oxygen is passed through the tube for 10 – 15 minute.
After oxidation the borosilicate glass layer becomes softend which can be easily
removed from the surface by low concentrate (10%) HF solution treatment. Now it is
ready for metalization.

H )Metalization

Metalization is one of the most important steps of device fabrication. Better

adhesion gives always better performance of the fabricated device. The substrate is
placed on the substrate holder. The vaccume level achieved upto 5 x 10-6 mm of Hg
with the help of rotary (RP) and diffusion pump (DP). High vaccume region is
required for metalization to achieve grater mean free path from source of metal
(which to be deposited) to the substrate (wafer have to be metalised) because to
avoid the collisions with other gas particles. Metalization has done by different
techniques such as (i) Thermal Evaporation for low melting point of metal (ii)
Electron beam technique when melting point of metal is high. (iii) RF sputtering
when metal oxide or bi-metals are used. (iv) plasma technique when both are gas.
Here the Electron beam technique is used.

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The schematic diagram of Vaccume coating unit is given below:

Fig. 3 (Vaccume coating unit)

Density of silicon is very low so it condenses easily and also evaporated quickly. Silicon
can capture air particles.

Operation Steps of vaccume coating unit:

i)Loading of the wafer.

ii)Rotary pump (RP) on, baking valve open, when vaccume
reached at 10-2 torr then backing closed.
iii)Roughing valve open, when vaccume level 10-2 Torr then
roughing valve closed.
iv)Again backing valve opened.
v)Water circulation on . Diffussion pump (DP) on, Baffel open
and achieved high vaccume.
vi)Then power switch on . After deposition (Here aluminium
deposition for ohmic contact) power switch off, baffel closed,
DP off.
vii)After 20 minutes water circulation off.
viii)Backing closed, RP off.

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Back side metalisation: Back side of the wafer Ag metalized same as above or
coating a silver paste with paint brush. After that heat treatment is required at 110 OC
for 10 minute and 700 OC for 45 second. If the backside coating is silver paste then it
is happened before the Al metalization because heat treatment is required for Al at
450 OC to 500 OC for 45 Second.

I )Photolithography

Photolithography is required for device isolation many deices can be fabricated in a

single wafer. It is done by the same process as stated earlier photolithography process.

Etching
Aluminum etching is done on the selective portion.

Hard-photoresist removal
Hard photoresist is removed by acetone.

J) Device-separation :

It is the process by which we can separate single device from the wafer (single P-N
junction diode from the wafer of many P-N junction diode). In our case the diamond
scriber is used for the separation of P-N junction diode.

K) Lead contact :

It is done with the help of bonding technique or otherwise soldering is required. Here
the soldering technique is used. A thin metallic ware is soldered on both side of the
device in our case.

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Lab Report on P-N Junction Diode Fabrication of 1st Semester of M-Tech in VLSI & Microelectronics
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PICTORIAL STEPS IN THE FABRICATION OF DIFFUSED P-N JUNCTION

1.Oxidize the Silicon wafer.

SiO2

2.Apply a layer of photoresist.

P hotoresist

3.Expose photoresist through mask A.

UV Ray

Mask

4.Remove unexposed photoresist.

5.Use HF etch to remove SiO2 windows. Etched out SiO2

6.Remove photoresist and diffuse Boron through windows in the SiO2 layer. Diffused Boron

7.Evaporate Aluminum onto the surface. Aluminum

8.Using steps 2-4 each away Aluminum except in P – contact areas.

Fig.4 (Operational Steps)

Characterization of the fabricated P-N junction diode

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Circuit Diagram

The basic circuit diagram of the voltage current characteristic of the P-N junction diode
is given below:

Variable Ammeter Diode to be tested

Voltage A
Source
Voltmeter
V

Fig. 5 (Circuit Diagram for performance test)

Connection Diagram

Power C onst. I C onst. V

Const ant Cur r ent Const ant Vol t age

Fine Course

Fig. 6 (Connection Diagram

Apparatus required for measurement:

i. Digital Multimeter as Ammeter. (Min step 1 μA in 200 μA range)

ii. Digital Multimeter as Voltmeter. (Min step 1 mV, Range 200 V DC)
iii. Variable voltage source (0-40 Volt with course and fine control).

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Lab Report on P-N Junction Diode Fabrication of 1st Semester of M-Tech in VLSI & Microelectronics
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Results:
Reverse Bias Result Forward Bias Results
Voltage Current Voltage Current
-10 -0.389 0.1 0.001
-9 -0.116 0.2 0.002
-8 -0.086 0.3 0.0035
-7 -0.06 0.4 0.005
-6 -0.053 0.5 0.0065
-5 -0.04 0.6 0.01
-4 -0.0215 0.7 0.0124
-3 -0.0133 0.8 0.0141
-2 -0.0075 1 0.018
-1 -0.0039 2 0.042
-0.5 -0.0027 3 0.202
-0.2 -0.002 4 0.318
0 0 5 0.666
6 1.3
7 2.68
8 3.97
9 6.4
10 10.77

V-I Charestics of P-N Junction Diode

12

11

10

7
Current in mA

-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10

-1

Voltage in Volts

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