NCP 3201 – Introduction to HDL

EXPERIMENT #4-3 – SELECTED SIGNAL ASSIGNMENTS

Objective(s):
The activity aims to demonstrate the procedures on how to develop VHDL
circuits using selected signal assignments
Intended Learning Outcomes (ILOs):
Design a VHDL model for a combinational logic circuit using selected signal
assignments.

Experiment 4-3A:
A selected signal assignment provides another technique to implement
concurrent signal assignments. In this approach, the signal assignment is based on a
specific value on the input signal.
The keyword with is used to begin the selected signal assignment. It is then
followed by the name of the input that will be used to dictate the value of the output.
Only a single variable name can be listed as the input. This means that if the
assignment is going to be based on multiple variables, they must first be concatenated
into a single vector name before starting the selected signal assignment.
After the input is listed, the keyword select signifies the beginning of the signal
assignments. An assignment is made to a signal based on a list of possible input values
that follow the keyword when. Multiple values of the input codes can be used and are
separated by commas. The keyword others is used to cover any input values that are
not explicitly stated.
One feature of selected signal assignments that makes its form even more
compact than other techniques is that multiple input codes that correspond to the same
output assignment can be listed on the same line pipe (|)-delimited.
Procedure:
a. Open ModelSim PE Student Edition.
b. In the Experiments Project tab. Create a file named Experiment4_3A.vhd
c. Write the following codes to the new file. If you imported an existing file
make sure that the code in the file is the same as shown below and its
filename is Experiment4_3A:
entity Experiment4_3A is
port (A, B, C : in bit;
F : out bit);
end entity;

architecture sim of Experiment4_3A is

signal ABC : bit_vector(2 downto 0);

begin
NCP 3201 – Introduction to HDL

ABC <= A & B & C;

with (ABC) select

F <= '1' when "000",
'0' when "001",
'1' when "010",
'0' when "011",
'0' when "100",
'0' when "101",
'1' when "110",
'0' when "111";

end architecture;

d. Compile the .vhd file by selecting the Experiment4_3A then click the
compile icon tool.
e. Make sure the file name is correct as Experiment4_3A the same as the
entity.
f. The compiled file will be by default under the “work” library in the library
tab.
g. Inside the work library, right-click the experiment4_3a entity and choose
Simulate to be redirected to the “sim” tab.
h. Click the run icon to simulate the program.
i. Change the value of each input signal by using the ‘Force’ property.

Result:

Observation:
The output follows the truth table. It’s like from the previous experiments except this
time it is implemented using the with and select. Also, it is noticeable that the bit vector
ABC is composed of concatenated bit A, B and C.
NCP 3201 – Introduction to HDL

Experiment 4-3B:
Procedure:
a. Open ModelSim PE Student Edition.
b. In the Experiments Project tab. Create a file named Experiment4_3B.vhd
c. Write the following codes to the new file. If you imported an existing file
make sure that the code in the file is the same as shown below and its
filename is Experiment4_3B:
entity Experiment4_3B is
port (A, B, C : in bit;
F : out bit);
end entity;

architecture sim of Experiment4_3B is

signal ABC : bit_vector(2 downto 0);

begin
ABC <= A & B & C;

with (ABC) select

F <= '1' when "000",
'1' when "010",
'1' when "110",
'0' when others;

end architecture;

d. Compile the .vhd file by selecting the Experiment4_3B then click the
compile icon tool.
e. Make sure the file name is correct as Experiment4_3B the same as the
entity.
f. The compiled file will be by default under the “work” library in the library
tab.
g. Inside the work library, right-click the experiment4_3b entity and choose
Simulate to be redirected to the “sim” tab.
h. Click the run icon to simulate the program.
i. Change the value of each input signal by using the ‘Force’ property.
NCP 3201 – Introduction to HDL

Result:

Observation:
The output is the same on the previous example, except this time it is much efficient in
terms of readability I’m not sure about the execution if it still processed as the previous
one but I guess this one will reduce the circuitry needed because of the don’t care
states.

Experiment 4_3C:
Procedure:
a. Open ModelSim PE Student Edition.
b. In the Experiments Project tab. Create a file named Experiment4_3C.vhd
c. Write the following codes to the new file. If you imported an existing file
make sure that the code in the file is the same as shown below and its
filename is Experiment4_3C:
entity Experiment4_3C is
port (A, B, C : in bit;
F : out bit);
end entity;

architecture sim of Experiment4_3C is

signal ABC : bit_vector(2 downto 0);

begin
ABC <= A & B & C;

with (ABC) select

F <= '1' when "000" | "010" | "110",
'0' when others;
NCP 3201 – Introduction to HDL

end architecture;
d. Compile the .vhd file by selecting the Experiment4_3C then click the
compile icon tool.
e. Make sure the file name is correct as Experiment4_3C the same as the
entity.
f. The compiled file will be by default under the “work” library in the library
tab.
g. Inside the work library, right-click the experiment4_3c entity and choose
Simulate to be redirected to the “sim” tab.
h. Click the run icon to simulate the program.
i. Change the value of each input signal by using the ‘Force’ property.

Result:

Observation:
Well, this is a much better version of the previous two examples.

Experiment 4_3D:
Procedure:
a. Open ModelSim PE Student Edition.
b. In the Experiments Project tab. Create a file named Experiment4_3D.vhd
c. Write the following codes to the new file. If you imported an existing file
make sure that the code in the file is the same as shown below and its
filename is Experiment4_3D:
entity Experiment4_3D is
NCP 3201 – Introduction to HDL

port (ABC : in bit_vector(2 downto 0);

F : out bit_vector(7 downto 0));
end entity;

architecture sim of Experiment4_3D is

begin

with (ABC) select

F <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111";

end architecture;

d. Compile the .vhd file by selecting the Experiment4_3D then click the
compile icon tool.
e. Make sure the file name is correct as Experiment4_3D the same as the
entity.
f. The compiled file will be by default under the “work” library in the library
tab.
g. Inside the work library, right-click the experiment4_3d entity and choose
Simulate to be redirected to the “sim” tab.
h. Click the run icon to simulate the program. Make sure that the Run length
is set to 100 ns.
i. Change the value of each input signal by using the ‘Force’ property. For bit
vector ABC if you want to have a data input of 011 you will force the value
3’h3 to the bit vector ABC rather than manipulating each of the bit values.

Result:
NCP 3201 – Introduction to HDL

Observation:
The output is the same from previous experiment which shifts the bit to the left each
clock pulse. The noticeable change here is now the input ABC was initialized as bit
vector and still implements the with and select.

Experiment 4_3E:
Procedure:
a. Open ModelSim PE Student Edition.
b. In the Experiments Project tab. Create a file named Experiment4_3E.vhd
c. Write the following codes to the new file. If you imported an existing file
make sure that the code in the file is the same as shown below and its
filename is Experiment4_3E:
entity Experiment4_3E is
port (ABC : in bit_vector(2 downto 0);
F : out bit_vector(6 downto 0));
end entity;

architecture sim of Experiment4_3E is

begin

with (ABC) select

F <= "1111110" when "000",
"0110000" when "001",
"1101101" when "010",
"1111001" when "011",
"0110011" when "100",
"1011011" when "101",
"1011111" when "110",
"1110000" when "111";

end architecture;

d. Compile the .vhd file by selecting the Experiment4_3E then click the
compile icon tool.
e. Make sure the file name is correct as Experiment4_3E the same as the
entity.
f. The compiled file will be by default under the “work” library in the library
tab.
g. Inside the work library, right-click the experiment4_3e entity and choose
Simulate to be redirected to the “sim” tab.
h. Click the run icon to simulate the program.
i. Change the value of each input signal by using the ‘Force’ property. For bit
vector ABC if you want to have a data input of 011 you will force the value
NCP 3201 – Introduction to HDL

3’h3 to the bit vector ABC rather than manipulating each of the bit values.

Result:

Observation:
The code is another version of the previous experiment where the output corresponds
to digit 0-7 in a seven segment display.

Experiment 4_3F:
Procedure:
a. Open ModelSim PE Student Edition.
b. In the Experiments Project tab. Create a file named Experiment4_3F.vhd
c. Write the following codes to the new file. If you imported an existing file
make sure that the code in the file is the same as shown below and its
filename is Experiment4_3F:
entity Experiment4_3F is
port (ABCD : in bit_vector(3 downto 0);
YZ : out bit_vector(1 downto 0));
end entity;

architecture sim of Experiment4_3F is

begin

with (ABCD) select

YZ <= "00" when "0001",
"01" when "0010",
"10" when "0100",
"11" when "1000",
"00" when others;
NCP 3201 – Introduction to HDL

end architecture;
d. Compile the .vhd file by selecting the Experiment4_3F then click the
compile icon tool.
e. Make sure the file name is correct as Experiment4_3F the same as the
entity.
f. The compiled file will be by default under the “work” library in the library
tab.
g. Inside the work library, right-click the experiment4_3f entity and choose
Simulate to be redirected to the “sim” tab.
h. Click the run icon to simulate the program.
i. Change the value of each input signal by using the ‘Force’ property. For bit
vector ABCD if you want to have a data input of 1000 you will force the
value 4’h8 to the bit vector ABCD rather than manipulating each of the bit
values.
Result:

Observation:
The code is another version of the previous experiment where the output looks like a 4
to 2 encoder.

Experiment 4_3G:
Procedure:
a. Open ModelSim PE Student Edition.
b. In the Experiments Project tab. Create a file named Experiment4_3G.vhd
c. Write the following codes to the new file. If you imported an existing file
make sure that the code in the file is the same as shown below and its
NCP 3201 – Introduction to HDL

filename is Experiment4_3G:
entity Experiment4_3G is
port (A,B,C,D : in bit;
Sel : in bit_vector(1 downto 0);
F : out bit);
end entity;

architecture sim of Experiment4_3G is

begin

with (Sel) select

F <= A when "00",
B when "01",
C when "10",
D when "11";

end architecture;

d. Compile the .vhd file by selecting the Experiment4_3G then click the
compile icon tool.
e. Make sure the file name is correct as Experiment4_3G the same as the
entity.
f. The compiled file will be by default under the “work” library in the library
tab.
g. Inside the work library, right-click the experiment4_3g entity and choose
Simulate to be redirected to the “sim” tab.
h. Click the run icon to simulate the program.
i. Change the value of each input signal by using the ‘Force’ property. For bit
vector Sel if you want to have a data input of 11 you will force the value
2’h3 to the bit vector ABCD rather than manipulating each of the bit
values.
Result:
NCP 3201 – Introduction to HDL

Observation:
The code is another version of the previous experiment where the output depends on
the value of bit that corresponds to state of SEL. In the last 200 ns of this simulation the
output follows the state of bit A when SEL<1:0> is ‘00’ and bit B when SEL<1:0> is ‘01’.

Experiment 4_3H:
Procedure:
a. Open ModelSim PE Student Edition.
b. In the Experiments Project tab. Create a file named Experiment4_3H.vhd
c. Write the following codes to the new file. If you imported an existing file
make sure that the code in the file is the same as shown below and its
filename is Experiment4_3H:
entity Experiment4_3H is
port (A : in bit;
Sel : in bit_vector(1 downto 0);
W,X,Y,Z : out bit);
end entity;

architecture sim of Experiment4_3H is

begin

with (Sel) select

W <= A when "00",
'0' when others;
with (Sel) select
X <= A when "01",
'0' when others;
with (Sel) select
Y <= A when "10",
'0' when others;
with (Sel) select
Z <= A when "11",
'0' when others;

end architecture;

d. Compile the .vhd file by selecting the Experiment4_3H then click the
compile icon tool.
e. Make sure the file name is correct as Experiment4_3H the same as the
entity.
f. The compiled file will be by default under the “work” library in the library
tab.
g. Inside the work library, right-click the experiment4_3h entity and choose
Simulate to be redirected to the “sim” tab.
h. Click the run icon to simulate the program.
NCP 3201 – Introduction to HDL

i. Change the value of each input signal by using the ‘Force’ property. For bit
vector Sel if you want to have a data input of 11 you will force the value
2’h3 to the bit vector ABCD rather than manipulating each of the bit
values.

Result:

Observation:
The code is another version of the last example of previous experiment where each bit
of the output depends on the value of bit that corresponds to state of SEL.