EECS 470 Lab 1

Verilog: Hardware Description Language

Department of Electrical Engineering and Computer Science

College of Engineering
University of Michigan

Thursday, 05th September, 2019

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Overview

EECS 470 Labs

Verilog

Verilog Flow Control

Testing

Project 1

Lab Assignment

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 EECS 470 Labs

Who?

I Contact Information
I Siying Feng - [email protected]
I Xueyang Liu - [email protected]
I Jielun Tan - [email protected]
I EECS 470 Piazza (click for link)
I Most of your project related questions should be asked here so that
other people can benefit from the answer.
I Reminder: Please do not post program code in public questions.
I See up-to-date office hours on the course website.

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 EECS 470 Labs

Where? When?

I Three Lab Sections

I 011 – Thursday 4:30 pm to 6:30 pm in 1620 BBB
I 012 – Friday 10:00 am to 12:00 pm in 1620 BBB
I 013 – Friday 12:30 pm to 2:30 pm in 1620 BBB
I These will become extra office hours after labs are over, for extra
project help.
I Please go to your assigned section: the class is very full.
I If you are on the wait list, you are welcome to attend if there is space.
I Please let enrolled students have first-priority for workstations.

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 EECS 470 Labs

What?

Lab 1 – Verilog: Hardware Description Language

Lab 2 – The Build System
Lab 3 – Writing Good Testbenches
Lab 4 – Revision Control
Lab 5 – Scripting
Lab 6 – SystemVerilog

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 EECS 470 Labs

Projects

Individual Verilog Projects

Project 1 – Priority Selectors
Project 2 – Pipelined Multiplier, Integer Square Root
Project 3 – Verisimple 5-stage Pipeline

NOTE: Your average of the individual projects must be over

50% to receive a passing grade in this class.
Group Project
Project 4 – Out-of-Order Processor (35%)

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 EECS 470 Labs

Advice

I These projects will take a non-trivial amount of time, especially if

you’re not a Verilog guru.
I You should start them early. Seriously. . .
I Especially Project 3

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 EECS 470 Labs

Project 4

I RV32IM Instruction Set Architecture (with some caveats)

I Groups of 4 to 5
I Start thinking about your groups now
I You’ll be spending hundreds of hours together this semester, so work
with people with whom you get along.
I Heavy Workload
I 100 hours/member, minimum
I 150 to 300 hours/member, more realistically
I This is a lower bound, not an upper. . .
I Class is heavily loaded to the end of the term

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 EECS 470 Labs

Administrivia

I Homework 1 is due Wednesday , 11th September, 2019 6:00 PM (turn

in via Gradescope)
I Project 1 is due Friday, 13th September, 2019 11:59 PM (turn in via
submission script)

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 Verilog

Intro to Verilog

What is Verilog?
I Hardware Description Language - IEEE 1364-2005
I Superseded by SystemVerilog - IEEE 1800-2009
I Two Forms
1. Behavioral
2. Structural
I It can be built into hardware. If you can’t think of at least one
(inefficient) way to build it, it might not be good.

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 Verilog

Intro to Verilog

What is Verilog?
I Hardware Description Language - IEEE 1364-2005
I Superseded by SystemVerilog - IEEE 1800-2009
I Two Forms
1. Behavioral
2. Structural
I It can be built into hardware. If you can’t think of at least one
(inefficient) way to build it, it might not be good.

Why do I care?

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 Verilog

Intro to Verilog

What is Verilog?
I Hardware Description Language - IEEE 1364-2005
I Superseded by SystemVerilog - IEEE 1800-2009
I Two Forms
1. Behavioral
2. Structural
I It can be built into hardware. If you can’t think of at least one
(inefficient) way to build it, it might not be good.

Why do I care?
I We use Behavioral Verilog to do computer architecture here.
I Semiconductor Industry Standard (VHDL is also common, more so in
Europe)
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 Verilog

The Difference Between Behavioral and Structural Verilog

Behavioral Verilog Structural Verilog

I Describes function of design I Describes construction of
I Abstractions design
I Arithmetic operations I No abstraction
(+,-,*,/) I Uses modules, corresponding
I Logical operations
(&,|,ˆ,~) to physical devices, for
everything

Suppose we want to build an adder?

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 Verilog

Structural Verilog by Example

a◦
u0 w_0
b◦ ◦s
u1
cin◦

w_1
u2
u4 ◦cout
w_2
u3

Figure: 1-bit Full Adder

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 Verilog

Structural Verilog by Example

module one_bit_adder(
input wire a,b,cin,
output wire sum,cout);
wire w_0,w_1,w_2;
xor u0(w_0,a,b);
xor u1(sum,w_0,cin);
and u2(w_1,w_0,cin);
and u3(w_2,a,b);
or u4(cout,w_1,w_2);
endmodule

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 Verilog

Behavioral Verilog by Example

module one_bit_adder(
input wire a,b,cin,
output wire sum,cout);
assign sum = a ^ b ^ cin;
assign cout = ((a ^ b) & cin) | a & b;
endmodule

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 Verilog

Behavioral Verilog by Example

module one_bit_adder(
input logic a,b,cin,
output logic sum,cout);

always_comb
begin
sum = a ^ b ^ cin;
cout = 1'b0;
if ((a ^ b) & cin) | (a & b))
cout = 1'b1;
end
endmodule

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 Verilog

Verilog Semantics

Lexical
I Everything is case sensitive.
I Type instances must start with A-Z,a-z,_. They may contain
A-Z,a-z,0-9,_,$.
I Comments begin with // or are enclosed with /* and */.

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 Verilog

Data Types

Synthesizable Data Types

wires Also called nets
wire a_wire;
wire [3:0] another_4bit_wire;

I Cannot hold state

logic Replaced reg in SystemVerilog
logic [7:0] an_8bit_register;
reg a_register;

I Holds state, might turn into flip-flops

I Less confusing than using reg with combinational logic
(coming up. . . )

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 Verilog

Data Types

Unsynthesizable Data Types

integer Signed 32-bit variable
time Unsigned 64-bit variable
real Double-precision floating point variable

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 Verilog

Types of Values

Four State Logic

0 False, low
1 True, high
Z High-impedance, unconnected net
X Unknown, invalid, don’t care

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 Verilog

Values

Literals/Constants
I Written in the format <bitwidth>’<base><constant>
I Options for <base> are. . .
b Binary
o Octal
d Decimal
h Hexadecimal

assign an_8bit_register = 8'b10101111;

assign a_32bit_wire = 32'hABCD_EF01;
assign a_4bit_logic = 4'hE;

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 Verilog

Verilog Operators
Arithmetic Shift
* Multiplication >> Logical right shift
/ Division << Logical left shift
+ Addition >>> Arithmetic right shift
- Subtraction <<< Arithmetic left shift
% Modulus Relational
** Exponentiation > Greater than
Bitwise >= Greater than or equal to
~ Complement < Less than
& And <= Less than or equal to
| Or != Inequality
~| Nor !== 4-state inequality
ˆ Xor == Equality
~ˆ Xnor === 4-state equality
Logical Special
! Complement {,} Concatenation
&& And {n{m}} Replication
|| Or ?: Ternary

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 Verilog

Setting Values
assign Statements
I One line descriptions of combinational logic
I Left hand side must be a wire (SystemVerilog allows assign statements
on logic type)
I Right hand side can be any one line verilog expression
I Including (possibly nested) ternary (?:)

Example

module one_bit_adder(
input wire a,b,cin,
output wire sum,cout);
assign sum = a ^ b ^ cin;
assign cout = ((a ^ b) & cin) | a & b;
endmodule
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 Verilog

Setting Values

always Blocks
I Contents of always blocks are executed whenever anything in the
sensitivity list happens
I Two main types in this class. . .
I always_comb
I implied sensitivity lists of every signal inside the block
I Used for combinational logic. Replaced always @*
I always_ff @(posedge clk)
I sensitivity list containing only the positive transition of the clk signal
I Used for sequential logic
I All left hand side signals need to be logic type.

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 Verilog

Always Block Examples

Combinational Block

always_comb
begin
x = a + b;
y = x + 8'h5;
end

Sequential Block

always_ff @(posedge clk)

begin
x <= #1 next_x;
y <= #1 next_y;
end

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 Verilog

Blocking vs. Nonblocking Assignments

Blocking Assignment Nonblocking Assignment

I Combinational Blocks I Sequential Blocks
I Each assignment is I All assignments occur
processed in order, earlier vs. “simultaneously,” delays are
assignments block later ones necessary for accurate
I Uses the = operator simulation
I Uses the <= operator

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 Verilog

Blocking vs. Nonblocking Assignment by Example

Blocking Example
always_comb
begin
x = new_val1;
y = new_val2;
sum = x + y;
end
I Behave exactly as expected new_val1
I Standard combinational logic x
new_val2
y
sum

Figure: Timing diagram for the

above example.
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 Verilog

Blocking vs. Nonblocking Assignment by Example

Nonblocking Example
always_ff @(posedge clock)
begin
x <= #1 new_val1;
y <= #1 new_val2;
sum <= #1 x + y;
end
I What changes between clock
these two examples?
new_val1
I Nonblocking means that x
sum lags a cycle behind
new_val2
the other two signals
y
sum

Figure: Timing diagram for the above example.

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 Verilog

Blocking vs. Nonblocking Assignment by Example

Bad Example
always_ff @(posedge clock)
begin
x <= #1 y;
z = x;
end
I z is updated after x clock
I z updates on negedge reset
clock x
y
z

Figure: Timing diagram for the

above example.

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 Verilog

Synthesis Tips

Latches
I What is a latch?

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 Verilog

Synthesis Tips

Latches
I What is a latch?
I Memory device without a clock
I Generated by a synthesis tool when a net needs to hold state without
being clocked (combinational logic)
I Generally bad, unless designed in intentionally
I Unnecessary in this class

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 Verilog

Synthesis Tips

Latches
I Always assign every variable on every path
I This code generates a latch
I Why does this happen?

always_comb
begin
if (cond)
next_x = y;
end

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 Verilog

Synthesis Tips

Possible Solutions to Latches

always_comb
begin
next_x = x;
if (cond)
next_x = y;
end

always_comb
begin
if (cond)
next_x = y;
else
next_x = x;
end

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 Verilog

Modules

Intro to Modules
I Basic organizational unit in Verilog
I Can be reused

Module Example

module my_simple_mux(
input wire select_in, a_in, b_in; //inputs listed
output wire muxed_out); //outputs listed
assign muxed_out = select_in ? b_in : a_in;
endmodule

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 Verilog

Modules

Writing Modules
I Inputs and outputs must be listed, including size and type
format: <dir> <type> <[WIDTH-1:0]> <name>;
e.g. output logic [31:0] addr;
I In module declaration line or after it, inside the module

Instantiating Modules
I Two methods of instantiation
1. e.g. my_simple_mux m1(.a_in(a),.b_in(b),
.select_in(s),.muxed_out(m));
2. e.g. my_simple_mux m1(a,b,s,m);
I The former is much safer. . .
I Introspection (in testbenches): module.submodule.signal

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 Verilog

How to Design with Verilog

I Remember – Behavioral Verilog implies no specific hardware design

I But, it has to be synthesizable
I Better be able to build it somehow

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 Verilog

Keys to Synthesizability

Combinational Logic
I Avoid feedback (combinatorial loops)
I Always blocks should
I Be always_comb blocks
I Use the blocking assignment operator =
I All variables assigned on all paths
I Default values
I if(...) paired with an else

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 Verilog

Keys to Synthesizability

Sequential Logic
I Avoid clock- and reset-gating
I Always blocks should
I Be always_ff @(posedge clock) blocks
I Use the nonblocking assignment operator, with a delay <= #1
I No path should set a variable more than once
I Reset all variables used in the block
I //synopsys sync_set_reset “reset”

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 Verilog Flow Control

Flow Control

All Flow Control

I Can only be used inside procedural blocks (always, initial, task,
function)
I Encapsulate multiline assignments with begin...end
I Remember to assign on all paths

Synthesizable Flow Control

I if/else
I case

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 Verilog Flow Control

Flow Control

Unsythesizable Flow Control

I Useful in testbenches
I For example. . .
I for
I while
I repeat
I forever

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 Verilog Flow Control

Flow Control by Example

Synthesizable Flow Control Example

always_comb
begin
if (muxy == 1'b0)
y = a;
else
y = b;
end

The Ternary Alternative

wire y;
assign y = muxy ? b : a;

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 Verilog Flow Control

Flow Control by Example

Casez Example

always_comb
begin
casez(alu_op)
3'b000: r = a + b;
3'b001: r = a - b;
3'b010: r = a * b;
...
3'b1??: r = a ^ b;
endcase
end

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 Testing

Testing

What is a test bench?

I Provides inputs to one or more modules
I Checks that corresponding output makes sense
I Basic building block of Verilog testing

Why do I care?
I Finding bugs in a single module is hard. . .
I But not as hard as finding bugs after combining many modules
I Better test benches tend to result in higher project scores

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 Testing

Intro to Test Benches

Features of the Test Bench

I Unsynthesized
I Remember unsynthesizable constructs? This is where they’re used.
I In particular, unsynthesizable flow control is useful in testbenches (e.g.
for, while)
I Programmatic
I Many programmatic, rather than hardware design, features are available
e.g. functions, tasks, classes (in SystemVerilog)

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 Testing

Anatomy of a Test Bench

A good test bench should, in order. . .

1. Declare inputs and outputs for the module(s) being tested
2. Instantiate the module (possibly under the name DUT for Device Under
Test)
3. Setup a clock driver (if necessary)
4. Setup a correctness checking function (if necessary/possible)
5. Inside an initial block. . .
5.1 Assign default values to all inputs, including asserting any available
reset signal
5.2 $monitor or $display important signals
5.3 Describe changes in input, using good testing practice

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 Testing

Unsythesizable Procedural Blocks

initial Blocks
I Procedural blocks, just like always
I Contents are simulated once at the beginning of a simulation
I Used to set values inside a test bench
I Should only be used in test benches

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 Testing

Unsythesizable Procedural Blocks

initial Block Example

initial
begin
@(negedge clock);
reset = 1'b1;
in0 = 1'b0;
in1 = 1'b1;
@(negedge clock);
reset = 1'b0;
@(negedge clock);
in0 = 1'b1;
...
end

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 Testing

Tasks and Functions

task function
I Reuse commonly repeated I Reuse commonly repeated
code code
I Can have delays (e.g. #5) I No delays, no timing
I Can have timing information I Can return values, unlike a
(e.g. @(negedge clock)) task
I Might be synthesizable I Basically combinational logic
(difficult, not recommended)

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 Testing

Tasks and Functions by Example

task Example
task exit_on_error;
input [63:0] A, B, SUM;
input C_IN, C_OUT;
begin
$display("@@@ Incorrect at time %4.0f", $time);
$display("@@@ Time:%4.0f clock:%b A:%h B:%h CIN:%b SUM:%h"
"COUT:%b", $time, clock, A, B, C_IN, SUM, C_OUT);
$display("@@@ expected sum=%b", (A+B+C_IN) );
$finish;
end
endtask

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 Testing

Tasks and Functions by Example

function Example
function check_addition;
input wire [31:0] a, b;
begin
check_addition = a + b;
end
endfunction

assign c = check_addition(a,b);

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 Testing

Intro to System Tasks and Functions

I Just like regular tasks and functions

I But they introspect the simulation
I Mostly these are used to print information
I Behave just like printf from C

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 Testing

List of System Tasks and Functions

$monitor Used in test benches. Prints every time an argument

changes. Very bad for large projects.
e.g. $monitor("format",signal,...)
$display Can be used in either test benches or design, but not after
synthesis. Prints once. Not the best debugging technique
for significant projects.
e.g. $display("format",signal,...)
$strobe Like display, but prints at the end of the current simulation
time unit.
e.g. $strobe("format",signal,...)
$time The current simulation time as a 64 bit integer.
$reset Resets the simulation to the beginning.
$finish Exit the simulator, return to terminal.
More available at ASIC World.
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 Testing

Test Benches by Example

Test Bench Setup

module testbench;
logic clock, reset, taken, transition, prediction;

two_bit_predictor(
.clock(clock),
.reset(reset),
.taken(taken),
.transition(transition),
.prediction(prediction));

always
begin
clock = #5 ~clock;
end

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 Testing

Test Benches by Example

Test Bench Test Cases
initial
begin
$monitor("Time:%4.0f clock:%b reset:%b taken:%b trans:%b"
"pred:%b", $time, clock, reset, taken,
transition, prediction);
clock = 1'b1;
reset = 1'b1;
taken = 1'b1;
transition = 1'b1;
@(negedge clock);
@(negedge clock);
reset = 1'b0;
@(negedge clock);
taken = 1'b1;
@(negedge clock);
...
$finish;
end
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 Testing

Test Bench Tips

Remember to. . .
I Initialize all module inputs
I Then assert reset
I Use @(negedge clock) when changing inputs to avoid race
conditions

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 Project 1

Project 1 Administrivia

Grading
I Objective Grading
I 70 points possible
I Test cases automatically run
I Subjective Grading
I 30 points possible
I Verilog style graded by hand

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 Project 1

Project 1 Administrivia

Submission Script
I Run from the directory above the directory your project is in. . .
I For example:
$ pwd
/afs/umich.edu/user/j/i/jieltan/
$ cd classes/eecs470/projects
$ ls
project1 project2 project3
$ /afs/umich.edu/user/j/i/jieltan/Public/470submit -p 1
project1

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 Project 1

Project 1 Hints

Hierarchical Design
I Used to expand modules
I Build a 64-bit adder out of 1-bit adders
I Build a 4-bit and out of 2-bit ands
I No additional logic needed

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 Project 1

Project 1 Hints

Hierarchical Design
I Used to expand modules
I Build a 64-bit adder out of 1-bit adders
I Build a 4-bit and out of 2-bit ands
I No additional logic needed
I Project 1 Part C and D
I Build a 4-bit priority selector out of 2-bit priority selectors
I Build a 4-bit rotating priority selector out of 2-bit priority selectors

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 Project 1

Project 1 Hints

module and2(
input [1:0] a,
output logic x
);
assign x=a[0] & a[1];
endmodule

module and4(
input [3:0] in,
output logic out
);
logic [1:0] tmp;
and2 left(.a(in[1:0]),.x(tmp[0]));
and2 right(.a(in[3:2]),.x(tmp[1]));
and2 top(.a(tmp),.x(out));
endmodule

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 Project 1

Project 1 Hints
out

and2
a[1] a[0]

tmp[1] tmp[0]
x x

and2 and2
a[1] a[0] a[1] a[0]
and4

in[3] in[2] in[1] in[0]

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 Project 1

Project 1 Questions

I Any questions about Project 1?

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 Lab Assignment

Lab Assignment

I Follow the tutorial, this is one of the most important documents in

this class. . .
I Assignment on the course website.
I Submission: Place yourself on the help queue and we will check you off

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