2/17/2021 GATE 2018 ECE (Electronics and Communication) Digital circuits questions - VLSI- Physical Design For Freshers

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GATE 2018 ECE (Electronics and Communication) Digital circuits
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 Physical_design  5:47 AM  Digital Circuits , GATE Questions  0 Comments

Digital Circuits Questions and Answers: GATE 2018 ECE (Electronics and
Communication)
Nonius Magnetic
Ques1: The logic function f X Y (,) realized by the given circuit is Rings
A)NOR
B)AND Compatible with
existing Nonius sensors
C)NAND and readheads, High
D)XOR quality magnetisation.

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2/17/2021 GATE 2018 ECE (Electronics and Communication) Digital circuits questions - VLSI- Physical Design For Freshers
Floorplanning
Questions Related to Floorplanning,Physical
Only Cells, & Inputs of Physical Design
Physical Only Cells
Questions Related To Physical Only Cells
Powerplanning
UPF & Special Cells Used For Power Planning
Interview Questions
Sources of Power dissipation in CMOS
Interview Questions Related To Power Planning
Placement
Interview Questions Related To Placement
Clock Tree Synthesis (Part-I)
Skew, Latency, Uncertainty & Jitter
Crosstalk & Useful Skew
Clock Bu er, Normal Bu er & Minumum Pulse
Width Violation
Clock Tree Routing Algorithm
STA,DTA,Timing Arc, Unateness
Transmission Gate,D Latch, D Flip Flop ,Setup &
Hold Time
Global Setup &Hold Time
GATE 2020 ECE Digital circuits questions
GATE 2019 ECE Digital circuits questions
GATE 2018 ECE Digital circuits questions
Setup & Hold Checks Defined in Library
Time Borrowing concept
Time stealing concept
From the fig, we can see that (P1 & P3) pairs are connected into series and similarly (P2 & Non Linear Delay Model (NLDM) in VLSI
Wire Load Model (WLM)
P4) are also connected into the series. So if one of the transistors in series is OFF then there Standard Parasitic Extraction Format (SPEF)
OCV & CRPR
is no connection from the supply. If both of the transistor those are connected into series PVT (Process Voltage Temperature)
are in ON condition then only output is directly connected to the supply (VDD).

From the fig we can see that (N1 & N3) pairs are connected into series and similarly (N2 &
N4) are also connected into the series. So if one of the transistors in series is OFF then there
is no connection from the ground (GND). If both of transistor those are connected into
series are in ON condition then only output is directly connected to the ground (GND).

On this basis make a truth table for this circuit:

TRANSLATE

Select Language ▼

So from the truth table, we see that this is XOR gate truth table, for same input it gives 0
output and for different input it gives 1 output.
Option (D) is the correct answer.

Ques2: A function F (A, B, C) defined by three Boolean variables A, B and C when expressed FOLLOWERS
as sum of products is given by
Followers (105)
F = A' B’ C’+ A’ B C’+ A ⋅ B’⋅ C’ Next

where, A’, B’, and C’ are the complements of the respective variables. The product of sums
(POS) form of the function F is
A) F = (A + B + C) ⋅ (A + B’+ C) ⋅ (A’+ B + C)
B) F = (A’+ B’ + C’) ⋅ (A’+ B + C’) ⋅ (A + B’ + C’)
C) F = (A + B + C’) ⋅ (A + B’+ C’) ⋅ (A’+ B + C’) ⋅ (A’+ B’ + C) ⋅ (A’+ B’ + C’)
D) F = (A’+ B’ + C) ⋅ (A’+ B + C) ⋅ (A + B’ + C) ⋅ (A + B + C’) ⋅ (A + B + C)

Sol: Given expression is SOP form i.e. min terms

F = A' B’ C’+ A’ B C’+ A ⋅ B’⋅ C’
A' B’ C’-> 000 = 0
A’ B C’ -> 010 = 2
A B’ C’ -> 100 = 4

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2/17/2021 GATE 2018 ECE (Electronics and Communication) Digital circuits questions - VLSI- Physical Design For Freshers

We can also write SOP (min terms) as F = ∑m (0, 2, 4)

And F=∑m (0, 2, 4) = ∏M (1, 3, 5, 6, 7) (max term)
F = ∏M (1, 3, 5, 6, 7) (max term)

Convert in to POS form

1 -> 001 -> A + B + C’
3 -> 011 -> A +B’ + C’
5 -> 101 -> A’ + B + C’
6 -> 110 -> A’ + B’ + C
7 -> 111 -> A’ +B’ + C’

So F = (A + B + C’). (A +B’ + C’). (A’ + B + C’). (A’ + B’ + C). (A’ +B’ + C’)

Option (C) is the correct answer.

Ques3: A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to
GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5
seconds and the RED is turned on for 75 seconds. This traffic light has to be implemented
using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period.
The minimum number of flip-flops required to implement this FSM is _______.

Sol: GREEN is turned on for = 70 sec

YELLOW is turned on for = 5 sec
RED is turned on for = 75 sec
So total time for lights turns on is = 70 + 5 + 75 = 150 sec
The given clock period is = 5 sec

Number of clock cycles (states) in one complete period (N) = 150/3 = 30

The minimum number of flip-flops is depends upon the number of states. So here we got 30
states.

NOTE: If N = total number of states and n = number of flip flop then the relation between N
and ‘n’ is N <=2n
30 < = 2n
n>= 4.90
So the minimum number of required flip flop is 5.

Ques4: A four-variable Boolean function is realized using 4:1 multiplexers as shown in the
figure. The minimized expression for F (U V W X) is
A) (U V+ U’ V’) W’
B) (U V +U’ V’) (W’ X’ + W’ X)
C) (U V’ + U’ V) W’
D) (U V’ +U’ V) (W’ X’ + W’ X)

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2/17/2021 GATE 2018 ECE (Electronics and Communication) Digital circuits questions - VLSI- Physical Design For Freshers

Sol: From the first MUX, we consider

, the output P is

P = S1’ S0’ I0 + S1’ S0 I1 + S1 S0’ I2 + S1 S0 I3

P = U’ V’.0 + U’ V .1 + U V’ .1 +U V .0
P = U’ V + U V’----------------(i)

From the second MUX, the output F is

F = W’ X’ P + W’ X P
= P W’ (X + X’)
= P W’ :: (X+ X’)=1

Put the value P from equation (i) then,

F = (U’ V + U V’) W’

Option (C) is the correct answer.

Ques5: A 2 x 2 ROM array is built with the help of diodes as shown in the circuit below.
Here W0 and W1 are signals that select the word lines and B0 and B1 are signals that are the
output of the sense amps based on the stored data corresponding to the bit lines during the
read operation.

During the read operation, the selected word line goes high and the other word line is in a
high impedance state. As per the implementation shown in the circuit diagram above, what
are the bits corresponding to Dij (where i = 0 or 1 and j = 0 or 1) stored in the ROM?

Sol:

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2/17/2021 GATE 2018 ECE (Electronics and Communication) Digital circuits questions - VLSI- Physical Design For Freshers

From the figure, NMOS N1 and N2 gates are connected to the power supply VDD (logic
high). N1 and N2 are in ON condition and connected to the ground. Now at the point, x and
y will be at zero (0) because of transistors.

If word select line W0 is at logic 1 and point x is at logic 0 so the diode D1 will be in the
forward biased and now the point x will be at logic 1 and this logic 1 is sense by B0 sense
amplifier so now the Bit line B0 is also at logic 1.
W0 = B0 =1

Similarly, if word select line W1 is at logic 1 and point y is at logic 0 so the diode D2 will be
in the forward biased and now the point y will be at logic 1 and this logic 1 is sensed by B1
sense amplifier so now the Bit line B1 is also at logic 1.
W1= B1 = 0

Option (C) is the correct answer.

Ques 6: The logic gates shown in the digital circuit below use strong pull-down nMOS
transistors for the LOW logic level at the outputs. When the pull-downs are off, high-value
resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some
nodes are intentionally shorted to implement “wired logic”. Such shorted nodes will be
HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.

The number of distinct values of X3X2X1X0 (out of the 16 possible values) that give Y = 1 is.

Sol: At the output, there is OR gate and OR gate output is 1 if any one of the inputs is 1.

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2/17/2021 GATE 2018 ECE (Electronics and Communication) Digital circuits questions - VLSI- Physical Design For Freshers

Truth table of OR gate is

From the fig. there are 4 inputs so 16 possible states will come into the picture and out of 16
how many states give the output 1 at the OR gate.

There is two wired logic (shorted nodes) at point A and B and it acts as AND gate. So only
X3 we will keep 1 always to get the OR gate output is 1. If we take X3 is zero then we will not
get the OR gate output Y equal to 1.

Let’s take X0 = 0 from the figure we see that OR gate has one input is 0 and other is X3 i.e. 1
so we got 1 output. X1, X2, and X3 we consider any value it does not affect the OR gate
output.

Let’s take X0 = 1 from the figure we see that OR gate has one input is 0 and other is X3 i.e. 1
so we got 1 output. X1, X2, and X3 we consider any value it does not affect the OR gate
output.

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2/17/2021 GATE 2018 ECE (Electronics and Communication) Digital circuits questions - VLSI- Physical Design For Freshers

If X3 is zero (0) then the output will be zero irrespective of the values of X1, X2,
and X3.

If X3 is 1 then the output will be 1 irrespective of the values of X1, X2, and X3.

So out of 16 possible values, the number of distinct values of X3X2X1X0 that gives Y =1 is 8.

Ques 7: In the circuit shown below, a positive edge-triggered D Flip-Flop is used for
sampling input data Din using clock CK. The XOR gate outputs 3.3 volts for logic HIGH and
0 volts for logic LOW levels. The data bit and clock periods are equal and the value of
ΔT/TCK = 0.15, where the parameters ΔT and TCK are shown in the figure. Assume that the
Flip-Flop and the XOR gate are ideal.

If the probability of input data bit (Din) transition in each clock period is 0.3, the average
value (in volts, accurate to two decimal places) of the voltage at node X, is _______.

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