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Constructing Effective UVM Testbench for DRAM Memory Controllers

Conference Paper · November 2018

DOI: 10.1109/NGCAS.2018.8572135

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Constructing Effective UVM testbench for

DRAM Memory Controllers
Khaled Salah1, Hassan Mostafa2
1 2
Mentor, a Siemens Business, Egypt. Electronics and Communications Engineering Department, Cairo University, Giza
12613, Egypt.
[email protected]
[email protected]

TABLE II presents comparison between the most

Abstract—In this paper, a general verification common architecture in terms of commands. TABLE III
architecture for DRAM memory controllers is compares between different memories controllers.
proposed. The proposed verification architecture is Enhancing the verification environment is a challenge
based on universal verification methodology (UVM) for DRAM memory controllers as they are very time
which makes use of the common features between consuming parts.
different DRAM memory controllers to generate In this paper, generic UVM-based verification
common and configurable scoreboard, sequences, architecture is proposed to verify the DRAM memory
stimulus, different UVM components, payload and controllers. The proposed architecture exploits the
test-cases. The proposed verification architecture uses common features to generate common UVM components
minimum number of macros, methods and classes. and tests. The rest of paper is organized as follows. In
Section II, The proposed architecture is introduced. In
The proposed verification architecture provides high
Section III, results are analyzed. Conclusions are given in
reusability for UVM tests.
section IV.

TABLE I
MEMORY CONTROLLERS FEATURES
Index Terms — UVM, DRAM, Verification, Features Explanation
Architecture. Topology Point to point, or multi-master/ multi-slave.
Physical interface Pins.
Initialization process Start operation and negotiation.
I. INTRODUCTION Command Sets • Read
• Write
• multiple read
As verification is now considered as the bottleneck of • multiple write
any complex VLSI design. So, improving the verification • Activate
efficiency is a must. Due to the exponential growth in • Refresh
design complexity, verification is facing a new level of Responses Types and size.
challenges. Mainly, there are two levels of verification, Internal registers Information about the memory controllers.
IP-level verification and SoC-level verification. For IP- Data rate DDR/ SDR.
Timing The time between different commands,
level verification, we need to verify the functionality. For responses, and data.
SoC-level verification, we need to verify the connectivity. Reliability CRC/ECC.
The verification cycle is mainly driven by time to market. Performance In terms of clock frequency.
A host controller is interested in correct and successful
communication with the device, high data through-put TABLE II
and in saving power. COMPARISON BETWEEN THE MOST COMMON
ARCHITECTURE IN TERMS OF COMMANDS
Memory controllers are considered a vital component in
3D 2D
many VLSI designs. They provide an efficient interface Features HMC WideIO LPDDRx DDRx
between the memory cores and the host in terms of Read   
maximizing transfer speed, processing data, ensuring data
integrity. Memory controllers can be flash-based or Write    
DRAM-based. DRAM memory controllers’ examples are Command queuing    
DDRx, LPDDRx, HMC, HMB, and WIDEIO [1]-[6]. The Retry 
architecture of these different controllers has many
Power management    
common features. TABLE I shows the main memory
Sleep 
controllers features.
Power down    
Deep power down 
self-refresh    

978-1-5386-7681-3/18/$31.00 ©2018 IEEE 178

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TABLE III
COMPARISON BETWEEN DIFFERENT DRAM MEMORY CONTROLLERS
HMC WIDEIO LPDDRx DDRx
Number of banks 8/16 Banks 4 Banks 16 banks 8 banks
Technology 3D 3D 2D 2D
Memory Cells DRAM DRAM DRAM DRAM
# Memory partitions 1 partition 1 partition 1 partition 1 partition
Modes of operations • Initialization • Idle • Idle • Idle
• Sleep • Active • Active • Active
• Active • Power Down • Power • Power
• Power • Deep Power
Down Down
Data Integrity CRC ECC CRC CRC
Number of Registers 15 8 64 64
Size of registers (bits) 32 19 8 8
Number Of Pins 29 48 12 12

Transmission Type Synchronous Synchronous Synchronous Synchronous

Number of commands 64 32 20 20
Command length (bits) 48 4 6 6
# Responses 5 1 0 0
Command/Data Bus share same No No No No
bus

Interface pins • CLK • CLK • CLK • CLK

• Reset • Command Bus • Command • Command
• CMD Bus • Address Bus Bus Bus
• Data Bus • Data Bus • Address Bus • Address Bus
• Data Mask • Data Bus • Data Bus
• Reset • Reset • Reset
Interface Type Parallel Parallel Parallel Parallel
Booting Optional - - -
Clock(MHz) 200 200 250 250
Speed (MB/s) 200 200 100 100
Data Rate SDR/DDR SDR DDR DDR
# Timing Modes 1 1 Many Many
Topology Point to point Point to point Point to point Point to point

The sequencer generates the data and the driver sends it

II. GENERIC UVM-BASED VERIFICATION to the DUT. The scoreboard compares the received data
ARCHITECTURE or response against the expected one. The monitor
samples the data and responses.
Mainly, there are two categories of memories: hard The proposed testbench overcomes many verification
disk driver (HDD) and solid-state driver (SSD) which challenges such as covering different levels of
uses volatile memory and nonvolatile memory to store communication, covering different parameters, generating
data. efficient random stimulus generation, coping with fast
The proposed verification architecture makes use of the protocols evolution and revisions. Moreover, it provides a
common features between different DRAM memory scoreboard that not only ensures transaction-level data
controllers to generate common and configurable correctness, but also automates common verification
scoreboard, sequences, stimulus, different UVM tasks, such as transaction order check [25]. Also, the
components, payload and test-cases. scoreboard is generic enough to allow in order checking
The proposed generic UVM-based verification and out of order checking. Moreover, it supports UVM
architecture for DRAM-based memory controllers is callback. UVM callbacks are used to add the new
shown in Fig. 1. A generic scenario is shown in Fig. 2. capabilities, without creating a huge OOP hierarchy.
UVM verification environment is composed of
different components such as stimulus, scoreboard,
driver, coverage, sequencer and monitor [7]-[23]. All
these components can be highly reused [24].

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III. RESULTS AND DISCUSSIONS

HMC, HBM, WIDE-IO, LPDDRx, and DDRx. Using the

proposed generic verification architecture, a fast coverage
closure is obtained as with each new protocol, we use the
previous verification and add new scenarios that will be
useful for the next protocol and so on.
For HMC, basic sequence generation is compared
against the proposed methodology. Results show that the
proposed verification exhibits a reduced simulation time
as shown in Fig. 3.

Conventional Seq Generic Seq

Fig. 3 The conventional tests generation method versus and the

proposed method.

IV. CONCLUSIONS

In this paper, generalized UVM-based verification

architecture for DRAM memory controllers is proposed.
Fig. 1 The generic UVM architecture for DRAM memory controllers.
The proposed architecture uses the most common features
between different DRAM memories to generate different
configurable test scenarios. The final results show that the
READ WRITE proposed architecture speedup simulation time 8x
REFRESH
Sequence Sequence ACTIVATE compared to conventional test generation methods.
Sequence
Sequence

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