21st International Conference on VLSI Design

A Modeling of a Dynamically Reconfigurable Processor using SystemC

Junji Kitamichi† Koji Ueda‡ Kenichi Kuroda†

† ‡
School of Computer Science and Engineering, NEC Electronics Corporation
The University of Aizu, 1753, Shimonumabe,
Tsuruga, Ikki-machi, Aizu-Wakamatsu, Nakahara-Ku, Kawasaki,
Fukushima 965-8580, JAPAN Kanagawa 211-8668, JAPAN
{kitamiti,kuroda}@u-aizu.ac.jp

Abstract and SystemVerilog[7], are proposed.

We have been developing a Dynamic Module Library
Recently, Dynamically Reconfigurable Processors (DML) [8] for the modeling of general DRSs from the
(DRPs) have been proposed. In this paper, we describe system level to the RT level, which provides the dynamic
a model of a DRP using a Dynamic Module Library generation and elimination of a module and the dynamic
(DML), which we have developed for the modeling of connection and dispatch of the port and channel. In
general-purpose dynamically reconfigurable systems. The SystemC2.1.v1, a dynamic process is introduced, which
DML is an extended SystemC library and enables the enables the dynamic process generation and elimination.
modeling of the dynamic generation and elimination of However, using this process, the modules, ports, and chan-
modules, ports and channels and the dynamic connection nels cannot be generated and eliminated dynamically and
and dispatch between port and channel. Using the DML, cannot be connected and dispatched dynamically after the
we can model the DRP naturally. The architecture of the simulation has started. Using the DML, the dynamic gener-
proposed DRP is based on an MIPS-type architecture and ation and elimination of a module and the dynamic connec-
supports the instructions, which are for the dynamically tion and dispatch of the port and channel are implemented
reconfigurable operational units and for their generation and modeled naturally.
and elimination. We describe the proposed DRP model and In this paper, we describe a DRP model at the RT level
its evaluation results. using the DML and its evaluation results. The proposed
processor is based on an MIPS-type processor which sup-
1 Introduction ports the dynamically reconfigurable operational units that
are dynamically generated and eliminated as well as the in-
structions for dynamic reconfiguration and their operations.
Recently, many types of Dynamically Reconfigurable
Processors (DRPs) based on FPGA technology have been
proposed[1] [2] [3]. DRPs are implemented on a unique 2 Background
Dynamically Reconfigurable Architecture (DRA), and a 2.1 System Modeling using SystemC
specialized design environment is provided for the DRP. In
the case of the system design for a new application-specific SystemC[5] is a system description language. SystemC
Dynamically Reconfigurable System (DRS), the existing has the ability for system modeling using a class library of
design methods and CAD systems can not deal with this C++. System models from the abstraction level to the con-
system design. In the case of a new DRP architecture de- crete RT level can be described in SystemC, and they can
sign, a design environment that is independent of the spe- be simulated at the different levels.
cific DRA will be needed at the system level, which is the The behavior of the system is described in the modules.
beginning of system design. In the module, the definitions of input and output ports
The system level design[4] is more abstract that the con- and the definitions and initializations of processes, such as
ventional Register Transfer (RT) level design, and system the behavior of the module, the generations of instances of
specification languages, such as SystemC [5], SpecC[6], sub-modules, the connection with ports in the sub-modules

1063-9667/08 $25.00 © 2008 IEEE 91

DOI 10.1109/VLSI.2008.13
to channels, and the behavior of processes are described.
The modules are defined by inheriting the sc module class,
a class of SystemC. The channels are the communication
paths between modules, and the ports are connected to
channels and the port of modules. For example, sc in and
sc fifo are types of an input port and a FIFO channel respec-
tively.
In the older version of SystemC than 2. 1.v1, processes
are initialized only at the start of a simulation and are never
generated or eliminated during a simulation. The idea of
a dynamic process is added in SystemC 2. 1.v1. With the
dynamic process, it is possible to activate processes after
the simulation has started. However, each port and chan-
nel is defined as static and is never generated or eliminated
dynamically during the simulation in SystemC 2. 1.v1.

2.2 Dynamically Reconfigurable Architec-

tures

Recently, Dynamically Reconfigurable Architectures Figure 1. Outline of two types of DRAs

(DRAs)[9] have been proposed. A DRA is based on FPGA,
whose configuration memory is SRAM, and can be recon- tion has started, even if SystemC 2.1.v1 is used. We have
figured while the system is operating. There are many types proposed a Dynamic Module Library(DML) [8] including
of DRAs[1][2][10][11], such as the multi-context type / par- dynamic modules, dynamic ports, and dynamic channels to
tially reconfigurable type and the fine-grain / course-grain solve these problems.
types. The reconfigurable units of fine-grain architectures If the DML is used in modeling, the dynamic module
are constructed by Look-Up Tables (LUTs) that use mem- class DynamicModule, which collects functions, such as
ory technology. LUTs can be constructed as any logic func- newmod(), new and delmod(), for the dynamic module, port
tion, so every region can be efficiently used. On the other and channel is used rather than the sc module class. In a
hand, ALUs construct reconfigurable units of coarse-grain dynamic module, the usual ports, such as sc port and chan-
architectures; therefore, they can compute numerical oper- nels, such as sc fifo cannot be used for their definition. In
ations faster than fine-grain architectures. However, some addition, the sc port and sc fifo have a binding method to
reconfigurable units cannot be utilized, and the usage of the connect with each other, but they do not have any method to
area is worse. dispatch. The dynamic port, such as dc port and dynamic
Multi-context DRA[1] and partially DRA[10] [11] make channel, such as dc fifo are used in a dynamic module and
up one classification of DRAs. Multi-context DRAs have have methods to connect and dispatch.
some configuration data memories, and the circuits are re-
The DML has a channel pool, which is a set of static
configured by switching the configuration data. The switch-
channels, and manages the connection and dispatch of the
ing of the configuration data takes place at once. The con-
channel and port in the channel pool. The dynamic ports are
tents of unused configuration memories can be rewritten.
implemented and managed in the same way as the dynamic
In the partially DRA, the reconfiguration of circuits corre-
channels.
sponds to the rewriting of the configuration data in some
areas. The dynamic module, ports and channel are imple-
mented by the specific hardware resources on the adopted
DRA. In the case of Multi-context DRA, one or more dy-
2.3 Dynamic Module Library
namic modules may be mapped into the context data, and
We describe a modeling method of the systems that in- dynamic channel may be mapped into the store operation
cludes the dynamic generation and elimination of modules into the memory outside DRA and the reload operation from
and interface at the system level. In the DRS, modules and the outside memory.
an interface are generated or eliminated while the system If the dynamic modules were used in the design, the sim-
is running. In order to express these behaviors naturally at ulation time could be increased because of the overhead of
the system level, modules, ports and channels have to be the operations of the DML. Therefore, several acceleration
generated or eliminated dynamically. However, their gener- methods[8] are built in the DML.
ation and elimination cannot be performed after the simula- Some modeling methods for DRSs using SystemC have

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been proposed. The method proposed in [12] has some con- and forwards the result to the ID stage or the EX stage.
straints on the modeling, such that all modules must be on The processor has an integer ALU in the EX stage as the
same level of hierarchy and instantiated in th same compo- static operational unit, and executes the Load/Store instruc-
nent. The target modeling class in [13] and [14] is more tions, Addition/Subtraction/logical instructions, and Multi-
limited type of DRAs than our proposed method. plication/Division instructions at 5, 4 and about 35 clocks.
The instructions on the dynamic reconfiguration are the
3 Proposed Processor Architecture Dynamically Generation (DG) instructions of the DROU
and the OPerational (OP) instructions using the DROU. The
DROUs are generated in the EFU, execute the operation for
We describe a proposed DRP architecture. The pro-
the data received from the ID stage, and send the results to
posed processor has some operational units, which are
the WB stage.
generated and eliminated dynamically. It consists of a
A PRISC[16] is developed with the DRP closely con-
processor core and an Extended Functional Unit(EFU),
nected with the RF, as in our proposed processor.
which contains some Dynamically Reconfigurable Opera-
tional Units(DROUs). The overview of the proposed pro- 3.2 EFU and its Interface to the Processor
cessor is shown in Figure 2. In this paper, we deal with the Core
modeling independently of a specific DRA. In the model-
ing, we use SystemC and the DML. The EFU has two input and one output ports and con-
tains several DROUs. The EFU contains the values of the
Configuration Address (CA) and Block Address (BA) in the
table in order to manage the status of the reconfiguration.
The DG and OP instructions are also 32-bit width. The
DG instructions contain a 6-bit CA field and a 3-bit BA
field. The value of the CA field denotes the type of DROUs,
and the value of the BA field denotes the location of the
dynamic reconfiguration blocks in the EFU.
We can describe more abstract specification of the con-
struction of instructions and the type of operations using the
parameters and abstract data types. In the proposed model,
for the simplicity, we adopted the fixed construction of in-
structions and the fixed types of operations.
We assume that the number of clocks for the generation,
elimination of the dynamic reconfiguration blocks and the
execution of the operation is defined according to the types
of DROUs and can be given as the parameter. The ID stage
Figure 2. Block Diagram of the Proposed Pro- is stalled during the cycles specified by these parameters.
cessor The OP instructions consist of 2 or 3 operands. A 3-bit
address field, which is one of the operands, specifies the lo-
3.1 Processor Core cation of dynamic reconfiguration blocks. The operational
results are sent to the WB stage.
The proposed processor is a 32-bit pipelined processor The execution of these instructions is shown in Figure
that executes the subset of instructions of MIPS[15] in the 3. In the case of the DG instructions, the ID stage sends a
5-stage pipeline. The instruction set consists of about 50 signal Config en, which indicates the start of dynamic re-
instructions, such as integer/logical operations, Load/Store, configuration, and a signal Config adr, which indicates the
and Jump/Branch, and each instruction is executed in order. type of operational units to be dynamically reconfigured,
The processor has an integer- and a floating-point register to the EFU. The EFU spends the time Creating time when
files, and has the data transfer instructions between each the through DROU must be reconfigured dynamically. If
other. the DROU has been configured and this DROU has to be
In the execution of instructions, the proposed proces- eliminated for new unit, the EFU spends the necessary time
sor executes the Instruction Fetch(IF), the Instruction De- Deleting time and then issues the signal Genend to the ID
code(ID), the EXecution(EX), the Memory Access(MA) stage.
and the Write Back(WB) stages in order. In some instruc- In the case of the OP instructions, the ID stage sends
tions, the processor skips some stages. For example, in the source operands FP data or INT data, i.e., floating point
case of integer arithmetic instructions, it skips the MA stage data or integer data, respectively, a signal Drou op, which is

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the type of operations, and and a signal Drou adr, which is the running process outputs the result sign1 tmp, exp5 tmp,
the location of dynamic reconfiguration blocks at the EFU. and man5 tmp through the port fout and waits for the next
The execution time at the DROU is specified as the param- operation . The description of the multiplication process is
eter Running time. The EFU sends the execution results to omitted in Figure 4.
the WB stage and sends a signal Exend to the ID stage. By
receiving the signal Exend, the ID stage restarts the issue of
instructions.

Figure 3. Interface of EFU and Processor

Core

3.3 Modeling of the Proposed DRP

We describe the proposed processor model using the

DML. We describe the IF, ID, MA, and WB stages as the
static modules in the original description style of SystemC
at the RT level. Then we omit these modeling. These are de-
scribed at the RT level, Hereafter, we describe the descrip-
tion about the EX stage, which concerns the dynamically
reconfiguration.
(a)Dynamically Reconfigurable Execution Unit
We modeled 4 types of modules; addition, subtraction, Figure 4. Description of DROU
multiplication, and division for the floating point as the
DROUs. The numbers of clocks for the generation and
elimination of modules and operational clocks are given as (b)Control of Dynamic Reconfiguration in EFU
parameters. We describe the model of dynamic reconfiguration con-
The part of the description of a multiplication DROU is trol in the EFU. Part of the description of the model is shown
shown in Figure 4. The Dynamic Mulf class is defined by in Figure 5. This control unit has 4 states;Idle, Creating,
inheriting the DynamicModule class. This class has the dy- Running, and Deleting. (1)The control unit transits the Idle
namic ports dc in and dc out and user processes, such as state by the Reset signal. (2)It transits the Creating state by
running. the Config en signal from the ID stage. In this state, it stalls
The running process executes the floating point multipli- for the Creating time. (3)Then it sends the Genend signal
cation using the values from the input ports fsin and ftim and to the ID stage and transits the Running state. (4) and(5)In
sends the results through the output port fout. The behavior the Running state, the OP instruction is executed. It stalls
of the running process, which is executed through the inter- for the Running time, sends the executed results to the WB
nal variables fs signTmp,ft signTmp and etc., is described in stage, sends the Exend signal to the ID stage, and waits for
the original description style of SystemC. mulf etime is used the next instruction issue. (6)By the arrival of the Config en
as the parameter, which is the period of the operation, and signal, it transits the Deleting state and stalls for the Delet-

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ing time. (7)To reconfigure a new DROU, it transits the
Creating state.
Creating time and Deleting time are the parameters,
which are defined according to the scale of module, adopted
DRA, and etc.
The transitions in (6) and (7) are the behavior in the case
that the DROU has been configured and this operational unit
should be eliminated for the new unit.

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Figure 6. Description of the Control for

Figure 5. State Diagram in EFU
DROUs

We describe the behavior for the dynamic reconfigura-

tion. This description, which is the part of step (6) reported
above, is shown in Figure 6. The behavior of the recon- The Mux model, which is modeled in the original de-
figuration for a new DROU Dynamic Addf at the unit[i], scription style of SystemC, is prepared as a comparison with
which denotes the specified block in the EFU by the issued the proposed processor using the DML. In the Mux model,
instruction is described. The controller executes following the generation and elimination of a module are described
procedures. using some multiplexers and de-multiplexers.
(1)With the method detach, the channels dina, dinb, The lengths of the codes after eliminating comments,
and dout and the ports fsin, stim, and fout are dispatched, blank lines, and macros for C++ with the preprocessor of
respectively. (2)With the method delmod, the module gcc are shown in Table 1.
is eliminated, and the time to eliminate the module is
passed. (3)With the method new, a new DROU is gener- Table 1. Code lengths of the models
ated. (4)With the method bind, the channels dina, dinb, and S Modules D Modules Control
dout and new generated ports are connected, respectively. Mux model 8248 787 507
(5)The time addf ctimeto to generate the module is passed. Proposed method 8248 751 588
Other channels dina, dinb, and dout are static and con-
nected to the outer ports of the EFU. In Table 1, “S Modules” denote the static modules of
data path and control units and the common description in
4 Experimental Results the proposed model and the Mux model. “D Modules”
denote the descriptions of DROUs in the proposed model
We show the experimental results of the proposed pro- and the descriptions of static DROUs, multiplexers, and de-
cessor model, which is described using SystemC 2.1.v1 and multiplexers in the Mux model. “Control” denotes the de-
the DML. The experimental environment is a Xeon 3.2GHz, scription of the control of the dynamic reconfiguration. In
Mem 4GB, Linux 2.6.9, GCC 3.4.6, and SystemC 2.1.v1 by the proposed model, this includes the descriptions of the
OSCI. generation and elimination of modules, ports, and channels

95
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