24AA256/24LC256: 256K I C Cmos Serial Eeprom
24AA256/24LC256: 256K I C Cmos Serial Eeprom
24AA256/24LC256: 256K I C Cmos Serial Eeprom
24xx256
A1 2 7 WP
24LC256 2.5-5.5V 400 kHz‡ I, E
† 100 A2 3 6 SCL
kHz for VCC < 2.5V.
‡ 100 kHz for E temperature range.
Vss 4 5 SDA
FEATURES
• Low power CMOS technology
SOIC
- Maximum write current 3 mA at 5.5V 1 8
A0 VCC
- Maximum read current 400 µA at 5.5V
24xx256
- Standby current 100 nA typical at 5.5V A1 2 7 WP
• 2-wire serial interface bus, I2C compatible A2 3 6 SCL
• Cascadable for up to eight devices
VSS 4 5 SDA
• Self-timed ERASE/WRITE cycle
• 64-byte page-write mode available
• 5 ms max write-cycle time
• Hardware write protect for entire array BLOCK DIAGRAM
• Schmitt trigger inputs for noise suppression
• 100,000 erase/write cycles guaranteed A0…A2 WP
HV GENERATOR
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC (208 mil) packages
• Temperature ranges: I/O MEMORY
EEPROM
CONTROL CONTROL XDEC
- Industrial (I): -40°C to +85°C LOGIC LOGIC
ARRAY
DESCRIPTION I/O
SCL
YDEC
The Microchip Technology Inc. 24AA256/24LC256
(24xx256*) is a 32K x 8 (256K bit) Serial Electrically SDA
Erasable PROM, capable of operation across a broad
voltage range (1.8V to 5.5V). It has been developed for VCC
advanced, low power applications such as personal SENSE AMP
VSS
communications or data acquisition. This device also R/W CONTROL
has a page-write capability of up to 64 bytes of data.
This device is capable of both random and sequential
reads up to the 256K boundary. Functional address
lines allow up to eight devices on the same bus, for up
to 2 Mbit address space. This device is available in the
standard 8-pin plastic DIP, and 8-pin SOIC (208 mil)
packages.
TF THIGH VHYS TR
SCL
TSU:STA
TLOW THD:DAT TSU:DAT TSU:STO
SDA
THD:STA
IN TSP
TBUF
TAA
SDA
OUT
WP (protected) THD:WP
TSU:WP
(unprotected)
2.4 WP The state of the data line represents valid data when,
after a START condition, the data line is stable for the
This pin can be connected to either VSS, VCC or left duration of the HIGH period of the clock signal.
floating. An internal pull-down on this pin will keep the
The data on the line must be changed during the LOW
device in the unprotected state if left floating. If tied to
period of the clock signal. There is one bit of data per
VSS or left floating, normal memory operation is
clock pulse.
enabled (read/write the entire memory 0000-7FFF).
Each data transfer is initiated with a START condition
If tied to VCC, WRITE operations are inhibited. Read
and terminated with a STOP condition. The number of
operations are not affected.
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0 FUNCTIONAL DESCRIPTION
4.5 Acknowledge
The 24xx256 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data Each receiving device, when addressed, is obliged to
onto the bus is defined as a transmitter, and a device generate an acknowledge signal after the reception of
receiving data as a receiver. The bus must be con- each byte. The master device must generate an extra
trolled by a master device which generates the serial clock pulse which is associated with this acknowledge
clock (SCL), controls the bus access, and generates bit.
the START and STOP conditions while the 24xx256
Note: The 24xx256 does not generate any
works as a slave. Both master and slave can operate as
acknowledge bits if an internal program-
a transmitter or receiver, but the master device deter-
ming cycle is in progress.
mines which mode is activated.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24xx256) will leave the data line HIGH to
enable the master to generate the STOP condition.
SDA
SCL 1 2 3 4 5 6 7 8 9 1 2 3
Transmitter must release the SDA line at this point Receiver must release the SDA line at this point
allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data.
acknowledge the previous eight bits of data.
A A A A A A A A A A A A
1 0 1 0 1 0 R/W X • • • • • •
2 14 13 12 11 10 9 8 7 0
CONTROL CHIP
CODE SELECT
BITS X = Don’t Care Bit
6.1 Byte Write The write control byte, word address, and the first data
byte are transmitted to the 24xx256 in the same way as
Following the start condition from the master, the in a byte write. But instead of generating a stop condi-
control code (four bits), the chip select (three bits), and tion, the master transmits up to 63 additional bytes,
the R/W bit (which is a logic low) are clocked onto the which are temporarily stored in the on-chip page buffer
bus by the master transmitter. This indicates to the and will be written into memory after the master has
addressed slave receiver that the address high byte will transmitted a stop condition. After receipt of each word,
follow after it has generated an acknowledge bit during the six lower address pointer bits are internally incre-
the ninth clock cycle. Therefore the next byte mented by one. If the master should transmit more than
transmitted by the master is the high-order byte of the 64 bytes prior to generating the stop condition, the
word address and will be written into the address address counter will roll over and the previously
pointer of the 24xx256. The next byte is the least signif- received data will be overwritten. As with the byte write
icant address byte. After receiving another acknowl- operation, once the stop condition is received, an inter-
edge signal from the 24xx256, the master device will nal write cycle will begin (Figure 6-2). If an attempt is
transmit the data word to be written into the addressed made to write to the array with the WP pin held high, the
memory location. The 24xx256 acknowledges again device will acknowledge the command but no write
and the master generates a stop condition. This ini- cycle will occur, no data will be written, and the device
tiates the internal write cycle, and, during this time, the will immediately accept a new command subject to
24xx256 will not generate acknowledge signals TBUF.
(Figure 6-1). If an attempt is made to write to the array
with the WP pin held high, the device will acknowledge 6.3 Write Protection
the command but no write cycle will occur, no data will
The WP pin allows the user to write-protect the entire
be written, and the device will immediately accept a
array (0000-7FFF) when the pin is tied to VCC. If tied to
new command. After a byte write command, the inter-
VSS or left floating, the write protection is disabled. The
nal address counter will point to the address location
WP pin is sampled at the STOP bit for every write com-
following the one that was just written.
mand (Figure 1-1) Toggling the WP pin after the STOP
bit will have no effect on the execution of the write cycle.
A A A A
BUS ACTIVITY C C C C
K K K K
X = don’t care bit
S
T S
BUS ACTIVITY A CONTROL ADDRESS ADDRESS T
MASTER R BYTE HIGH BYTE LOW BYTE DATA BYTE 0 DATA BYTE 63 O
T P
SDA LINE A A A X P
S10 1 0 2 1 0 0
A A A A A
BUS ACTIVITY C C C C C
K K K K K
X = don’t care bit
Did Device NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
FIGURE 8-1: CURRENT ADDRESS READ Sequential reads are initiated in the same way as a
random read except that after the 24xx256 transmits
S the first data byte, the master issues an acknowledge
T S
BUS ACTIVITY A CONTROL DATA T as opposed to the stop condition used in a random
MASTER R BYTE BYTE O read. This acknowledge directs the 24xx256 to transmit
T P
the next sequentially addressed 8-bit word (Figure 8-
SDA LINE S 1 0 1 0 A AA 1 P
2 1 0 3). Following the final byte transmitted to the master,
A N the master will NOT generate an acknowledge but will
BUS ACTIVITY C O
K generate a stop condition. To provide sequential reads,
A
C the 24xx256 contains an internal address pointer which
K is incremented by one at the completion of each
operation. This address pointer allows the entire
memory contents to be serially read during one
operation. The internal address pointer will automati-
cally roll over from address 7FFF to address 0000 if the
master acknowledges the byte received from the array
address 7FFF.
SDA LINE P
A A A A N
C C C C O
BUS ACTIVITY K K K K A
C
K
24xx256 — /P
P = Plastic DIP (300 mil Body), 8-lead
Package: SM = Plastic SOIC (208 mil Body, EIAJ standard), 8-lead
Temperature I = -40°C to +85°C
Range: E = -40°C to -125°C
All rights reserved. © 1998, Microchip Technology Incorporated, USA. 1/98 Printed on recycled paper.
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