S $UUD\

ource-circuit configuration is arguably the most

important aspect of PV system design. The electri-
cal and mechanical characteristics of a PV array fol-
low from this fundamental design decision, which
has a bearing on both labor and material costs. In
addition, source-circuit configuration impacts system per-

9ROWDJH
formance, in some cases negatively. Low dc array voltage, for
example, is a common cause of substandard performance
that occurs when open-circuit or operating voltages for an
array persistently fail to meet minimum inverter dc input
voltage thresholds over time. In this situation, the system
design does not take into account the cumulative effects of
a variety of real-world circumstances, including high ac grid
voltage, array degradation, module-to-module voltage toler-
ance and high ambient temperatures. Fortunately, low dc
array voltage is avoidable.
In this article, I detail array design best practices for deter-
mining the maximum number of modules in a source circuit.
My approach is slightly less conservative than the industry
standard and is supported by changes to the National Electri-
cal Code that are introduced in the 2011 cycle. I also present
recommendations for determining the minimum number of
modules per source circuit. While these may be more conser-
vative than current design standards, my opinions are based
on years of experience. They are not influenced by the desire
to sell more or less of any specific product but rather by the
general desire to propagate well-designed PV systems that
perform optimally for decades.

CONSIDER THE SOURCE

Interestingly enough, over the past decade inverter manufac-
turers have been the primary source of education regarding
array design and source-circuit sizing. With all due respect,
these companies usually have expertise in power electronics
and not necessarily in PV array design. However, since the
advent of the first string-sizing program—which was devel-
oped by John Berdner while he was the president of SMA
America—it has become the industry standard for inverter
manufacturers to provide PV array configuration advice.
The main drawback to having inverter manufacturers
dictate array design is that they have a conflict of inter-
est. Manufacturers want their products to be used as often
as possible, and this is facilitated in part by allowing the
maximum number of module configurations. In addition,
although most manufacturers have stern warnings about
exceeding the maximum inverter input voltage, they gener-
ally have little to say about circumstances where there is too
little voltage for the inverter to fully operate the PV array.
This skewed perspective informs both the string-sizing
tools and the training materials that inverter manufacturers
develop. The upshot is that inverters in the field seldom have a
problem with high array voltage but routinely have problems
with low array voltage. While low array voltage will not dam-
age the inverter, it will compromise system performance.

68 S O L A R P R O | October/November 2010
\H&RQVLGHUDWLRQV By Bill Brooks, PE

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C o u r te sy S P G S o l ar an d X an te r ra Par k s & Re so r t s

solarprofessional.com | S O L A R PR O 69
 Array Voltage Considerations

If the inverter cannot operate the array at its MPP, for

example, then power production and energy harvest suf- >T
fer. Problems can also result from open-circuit voltage 
being too low. On hot days, an array’s Voc can pass below  >T
the restart voltage of the inverter. The consequence is that
if the inverter shuts down in the middle of the day due to 

*\YYLU[(
a utility disturbance, it will not restart until the late after-
 >T
noon when the Voc increases. This can reduce the system’s
operating availability by several percentage points annually 
if utility disturbances are common in the summer, such as >T

when utilities switch in distribution capacitors around noon
on hot days to accommodate high air conditioning loads. To  >T
design a PV array that is well-matched to an inverter’s oper-
ating window, system designers need to pay attention to the 
low end of the inverter operating voltage range, as well as to 
the maximum voltage allowed.     

HIGH DC VOLTAGE =VS[HNL=

The maximum dc voltage for an inverter is clearly stated on
the product specification sheet, installation manual or in Figure 1 This representative module I-V curve is based on
tables, such as the one on pages 46–57. While relevant UL published curves for Yingli polycrystalline modules. It
standards and NEC requirements certainly apply, the maxi- assumes a 25°C cell temperature and illustrates how open-
mum voltage is generally set by the input capacitors and the circuit voltage responds to decreasing irradiance.
ratings of the transistors in the inverter, so it is a constant
rather than a variable limit. “Low Design Temperature,” p. 72), it is also overly conserva-
Because it is possible to create overvoltage in an inverter tive for maximum voltage calculations. The record low tem-
by putting too many modules in series, some manufacturers perature is usually too conservative for design calculations
keep the maximum dc input voltage in nonvolatile memory because temperature is only one of two major factors that
for warranty purposes. This allows the manufacturer’s ser- impact array open-circuit voltage. The other major factor is
vice technicians to verify the maximum dc voltage input to irradiance. As an example, look at the set of I-V curves in
any inverter that is returned from the field under warranty. Figure 1, which assumes constant cell temperature and vari-
If the inverter was exposed to overvoltage conditions, then able irradiance, and notice where the I-V curves intersect
the manufacturer may choose not to provide a free replace- the horizontal axis. As irradiance decreases, so does open-
ment inverter. Historically, the most common cause of over- circuit voltage.
voltage is putting two source circuits in series rather than in The NEC, however, uses temperature only to determine
parallel. This is a relatively easy mistake to make, especially maximum system voltage. The criterion for determining the
in a small system with only two source circuits. Failure to maximum PV system voltage, according to Article 690.7(A), is
properly account for low ambient temperatures is another to correct the source circuit open-circuit voltage for the “low-
potential cause of inverter overvoltage. est expected ambient temperature.” Prior to the 2011 cycle,
Some inverter manufacturers have claimed in their train- the NEC did not define the term lowest expected ambient tem-
ings that a 600 Vdc inverter will spontaneously combust if perature. However, the 2011 NEC will define it in an Informa-
the array reaches 601 Vdc. While the inverter warranty may tional Note (formerly known as a Fine Print Note) as follows:
be voided if the array goes above the published maximum “One source for statistically valid, lowest expected ambient
voltage, it is inconceivable that the capacitor or transistor temperature design data for various locations is the Extreme
tolerances are tight enough for the devices to operate well at Annual Mean Minimum Design Dry Bulb Temperature found
600 Vdc and explode at 601 Vdc. If that were true, inverters in the American Society of Heating, Refrigeration, and Air
would also explode at 580 Vdc and they (usually) do not—at Conditioning Engineers’ ASHRAE Handbook—Fundamentals.
least not because of component tolerance. These temperature data can be used to calculate maximum
Low temperature calculation. Most inverter manufacturers voltage using the manufacturer’s temperature coefficients
recommend using the site’s record low temperature to deter- relative to the rating temperature of 25°C.”
mine the maximum number of modules per source circuit. An Informational Note is not a Code requirement and
While the record low temperature is easily attainable (see cannot be interpreted as such. System C O N T I N U E D O N P A G E 7 2

70 S O L A R P R O | October/November 2010
 Array Voltage Considerations

When using string-

designers can use any authoritative source of
sizing programs, likely that peak irradiance (1,000 W/m2)
data for the lowest expected ambient tempera-
ture. However, this Note is intended to help the
the simple rule I will accompany the record low temper-
ature, which is a necessary coincidence
designer and the AHJ focus on the most appro- recommend is to to achieve the calculated maximum
priate data for balanced array design. Since many voltage based on temperature. Third,
system designers may not have ready access eliminate the lowest to achieve in the field the maximum
to the ASHRAE Handbook, the Extreme Annual voltage that is possible on paper, the
Mean Minimum Design Dry Bulb Temperature voltage option—the PV array must be in a condition that
data—hereafter referred to as the ASHRAE low is as good as new. The modules can-
design temperature data—is included in Appen- source circuit with not be soiled, mismatched or degraded;
dix E of the Expedited Permit Process for PV Sys-
tems document that I wrote for the Solar America
the least number of the maximum voltage for each of the
installed modules must equal its pub-
Board for Codes and Standards (Solar ABCs). This
document is readily available on the SolarABCs
modules in series. lished rating. The statistical likelihood
of these conditions occurring at the
website (see Resources) and includes data for same time is low.
more than 650 cities in the US. The ASHRAE data provide statistically derived expected
Some may ask why ASHRAE data is better to use than the low temperatures. Although ASHRAE processes National
record low temperature. One reason is that using the record Weather Service data for use by engineers sizing heating and
low temperature sometimes excludes acceptable source- cooling equipment, the data are also relevant to many other
circuit configurations that may in fact be preferred over fields, including the electrical industry. The ASHRAE low design
shorter source circuits. (This is illustrated in “Case Study: temperature data is derived by averaging the annual low tem-
Example dc Voltage Calculations,” p. 75.) In addition, the extra perature for every year on record. The result is a low tempera-
margin of safety that the record low temperature design pro- ture that has a 50% chance of occurring once a year at a specific
vides is often statistically insignificant when compared to the location. Statistically, 50% of the years that a PV system is in
ASHRAE design. service, the low for the year will be colder than this value—and
System designers must consider three important issues for the other 50%, the low will never reach this value.
when determining an appropriate design temperature. First, This does not mean that there is a 50:50 chance that the
statistically, the record low temperature may never occur again. maximum voltage to the inverter will be exceeded in a given
Second, lower irradiance conditions in winter make it even less year. Remember that peak irradiance must C O N T I N U E D O N P A G E 7 4

/RZ'HVLJQ7HPSHUDWXUH
T o find the record low temperature for any location in the US,
go to Weather.com’s Monthly Climatology web page at the
following URL and specify the desired zip code:
weather.com/weather/climatology/monthly/zipcode.
For design purposes, however, a location’s record low
temperature is very conservative, generally lower than the
minimum expected ambient temperature at peak irradiance.
C o u r tes y S t eve P ro eh l

The Extreme Annual Mean Minimum Design Dry Bulb Tem-

perature data published by ASHRAE generally provide better
low temperature design data in terms of statistical validity.
These data are included in Appendix E of the Expedited Permit
Process for PV Systems, which is available at the website for
the Solar America Board for Codes and Standards.
One note of caution, however: All generalizations have excep- Proceed with caution While the Extreme Annual Mean
tions. For example, a steeply tilted PV array in a high-altitude Minimum Design Dry Bulb Temperature data published
location subjected to snow reflectance may experience extreme by ASHRAE are generally statistically valid for maximum
open-circuit voltage conditions that even record low temperature array Voc calculations, more conservative data may be
design calculations will underestimate. { required for PV arrays in higher-altitude locations.

72 S O L A R P R O | October/November 2010
 Array Voltage Considerations

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LOW DC VOLTAGE
Inverter specification sheets seem
simple enough to use, but some knowl-

T he set of I-V curves in Figure 2 assumes source circuits of 14 Evergreen ES-195

modules, with 20 circuits connected in parallel to a Satcon PVS-50 inverter with
a 305 Vdc minimum MPPT voltage. The ASHRAE low design temperature is 0°C,
edge of how inverters work is required
to interpret them. For example, in con-
trast to an inverter’s published high dc
and the ASHRAE 2% design temperature is 45°C. The latter results in a minimum voltage limit, the low dc voltage limit for
array operating voltage of 289.8 Vdc. (To see the underlying design calculations, most inverters is a variable that changes
refer to “Array to Inverter Matching,” December/January 2009, SolarPro magazine.) in response to the grid voltage. In addi-
As evidenced by the intersection of the dotted line and the I-V curve for the tion, the voltage that an array is capable
ASHRAE 2% design temperature, on the hottest days of summer when the solar of, given specific environmental condi-
resource is greatest, the inverter is unable to operate the array at its maximum tions like irradiance and cell tempera-
power point. Any energy the inverter cannot harvest is money left on the table. This ture, diminishes over time. Designers
is clearly not an acceptable array design. must also account for the effects of mod-
Adapting the design to 15 modules per source circuit gets the minimum array ule voltage tolerance when performing
operating voltage up to 310.5 Vdc, which is higher than the minimum inverter acceptable low dc voltage calculations.
MPPT voltage. However, this does not provide adequate margin to account for the Many of the most egregious PV source-
cumulative effects of high ac grid voltage, array degradation or voltage mismatch. circuit design mistakes are due to a
The best array design is actually 16 modules per source circuit, which results in failure to account for these combined
a minimum array operating voltage of 331.2 Vdc, before any other derates are factors; these designs result in array volt-
applied, and a maximum open-circuit voltage of 571.2 Vdc. { ages that are too low for the inverter.
High ac grid voltage. While a manu-
 facturer might state that the low dc
4PUPU]LY[LY477;]VS[HNL$=KJ
voltage for its inverter is 330 Vdc, this
is usually the lowest acceptable dc

input voltage at the nominal grid volt-
:[H

 =TW
age. For residential systems, the nomi-
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 nal single-phase voltage is 240 Vac;

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for larger systems, the nominal 3-phase

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the ac voltage varies above nominal, the
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minimum dc input voltage rises as well.

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If the ac voltage rises 5%, which is


       possible on hot summer afternoons,
the minimum dc voltage also rises 5%.
=VS[HNL
Therefore, an inverter with a minimum
Figure 2 With only 14 modules in series, the maximum power point for the I-V voltage rating of 330 Vdc has a mini-
curve in red occurs below the inverter’s minimum MPPT voltage. mum voltage of 347 Vdc under those 5%
higher ac voltage conditions. This con-
dition often occurs at precisely the time
accompany this temperature, and the modules must perform when the array dc voltage is at its lowest level due to the high
as if they were new and perfectly matched. Ultimately, engineer- ambient temperatures. While 5% higher ac voltage is unusual,
ing design involves a series of decisions based on the likelihood 2–3% higher voltage is common on hot days, since utilities raise
of an occurrence and the consequences should the worst case voltage to enable them to run more power through their distri-
happen. Good system engineering balances valid concerns to bution circuits to satisfy air conditioning loads.
develop a design that keeps all the equipment operating prop- Array degradation. System designers must be aware that
erly within acceptable limits. Using the record low temperature the minimum voltage from a PV module, and thus an array,
does not eliminate the statistical possibility of exceeding an changes over time. All PV arrays degrade in power, both in
inverter’s maximum input voltage; it simply lowers the possi- voltage and current. At a minimum, designers should factor
bility relative to a higher temperature. I recommend using the in an annual power loss of 0.5%.
ASHRAE low design temperature data unless there is a specific Since no conclusive data exists regarding how much of
need for more conservative design data. this loss is expressed in voltage versus current, a reasonable

74 S O L A R P R O | October/November 2010
 5+H\FR[/D\RXW$03DJH

New from HEYCO … ®

design decision is to equally allocate the loss between cur-

Wire Protection/Installation
rent and voltage. This means that a typical array should be Products for Solar Installers
designed with the understanding that it will lose 0.25% or
more of its voltage each year. Over 25 years, a minimum loss and Integrators
to calculate would be about 6% (0.997525 = 0.939).
Voltage tolerance. While PV modules may have relatively
tight power tolerances (averaging about +3%/-3%), the volt- Heyco® Solar Masthead™ II Cordgrips
age and current tolerances are typically much larger—per-
haps as large as +10%/-10%. This uncertainty is difficult to • Accommodate USE-2 12 AWG and 10 AWG wire
plan for in design. If a module is relatively low in voltage, • Feature skinned-over glands that
offer flexibility to use from 1 to 13
its power specification is met by having an offsetting high available holes while still
current, because power is the product of volts times amps. providing a liquid tight seal
Given the lack of information on module voltage tolerance around the wire
available, it is best to err on the side of caution and assume • Designed for solar
an extra 5% dc voltage loss in the array. rooftop installations
Combined impacts. To arrive at an optimal minimum dc • Provide a watertight seal
for PV module output leads
voltage for the array, add the effects of all the issues together.
to inverters
Currently, string-sizing programs calculate the minimum volt-
age based on the temperature-adjusted maximum power volt-
• Secure input PV leads from
solar panel array strings to fuse holder hookup
age of the module. If the high ac voltage accounts for 3%, array within solar combiner boxes
degradation for 6%, and module voltage tolerance for 5%, then • No disassembly required for installation
the array should be designed to operate with a voltage that is • Available in other sizes and gland configurations–
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The way to avoid problems associated with low dc volt-
Snap-In “Solar Combiner
age is to increase the array voltage. When using string-
Box” Cordgrips
sizing programs, the simple rule I recommend is to eliminate
the lowest voltage option—the source circuit with the least • House multiple wires at
one entry point to provide
number of modules in series. If possible, throw away the two
a liquid tight seal around
shortest source-circuit options. For example, if the sizing each wire and at the panel
program allows 12, 13, 14 or 15 modules in series, limit the • Ideal when individual conductors for power or control
choices to 14 or 15 modules. are used rather than jacketed cable
While this approach may work well in general, it is impor- • Feature a secure “click in place” fit that reduces
tant for system designers to perform detailed low dc volt- tightening errors by installers
age calculations for specific array configurations. Designers • Easy to install–no tools required
should use the highest expected continuous ambient tem- • Have unique fingers that securely lock into a range
perature for calculation purposes. According to the Copper of panel sizes without use of a locknut
Development Association, the highest ASHRAE temperature • Offer limited intrusion into the combiner box enclosure
data that is likely to create a 3-hour continuous condition, where access is tight
per the definition of continuous found in NEC Article 100, is • Rated IP 64
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perature is not high enough, the same table also includes website at www.heyco.com
ASHRAE Extreme Annual Mean Maximum Design Dry Bulb
Temperature data, which can be used for even more conser-
vative voltage or ampacity calculations.

CASE STUDY: EXAMPLE DC VOLTAGE CALCULATIONS w w w. h e y c o . c o m

This case study illustrates how to implement the high and “The First Name in Wire Protection…and So Much More”
low dc voltage recommendations described in this article. It Box 517 • Toms River, NJ 08754 • P: 732-286-4336 • F: 732-244-8843
assumes a 50 kW inverter because designers working on smaller

solarprofessional.com | S O L A R PR O 75
 Array Voltage Considerations

arrays, especially those under 10 kW, can be heavily influenced considering array mounting (typically 20°C to 30°C), and
by a desire to fully exploit the available inverter capacity. This βVMP is the temperature coefficient of Vmp.
often leads to array voltage compromises that are unnecessary
in larger systems. The inverter in this case is large enough that VMIN = 29.5 V + ((34°C + 20°C − 25°C) x -0.133 V/°C)
its capacity does not drive array voltage design. The relevant = 29.5 V + (29°C x -0.133 V/°C)
design details for this case study are as follows. = 29.5 V − 3.9 V
= 25.6 V
Location: Raleigh, NC
Low design temperature: -13°C, per ASHRAE Extreme Annual Select and apply a multiplier to account for the com-
Mean Minimum Design Dry Bulb Temperature bined effects of high ac grid voltage, array degradation and
Record low temperature: -21°C, per Weather.com module voltage tolerance. 0.85 is used in this case:
High design temperature: 34°C, per ASHRAE 2% Annual Design
Dry Bulb Temperature VMIN = 25.6 V x 0.85
PV module: Yingli YL230P-29b, 230 W STC, 29.5 Vmp, 7.8 Imp, = 21.8 V
37.0 Voc, 8.4 Isc, -0.137 V/°C temperature coefficient of Voc
(-0.37%/°C x 37.0 Voc), -0.133 V/°C temperature coefficient of Divide the minimum MPPT voltage by the minimum
Vmp (based on the published temperature coefficient for Pmp, voltage per module and round up to the nearest whole num-
-0.45%/°C x 29.5 Vmp) ber to determine the minimum number of modules in series:
Inverter: Satcon PVS-50, 50 kW, 600 Vdc maximum input,
305–600 Vdc MPPT range NMIN = 305 V / 21.8 V = 13.99
= 14 module in series
Maximum modules in series. To determine the maximum
number of modules in series, first calculate the per-module Comparison of results. It is now possible to recalculate
maximum voltage as follows: the acceptable source-circuit configurations using standard
assumptions for a string-sizing program. There are two main
VMAX = VOC + ((TLOW − TREF) × αVOC) differences in the calculations.
First, use the record low temperature for the location in
where TLOW is the ASHRAE Extreme Annual Mean Mini- place of the ASHRAE Extreme Annual Mean Minimum Design
mum Design Dry Bulb Temperature; TREF is the cell tempera- Dry Bulb Temperature for the VMAX and NMAX calculations:
ture at STC; and αVOC is the temperature coefficient of Voc.
VMAX = 37.0 V + ((-21°C - 25°C) x -0.137 V/°C)
VMAX = 37.0 V + ((-13°C − 25°C) x -0.137 V/°C) = 37.0 V + (-46°C x -0.137 V/°C)
= 37.0 V + (-38°C x -0.137 V/°C) = 37.0 V + 6.3 V
= 37.0 V + 5.2 V = 43.3 V
= 42.2 V
NMAX = 600 Vdc / 43.3 V = 13.9
Divide the maximum inverter input voltage by the = 13 modules in series
temperature-corrected open-circuit voltage and round
down to the nearest whole number to determine the maxi- Second, do not apply a 0.85 multiplier as part of the VMIN
mum number of modules in series: calculations. This means that the minimum number of mod-
ules per source circuit is calculated using a Vmp of 25.6 Vdc:
NMAX = 600 Vdc / 42.2 V = 14.2
= 14 modules in series NMIN = 305 V / 25.6 V = 11.9
= 12 module in series
Minimum modules in series. To determine the minimum
number of modules in series, first calculate the per module The best array design for this case study calls for 14 mod-
minimum voltage as follows: ules per source circuit. However, the simplest string-sizing
program specifies 12 to 13 modules per source circuit. More
VMIN = (VMP + ((THI + TRISE − TREF) × βVMP)) sophisticated string-sizing programs apply a margin of
safety to the minimum expected dc voltage to account for
where THI is the ASHRAE 2% Annual Design Dry Bulb high ac grid voltage, array degradation and module-to-module
Temperature, TRISE is the rise in cell temperature expected voltage mismatch. Using PVSelect.com, for C O N T I N U E D O N P A G E 7 8

76 S O L A R P R O | October/November 2010
 Array Voltage Considerations

example, to calculate the acceptable string sizes for this case conductors. Longer strings also increase the array voltage,
study disqualifies source circuits of 12 modules. However, if the which has voltage drop benefits when cables are sized. Get-
designer is not using ASHRAE low design temperature data, ting the array voltage up also provides insurance when it is
even PVSelect.com cannot identify the best design option. needed most against insidious low dc voltage problems that
Assuring the best design requires both accurate calculations result in poor system performance precisely when the solar
and proper data. resource is greatest. On 5 kW or 50 kW net-metered projects,
the difference in performance between having 14 modules
SIZING THINGS UP in series or 12 or 13 modules in series might not register with
I am not suggesting that inverter manufacturers do not pro- the customer. However, on 500 kW or 5 MW projects that are
vide a valuable service with their string-sizing tools. With- PPA financed, this will make a world of difference in both
out these resources, the number of array design mistakes the installed costs and the revenue generated over the life of
would undoubtedly be many times what it is today. Never- the systems.
theless, system designers routinely make mistakes, in spite
of the fact that they have ready access to many easy-to-use g C O N TAC T
string-sizing tools. The results of the low voltage mistakes Bill Brooks / Brooks Engineering / Vacaville, CA / [email protected] /
described here are not dangerous; they do not pose a hazard brooksolar.com
to persons or property; they do not violate Code. They simply Resources
miss the mark of reducing up-front system cost and optimiz- American Society of Heating, Refrigeration, and Air-Conditioning
ing long-term performance. Designers need to keep in mind Engineers / ashrae.org
that all “approved” string sizes are not created equal. Blue Oak PV Selection Tool / pvselect.com
From an installed cost point of view, it is always better to
Solar America Board for Codes and Standards (Solar ABCs) /
put the maximum number of modules in series. This deliv-
solarabcs.org/permitting
ers the greatest amount of power per pair of source-circuit

78 S O L A R P R O | October/November 2010