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COA Syllabus

This document outlines a computer organization and architecture course. It provides details on course objectives, outcomes, modules, textbook, and evaluation. The course covers topics like computer components, processing units, control units, memory, I/O, parallelism, and multiprocessors.

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70 views2 pages

COA Syllabus

This document outlines a computer organization and architecture course. It provides details on course objectives, outcomes, modules, textbook, and evaluation. The course covers topics like computer components, processing units, control units, memory, I/O, parallelism, and multiprocessors.

Uploaded by

Fme
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ECE3004 Computer Organization and Architecture L T P J C

3 0 0 0 3
Pre-requisite ECE2003 - Digital Logic Design Syllabus version
1.0
Course Objectives:
1. To discuss about architecture, bus interconnection, data processing units and control unit
operations.
2. To elucidate memory systems, mapping techniques and various I/O interfacing methods.
3. To introduce parallelism and pipelining concepts, Flynn taxonomy and multi-processor
architectures.

Course Outcomes:
1. Understand the functional components of a computer and ability to understand different
types of bus architectures and differences between Von-Neumann vs. Harvard
architectures.
2. Understand how basic arithmetic operations are implemented in computer architecture and
how signed multiplication and divisions are carried out using Booth multiplier and divider
in processor architectures.
3. Compare the differences between CISC and RISC architectures and ability to understand
and design the hardwired and micro programmed control units.
4. Gain knowledge between the levels of memory subsystems like Cache memory and Virtual
memory and ability to understand memory mapping schemes used in computer
architectures
5. Classify types of I/O schemes and their operations and ability to choose the scheme based
on the requirements.
6. Comprehend the methods of performance enhancement techniques such as pipelining and
their hazards, Scalar and Vector processing architectures, Multiprocessing techniques like
SMP.

Student Learning Outcomes (SLO): 1, 2, 4


Module:1 Introduction to Computing Systems 5 hours
Organization vs. Architecture, Function and structure of a computer, Functional components of a
computer, Interconnection of components – Simple Bus Interconnect. Evolution of Computers,
Moore’s law, Von-Neumann vs. Harvard architectures.

Module:2 Processing Unit – Data Path 6 hours


Register organization, Arithmetic and Logic Unit – signed addition/subtraction, Multiplier
Architecture – signed/unsigned multiplication – Booth multiplier, array multipliers, restoring and
non-restoring division

Module:3 Processing Unit – Control Path 6 hours


Machine instructions, Operands, Addressing modes, Instruction formats, Instruction set
architectures - CISC and RISC architectures. Instruction Cycle – Fetch-Decode-Execute, Control
Unit- Organization of a control unit - Operations of a control unit, Hardwired control unit, Micro-
programmed control unit.
Module:4 Memory Subsystem 8 hours
Semiconductor memories, Memory cells - SRAM and DRAM cells, Internal Organization of a
memory chip, Organization of a memory unit, Cache memory unit - Concept of cache memory,
Mapping methods, Organization of a cache memory unit, Fetch and write mechanisms, Memory
management unit - Concept of virtual memory, Address translation.

Module:5 I/O Subsystem 8 hours


Access of I/O devices, I/O ports, I/O control mechanisms - Program controlled I/O, Interrupt
controlled I/O, and DMA controlled I/O, I/O interfaces - Serial port, Parallel port, PCI bus, SCSI
bus, USB bus.

Module:6 Instruction Level Parallelism 5 hours


Instruction level parallelism - overview, Design issues, Super Scalar Processors, VLIW
processors, Performance Evaluation, Pipelining and Pipeline hazards.

Module:7 Multiprocessors 5 hours


Processor level parallelism - Dependency, Flynn taxonomy, Memory organization for
Multiprocessors system, Symmetric Multiprocessor, Cache Coherence and The MESI Protocol

Module:8 Contemporary issues: 2 hours

Total lecture hours: 45 hours


Text Book(s)
1. David A. Patterson, John L. Hennessy, “Computer Organization and Design-The
hardware/software interface”, 2013, 5th edition, Morgan Kaufmann Publishers, USA
Reference Books
1 Carl Hamacher, ZvonkoVranesic, SafwatZaky and NaraigManjikian, “Computer
Organization and Embedded Systems”, 2012, 6th edition McGraw Hill, USA.
2 William Stallings, “Computer Organization and Architecture”, 2016, 10th edition, Pearson
/ PHI, USA

Mode of evaluation: Internal Assessment (CAT, Quizzes, Digital Assignments) & Final
Assessment Test (FAT)
Recommended by Board of Studies 13/06/2015
Approved by Academic Council No. 37 Date 16/06/2015

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