ADC Guide, Part 4: Gain Error and Gain Error Drift: by Sachin Gupta and Akshay Phatak, Cypress Semiconductor
ADC Guide, Part 4: Gain Error and Gain Error Drift: by Sachin Gupta and Akshay Phatak, Cypress Semiconductor
Previously, this series discussed offset error, offset drift, and ways to deal with both. This time, we’ll
focus on gain error in the ADC and calibration techniques to address this error.
Gain error
The gain error of an ADC represents how close an ADC’s actual transfer function is to the transfer
function of an ideal ADC. Gain error is specified in % full scale range or number of LSBs. If not calibrated,
gain error limits the overall accuracy of the signal chain. For example, for a 16 bit ADC, a gain error of
±0.2%, means there can be about 7 bits of inaccuracy (131 counts) at the highest ADC output just due to
gain error. Figure 1 shows the transfer curve of a 3-bit ADC representing the gain error.
In Figure 1, the red plot shows the transfer curve of an ideal ADC. The blue curve shows the transfer
curve of a practical ADC (not considering other source of errors and linearity). For an ideal ADC, if analog
value and digital codes are placed at equal distance on the x axis and y axis, the transfer curve will be
the line with slope 1. However, this is not true for practical ADCs. Thus, calibration for this error needs to
determine the actual slope of the transfer curve to compensate for the error.
Dealing with Gain error: It is a straightforward process to calibrate an ADC for gain error (see Figure 2).
Vin
Vref1
MUX
Vref2 ADC
Vref3
To calibrate the ADC requires an accurate reference. For a practical ADC, the transfer function is not a
straight line. Put another way, the gain error is not constant throughout the ADC’s input range (Figure
3). However, calibration can be done based on the precision requirements of the application.
Figure 3: ADC transfer curve with actual variations of gain across input range.
One of the most commonly used calibration techniques is two-point calibration. This method assumes
that the transfer characteristic is a straight line and ignores the deviation of the actual characteristic
from the straight line. This method gives reasonably good performance at the lowest processing and
resource cost. In two-point calibration, one reference can be close to the low end of input range and
another one close to the upper end.
As discussed in a previous part of this series, there is offset error to account for as well. Before
calibrating the ADC for gain error, it must be calibrated for offset error. From here onwards, we will
consider every ADC output to be offset error compensated for the ease of understanding.
If we have a single-ended ADC with a range from 0V to 1.024V and we have a 1V accurate reference for
calibration for the higher end of input range and 0V for the lower end, the actual gain of the ADC can be
given by Equation 1:
GainActual = Output Count of ADC at VREF/Output count of ideal ADC at VREF (1)
Let us take an example. If the output count of the ADC is 99 when an ideal ADC would have given output
count of 100, GainActual will turn out to be 0.99. GainActual represents the actual gain of a given ADC.
Now, during normal operation of ADC, every valid measurement count can be divided by the factor
GainAcutal to get the compensation for gain error of ADC. For example, for a practical ADC which has
actual gain of 0.99 (i.e., the output count is 99), when the count is divided by 0.99, the resultant output
is 100 which is the output of ideal ADC.
As mentioned earlier, two-point calibration considers the ADC’s transfer curve to be linear, which is not
really true. For better accuracy, one can go with multi-point calibration. With multi-point calibration, the
transfer curve is broken in several pieces and, for each piece, the slope of line is calculated.
The challenge for implementing multipoint calibration is the availability of multiple accurate references.
Therefore, most of the time, even for precision applications, 3-point calibration is used.
While calibrating the ADC, one may think that a DAC can be used as a reference voltage generator.
However, DACs themselves have offsets and nonlinearity. Thus, the accuracy of the DAC will limit the
accuracy of the ADC, which may not be acceptable for many applications. In addition, if the DAC is not
calibrated before calibrating an ADC using it, accuracy will further suffer.
While designing any system, accurate references are not generally available. This imposes a challenge
for implementing multi-point calibration. However, many SoCs available on the market today, in
addition to offering higher integration and lower cost, also have on-chip accurate references which are
generated by a band gap voltage.
For example PSoC devices from Cypress have multiple high-precision references which can be used for
calibration. Another advantage which SoCs provide while calibrating an ADC is that these references can
be routed to ADC internally, avoiding the need to allocate extra pins for references.
Figure 4 shows the schematic entry of PSoC Creator. Here, all the references are inside the chip and no
physical pins are need for routing. These internal references can be about ±0.1% accurate. If one needs
better accuracy, external references must be used for calibration.
Figure 4: Internal references for calibration of ADC in a typical SoC
Gain error drift: Gain error is not a constant value, and it varies over the complete operating
temperature range of ADC. This change in gain error due to temperature is known as gain error drift. For
precision measurements, gain error needs to be measured and compensated for more frequently rather
than just measuring once and storing it in FLASH/EEPROM. Gain drift is defined in PPM.
Based on the specified value of drift, one can decide if run-time calibration is needed or if one time
calibration is enough. One limitation of run-time calibration is the time needed to calibrate the ADC,
which may impact processing. The designer will also need to optimize the time needed to calibrate the
ADC. In contrast, with one-time calibration, the gain error will be a constant value and code can be
optimized to deal with it.
Akshay Phatak is an Applications Engineer with Cypress Semiconductor. He holds a Bachelor's degree in
Electronics and Telecommunications form College of Engineering, Pune (India). He likes to work on
mixed-signal embedded systems. He can be reached at [email protected].