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ORG ; ONE
The x86
Microprocessor

Chapter 1b
1.2 INSIDE THE 8088/86
The Von Neumann Model
1.2 INSIDE THE 8088/86
The Von Neumann Model
1.2 INSIDE THE 8088/86
EU & BIU
1.2 INSIDE THE 8088/86

• There are two ways to

make the CPU process
information faster:
– Increase the working
frequency.
• Using technology
available, with cost
considerations.
– Change the internal
architecture of the CPU.
Figure 1-1
Internal Block Diagram of the 8088/86 CPU
(Reprinted by permission of Intel Corporation,
Copyright Intel Corp.1989)
1.2 INSIDE THE 8088/86
BIU
• The BIU is responsible for:
– Instruction fetching
– Reading and writing data operands to/from
memory
– Inputting and outputting data to/from peripherals (i.e., attached
devices)
– Instruction queuing and address generation
• BIU transfers information using the system bus which includes
– 16-bit bidirectional data bus for 8086 (8 for 8088)
– 20-bit address bus
– Control signals needed to transfer data over the bus
1.2 INSIDE THE 8088/86
BIU
• BIU contains:
– Segment registers
– Instruction pointer (IP)
– Address generation adder
– Bus control logic
– Instruction queue (4 bytes
in 8088 and 6 bytes in 8086)
• BIU pre-fetches instructions when
it’s not being asked to access data
from memory
• The instruction queue is a FIFO.
Instructions are automatically shifted closer to
the output.
1.2 INSIDE THE 8088/86
EU
• The execution unit is responsible for:
– Decoding instructions; Executing instructions
• EU consists of:
– Arithmetic logic unit (ALU)
– Status and control flags
– General purpose registers (GPRs) and temporary-operand registers
• The EU accesses instructions from the output end of the FIFO
and data from the GPRs or memory
• EU performs the following steps:
– Reads from FIFO one byte at a time
– Decodes the instruction read
– Generates data addresses if necessary
Ø passes them to the BIU
Ø requests BIU to perform the read or write cycle to memory or I/O
– Performs the operation specified
• During execution, EU may test the flags and updates them based on the results
of the execution
• If queue is empty, EU waits for the next instruction byte to be fetched and shifted
to top of the queue
1.2 INSIDE THE 8088/86
EU & BIU
q The BIU uses the instruction queue to store six bytes of
instructions for 8086.
q The segment registers store the base addresses for code, data, and
stack of external memory.
q The instruction pointer stores the offset address of the instruction
being executed.
q The EU uses the general registers to store the operands and
opcode for the operation.
q The ALU performs the specified arithmetic or logical operations
on the operands transferred from the general registers.
q The flags are typically used to indicate the status of an operation.
1.2 INSIDE THE 8088/86
EU & BIU
1.2 INSIDE THE 8088/86 pipelining

• 8086 could fetch or execute at any given time.

– The idea of pipelining in its simplest form is to allow the
CPU to fetch and execute at the same time.

Figure 1-2 Pipelined vs Nonpipelined Execution

1.2 INSIDE THE 8088/86 pipelining

• Intel implemented pipelining in 8088/86 by splitting

the internal structure into two sections:
– The execution unit (EU) and the bus interface unit (BIU).
• These two sections work simultaneously.
• The BIU accesses memory and peripherals, while
the EU executes instructions previously fetched.
– This works only if the BIU keeps ahead of the EU, so
the BIU of the 8088/86 has a buffer, or queue
• The buffer is 4 bytes long in 8088 and 6 bytes in 8086.
• 8088/86 pipelining has two stages, fetch & execute.
– In more powerful computers, it can have many stages.
1.2 INSIDE THE 8088/86 pipelining

• Fetch and Execute

§ The organization of the CPU into a separate BIU
and EU allows the fetch and execute cycles to
overlap
1. The BIU outputs the contents of the instruction pointer
register (IP) onto the address bus, causing the selected
byte or word to be read into the BIU.
2. Register IP is incremented by 1 to prepare for the next
instruction fetch.
1.2 INSIDE THE 8088/86 pipelining

• Fetch and Execute

3. Once inside the BIU, the instruction is passed to the
queue. This is a first-in, first-out storage register
sometimes likened to a "pipeline".
4. Assuming that the queue is initially empty, the EU
immediately draws this instruction from the queue and
begins execution.
5. While the EU is executing this instruction, the BIU
proceeds to fetch a new instruction. Depending on the
execution time of the first instruction, the BIU may fill the
queue with several new instructions before the EU is
ready to draw its next instruction. The described
architecture is called a pipelined architecture.
1.2 INSIDE THE 8088/86 registers

• In the CPU, registers store information temporarily.

– One or two bytes of data to be processed.
– The address of data.

• General-purpose registers in 8088/86 processors

can be accessed as either 16-bit or 8-bit registers
– All other registers can be accessed only
as the full 16 bits.
• In 8088/86, data types are either 8 or 16 bits
– To access 12-bit data, for example, a 16-bit register
must be used with the highest 4 bits set to 0.
1.2 INSIDE THE 8088/86 registers

• The bits of a register are numbered in descending

order, as shown:

• The first letter of each register indicates its use.

– AX is used for the accumulator.
– BX is a base addressing register.
– CX is a counter in loop operations.
– DX points to data in I/O operations.
1.2 INSIDE THE 8088/86 registers
1.2 Registers
1.2 The Software Model
1.2 Buses and Operations

q All internal registers, as well as internal and external data

buses, are 16 bits wide, firmly establishing the "16-bit
microprocessor" identity of the 8086.
q A 20-bit external address bus gave a 1 MB physical address
space (220 = 1,048,576).
q The data bus was multiplexed with the address bus in order
to fit a standard 40-pin dual in-line package. 16-bit I/O
addresses meant 64 KB of separate I/O space (216 =
65,536).
q The maximum linear address space was limited to 64 KB,
simply because internal registers were only 16 bits wide.
q Programming over 64 KB boundaries involved adjusting
segment registers.
1.2 General Purpose Registers of 8086

• 8086 CPU has 8 general purpose registers, each

register has its own name:

• AX - the accumulator register (divided into AH / AL):

1. Generates shortest machine code
2. Arithmetic, logic and data transfer
3. One number must be in AL or AX
4. Multiplication & Division
5. Input & Output
1.2 General Purpose Registers of 8086

• BX - the base address register (divided into BH / BL).

• CX - the count register (divided into CH / CL):
1. Iterative code segments using the LOOP instruction
2. Repetitive operations on strings with the REP
command
3. Count (in CL) of bits to shift and rotate
• DX - the data register (divided into DH / DL):
1. DX:AX concatenated into 32-bit register for some
MUL and DIV operations
2. Specifying ports in some IN and OUT operations
1.2 General Purpose Registers of 8086

• SI - source index register:

1. Can be used for pointer addressing of data
2. Used as source in some string processing
instructions
3. Offset address relative to DS
• DI - destination index register:
1. Can be used for pointer addressing of data
2. Used as destination in some string processing
instructions
3. Offset address relative to ES
1.2 General Purpose Registers of 8086

• BP - base pointer:
1. Primarily used to access parameters passed via
the stack
2. Offset address relative to SS
• SP - stack pointer:
1. Always points to top item on the stack
2. Offset address relative to SS
3. Always points to word (byte at even address)
4. An empty stack will have SP = FFFEh
1.2 Segment Registers of 8086

• CS - points at the segment containing the current

program.
• DS - generally points at segment where variables
are defined.
• ES - extra segment register, it's up to a coder to
define its usage.
• SS - points at the segment containing the stack.
• Although it is possible to store any data in the segment
registers, this is never a good idea. The segment registers
have a very special purpose - pointing at accessible blocks
of memory.
1.2 Segment Registers of 8086

• Segment registers work together with general

purpose register to access any memory value.
For example if we would like to access memory
at the physical address 12345h (hexadecimal),
we could set the DS = 1230h and SI = 0045h.
This way we can access much more memory
than with a single register, which is limited to 16
bit values.
1.2 Segment Registers of 8086

• The address formed with 2 registers is called an

effective address.
By default BX, SI and DI registers work with DS
segment register;
BP and SP work with SS segment register.
Other general purpose registers cannot form an
effective address.
Although BX can form an effective address, BH and
BL cannot.
1.2 Registers of 8086

• IP - the instruction pointer:

1. Always points to next instruction to be executed
2. Offset address relative to CS
1.2 Registers of 8086 & Others

• 80286 and above contain registers to control and

operate protected memory.
– and other features of the microprocessor
• 80386 through Core2 microprocessors contain full
32-bit internal architectures.
• 8086 through the 80286 are fully upward-
compatible to the 80386 through Core2.
1.2 Registers of
8086 & Others

Figure illustrates the

programming model
8086 through Core2
microprocessor
1.2 Anatomy of Registers
1.2 Multipurpose Registers

• RAX - a 64-bit register (RAX), a 32-bit register

(accumulator) (EAX), a 16-bit register (AX), or as
either of two 8-bit registers (AH and AL).
• The accumulator is used for instructions such as
multiplication, division, and some of the adjustment
instructions.
• Intel plans to expand the address bus to 52 bits to
address 4P (peta) bytes of memory.
• RBX, addressable as RBX, EBX, BX, BH, BL.
– BX register (base index) sometimes holds offset address
of a location in the memory system in all versions of the
microprocessor.
• RCX, as RCX, ECX, CX, CH, or CL.
– a (count) general-purpose register that also holds the
count for various instructions
• RDX, as RDX, EDX, DX, DH, or DL.
– a (data) general-purpose register
– holds a part of the result from a multiplication
or part of dividend before a division
• RBP, as RBP, EBP, or BP.
– points to a memory (base pointer) location
for memory data transfers
• RDI addressable as RDI, EDI, or DI.
– often addresses (destination index) string destination
data for the string instructions
• RSI used as RSI, ESI, or SI.
– the (source index) register addresses source string data
for the string instructions
– like RDI, RSI also functions as a general-purpose register
• R8 - R15 found in the Pentium 4 and Core2 if 64-bit
extensions are enabled.
– data are addressed as 64-, 32-, 16-, or 8-bit
sizes and are of general purpose
– Most applications will not use these registers until 64-bit
processors are common.
– the 8-bit portion is the rightmost 8-bit only
– bits 8 to 15 are not directly addressable as a byte
1.2 Special-Purpose Registers

• Include RIP, RSP, and RFLAGS

– segment registers include CS, DS, ES, SS, FS, and GS
• RIP addresses the next instruction in a section of
memory.
– defined as (instruction pointer) a code segment
• RSP addresses an area of memory called
the stack.
– the (stack pointer) stores data through this pointer
1.2 Flag Register

• RFLAGS indicate the condition of the

microprocessor and control its operation.
• Figure 2–2 shows the flag registers of all versions of
the microprocessor.
• Flags are upward-compatible from the 8086/8088
through Core2 .
• The rightmost five and the overflow flag are
changed by most arithmetic and logic operations.
– although data transfers do not affect them
1.2 Flag Register

• The EFLAG and FLAG register counts for the entire

8086 and Pentium microprocessor family.
1.2 Flag Register
1.2 Flag Bits

• C (carry) holds the carry after addition or borrow after

subtraction.
– also indicates error conditions
• P (parity) is the count of ones in a number expressed as even
or odd. Logic 0 for odd parity; logic 1 for even parity.
– if a number contains three binary one bits, it has odd parity
– if a number contains no one bits, it has even parity
• A (auxiliary carry) holds the carry (half-carry) after addition or
the borrow after subtraction between bit positions 3 and 4 of the
result.
• Z (zero) shows that the result of an arithmetic or logic operation
is zero.
1.2 Flag Bits

• S (sign) flag holds the arithmetic sign of the result after an

arithmetic or logic instruction executes.
• T (trap) this enables trapping through an on-chip debugging
feature.
• I (interrupt) controls operation of the INTR (interrupt request)
input pin.
• D (direction) selects increment or decrement mode for the DI
and/or SI registers.
• O (overflow) occurs when signed numbers are added or
subtracted.
– an overflow indicates the result has exceeded the capacity of
the machine.
• IOPL used in protected mode operation to select the privilege level for
I/O devices.
• NT (nested task) flag indicates the current task is nested within another
task in protected mode operation.
1.2 Flag Bits

• RF (resume) used with debugging to control resumption of execution

after the next instruction.
• VM (virtual mode) flag bit selects virtual mode operation in a
protected mode system.
• AC, (alignment check) flag bit activates if a word or doubleword is
addressed on a non-word or non-doubleword boundary.
• VIF is a copy of the interrupt flag bit available to the Pentium 4–
(virtual interrupt)
• VIP (virtual) provides information about a virtual mode interrupt for
(interrupt pending) Pentium.
– used in multitasking environments to provide virtual interrupt flags
• ID (identification) flag indicates that the Pentium microprocessors
support the CPUID instruction.
– CPUID instruction provides the system with information about the
Pentium microprocessor.