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Part-I:: in Out in OL in OH in

This document is a continuous evaluation test for the 7th semester BTech EEE course VLSI & Microelectronics. It contains 3 parts testing students' knowledge of the subject. Part 1 contains 5 multiple choice questions about short channel effects, scaling techniques, pinch-off, and threshold voltage. Part 2 has two circuit analysis questions asking students to draw and explain a CMOS NAND gate and define equations and concepts related to nMOS transistors. Part 3 offers two longer form questions where students must choose one to answer in detail about scaling techniques, punch-through effect, or the operation and voltage transfer characteristics of a CMOS inverter.

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53 views2 pages

Part-I:: in Out in OL in OH in

This document is a continuous evaluation test for the 7th semester BTech EEE course VLSI & Microelectronics. It contains 3 parts testing students' knowledge of the subject. Part 1 contains 5 multiple choice questions about short channel effects, scaling techniques, pinch-off, and threshold voltage. Part 2 has two circuit analysis questions asking students to draw and explain a CMOS NAND gate and define equations and concepts related to nMOS transistors. Part 3 offers two longer form questions where students must choose one to answer in detail about scaling techniques, punch-through effect, or the operation and voltage transfer characteristics of a CMOS inverter.

Uploaded by

anupnaskar naskar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Pailan College of Management & Technology

Continuous Evaluation Test (Phase III)


Odd Semester of AY 2020-2021

Course: BTech (EEE) Sem:- 7th


Subject: VLSI & Microelectronics Subject Code: EEE-701
Exam Time: 1hr Full Marks: 25

Part-I: ANSWER All QUESTIONS (marks:1 x 5)

Q.1. Which of the following is not associated with Short Channel Effects?
a) Punch-through
b) DIBL
c) Oxidation
d) Hot carrier effects

Q.2. Scaling is done for


a) Decreasing the chip size
b) Increasing the switching speed
c) Reducing the power dissipation
d) None of the above

Q.3. Which of the following scaling techniques requires multiple power supplies or level shifters?
a) Full scaling
b) Constant voltage scaling

Q.4. Pinch-off occurs at the


a) Cut-off region
b) The transition from cut-off to linear region
c) The transition from linear to saturation region
d) The transition from cut-off to saturation region

Q.5. Threshold voltage of CMOS inverter indicates a point on VTC where


a) Vin =Vout
b) Vin = VOL
c) Vin = VOH
d) Vin = 0
Part-II: ANSWER All QUESTIONS (marks:5 x 2)

Q.6. Draw a two input NAND gate circuit in CMOS logic. Explain its operation for any one of the input
combinations (00, 01, 10, 11). 3+2

Q.7. Write down ID equations for all three operating regions for nMOS. Define Body effect and
Inversion. 3+2

Part-III: ANSWER Any one QUESTION (marks:10 x 1)

Q.8. Why scaling is done? Make a comparison between two scaling techniques.
Explain Punch-through effect. 2+5+3

Q.9. Explain the operation of a CMOS inverter circuit with neat circuit diagram and its voltage transfer
characteristics (with proper labeling). 10

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