VLSI ARCHITECTURE ASSIGNMENT-2

Name: Vithya M

BITS ID: 2019HT01605

Architecture Diagram

IF_ID; ID_EX; EX_WB are pipeline registers

Verilog Code

module MainModule(clk, reset);

input clk, reset;

wire [31:0]PC, instruction, writeData, writeData_2, writeData_3, readData1, readData2, aluInput1,

aluInput2, aluOutput, feedback;

wire [4:0]readReg1, readReg2, writeReg, writeReg_1, writeRegIDtoEX, writeRegIDtoEX_1, writeReg_2,

writeReg_3;

wire [2:0]opcode, aluCtrl, opcode_1;

wire instMem_RE, instMem_RE_o, instMem_RE_o1, portA_RE, portB_RE, portC_RE, portC_RE_o,

portC_RE_o1, portC_RE_o2, portC_RE_o3, portC_RE_o4;

ProgramCounter ProgCounter(.clk(clk), .reset(reset), .feedback(feedback), .PC(PC),

.instMem_RE(instMem_RE));

InstructionMemory InstructionMemory(.instMem_RE(instMem_RE), .PC(PC),

.instruction(instruction), .feedback(feedback));

IF_ID_PipelineRegister IF_ID_PipelineRegister(.instruction(instruction), .instMem_RE(instMem_RE),

.instMem_RE_o(instMem_RE_o), .readReg1(readReg1), .readReg2(readReg2), .writeReg(writeReg),
.opcode(opcode));

ALUControl ALUControl(.clk(clk), .portA_RE(instMem_RE_o), .portB_RE(instMem_RE_o),

.opcode(opcode), .writeReg(writeReg), .opcode_1(opcode_1), .writeReg_1(writeReg_1),
.portC_RE_o(portC_RE_o));

RegisterFile RegisterFile(.clk(clk), .readReg1(readReg1), .readReg2(readReg2),

.writeReg(writeReg_3), .writeData(writeData_3), .portA_RE(instMem_RE_o), .portB_RE(instMem_RE_o),
.portC_RE(portC_RE_o4), .readData1(readData1), .readData2(readData2));

ID_EX_PipelineRegister ID_EX_PipelineRegister(.portC_RE_o(portC_RE_o),
.portC_RE_o1(portC_RE_o1), .readData1(readData1), .readData2(readData2), .writeReg(writeReg_1),
.opcode(opcode_1), .aluCtrl(aluCtrl), .aluInput1(aluInput1), .aluInput2(aluInput2),
.writeRegIDtoEX(writeRegIDtoEX));

ALU ALU(.clk(clk), .aluCtrl(aluCtrl), .aluInput1(aluInput1), .aluInput2(aluInput2),

.aluOutput(aluOutput));

Delay Delay(.clk(clk), .portC_RE_o1(portC_RE_o1), .portC_RE_o2(portC_RE_o2),

.writeRegIDtoEX(writeRegIDtoEX), .writeRegIDtoEX_1(writeRegIDtoEX_1));

EX_WB_PipelineRegister EX_WB_PipelineRegister(.aluOutput(aluOutput),
.portC_RE_o2(portC_RE_o2), .portC_RE_o3(portC_RE_o3), .writeRegIDtoEX(writeRegIDtoEX_1),
.writeReg(writeReg_2), .writeData(writeData_2));
 Delay2 Delay2(.clk(clk), .portC_RE_o3(portC_RE_o3), .portC_RE_o4(portC_RE_o4),
.writeReg(writeReg_2), .writeData(writeData_2), .writeReg_3(writeReg_3), .writeData_3(writeData_3));

endmodule

module RegisterFile(clk, readReg1, readReg2, writeReg, writeData, portA_RE, portB_RE, portC_RE,

readData1, readData2);

input clk, portA_RE, portB_RE, portC_RE;

input [4:0] readReg1, readReg2, writeReg;

input [31:0] writeData;

output [31:0] readData1, readData2;

reg [31:0] regFile[0:31];

reg [31:0] t_readData1, t_readData2;

initial begin

regFile[1] = 32'h40;

regFile[2] = 32'h60;

regFile[4] = 32'h60;

regFile[5] = 32'h40;

regFile[7] = 32'hFFFF856D;

regFile[8] = 32'hEEEE3721;

regFile[10] = 32'h1FFF756F;

regFile[11] = 32'hFFFF765E;

end

always @(posedge clk) begin

if (portA_RE == 1)

t_readData1 <= regFile[readReg1];

if (portB_RE == 1)
 t_readData2 <= regFile[readReg2];

end

always @(writeReg or writeData)

if (portC_RE == 1)

regFile[writeReg] <= writeData;

assign readData1 = t_readData1;

assign readData2 = t_readData2;

endmodule

module ProgramCounter(clk, reset, feedback, instMem_RE, PC);

input clk, reset;

input [31:0] feedback;

output [31:0]PC;

output instMem_RE;

reg [31:0]temp;

reg t1;

always @(posedge clk or posedge reset) begin

if (reset == 1) begin

temp <= 0;

t1 <= 1'b1;

end

else begin

if (feedback != 32'hFFFFFFFF) begin

temp <= temp+4;

t1 <= 1'b1;

end
 else

t1 <= 1'b0;

end

end

assign PC = temp;

assign instMem_RE = t1;

endmodule

module InstructionMemory(instMem_RE, PC, instruction, feedback);

input instMem_RE;

input [31:0]PC;

output [31:0]instruction, feedback;

reg [7:0] instMem[0:63];

reg [31:0] temp, temp1;

initial begin

instMem[0] = 8'h41;

instMem[1] = 8'h8C;

instMem[2] = 8'h02;

instMem[3] = 8'h00;

instMem[4] = 8'hA4;

instMem[5] = 8'h18;

instMem[6] = 8'h03;

instMem[7] = 8'h00;

instMem[8] = 8'h07;

instMem[9] = 8'hA5;
instMem[10] = 8'h03;

instMem[11] = 8'h00;

instMem[12] = 8'h6A;

instMem[13] = 8'h35;

instMem[14] = 8'h02;

instMem[15] = 8'h00;

instMem[16] = 8'hff;

instMem[17] = 8'hff;

instMem[18] = 8'hff;

instMem[19] = 8'hff;

temp = 32'h00000000;

temp1 = 32'h00000000;

end

always @(PC) begin

if (instMem_RE == 1)

temp <= {instMem[PC+3],instMem[PC+2],instMem[PC+1],instMem[PC]};

temp1 <= {instMem[PC+7],instMem[PC+6],instMem[PC+5],instMem[PC+4]};

end

assign instruction = temp;

assign feedback = temp1;

endmodule
module IF_ID_PipelineRegister(instruction, instMem_RE, readReg1, readReg2, writeReg, opcode,
instMem_RE_o);

input [31:0]instruction;

input instMem_RE;

output [4:0]readReg1, readReg2, writeReg;

output [2:0]opcode;

output instMem_RE_o;

assign readReg1 = instruction[9:5];

assign readReg2 = instruction[4:0];

assign writeReg = instruction[14:10];

assign opcode = instruction[17:15];

assign instMem_RE_o = instMem_RE;

endmodule

module ID_EX_PipelineRegister(portC_RE_o, readData1, readData2, writeReg, opcode, aluCtrl,

aluInput1, aluInput2, writeRegIDtoEX, portC_RE_o1);

input [31:0]readData1, readData2;

input [2:0] opcode;

input [4:0] writeReg;

input portC_RE_o;

output [4:0]writeRegIDtoEX;

output [2:0]aluCtrl;

output [31:0]aluInput1, aluInput2;

output portC_RE_o1;
assign aluInput1 = readData1;

assign aluInput2 = readData2;

assign aluCtrl = opcode;

assign writeRegIDtoEX = writeReg;

assign portC_RE_o1 = portC_RE_o;

endmodule

module EX_WB_PipelineRegister(aluOutput, writeRegIDtoEX, portC_RE_o2, writeReg, writeData,

portC_RE_o3);

output [4:0] writeReg;

output [31:0] writeData;

output portC_RE_o3;

input [4:0] writeRegIDtoEX;

input [31:0] aluOutput;

input portC_RE_o2;

assign writeData = aluOutput;

assign writeReg = writeRegIDtoEX;

assign portC_RE_o3 = portC_RE_o2;

endmodule

module Delay(clk, portC_RE_o1, writeRegIDtoEX, writeRegIDtoEX_1, portC_RE_o2);

output [4:0] writeRegIDtoEX_1;

output portC_RE_o2;

input [4:0]writeRegIDtoEX;

input clk, portC_RE_o1;

reg [4:0]temp1;

reg temp2;

always@(posedge clk) begin

temp1 <= writeRegIDtoEX;

temp2 <= portC_RE_o1;

end

assign writeRegIDtoEX_1 = temp1;

assign portC_RE_o2 = temp2;

endmodule

module Delay2(clk, writeReg, writeData, portC_RE_o3, writeReg_3, writeData_3, portC_RE_o4);

input [4:0] writeReg;

input [31:0] writeData;

input portC_RE_o3;

input clk;

output [4:0] writeReg_3;

output [31:0] writeData_3;

output portC_RE_o4;

reg [4:0] temp1;

reg [31:0] temp2;

reg temp3;

always @(posedge clk) begin

temp1 <= writeReg;

temp2 <= writeData;

temp3 <= portC_RE_o3;

end
assign writeReg_3 = temp1;

assign writeData_3 = temp2;

assign portC_RE_o4 = temp3;

endmodule

Test Bench

module testBench();

reg clk, reset;

MainModule MainModule(.clk(clk), .reset(reset));

initial begin

clk = 1;

reset = 1;

#10 reset = 0;

end

always

#5 clk = !clk;

initial #70 $finish;

endmodule
Result