958 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO.

5, MAY 2015

Transactions Briefs
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned
Boosted Write Wordline and Negative Write Bitline Write-Assist
Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang,
Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, and Yung-Shin Kao
Abstract— This brief presents a two-port disturb-free 9T subthreshold
static random access memory (SRAM) cell with independent single-ended
read bitline and write bitline (WBL) and cross-point data-aware write
structure to facilitate robust subthreshold operation and bit-interleaving
architecture for enhanced soft error immunity. The design employs a
variation-tolerant line-up write-assist scheme where the timing of area-
efficient boosted write wordline and negative WBL are aligned and
triggered/initiated by the same low-going global WBL to maximize
the write-ability enhancement. A 72-kb test chip is implemented in
United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full
functionality is achieved for V DD ranging from 1.5 to 0.32 V without
redundancy. The measured maximum operation frequency is 260 MHz
(450 kHz) at 1.1 V (0.32 V) and 25 °C. At 0.325 V and 25 °C, the chip
operates at 600 kHz with 5.78 µW total power and 4.69 µW leakage
power, offering 2× frequency improvement compared with 300 kHz of
our previous 72-kb 9T subthreshold SRAM design in the same 40LP
technology. The energy efficiency (power/frequency/IO) at 0.325 V and
25 °C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our
previous design.

Index Terms— 9T static random access memory (SRAM),

boosted wordline, line-up write-assist (LUWA), negative bitline,
subthreshold, ultralow voltage.
I. I NTRODUCTION
Near-threshold/subthreshold embedded memory is desired to
reduce overall system power dissipation and prolong battery life for
ultralow power biomedical and wireless sensor applications. Various
static random access memory (SRAM) cells have been proposed to Fig. 1. (a) Schematic of the proposed disturb-free 9T cell. (b) Layout of the
mitigate the deteriorated design window and functional margins of 9T cell in UMC 40LP CMOS technology.
the conventional 6T SRAM cell [1]–[3] for low-voltage operation This brief presents a two-port disturb-free 9T SRAM cell for
[4]–[22]. Independent read port that isolates the cell storage node subthreshold operation. Section II describes the features and operation
from the read current path to eliminate the read disturb has been of the proposed 9T SRAM cell, and stability evaluation and com-
commonly used to improve read VMIN [5]–[18]. However, most parison with the prior 9T subthreshold SRAM cell in [21] and [22].
of the cells [5]–[17] still suffer write half-select disturb and thus Section III presents the variation-tolerant line-up write-assist (LUWA)
cannot support bit-interleaving architecture for soft error immunity scheme to maximize the write-ability enhancement. Section IV
improvement with error correction code (ECC) [23]–[25]. Various discusses the 72-kb test chip implementation in United Microelec-
cross-point addressing schemes [19]–[22] have been proposed to tronics Corp. (UMC) 40LP CMOS and measurement results. The
achieve disturb-free cell characteristics and facilitate low VMIN and conclusion of this brief is given in Section V.
bit-interleaving architecture simultaneously.
Manuscript received October 18, 2013; revised February 6, 2014; accepted
II. P ROPOSED 9T SRAM C ELL
March 30, 2014. Date of publication May 8, 2014; date of current version The proposed 9T SRAM cell is shown in Fig. 1(a). M4-M5 form
April 22, 2015. This work was supported in part by the Ministry of Economic the dedicated two-stacked read port with row-based Virtual Ground
Affairs in Taiwan under Contract 100-EC-17-A-01-S1-124, in part by the
National Science Council of Taiwan under Contract NSC 102-2218-E-009-
(VGND) control. M1-M2 are write access transistors controlled
025, and in part by the Ministry of Education in Taiwan under ATU Program. by data-aware column-based write wordline (WWL) WWLA and
C.-Y. Lu, C.-T. Chuang, and S.-J. Jou are with the Department of Electronics WWLB, respectively. The source nodes of M1-M2 connect to the
Engineering, Institute of Electronics, National Chiao Tung University, Hsinchu drain node of M3. The gate of M3 is controlled by row-based WWL
300, Taiwan (e-mail: [email protected]; [email protected]; enable (WWLE) signal, while the source node of M3 connects to
[email protected]).
M.-H. Tu, Y.-P. Wu, C.-P. Huang, P.-S. Kan, H.-S. Huang, the single-ended column-based write bitline (WBL). The column-
K.-D. Lee, and Y.-S. Kao are with Faraday Technology Corporation, Hsinchu based WWLA and WWLB control M1-M2 based on data-in to form
300, Taiwan (e-mail: [email protected]; [email protected]; cross-point write access with row-based WWLE. The layout of the
[email protected]; [email protected]; huanshun@faraday- proposed 9T cell based on UMC 40LP logic rules is shown in Fig.
tech.com; [email protected]; [email protected]).
Color versions of one or more of the figures in this paper are available
1(b). The cell size is 0.82 μm × 1.03 μm, same as the previous 9T
online at http://ieeexplore.ieee.org. cell in [21] and [22], and about 1.53× of the conventional 6T cell
Digital Object Identifier 10.1109/TVLSI.2014.2318518 and 1.24× of the conventional 8T cell under the same logic rules.
1063-8210 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 5, MAY 2015 959

Fig. 3. (a) Data-dependent RBL leakage. (b) RBL read 1 leakage of the
proposed 9T cell, foundry-based 6T cell, and prior 9T cell [21], [22] in 40LP
CMOS.

pattern is considered where all unselected cells in the selected column

store 0 at the right cell storage node. In the prior 9T cell, the
cross-point write structure is formed by two series-connected pass
Fig. 2. (a) Write operation of the proposed 9T cell. (b) Disturb-free transistors. As such, leakage paths are present from the RBL to the
characteristics of row and column half-selected cells during write operation. right cell storage nodes of unselected cells, similar to the conventional
6T cell. In the proposed 9T cell, the cross-point write structure is
formed by the row-based WWLE and column-based WWLA/WWLB,
allowing the read port current path to be isolated from the cell storage
For read operation, the row-based high-going Read Wordline and node. Furthermore, due to the row-based VGND control, there is
row-based low-going VGND enable the two-stacked read port, and no voltage drop between RBL and VGND for unselected cells on
if QB is 1, read bitline (RBL) would be discharged (Sense Q = 0). the selected column. Consequently, there is no leakage path from
Fig. 2(a) illustrates the selected cell during write operation. RBL to the unselected cell storage nodes or through the read stacks,
Depending on data-in, either WWLA or WWLB goes high. The row- thus providing solid read 1 holding capability regardless of data
based WWLE goes high to turn ON M3 to pass WBL voltage into pattern. As shown in Fig. 3(b), the RBL leakage (under worst case
Q or QB through two-stacked nMOS (M3 and one of M1/M2). The data pattern) for the proposed 9T cell is one order of magnitude lower
cross-point write structure formed by column-base WWLA/B and than the prior 9T cell across all process corners, resulting in superior
row-based WWLE eliminates write half-select disturb [Fig. 2(b)]. The functionality for low-voltage operation. Notice that in Fig. 3(b), the
row half-selected cells are protected by unselected WWLA/B, while RBL leakage for the prior 9T cell (through two series-connected pass
the column half-selected cells are protected by unselected WWLE. transistors) is higher than the conventional 6T cell (through one pass
The influence of the floating node joining M1/M2/M3 on the stability transistor). This is because the prior 9T cell and the proposed 9T cell
of half-selected cells on the selected column is minimized through are laid out using logic rules, hence the cell transistors and cell size
careful/optimized physical layout. Extensive transient Monte Carlo are substantially larger than the conventional 6T cell offered by the
simulations across all Process, Voltage and Temperature corners and foundry (0.303 μm2 ).
measurement results indicate that the floating node does not produce
appreciable impact on the cell’s column half-select stability. III. L INEUP W RITE -A SSIST
Monte Carlo simulations with 17 000 samples at 0.35 V, PMOS
The design employs a variation-tolerant LUWA scheme where the
Slow, NMOS Fast (where Read Static Noise Margin and write half-
select SNM are the worst) with 3σ local random variation at 25 °C timing of area-efficient boosted WWL and negative WBL are aligned
and triggered/initiated by the same low-going global WBL (GWBL)
show that the proposed 9T cell exhibits 3× larger mean write half-
to maximize the write-ability enhancement.
select SNM (98 mV versus 33.37 mV) with much tighter distribution
(μ/σ = 7.61 versus 3.37) compared with the conventional 6T cell.
The proposed 9T cell offers better data-dependent RBL leakage A. Area-Efficient Boosted WWL
suppression compared with the prior 9T cell in [21] and [22]. Fig. 3 Fig. 4(a) shows the proposed area-efficient boosting structure.
illustrates the data-dependent RBL leakage and RBL read 1 leakage Notice that Fig. 4(a) uses the boosting of worldline (WL) as an
comparison of the proposed 9T cell, the foundry-based conventional example, while in the proposed 9T SRAM design the boosting
6T cell and the prior 9T cell [21], [22] at 0.35 V, 25 °C across structure is used to boost the column-based WWL. The boost-
various process corners with 64 cells per RBL. The worst case data ing circuitry consists of 3 parts: driver, booster and floodgate.

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 960 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 5, MAY 2015

Fig. 4. (a) Proposed area-efficient boosting structure. (b) Pertinent wave-

forms. A single Booster is shared by all WLs in a local bank. Notice that
in the proposed 9T SRAM design the boosting structure is used to boost the
column-based WWL. Fig. 5. Proposed LUWA scheme and pertinent waveforms. Both boosted
WWL and negative WBL are initiated/triggered by the low-going GWBL.

Driver swings WL to full VDD and is then isolated from WL during

boosting stage. Booster contains the boosting capacitor (CB ) to store
charges for coupling node VST to a higher than VDD voltage. The
booster is shared by all WLs in a local bank to minimize the area
and energy overhead. Floodgate transfers the charges at the boosted
Voltage Boosting (VST) node to the selected WL. For the selected
WL [WL(ON)], charges at boosted VST node would pass through
MPG1 in floodgate(ON), charging WL(ON) to higher than VDD . For
unselected WL [WL(OFF) in Fig. 4(a)], the corresponding MPG2 is
OFF, thus isolating node VST from the unselected WL.
Fig. 4(b) shows the pertinent waveforms. Boosting enable bar
(BSTEN) is initially at high to precharge booster (precharge VST
to VDD ) and power up the driver (precharge VDD1/VDD2 to VDD ).
When the selected WL1 goes low, WL(ON) is charged to full VDD
by Inv1 (in driver). Once boosting commences, BSTEN goes low
Fig. 6. Layout view and die photo of the 72-kb test chip. The macro size is
to turn ON M2 and turn OFF M1 [in driver(ON)], thus equalizing 446 μm × 441 μm in UMC 40LP CMOS.
node N1 and VDD1 (N1 ≈ VDD1 ≈ VDD ). The unselected WLs
[WL(OFF) × N] stay at low. At the same time, BSTEN triggers the
booster, boosting VST from VDD to a higher voltage by capacitor CB .
B. Timing Alignment of Boosted WWL and Negative WBL
The boosted voltage/charge at VST is shared with WL(ON) and its
related parasitic loading (at node N1 and VDD1 via the ON Fig. 5 illustrates the proposed LUWA scheme and pertinent wave-
pull-up pMOS of Inv1) through MPG1 of floodgate(ON), forms where the timing of boosted WWL write-assist and negative
thus boosting WL(ON) from VDD to VDD+ . Notice that WBL write-assist [21], [22], [26] are aligned and triggered/initiated
VST ≈ WL(ON), hence the pMOS of G1 is completely OFF. by the same low-going GWBL to maximize the write-ability enhance-
Similarly, WL(ON) ≈ VDD1 ≈ N1 ≈ VDD+ , hence M1 is also ment. GWBL sources the WBL node [Fig. 1(a)] of cells in the
completely OFF. As such, the selected WL(ON) could efficiently selected column through column MUX (MUX[0] in Fig. 5). GWBL
keep its VDD+ without any discharging path. is also buffered through inverter Y1, and together with bank-select
The 72-kb test chip is organized into 32 banks. Each bank consists signal (BankSel) initiate/trigger the booster of the selected bank
of 32 rows and 72 columns with interleaving four architecture. There through NAND gate Y2. Furthermore, GWBL initiates/triggers the
is one boosting capacitor for each bank, so each boosting capacitor Negative Bitline circuit (at Global DIDO) of the selected bank
is driving 72/4 = 18 selected WWLs. through NAND_UD→X1→X2→X3 to beget the negative transient

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 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 5, MAY 2015 961

Fig. 7. Measured error-free full-functionality die yield versus VDD without

redundancy at room temperature. Sixty-five dies are measured.

Fig. 9. (a) Measured bit failure rate (BFR) versus VDD . (b) Comparison of
measured BFR of negative WBL and LUWA for VDD below 0.3 V.

TABLE I
F EATURES OF THE 72-kb T EST C HIP

Fig. 8. (a) Measured maximum operation frequency, leakage power, and total
power of the 72-kb test chip versus VDD . In addition, shown is the maximum
operation frequency of a 72-kb SRAM macro using the previous 9T cell [22].
(b) Comparison of measured maximum operation frequency and performance
improvement of the present design with that using the previous 9T cell [22]
at low voltage.

pulse at GWBL and pass it into WBL of the selected column. The (from 0.75 V without write-assist to 0.6 V). The introduction of
timing difference of boosting WWL and negative WBL is contained negative WBL improves VMIN by another 200 mV (from 0.6 to 0.4
to within two local delays, with only few gates and local wire V). At 0.35 V, the die yield of the present design is 2.75× of the
connection. Thus, LUWA offers variation-tolerant alignment of the previous design [22]. The present design also extends the error-free
timing of WWL boosting and negative WBL to maximize the write- full functionality VMIN (of the best two dies) to 0.325 V from 0.35 V
ability enhancement. for the previous design.
The measured maximum operation frequency, leakage power and
IV. T EST C HIP I MPLEMENTATION AND M EASUREMENT total power versus VDD of the 72-kb test chip are shown in Fig. 8(a).
A 72-kb test chip is implemented in UMC 40LP CMOS. The layout The maximum operation frequency is 260 MHz (450 kHz) at 1.1 V
view and die photo are shown in Fig. 6. The 72-kb macro is organized (0.32 V) and 25 °C. In addition, shown for comparison is the
into 32 banks. Each bank consists of 32 rows and 72 columns with maximum operation frequency versus VDD of a 72-kb SRAM macro
interleaving four architecture for soft error immunity improvement using the previous 9T cell [22] with the same organization in the same
with ECC [23]–[25]. The local RBL/WBL length is 32 bit. The data 40LP technology. The present design achieves 25% (100%) frequency
I/O width is 36 bit. The macro size is 446 μm × 441 μm. In the test improvement at 0.4 V (0.325 V) compared with the previous 9T
chip, the boosted WWL write-assist and negative WBL write-assist design [Fig. 8(b)]. At 0.325 V, the present design operates at 600 kHz
can be enabled individually for testing. with 5.78-μW total power and 4.69-μW leakage power with an
Sixty-five packaged dies are tested with Credence SC312 tester. energy efficiency (power/frequency/IO) of 0.267 pJ/bit, compared
Dies are tested with full suits of industry standard SRAM compiler with 300 kHz and 0.350 pJ/bit of the previous 9T design [22],
product qualification patterns, including CHECKBOARD, MATS+, representing a 23.7% energy efficiency improvement.
MARCH C−, and MARCH C+ with all high/low-read/write com- Fig. 9(a) shows the measured bit failure rate (BFR) versus VDD
binations. Fig. 7 shows the measured error-free full-functionality die without/with write-assist techniques. Without any write-assist, VMIN
yield versus VDD without redundancy. It can be seen that boosted is limited at 0.65 V. With boosted WWL only, VMIN improves by
WWL improves VMIN (defined at 90% die yield) by about 150 mV about 125 mV to 0.525 V. With either negative WBL or LUWA,

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 962 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 5, MAY 2015

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