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Technical Explanation: Skiip 3 V3

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170 views49 pages

Technical Explanation: Skiip 3 V3

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Technical

Explanation SKiiP®3 V3

Revision: 03
Issue Date: 2014-10-30
Prepared by: Schiller Anastasia (eds.)
Approved by: RW E-KAZ

® ®
This document is valid for all SKiiP 3 V3 katalogue types as well as for the customized SKiiP 3 V3 with
restrictions according to the customer specification.
The document remains effective until replaced by subsequent revision of this document.

Technical Explanation SKiiP®3 V3

Please note:
Unless otherwise specified, all values in this technical explanation are typical values. Typical values are the average values
expected in large quantities and are provided for information purposes only. These values can and do vary in different applications.
All operating parameters should be validated by user’s technical experts for each application.
This document is valid for the entire catalogue SKiiP types with the delivery dates from 01.01.2012 ongoing. The document remains
effective until replaced by subsequent revision of this document.

© by SEMIKRON 30.10.2014-Rev03 1 / 49
PROMGT.1026 / Rev. 1 / Template Technical Explanation
Technical Explanation
SKiiP®3
Table of Content
1. Related documents ......................................................................................................................................... 3
2. Introduction ...................................................................................................................................................... 4
2.1 Heat sink ................................................................................................................................................... 5
2.2 Power section ........................................................................................................................................... 5
2.3 Gate Driver board ..................................................................................................................................... 5
3. Topologies and selection guide ....................................................................................................................... 6
3.1 Type Designation Code ............................................................................................................................ 6
3.2 Overview of the available types and current ratings ................................................................................. 7
4. Tests and Standards ....................................................................................................................................... 9
4.1 Tests for qualification and re-qualification ................................................................................................ 9
4.2 Electromagnetic compatibility (EMC) ........................................................................................................ 9
4.3 Isolation coordination .............................................................................................................................. 10
4.4 Installation altitude .................................................................................................................................. 10
5. Gate Driver Board ......................................................................................................................................... 13
5.1 Overview ................................................................................................................................................. 13
5.2 Gate driver interface ............................................................................................................................... 14
5.2.1 Overview .......................................................................................................................................... 14
5.2.2 Pin description .................................................................................................................................. 16
5.2.3 External Power Supply ..................................................................................................................... 19
5.2.4 Switching Signal Inputs .................................................................................................................... 20
5.2.5 Analogue Output Signals ................................................................................................................. 21
5.2.6 Error output ...................................................................................................................................... 23
5.2.7 Ground connection ........................................................................................................................... 24
5.2.8 Shield and protective earth/chassis connection ............................................................................... 24
5.3 Gate driver board .................................................................................................................................... 25
5.3.1 Overview .......................................................................................................................................... 25
5.3.2 Power-On-Reset .............................................................................................................................. 25
5.3.3 Interlock Dead Time Generation ...................................................................................................... 25
5.3.4 Short pulse suppression ................................................................................................................... 26
5.3.5 Switching frequency rating ............................................................................................................... 27
5.3.6 Failure Management ........................................................................................................................ 28
5.3.7 Analogue signals / sensor functionality ............................................................................................ 32
6. Power terminals ............................................................................................................................................. 35
7. Application hints ............................................................................................................................................ 36
7.1 Verification of design .............................................................................................................................. 36
7.2 Definition of Thermal Resistance ............................................................................................................ 36
7.3 Maximum blocking voltage and snubber capacitors ............................................................................... 38
7.4 Isolation voltage test (IVT) ...................................................................................................................... 38
7.5 Current sharing between paralleled half bridge modules ....................................................................... 39
7.6 Recommended temperature rating ......................................................................................................... 40
7.7 Paralleling of SKiiP®3 V3 ....................................................................................................................... 41
7.8 Prevention of condensation .................................................................................................................... 43
8. Logistics ......................................................................................................................................................... 44
8.1 Label ....................................................................................................................................................... 44
8.1.1 System Label ................................................................................................................................... 44
8.1.2 Halfbridge Laser Label ..................................................................................................................... 44
8.1.3 Warranty Label ................................................................................................................................. 45
8.1.4 Data Matrix Code ............................................................................................................................. 45
9 Abbreviations ................................................................................................................................................. 47

1. Related documents


®
Data sheets SKiiP 3 V3

®
Data sheet SKiiP 3 F-Option

®
Technical Explanation SKiiP 3 F-Option

®
Data sheets SKiiP 3 Parallel Board

®
Technical Explanation SKiiP 3 Parallel Board

All these documents can be found on the SEMIKRON internet page.

2. Introduction
th ®
The 3 generation SKiiP, by name SKiiP 3 V3, is an intelligent power module (IPM) with high power density
and reliability. SEMIKRON´s SKiiP stands for “SEMIKRON intelligent integrated Power” what means that
three perfectly matched components are integrated to one IPM:
 heat sink
 power section
 gate driver board
®
Figure 2.1: 4-fold SKiiP 3 V3

The power section consists of 2, 3 or 4 in parallel connected half bridge modules for GB-type or of 3
separetely controlled half bridge modules (1 half bridge per phase) for GD-type, whereas a half bridge is
defined as shown in Figure 2.2. Explosion picture of half bridge module is shown in Figure 2.3. The IGBT
and the diode connected between DC+ and AC are named TOP IGBT / TOP diode. Consequently, the IGBT
and the diode between AC and DC- are named BOT IGBT / BOT diode.
Figure 2.2: Half bridge definition
DC+

TOP

BOT

DC-

© by SEMIKRON 30.10.2014-Rev03 4 / 49
Technical Explanation
SKiiP®3
In this document following synonyms will be used for a power section with
 2 half bridge modules in parallel = 2-fold
 3 half bridge modules in parallel = 3-fold
 4 half bridge modules in parallel = 4-fold
Figure 2.3: Half bridge “explosion picture”

2.1 Heat sink

SEMIKRON offers high efficient water cooled heat sinks and air cooled aluminium heat sinks. Technical
details can be seen in the corresponding data sheets. Customer specified heat sinks can be assembled on
request as well. However there are several limitations, which should be considered for the customer specific
heatsinks to enable SEMIKRON to handle them. Please refer to the PI 12-034 for additional information.

2.2 Power section

®
SKiiP 3 V3 power section is based on the SKiiP pressure contact technology, which allows a compact power
module design with very low thermal resistances, high thermal cycling capability and low parasitic stray
inductances. The pressure contact technology means the Al2O3 or AlN DCB (direct copper bonded)
substrate is pressed directly onto the heat sink without the use of a base plate. The pressure is induced by a
pressure part on top, which is screwed to the heat sink.
Contact springs are used for all of the auxiliary contacts (gate, auxiliary emitter and temperature sensor).
These spring contacts allow the solder-free connection of the driver PCB.

2.3 Gate Driver board

The task of the driver unit is both transferring incoming signals into powerful output signals to control the
IGBT and to ensure signal isolation between low and high voltage sides of the driver board. Additionally, fault
conditions need to be monitored to protect the power section in case of a failure. For these purposes the
normalized analogue voltage signals of the actual AC-current value, the actual ceramic substrat temperature
®
value and the actual DC-Link voltage value (optional, depends on SKiiP 3 V3 type, please see Chapter 3,
®
page 6 for the information) are available at the SKiiP 3 V3 DIN41651 gate driver connector for use in the
control unit.

3. Topologies and selection guide

3.1 Type Designation Code

SKiiP2413GB17 2- 4DUL
Nominal current
ICnom divided by 100, i.e. 2400A / 100 = 24.

Isolation DCB ceramic substrate type

1...aluminium oxide (Al2O3) DCB ceramic
0....aluminium nitride (AlN) DCB ceramic

SKiiP generation
3...third generation of SKiiP

Chip type
G...IGBT

Circuit
B...2 pack (half bridge, dual)
D...6 pack (3 phase bridge)

Voltage class
12...VCES = 1200V
17...VCES = 1700V

Chip generation
2....IGBT2 Chip

Number of used half bridges

2
3
4

Gate driver designator

DU...integrated DC-Link measurement
DF...Fiber Optic board

Heat sink designator

L...standard air forced cooling profile
W...standard liquid cooling profile
K...customized cooling profile

© by SEMIKRON 30.10.2014-Rev03 6 / 49
Technical Explanation
SKiiP®3
3.2 Overview of the available types and current ratings
Table 3-1 gives an overview of the available types and current ratings (ICnom).
®
Table 3-1: SKiiP 3 V3 standard product range
GB-Type (2-pack):

2-fold 3-fold 4-fold

SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP

1213GB 1013GB 1203GB 1813GB 1513GB 1803GB 2413GB 123- 2013GB 2403GB
123-2DW 172-2DW 172-2DW 123-3DW 172-3DW 172- 4DW 172-4DW 172-4DW
3DW

SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP

1213GB 1013GB 1203GB 1813GB 1513GB 1803GB 2413GB 123- 2013GB 2403GB
123-2DL 172-2DL 172-2DL 123-3DL 172-3DL 172-3DL 4DL 172-4DL 172-4DL

ICnom = 1000/1200A ICnom = 1500/1800A ICnom = 2000/2400A

SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP SKiiP

603GD123- 613GD 513GD172- 603GD172- 603GD123- 613GD 513GD172- 603GD172-
3DUL 123-3DUL 3DUL 3DUL 3DUW 123-3DUW 3DUW 3DUW

ICnom = 600A ICnom = 600A ICnom = 500A ICnom = 570A ICnom = 600A ICnom = 600A ICnom = 500A ICnom = 570A

®
For SKiiP 3 V3 there are two types of ceramic substrate available: Aluminum Nitrite and Aluminum Oxide.
The first one has a very good thermal conducivity which is suitable for the water cooled applications,
whereas the second one is basically supposed for the standard forced air cooled applications.

4. Standards and qualification tests

4.1 Tests for qualification and re-qualification

®
Table 4-1: SKiiP 3 V3 Tests for qualification and re-qualification
No Test Test Conditions Standard
01 High Temperature Reverse 500h, UDC=1615V, VGE = 0V, Tjmax=140°C IEC 60747-9
Bias
02 High Temperature Gate 500h, +/- VGSmax/ VGEmax, IEC 60747-9
Stress TC= Tjmax – 10°C
03 High Humidity High 504h, 85°C, 85% RH, VCE = 80% of VCEmax, IEC 60068 Part 2-67
Temperature Reverse Bias VGE = 0V
04 High Temperature Storage 1000h, Ta= +125°C IEC 60068 Part 2-2
05 Low Temperature Storage 1000h, Ta = -40°C IEC 60068 Part 2-1
06 Thermal Cycling 100 cycles, -40°C/ +125°C IEC 60068 Part 2-14
07 Power Cycling 20.000 load cycles @ ΔTj = 110K, Tjm=95°C IEC 60747-9
08 Vibration Sinusoidal Sweep, 5g, x, y, z – axis, 2h/ axis IEC 60068 Part 2-6
09 Shock Halfsinusoidal Pulse, 30g, +/- x, +/- y, +/- z IEC 60068 Part 2-27
direction, 1000 times/ direction

4.2 Electromagnetic compatibility (EMC)

®
The SKiiP 3 is designed to withstand the following immunity tests with EMC compliant installation:
®
Table 4-2: SKiiP 3 V3 Electromagnetic compatibility
Immunity test Conditions Test level
Fast transients (Burst) (61000-4-4) On driver board interfaces 4kV / 5kHz
Radio Frequency Fields (61000-4-3) Polarisation: vertical + horizontal
Frequency: 80 MHz - 1000 MHz
Modulation: 80% AM, 1kHz
Far field, homogeneous 15V/m
RF Conducted Disturbance (61000-4-6) Frequency: 150 kHz - 80 MHz 20V
Modulation: 80 % AM, 1kHz
Electrostatic discharge (ESD) Contact discharge 8kV
EN 61000-4-2

4.3 Isolation coordination

®
The isolation of the SKiiP 3 V3 is designed according to EN50178.
Please note: The isolation of the temperature signal is a basic isolation only. In a failure case the plasma
of an arc can apply high potential to the temperature sensor. Equipment which is designed for reinforced
isolation must have additional isolation for all parts which might be touched by a person.
®
For working conditions please refer to the datasheet SKiiP 3 V3, p.3.
®
Table 4-3: Isolation limits SKiiP 3 V3
Isolation / Test level Min value
Partial discharge extinction voltage (IEC60664-1)
between high voltage and low voltage sides of 1700Vrms; QPD < 10pC
driver board
Rated impulse voltage (IEC60664-1)
high voltage to low voltage and low voltage to 8kV 1,2/50µs
heat sink

4.4 Installation altitude

®
Isolation coordination for SKiiP 3 V3 is done for overvoltage category III and altitudes up to 2000m.
The required clearance distances between mains-circuits and their environment for overvoltage category III
are listed in EN50178.
For an earthed-neutral system the rated isolation voltage is defined in chapter 5.2.16.1 of EN50178 as:
“…the peak value of the rated voltage between phase and earthed neutral point.”
Based on this sentence the rated isolation voltage in case of a grounded delta grid (Figure 4.1) and a star
grounded grid (Figure 4.2) can be derived as:
Rated isolation voltage in case of 690V grounded delta grid: 690V
Rated isolation voltage in case of 690V star grounded grid: 400V

Figure 4.1: Grounded delta grid Figure 4.2: Star grounded circuit
network (690V-TN-grid)
L1 L1
690V
UL13 UL12 UL1 ULE=400V

UL3 UL2 ULL=690V

L2
L3
L3 L2
UL23
Based on the kind of grid and the voltage level the required clearance distances for basic and reinforced
isolation differ from the designed ones.
According to HD625 S1 and IEC60664-1 the maximum altitude can be calculated based on the factors
between required and designed clearance distances.
Table 4-4: Altitude correction factors (IEC 60664-1)
Normal barometric Multiplication factor
Altitude
pressure for clearances
m kPa
2 000 80,0 1,00
3 000 70,0 1,14
4 000 62,0 1,29
5 000 54,0 1,48
6 000 47,0 1,70

7 000 41,0 1,95

8 000 35,5 2,25
9 000 30,5 2,62
10 000 26,5 3,02
15 000 12,0 6,67
20 000 5,5 14,5
The overvoltage category influences the installation altitude too. To increase the altitude further the
overvoltage category need to be reduced (EN50178):
“As an alternative to the values of table 3, columns 2 to 5, the clearances between mains-circuits of an EE
and its environment may be designed in accordance with overvoltage category II, if facilities are provided
which reduce overvoltages of category III to values of category II…However for reinforced isolation
according to column 7 shall not be reduced.”
The required clearance distances between mains-circuits and their environment for overvoltage category II
are listed in EN50178.
®
If safety isolation is necessary the maximum altitude of SKiiP 3 V3 is 2857m (independent from overvoltage
category).
If only basic isolation is required even higher altitudes are possible. In case of 690V TN grid and overvoltage
®
category II an altitude of theoretically 8305m for SKiiP 3 V3 is possible.
This is the case when an additional basic isolation is implemented between SKiiP driver interface and
controller board. This can be realized by the following means:
• Use of fiber optic for control signals (TOP, BOT, Error) and

• SKiiP analogue signals (current, DC-voltage and temperature measurement) are not used
and

• all SKiiPs are supplied by separate power supplys on which no other circuit is connected.

The above described implementation is shown in the Figure 4.3.

Figure 4.3: Implementation of additional basic isolation between

®
SKiiP 3 V3 driver interface and controller board
Supply
Power

Supply
Power
-SKiiP PWM signals
Controller board
- Regulation
Analogue interface
Not used

Finally, the installation altitude of SKiiP depends on:

 The kind of grid (star grounded grid, delta grounded grid)
 The voltage level of the line to earth voltage (rated isolation voltage)
 The overvoltage category (II or III)
 Whether safety isolation is required or not
®
Table 4-5 summarizes the installation altitudes for SKiiP 3 V3.
®
Table 4-5: Installation altitudes for SKiiP 3 V3 in dependency on kind of grid, overvoltage category and
kind of required isolation
Overvoltage category III Overvoltage category II
Grounded delta grid TN 690V Grounded delta grid TN 690V
L1 L1 L1 L1
SKiiP®3 V3 <600V
690V <600V
690V
UL13 UL12 UL1 ULE=400V UL13 UL12 UL1 ULE=400V
(with 600V
grounded delta) ULL=690V UL3 UL2 ULL=690V
UL3 UL2
L2 L2
L3
L3 L 2 L3 L3 L2
UL23 UL23
Basic Required
isolation to for 5,5 mm 5,5 mm 3 mm 3 mm
2000m
ground
Existing 7,1 mm
Factor 1,29 1,29 2,36 2,36
Altitude 4000m 4000m 8305m 8305m
Reinforced Required
isolation for 8 mm 8 mm 8 mm 8 mm
2000m
Existing 9 mm
Factor 1,12 1,12 1,12 1,12
Altitude 2857m 2857m 2857m 2857m
Maximum altitude
2857m 2857m 2857m 2857m
with safety isolation
Maximum altitude
without safety 4000m 4000m 8305m 8305m
isolation

5. Gate Driver Board

5.1 Overview
The functionality of the Gate Driver can be seen in following block diagram.

®
SKiiP 3 V3 DIN41651 gate driver connector, red block in the Figure 5.1 (refer to Chapter 5.2)
 Gate driver board, green block in the Figure 5.1 (refer to Chapter 5.3)

Figure 5.1: Gate Driver Board block diagram

5.2 Gate driver interface

5.2.1 Overview

®
The gate driver interface SKiiP 3 V3 DIN41651 is Figure 5.2: Gate Driver Interface
marked in Figure 5.2. It is a 14 pin (GB-Type) or 26
pin (GD-Type) plug connector. The picture, the pin-out
and the dimensions are summarized in Figure 5.3 for
GB-Type and Figure 5.4 for GD-Type.
The connector includes pins for:
 External Power Supply (refer to chapter 5.2.3)
 Switching signal input (refer to chapter 5.2.4)
 Analogue signals (refer to chapter 5.2.5)
 Error output (refer to chapter 5.2.6)
 15V output for external components (refer to
chapter 5.2.3)
Magnetic transformers are used for isolation between
gate driver low voltage and high voltage sides. The
circuit used for the DC-Link voltage measurement is
designed, manufactured and tested according to
reinforced isolation (EN50178). The temperature sensor is isolated on the ceramic substrate. Please see the
®
datasheet SKiiP 3 V3, page 3 for Isolation Coordination information.

Please note: The isolation of the temperature signal is a basic isolation only. In a failure case the plasma
of an arc can apply high potential to the temperature sensor. Equipment which is designed for reinforced
isolation must have additional isolation for all parts which might be touched by a person.

®
Figure 5.3: SKiiP 3 V3-connector DIN41651, GB Type, male plug, vertical, top view
Picture Pin Description Dimensions

Pin 1 is marked with the triangle (see the Figure 5.3, right) both on the male and female connectors.

®
Figure 5.4: SKiiP 3 V3-connector DIN41651, GD Type, male plug, vertical, top view
Picture Pin Description Dimensions

®
For connecting the SKiiP 3 V3 to a controller the following recommendations should be considered when
choosing a cable:
 Cable length should be kept shorter than 3m
 Longer cables must be shielded on the customer side. They could be connected to pin 1 on driver
interface additionally

Verification according to mechanical stability and EMC behaviour in customer’s application is necessary.

Please note: Do not remove the plug with applied voltage of the power supply. This can lead to the
unspecified voltage levels on the driver with the risk of destruction.

5.2.2 Pin description

®
Table 5-1: Pin description SKiiP 3 V3 GB-Type
PIN Signal Function Specification
1 Shield
positive 15V CMOS logic;
Switching signal input for low side
2 BOT IN 10 kOhm impedance
IGBT
For more details see Chapter 5.2.4
LOW = NO ERROR; open collector output
3 ERROR OUT Error signal
For more details see Chapter 5.2.6
positive 15V CMOS logic;
Switching signal input for high side
4 TOP IN 10 kOhm impedance
IGBT
For more details see Chapter 5.2.4
LOW = NO ERROR; open collector output
5 Overtemp. OUT Overtemperature error
For more details see Chapter 5.2.6
6 13V… 30V
+ 24 VDC IN Wide range Power Supply
7 For more details see Chapter 5.2.3

8 50mA load
+ 15 VDC OUT 15V output for external components
9 For more details see Chapter 5.2.3

10
GND Power ground
11

Temp. ana OUT or Temperature signal out or For more details see Chapter 5.2.5 and
12
UDC ana OUT DC-Link voltage out data sheets SKiiP®3 V3, page 2

Reference for analogue output

13 GND aux
signals
For more details see Chapter 5.2.5 and
14 I ana OUT Current sensor out
data sheets SKiiP®3 V3, page 2

®
Table 5-2: Pin description SKiiP 3 V3 GD-Type
PIN Signal Function Specification
1 Shield
positive 15V CMOS logic;
Switching signal input for low side
2 BOT HB1 IN 10 kOhm impedance
IGBT phase U (half bridge1)
For more details see Chapter 5.2.4
LOW = NO ERROR; open collector output
3 ERROR HB1 OUT Error signal phase U (half bridge1)
For more details see Chapter 5.2.6
positive 15V CMOS logic;
Switching signal input for high side
4 TOP HB1 IN 10 kOhm impedance
IGBT phase U (half bridge1)
For more details see Chapter 5.2.4
positive 15V CMOS logic;
Switching signal input for low side
5 BOT HB2 IN 10 kOhm impedance
IGBT phase V (half bridge2)
For more details see Chapter 5.2.4
LOW = NO ERROR; open collector output
6 ERROR HB2 OUT Error signal phase V (half bridge2)
For more details see Chapter 5.2.6

Switching signal input for high side positive 15V CMOS logic;
7 TOP HB2 IN
IGBT phase V (half bridge2) 10 kOhm impedance

For more details see Chapter 5.2.4

positive 15V CMOS logic;
Switching signal input for low side
8 BOT HB3 IN 10 kOhm impedance
IGBT phase W (half bridge3)
For more details see Chapter 5.2.4
LOW = NO ERROR; open collector output
9 ERROR HB3 OUT Error signal phase W (half bridge 3)
For more details see Chapter 5.2.6
positive 15V CMOS logic;
Switching signal input for high side
10 TOP HB3 IN 10 kOhm impedance
IGBT phase W (half bridge 3)
For more details see Chapter 5.2.4
LOW = NO ERROR; open collector output
11 Overtemp. OUT Overtemperature error
For more details see Chapter 5.2.6
12 reserved
For more details see Chapter 5.2.5 and
13 UDC ana OUT DC-link voltage out ®
data sheets SKiiP 3 V3, page 2
14 13V… 30V
+ 24 VDC IN Wide range Power Supply
15 For more details see Chapter 5.2.3

16 50mA load
+ 15 VDC OUT 15V output for external components
17 For more details see Chapter 5.2.3

18 GND Power ground

19 GND Power ground
For more details see Chapter 5.2.5 and
20 Temp. ana OUT Temperature signal out ®
data sheets SKiiP 3 V3, page 2
Reference for analogue output
21 GND aux
signals
For more details see Chapter 5.2.5 and
22 I ana OUT HB1 Current sensor out phase U ®
data sheets SKiiP 3 V3, page 2
Reference for analogue output
23 GND aux
signals
For more details see Chapter 5.2.5 and
24 I ana OUT HB2 Current sensor out phase V ®
data sheets SKiiP 3 V3, page 2
Reference for analogue output
25 GND aux
signals
For more details see Chapter 5.2.5 and
26 I ana OUT HB3 Current sensor out phase W ®
data sheets SKiiP 3 V3, page 2

The Figure 5.5 left side shows the equivalent circuit diagram of the driver board GB-topology with ground
connections. The right side shows an application example for the controller side. The circuit diagramm for
the driver board GD type is analogue, just with separate switching signal inputs and error outputs for each
phase.

®
Figure 5.5: Overview schematics SKiiP 3 V3 interface, GB-Topology

SKiiP3 Driver interface Controller interface

External power supply
0V 24V

R≥300Ω

Capacitive
Chassis / PE grounding

+15V DC out
8,9
direct
shield
grounding
1

GND = power ground

DC 10,11
VS VS GND

DC GND +24 VDC IN

GND
6,7
Analogue output

Analogue input
Temp. ana OUT = Temp. signal

12
GND aux = Analogue ground
13

Analogue output
or optional:
GND

Analogue input
UDC ana OUT = DC-Link voltage
12
GND aux= Analogue ground
13

GND
Analogue output

GND

Analogue input
I ana OUT = Current signal
14
GND aux = Analogue ground
13

GND

GND
Digital input Digital output 15V

TOP IN = Switching signal TOP

ASIC
4

GND

Digital input GND GND

Digital output 15V
BOT IN = Switching signal BOT
ASIC
2

Vs
GND
GND GND
Rpull_up
ERROR out = error signal

3
Error
Detection
GND
Vs

GND Rpull_up
Overtemp out = overtemperature error

Error 5
Detection
GND

GND

5.2.3 External Power Supply

®
Table 5-3 shows the required features of an appropriate external power supply for a SKiiP 3 V3. All values
are related to one SKiiP. In case the gate driver is supplied with supply voltage >15V it is possible to use 15V
provided at the DIN 41651 connector of the gate driver as an external power supply, e.g. for a level shifter at
the controller’s output signals.
Table 5-3: Requirements to the external power supply
The maximum ratings for the supply voltage are given in the
®
SKiiP 3 V3 data sheet on page 1 (refer to symbol Vs). The
Unregulated 24V power supply ®
supply voltage is defined at the SKiiP 3 V3 input, not at the
controller output (consider voltage drop on connection cable)
IOUT 15V (can be used if VDCin >15V) <50mA
Maximum rise time of 24V <2 s
Rated current 1,5 times of the maximum driver input current
2 times of the maximum driver input current
Minimum peak current
(At least 1,5A)
Please note: Do not apply switching signals during power on reset.
The external power supply may not be turned-off for a short time as consequence of its current limitation. Its
output characteristic needs to be considered. Power supplies with fold-back characteristic or hiccup-mode
can create problems if insufficient over current margin is available. The voltage has to rise continuously and
without any plateau formation.
In order to ensure continuous operation and to have some margin in case of overload it is recommended to
choose the rated current of the external power supply 50% higher than the maximum driver input current
®
(see symbol Is on page 2 of the corresponding SKiiP 3 V3 datasheet). The rated peak current of the supply
must fulfill the specification in the Table 5-3.
If the power supply is able to provide a higher current, a peak current will flow in the first instant to charge up
the input capacitances on the driver. The peak current value will be limited only by the external power supply
and the effective impedances (e.g. distribution lines). It is recommended to avoid the paralleling of several
customer side external power supply units. Their different current limitations may lead to drops in the supply
voltage.
®
The formula given in the SKiiP 3 V3 datasheet for calculating the supply current IS (page 2) assumes supply
with 24V. The equation consists of three parts:
The first part, IS0, is the current consumption of the driver during Standby. No switching signals are applied.
Consequently, no AC-current flows. Example below: SKiiP2413GB123 (ISO=330mA)
The second part, k1*fsw, is the required current consumption of the driver in switching mode.
2
The third part, k2*IAC , is the current consumption required by the integrated current sensor to compensate
the actual value of the AC-current.
I S 0  k1  f sw  k2  I AC
2

Current consumption of integrated current sensor

Current consumption of driver in switching mode

Standby current consumption of the driver

5.2.4 Switching Signal Inputs

The switching signal inputs TOP IN for the TOP and BOT IN for the BOT IGBT have a digital positive / active
high logic (input HIGH = IGBT on; input LOW = IGBT off) characteristic.
For driving the inputs TOP IN and BOT IN it is mandatory to use line drivers that switch between 15V and
0V. Pull up and open collector output stages must not be used for driving these inputs.
Please note: A non connected input will be considered as LOW signal.

Figure 5.6: TOP/BOT PWM Signal Input GB-type

6,81kOhm TOP IN TOP PWM signal

ASIC from user controller board

3,32kOhm 68pF 1nF

GND GND GND

6,81kOhm BOT IN
BOT PWM signal
ASIC from user controller board

3,32kOhm 68pF 1nF

GND GND GND

Figure 5.7: TOP/BOT PWM Signal Input GD-type

6,81kOhm TOP IN TOP PWM signal

ASIC from user controller board

3,6kOhm 68pF 1nF

GND GND GND

6,81kOhm BOT IN
BOT PWM signal
ASIC from user controller board

3,6kOhm 68pF 1nF

GND GND GND

A 1nF capacitor is connected to the switching signal input to obtain high noise immunity. This capacitor can
cause a delay of few ns for current limited line drivers, which can be neglected.
The choice of a line driver according to the demanded length of the ribbon cable is recommended. It is
compulsory to use circuits which switch active to +15V and 0V. Pull up and open collector output stages
must not be used for TOP/BOT control signals.
Input resistance is about 10kOhm

As shown in Figure 5.8. the switching signal will be considered as:

 High when > VIT+
 Low when < VIT-

Figure 5.8: Threshold level for TOP IN and BOT IN

®
The threshold values VIT+ and VIT- are given in the SKiiP 3 V3 datasheet on page 2.
For VIT+ the value is given as minimum value that is at least necessary in order to switch on the IGBT.
For VIT- the value is given as maximum value that should not be exceeded in order to switch off the IGBT.
5.2.5 Analogue Output Signals
The schematic in the Figure 5.9 shows the analogue output circuit of the gate driver.
This circuit is part of:
- Measurement of AC-current
- Measurement of DC-link voltage
- Measurement of DCB-sensor temperature
Figure 5.9: Schematics analogue output signals

10kOhm

100pF

475Ohm
I ana out

1nF
GND aux

GND

The 475Ω resistor in series with the voltage follower avoids damages caused by a temporary short circuit at
the analogue output.

Please ensure that the maximum driven current by the output operational amplifier does not exceed 5mA.
A 1nF capacitor is used on the outputs to obtain high noise immunity.
On the user controller board a differential amplifier should be used which is connected to the analogue
output and the corresponding ground signal GND aux. This ensures accurate measurement of the analogue
signals because this line is not used for supply currents and no voltage drop due to supply current will be
caused.

A description for an equivalent analogue input circuit on the user controller board is given in Figure 5.10.
Figure 5.10: Application Example – Symmetric Wired differential Amplifier. Terminal description
of pins I ana out and GND aux for current measurement

+Vcc
User Controller Board

L1 +Vcc
I ana out R2 R2

+Vcc
C1 R4
PE R1
C1
GND aux -Vcc

R2 R2 C4
-Vcc
R3

R3
-Vcc
AGND AGND

The recommended values below have to be checked in the application.

 The input capacitance C1 should not be higher than 1nF for current measurement and 10nF for
temperature and voltage measurement to achieve stable operation of the amplifier circuit on the
®
SKiiP 3 V3 board. Its signal response has to be checked in combination with the used signal
cable.
 C1 leaks differential and common mode high-frequency interference currents. This capacitor
reduces the bandwidth of the analogue signal. This can lead to regulation problems like AC
current harmonics. Depending on application PE should be connected to an appropriate ground,
e.g. chassis ground.
 Resistor (R1). The interference sensitivity of the overall circuit (user control, driver) is reduced by
a continuous current flow through this resistor. Recommended value: 10kOhm

Please note: Capacitors should not be used in parallel to the feedback resistor (R3) and also to the
resistor of the non-inverting input to ground (R3). These capacitors have often high tolerances, so the
common-mode rejection of the circuitry is reduced by this effect. It should be no capacitor between the
plus- and the minus-pin of the operational amplifier as well. This additional cut off frequency can lead to
an oscillating signal.

 The input resistor (R2) should be splitted up and installed between the clamping-diodes. The
current in the diodes is limited by this resistor. A diode with a low reverse current should be
selected e.g. BAV99.
 To achieve a good noise performance a low-impedant feedback-resistor should be used (R3).
The value for the resistor must be chosen depending on the required gain factor.
 A low pass filtering should be implemented to avoid remaining differential interferences. It can be
realised by a simple R-C network (R4, C4) at the end of operational amplifier. The cut off
frequency of the filter should be adjusted with the behaviour of the operational amplifier used
and the necessary bandwidth of the analogue signal (Temp/DC-Link/Current).
 Rail-to-Rail amplifier is recommended for better performance. If not using Rail-to-Rail amplifier,
the pin -VCC must be connected to the negative voltage instead of ground in order to use the
complete voltage range of the amplifier especially close to 0V. The possible negative output
voltage of the amplifier has to be considered by designing the following circuit.
 AGND should be connected to the ground of the analogue signal processing at the user
controller board.

5.2.6 Error output

Characteristics and functionality:
 shows the status of the gate driver: enabled/disabled
 high active: HIGH = IGBT driver disabled, LOW = IGBT driver enabled (wire break monitoring)
 open collector output
The driver will turn off the open collector transistor to set the ERROR out signal to HIGH state over the pull-
up resistor Rpull_up by following errors:
o Undervoltage at low voltage side of the driver board (refer to chapter 5.3.6.1)
o Undervoltage at high voltage side of the driver board (refer to chapter 5.3.6.1)
o SKiiP internal short circuit of DC+ and DC- (refer to chapter 5.3.6.2)
o OCP Protection (refer to chapter 5.3.7.1)
o Exceeding maximum DCB temperature (refer to chapter 5.3.7.2)
o DC-link overvoltage (refer to chapter 0)
For information about failure management and error processing please refer to chapter 5.3.6, p.28.
®
The error output of SKiiP 3 V3 is short circuit proof. All logical error outputs are open collector transistors
with Vs=3,3-30V and Imax=15mA (see Figure 5.11). The external pull-up voltage should be set as high as
possible (not higher than VS). An external pull-up resistor to the controller logic high level in the range of
Vs/Imax< Rpull_up <10kOhm is required.
EXAMPLE: for Vs=15V the resistor should be in the range (15V/15mA) < Rpull_up <10kOhm, that is
1kOhm < Rpull_up < 10kOhm.
The external filter capasitor Cext is not compulsory but is recommended for noise immunity reasons. The
value in the range of a few nF should be chosen, because the RC-time constant must not exceed the
®
minimum error memory reset time tpRESET (given in the SKiiP 3 V3 data sheets, page 2).
Figure 5.11: SKiiP 3 Open Collector Error Transistor

SKiiP3 Vs
Driver
Board Rpull_up

Error
Detection Cext
1nF
User
Controller
Board

5.2.7 Ground connection

®
SKiiP 3 V3 has power ground and analogue ground. The ®
Table 5-4: Ground connections of SKiiP 3
power ground is used for power supply and reference of
V3
digital signals. The analogue ground is used for accurate
measuring of analogue signals. All grounds are Function Signal
physically connected to each other on the gate driver
board. Power ground and
GND
The analogue ground should be used for differential digital grounds
amplifier input on the controller board to ensure accurate Analogue ground GND aux
measurement (refer to Table 5-4).
For the GD-Type SKiiP3 it is recommended:
 do not use one analogue ground for more than 2 analogue signals
 always use the nearest analogue ground

5.2.8 Shield and protective earth/chassis connection

The shield pin 1 of the DIN41651 connector is connected to GND at the Gate Driver board. At the Gate
Driver board there is neither connection to heat sink nor other protective earth connections. On the user
controller board the shield should be connected to chassis which is protective earth in isolation class 1
systems. This single ended grounding is effective against capacitive coupling e.g. from neighbouring
conductors since the grounded shield forms the opposite pole of the parasitic capacitance. The shielded
internal conductor is in a Faraday cage. The interference current flows away via the shield. The GND of the
user controller board can be connected to protective earth/chassis either directly or via a capacitor. This
connection should be low inductive (e.g. metal bolts from PCB to chassis) and located close to the DIN41651
connector. Further each signal output and input should have a capacitor to chassis. These measures are for
bypassing burst signals.
Figure 5.12: Ground and shield connection. Principle schematics for switching signal
inputs

Driver Board DIN41651 Cable Shield

User Controller Board
Digital input stage Digital output stage

TOP IN, BOT IN

ASIC
GND

Shield direct or
capacitive grounding

GND GND
Chassis / PE

Figure 5.13: Ground and shield connection. Principle schematics for analogue output
signal (Example: Temperature output)

Driver Board User Controller Board

Analogue output stage DIN41651 Cable Shield
Analogue input stage

TEMP ana out

GND aux

AGND

AGND
Shield hard or
capacitive grounding

GND GND

Chassis / PE

5.3 Gate driver board

5.3.1 Overview
®
The SKiiP 3 V3 gate driver board includes following functions:
 Transferring digital input signals into powerful output signals to control the IGBT
 Power-on Reset (refer to chapter 5.3.2)
 Dead time generation (refer to chapter 5.3.3)
 Short pulse suppression (refer to chapter 5.3.4)
 Failure management (refer to chapter 5.3.6)
The gate voltages are +15V for turn on and -8V for turn off.
5.3.2 Power-On-Reset
The Power-On-Reset is completed after supply voltage will reach the level of 13V. It could take up to 150ms,
this time is defined as tPOR.
Please note: After open collector transistor of error output will be reset (typ. 8ms) no error will be
signalized during the remaining time of power on reset.To assure a high level of system safety the high
and low side signal inputs should stay in a defined state (OFF state) during driver turn-on time. Only after
the end of the power on reset, IGBT operation is permitted.

5.3.3 Interlock Dead Time Generation

®
The interlock dead time is defined as tTD in the SKiiP 3 V3 data sheet, page 2.
The dead time circuit prevents, that high and low side IGBT of one half bridge are switched on at the same
time. The internal interlock time is adapted to the power semiconductors, i.e. is chosen as small as possible
to allow high duty cycle but guarantees a safety margin against shoot through losses due to tail currents.
®
It is allowed to control the SKiiP 3 V3 by inverted pulses that means without controller dead time. tTD is not
added to a dead time given by the controller. Additionally the switching on/off time of the IGBT td(on/off)IO given
®
in the data sheet SKiiP 3 V3, page 3, has to be taken into account (see Figure 5.14).
Please note: In case both channel inputs TOP IN and BOT IN are at HIGH level, the driver outputs
VGETOP and VGEBOT will be turned off, but no error signal will be generated (see Figure 5.15).

5.3.4 Short pulse suppression

®
The short pulse suppression time is defined as tSIS in the SKiiP 3 V3 data sheet.
This function suppresses short turn-on and off pulses at the pins TOP IN and BOT IN of the DIN41651
interface. In this way the IGBT chips are protected against spurious noise which can occur due to bursts on
the signal lines. Since the switch on pulse is detected on one of the channels, the counter starts which
measures the duration of the pulse. If the overlaping is shorter than tSIS the pulse will be suppressed, the
other chanel remains on. No error will be indicated. The short pulse suppression time is included in the driver
®
switch on/off delay time td(on/off)IO given in the data sheet SKiiP 3 V3, page 3 (see Figure 5.14).
Please note: Noise pulses longer than tSIS generate additional switching losses (min. on-time of the diode
is > 3 µs) and must be considered during the junction temperature calculation in case of operation in
harsh EMI environment.

Figure 5.14: Short pulse suppression, tpulse<tsis

TOP IN
td(on/off) IO tSIS

t < tSIS

BOT IN

VGETOP

Interlock time tTD

VGEBOT

ERROR out

Figure 5.15: Short pulse suppression, tpulse>tsis

td(on/off) IO tSIS
TOP IN

t > tSIS

BOT IN

VGETOP

tTD
VGEBOT

ERROR out

5.3.5 Switching frequency rating

®
The maximal possible switching frequency for SKiiP 3 V3 is given in the data sheet, page 2. No error signal
®
will be set if the maximal allowed switching frequency for the particular SKiiP 3 V3 will be exceeded. It is the
customer responsbility to limit the frequency according to the data sheet maximal ratings.
®
The ambient temperature has also influence on the max. possible switching frequency of SKiiP 3 V3. In case
®
of higher ambient temperature the derating of the switching frequency must be considered (for al SKiiP 3 V3
types except of 4-fold GB-type). The derating diagrams for 2-fold and 3-fold GB-types as well as GD-type are
shown in the Figure 5.16, Figure 5.17 and Figure 5.18 correspondingly.
Please note: Exceeding of the max value ratings for the switching frequency from the
®
corresponding SKiiP 3 V3 data sheet can lead to the damage of SKiiP system and will result in
loss of warranty in case of product reclamation.
®
Figure 5.16: Derating diagram for 2-fold GB-Type SKiiP 3 V3

®
Figure 5.17: Derating diagram for 3-fold GB-Type SKiiP 3 V3

®
Figure 5.18: Derating diagram for GD-Type SKiiP 3 V3

5.3.6 Failure Management

In case of failure caused by

 Undervoltage primary side (refer to chapter 5.3.6.1)
 Undervoltage secondary side (refer to chapter 5.3.6.1)
 SKiiP internal Short Circuit (refer to chapter 5.3.6.2)
 Overcurrent protection error (refer to chapter 5.3.7.1)
 Exceeding maximum DCB-sensor temperature (refer to chapter 5.3.7.2)
 DC-link overvoltage (refer to chapter 0)
the driver will turn off the open collector transistor to set the ERROR out signal on the corresponding pins
®
(see Table 5-5 for GB-type and Table 5-6 for GD-type SKiiP 3 V3) to HIGH state (not ready to operate) for
the time error is present + at least error memory reset time. The IGBTs will be switched off and switching
pulses from the controller won´t be transferred to the output stage. If the error is not present anymore the
driver will check if the switching input signals TOP IN and BOT IN are both set to LOW for the tpRESET time
®
(refer to SKiiP 3 V3 data sheet, page 2). If this is the case the driver will release the ERROR out signal. If
both input signals have not been switched to LOW state during the tpRESET the driver will hold the open
collector transistor turned off (to set the ERROR out signal to HIGH) as long as the switching input signals
TOP IN and BOT IN are not LOW for tpRESET time (see Figure 5.19). So the switching input signals TOP IN
and BOT IN should be set to LOW after error message from driver has come and should not be activated
before the ERROR out signal is in LOW state again.

Figure 5.19: Processing of ERROR out signal

TOP IN
td(on/off) IO tSIS

Error
BOT IN occurs

Both TOP and BOT switching

signals must be LOW during
tpRESET to continue with
Error switching again when error is
VGETOP removed removed

VGEBOT

tpRESET

ERROR out

Table 5-5: Error management GB-type

Pin 3: ERROR out Pin 5: Overtemp. out

VCE-Protection x

OCP-Protection x

Overtemperature protection x x

DC-Link overvoltage protection x

Internal supply voltages error x

Table 5-6: Error management GD-type

Pin 3: Pin 6: Pin 9: Pin 11:
ERROR HB1 out ERROR HB2 out ERROR HB3 out Overtemp. out

VCE-Protection HB1 x

VCE-Protection HB2 x

VCE-Protection HB3 x

OCP-Protection HB1 x x x

OCP-Protection HB2 x x x

OCP-Protection HB3 x x x

Overtemperature x x x x
protection

DC-Link overvoltage x x x
protection

Internal supply voltages x x x

error

5.3.6.1 Under Voltage Protection (UVP) supply voltage

The Gate Driver board is equipped with a UVP of the supply voltage based on observing of the internal
voltage level. The UVP of the low voltage side monitors the internal voltage 15V DC which is provided by the
internal DC-DC converter (converts the unregulated input voltage to 15 V DC). Table 5-7 summarizes the trip
level.

Table 5-7: Signal characteristics of Under Voltage Protection primary

side
Signal Characteristics typ. value
Undervoltage protection trip level for internal
13,9V
regulated +15V
Undervoltage protection trip level for internal
-13,9V
regulated -15V
High voltage side protection level 10V
If the supply voltage of the driver board falls below the trip level, the IGBTs will be turned off (IGBT driving
signals set to LOW). The switching input signals TOP IN and BOT IN will be ignored and the error signal
ERROR out changes to the HIGH state. The system restarts after the error memory reset time, if the supply
voltage exceeds the threshold level and the TOP/BOT switching signals are LOW.

5.3.6.2 Dynamic Short Circuit Protection (DSCP)

The DSCP circuit is responsible for short circuit sensing in case of internal short circuit (“shoot through”
protection). It monitors the collector-emitter voltage VCE of the IGBT during its on-state. Due to the direct
measurement of VCEsat on the IGBT's collector, the DSCP circuit switches off the IGBTs and an error is
indicated if the VCEsat is too high.
Figure 5.20: Reference voltage (VCEref) characteristic

VCEref
VCEstat
5
VCE
VCEsat

0
t
turn on instant tbl

After tbl is over, the VCE monitoring will be triggered as soon as VCE > VCEref and will turn off the IGBT. The
switching input signals TOP IN and BOT IN will be ignored and the error signal ERROR out changes to the
HIGH state.
Figure 5.21: Turn on of IGBT Figure 5.22: Short circuit Figure 5.23: Short circuit
too slow* during operation during turn on
V V V

15 15 15

VCE

10 10 10
VCEref VCEref
VCEref
VCEstat VCEstat VCEstat
5 5 5
VCE VCE
VCEsat VCEsat VCEsat
0 0
0
t t
t turn on instant tbl turn on instant tbl
turn on instant tbl

* or adjusted blanking time too short

5.3.7 Analogue signals / sensor functionality

5.3.7.1 AC-Current sensor

Each half bridge module (refer to Figure 2.1) integrates one AC-current sensor. The measured current is
normalized to a corresponding voltage and is available at the DIN41651 interface with the characteristic
given below:
Table 5-8: Signal characteristic of current measurement
®
Signal Characteristics per SKiiP 3 V3 Value
Please see the corresponding data
Analogue current trip level ITRIPSC @ I ana out = 10V ®
sheet SKiiP 3 V3, page 2
Small signal bandwidth, f0Iana 50 kHz
1)
Signal Offset for low currents ± 5mV
The current sensor signal could be used for AC current control. In addition these sensors are used to protect
the SKiiP against over currents. The over current protection reacts independently to the temperature level
and provides a reliable protection of the SKiiP system. If the AC output current is higher than ITRIPSC (please
®
see corresponding data sheet SKiiP 3 V3 page 2 for exact value), the IGBTs are immediately switched off
and switching pulses from controller are ignored. The error signal ERROR out will be set in HIGH state.
®
In all SKiiP 3 V3 with Al2O3 ceramic substrate 100% of the rated DC current IC corresponds to 8V and the
over current trip level ITRIPSC is set to 125% IC, equivalent to 10V.
®
SKiiP 3 V3 systems with AlN ceramic substrate are from the electrical point of view similar to the same sized
Al2O3 substrate based systems but have a better thermal conductivity and therefore a higher rated DC-
current. As there is no difference of the driver boards for AlN and Al2O3 DCB regarding current normalization,
over current trip level and so on, both systems have the same relation between the absolute values of
current and corresponding voltage. Only the relation in percent to I c is different (please see corresponding
®
data sheet SKiiP 3 V3 page 2 for exact value).
Please note: Over current protection cannot protect the diodes from overload, because diode current
cannot be turned off. Please use the fuses to protect the diodes.

Current sensor working principle

The current transformers work according to the compensation principle. The magnetic field caused by the
load current is detected by a magnetic field sensor. This is not a Hall element but a small coil with a high
permeable core. Due to the properties of this sensing element there is low gain and linearity failure. An
electronic circuit evaluates the value of the field sensor and feeds a current into the compensation coil thus
keeping the effective magnetic field to zero. The compensation current is evaluated across a burden resistor
®
with an electronic circuit and gives an image of the load current. The SKiiP 3 V3 current sensor uses a
digital controller for the compensation current versus an analogue controller used in the SKiiP2 design.
®
Figure 5.24 illustrates the compensation principle with the current sensor of SKiiP 3 V3.
®
Figure 5.24: Compensation principle of SKiiP 3 V3 current
sensor

1) By calculation of accuracy for low currents this offset value cannot be neglected and has to be considered as
additional tolerance

®
The Table 5-9 gives an overview of the SKiiP 3 V3 current sensor:
®
Table 5-9: Characteristics of the SKiiP 3 V3 current sensor
®
Parameter SKiiP 3 V3
Continuous output current per current sensor 400 Arms
Short time output current, 2 s per current sensor 500 Arms
Peak current, 10 µs 3000 A
Parasitic capasitance prim. – sec. per current sensor 30 pF
The accuracy of the current sensor depends on several points as there are:
 tolerance of current sensor
 tolerance of burden resistor of current sensor
 tolerance of SKiiP 3 V3 internal amplification circuitry (e.g. by offset of operational amplifiers,
®

tolerances of external passive components etc.)

 tolerance due to temperature drift
1)
The maximum tolerance values can be calculated by the following equation :
ΔI=IC * 0,13% + I actual (1,37% + ΙΔTΙ * 0,002%/K), where:
 ΔI is the absolute deviation of the current value per half bridge
 Ic is the nominal current per half bridge
 Iactual is measured current level per half bridge at the moment
 ΔT is difference between Tamb and 25°C
®
Example: For a SKiiP 3 V3 GD-Type (SKiiP513GD172 with Ic = 500A) the deviation at the current level of
Iactual =300A and Tamb=85°C:
ΔI = 500A *0,13% +300A* (1,37% + Ι 85°C-25°C Ι*0,002%/°C) =5,12A
1)
By calculation of accuracy for low currents the offset value from Table 5-8 cannot be neglected and has to
be considered as additional tolerance

5.3.7.2 Integrated DCB-temperature sensor

The integrated DCB-temperature sensor is a chip resistor with PTC characteristic. The sensor is soldered
onto the ceramic substrate close to the IGBT and freewheeling diode chips and is isolated. An evaluation
circuit realized on the integrated driver provides a normalized, analogue voltage signal of the actual ceramic
substrate temperature value (see Figure 5.25). The analogue temperature signal is available at the
DIN41651 interface with the characteristic given below:
Table 5-10: Characteristics of the DCB-temperature sensor circuit
Temperature signal characteristics Value
Trip level Ttrip 115°C
Minimum measurable temperature TMIN +30°C
Analogue temperature signal TEMP ana out @ 115°C 10V
Analogue temperature signal TEMP ana out @ 30°C 1V
Accuracy of analogue signal @ Ttrip ±3%
Bandwidth, f0Tana 5Hz

Please note: The temperature sensor is designed for T r > 30°C, because the tolerance band is too wide
for temperatures below 30°C.

If the signal Temp ana out from temperature sensor reaches the trip level, the IGBT are switched off and
switching pulses from controller are ignored. The error signals ERROR out and Overtemp out will be set in
HIGH state.
The ceramic substrate temperature is very close to the heat sink temperature. The trip level of 115°C is
sufficient for most air cooled applications to protect the system, but for water cooled systems or short time
overloads the threshold might be too high. In this case another protection trip level is needed and the
customer can use the analogue temperature output to protect the system.

Please note:The ceramic substrate temperature is very close to the heat sink temperature, therefore it
®
can be used for check of the SEMISEL calculation: if the DCB-temperature value coming from SKiiP 3 V3
during the real operation is close to the heat sink temperature given in the results of SEMISEL
calculation, then the calculated chip temperature is also very close to the real chip temperature.

Figure 5.25: Characteristic between DCB-sensor temperature and the voltage at TEMP ana out

5.3.7.3 DC-Link-Voltage Sensing

® ®
Please note: The DC-link-voltage sensing is available for all GD-type SKiiP 3 V3. For GB-type SKiiP 3
V3 the DC-link-voltage sensing is available only on request instead of temperature measurement.
The DC-link-voltage (VDC) is sensed at DC plus and DC minus terminal by means of serial resistors and a
high impedance differential amplifier. The circuit is designed, manufactured and tested for safety isolation
according to standard EN50178. The normalized analogue DC-link voltage signal is available at the
DIN41651 interface with the characteristic given in Table 5-11. The analogue output signal UDC ana out is
filtered with a time constant of 500µs.

Table 5-11: VDC characteristics

VDC signal characteristics 1200V System 1700V System
Analogue DC-link voltage signal UDC ana out @ 900 V 9V 6,5V
Analogue DC-link voltage signal UDC ana out @ 1170 V 9V
Accuracy of analogue signal @ VDCtrip over full temperature range ±2,5%
Bandwidth, f0Uana 320Hz
®
The DC-Link overvoltage protection is implemented for GD-types SKiiP 3 V3 and optional for some
customized GB-types. In case the DC-Link overvoltage protection is implemented if the operating DC-Link
®
voltage is higher than VDCtrip given in the corresponding data sheet SKiiP 3 V3 page 2, the IGBTs are
immediately switched off and switching pulses from controller are ignored. The error signal ERROR out will
be set in HIGH state.

6. Power terminals
®
The power terminals of the SKiiP 3 V3 are robust against external forces which may be caused by the
connection of the DC-link and load cables. Nevertheless, the SKiiP module is NOT MEANT to support the
DC link. The mechanical support must also be provided for the AC connection (e.g. inductor or motor cables)
in order to protect the power terminals from mechanical forces and vibration stress. The maximum forces
that must not be exceeded are given in Table 6-1.

Table 6-1: Maximum allowed forces to

terminals
Force Maximum allowed force [N]
F+x/ F-x <100
F+y/ F-y <100
F+z <100
F-z <200

The following should be considered in the design process:

 DC connection:
o Mechanical tolerances, especially when larger DC-links are used which are connected on
more than one SKiiP
 Thermal expansion:
o The DC-link is heated up under load and expands. This causes mechanical forces on the
terminals.
 Stiffness of terminals for DC connection:
o The connections should be soft in order to minimize the mechanical forces. This can be
realized e.g. by using of tempered copper.
 Terminal hole diameter:
o Should be large enough that the screw fits through the hole into the SKiiP connection.
 Dimensions of the DC connections:
o Considering the heating and isolation. The terminals must not heat up snubber capacitors.
Recommended AC connection:
 Symmetrical AC connections for symmetrical current sharing between the paralleled half bridge
modules. The load cable should be connected in the middle of the AC terminal and have equal
distance to the each half bridge module.
 Connect a plate (e.g. copper) on all AC terminals of one SKiiP
 Cables can be connected on the same plate but it has to make sure that the cables do not apply
force on the terminals (pull or push). Therefore flexible cables with stress relief should be used.
 The plate should be fixed by fixing poles. These poles shall be mounted directly on to the heat sink
or a fixed frame construction and placed close to the SKiiP device.

7. Application hints

7.1 Verification of design

Measurements and calculations have to be carried out to be sure that the design works reliable. The
following points have to be considered:
 Recommended IGBT and diode junction temperatures must not be exceeded also considering
overload conditions
 Maximum blocking voltage VCES/VRRM must not be exceeded in any case (normal conditions, short
circuit)
 Load current of snubber capacitors
 Current sharing between paralleled half bridge modules
 Environmental temperature of driver board which affects the lifetime of the driver board electronics
 Load and temperature cycles which affect the lifetime of the power section
 Environmental conditions during operation, transport and storage
 EMC design
 Mechanical design
Besides these general points application specific conditions and requirements may be considered too.

7.2 Definition of Thermal Resistance

®
The definition of the thermal resistances given in the SKiiP 3 V3 datasheet are shown in the Figure 7.1.
Figure 7.1: Definition of thermal resistances

Tj junction temperature of the hottest chip

Tsensor DCB-sensor temperature
Tsink heat sink temperature in a drill hole 2mm underneath the chip
Ta ambient temperature (coolant air or liquid)
Rth(j-r) thermal resistance between junction and temperature sensor
Rth(j-s) thermal resistance between junction and heat sink
Rth(s-a) thermal resistance between heat sink and ambient (coolant air or liquid)
Rth(r-a) thermal resistance between temperature sensor and ambient (coolant air or liquid)
Plosses Power losses of the chip

In general, the thermal resistance between two points 1 and 2 is defined according to following equation:

T12 T1  T2
Rth (1 2)  
Plosses Plosses
The data sheet values Rth(j-s), Rth(r-a) and Rth(j-r) for the thermal resistance are calculated from measured
values. The point of the temperature measurement has a major influence on the thermal resistance because
of a temperature profile between the different chip positions and across the heatsink surface.
®
The reference points for SKiiP 3 V3 modules are: virtual junction temperature of the hottest chip (T j); heat
sink temperature underneath the hottest chip (T sink) and DCB-sensor temperature (Tsensor). A principle sketch
with the positions is shown in Figure 7.1. The junction temperature Tj can be calculated by using the thermal
resistors Rth(j-r) and Rth(r-a). SKiiP modules have no base plate, therefore the case temperature T C can not be
measured without disturbance of the thermal system and the thermal resistance R th(j-c) cannot be given.
®
To simplify the comparison to the other semiconductor modules SKiiP 3 V3 data sheets also contain th
thermal resistance between chip junction and heat sink Rth(j-s). TSink is measured in a drill hole 2mm
underneath the heatsink surface. The 2 mm distance guaranties a low disturbance of the thermal path and a
minimum effect of heat sink parameters like size, thermal conductivity, cooling medium etc.
The temperature sensor is located close to the DCB-edge on the separate DBC copper layer. This makes
the temperature difference between junction and sensor higher and between sensor and ambient lower in
comparisson to SKiiP4.
Only one of the temperature sensors is monitored by the Gate driver. The monitored sensor is in the middle
of the SKiiP (refer to Figure 7.2). The protection level is matched to the maximum operation temperature of
the power semiconductors.
During operation there will be a temperature profile along the heatsink from cool at the inlet of the coolant to
warm at the outlet.
®
Figure 7.2: Sensor position in SKiiP 3 GB- and GD-Type (2fold, 4fold, 3fold) with proposed cooling
(water inlet) direction
1 2 3 4 1 2 3
AC AC AC AC AC AC AC

DC DC DC DC DC DC DC

SKiiP SKiiP
®
SKiiP 3 V3 are equipped with high performance heat sinks. The data sheets contain transient thermal data
referenced to the built-in temperature sensor. This allows the calculation of junction temperature Tj, if the
generated losses are known. The thermal resistances given in the data sheets represent worst case values.
Evaluation of thermal impedance:
 Junction to sensor
-t/Ƭn
Zth(j-r) =Ʃ Rth(j-r)n * (1-e ), n=1,2,3,….
 Sensor to ambient
 Zth(r-a) =Ʃ Rth(r-a)n * (1-e
-t/Ƭn
), n=1,2,3,….
Please note: The values for transient thermal impedance given in the data sheets (Zth(j-r)) are only
valid together with the SEMIKRON standard heat sinks and under conditions given in the data
sheets. The usage of these values for other heat sinks/conditions might cause deviations in
calculation of thermal resistance!

7.3 Maximum blocking voltage and snubber capacitors

®
The maximum blocking voltage VCES/VRRM which is given in the SKiiP 3 V3 datasheet must not be exceeded.
It must also be considered that IGBT switches faster if the junction temperature is low. The first
countermeasure is a low inductive DC-link design to keep the overvoltage on the semiconductor low. In
addition, snubber capacitors are recommended, which should be mounted directly on the DC-link terminals
of each half bridge module. Application note AN-7006 “Peak voltage measurement and snubber capacitor
specification” provides information how to perform the tests and to select the snubber capacitors. The
®
following snubber capacitors are recommended for SKiiP 3 V3. But nevertheless it has to be validated by
testing that the capacitors are compatible with the design and will not be overloaded.
®
Table 7-1: Snubber capacitors for SKiiP 3 V3
Capacitance / DC voltage For use with
470 nF / 1000V 1200V device
220 nF / 1250V 1700V device

7.4 Isolation voltage test (IVT)

During production test the isolation voltage of 5600Vdc (1700V devices) or 4300Vdc (1200V devices), DC,
each polarity, is applied to the 100% of SKiiP-systems for 1s with test set up shown in the Figure 7.3 These
values are also available in the corresponding datasheets.
Figure 7.3: Graphic presentation of the electrical connections by the IVT procedure

The polarity change (whereby heat sink is always grounded) is only possible if the customer uses a
galvanically isolated test control device. Otherwise the plus and minus pole of the isolation test control
device will be shorted.

Please note: Because of the safety measures during and after the test procedure the heat sink
should be grounded: if the DUT fails with an arcing and if the test control device recognizes it and
disconnects from the DUT, it is possible the DUT is still electrically charged. In this case it would be
dangerous to touch the DUT after the test procedure. In addition to this without grounding the test
voltage could drift and the voltage to ground will be even higher than the nominal test voltage.

All isolation voltage tests must be performed at an ambient temperature of 15…35°C, a relative humidity of
45…75% and an atmospheric pressure of 860…1060 hPa. The norms define no certain leakage current
value, thus the isolation test (dielectric test) is considered passed if no electrical breakdown has occurred,
i.e. small leakage currents that occur are irrelevant.
There are two forms of an isolation damage:
1. Fully breakdown (according the norms)
2. High leakage current (not according the norms!)

According to the corresponding norms it is required to do an IVT with AC voltage. Despite of this the IVT with
DC voltage is recommended because in case of AC IVT the high leakage currents lead to the uncertain
identification of the isolation problems.
It is recommended to ramp up the isolation voltage with 10kV/s. Faster ramp up leads to capacitive leakage
currents and could cause the faulty activation of the isolation test control unit. Slower ramp up leads to the
longer testing time. The count of the test time 1s, specified in the data sheet, begins after ramp up of the full
isolation voltage. The isolation voltage could be switched off without a ramp down. After finishing the test it
must be checked that the DUT is not charged anymore.
Please note: The isolation test voltage should not be greater than necessary for the application
and the corresponding standards.
The isolation measurement is performed in two steps:
1. high voltage isolation test
2. repeated isolation test
The high-voltage isolation test and repeated test of an isolation barrier can degrade isolation capability due
to partial discharge. During the IVT since the isolation voltage is applied the partial discharge starts after the
voltage goes beyond the partial discharge inception voltage. The higher and the longer the voltage value is
applied, the stronger the damage of the isolation through the partial discharge will be. Thus each IVT leads
to the weakening of the isolation. The partial discharge in the DCB doesn’t lead to the weakening of the
isolation, because the ceramic is resistant to the partial discharge. First of all the organic materials (plastic),
e.g. circuit boards and compound of transducers, will be damaged.
Since every isolation test may cause premature damage to the module as a result of partial discharge, the
number of tests should be kept low. If they can not be avoided, however, a regeneration time of at least 10
minutes must be complied with between 2 tests and the repeated isolation voltage tests should be performed
with reduced voltage. The test voltage must be reduced by 20% for each repeated test.
Please note: The F-option must be removed during the IVT (mounting instruction on request).
Then the normal test procedure as above described should be done.

7.5 Current sharing between paralleled half bridge modules

When the IGBT is switched on the current is commutated over the paralleled IGBT half bridge modules. The
busbar design has to be symmetrical to make sure that the current sharing is equal. Unequal current sharing
can overload single
half bridge modules and leads to imbalance during switching off which can finally destroy the power section.
Symmetrical AC and DC-link design leads to equal stray inductances between the half bridge modules which
ensures equal commutation and current sharing. Each half bridge module has to have the same stray
inductance to the DC-link capacitors.
The current sharing should be measured in the design phase by “double pulse testing” (see AN-7006) and in
the final design under real operation conditions. This can be done e.g. by Rogowski current sensors which
are located around the DC+ and DC-terminals.

7.6 Recommended temperature rating

Please note: The compliance of temperature characteristics recommended in this chapter are
®
extremely important for the SKiiP 3 V3 reliability and therefore for the long life time of the product.

The failure rate describes the probability of a failure within a certain time. Usually, the failure rate follows the
so-called bathtub curve, shown in Figure 7.4: high in the beginning (failures known as early failures), then
dropping to a low and more or less constant value (the random failures) before it rises again as wear-out
begins to set in and end-of-life failures set a limit to the useful life of a component.

Figure 7.4: Probability of a failure during operation time.

The evaluation of the failure rate for different temperatures shows that its expected failure rate roughly
doubles for a 20 C increase in operating temperature (see Figure 7.5).
Figure 7.5: SKiiP driver failure rate temperature dependence calculated according to SN29500

The less stress a device is subjected to, the less likely it is to fail. Low operation time, low current, low
temperature and low dc-link voltage prolong its life and reduce the failure rate. Therefore, the design has to
find a working compromise between exhausting a device to maximum capacity and obtaining an acceptable
failure rate and life time.
®
The following temperature rating is recommended for the SKiiP 3 V3 systems:
1. Power section: It is necessary to make sure by calculations and measurements that the
recommended IGBT and diode junction temperatures are not exceeded also considering overload
conditions. The recommended maximum junction temperatures are 125°C which is 25°C lower than
the maximum temperature of 150°C. That is to ensure the reliable operation. Calculations can be
carried out by the SEMIKRON simulation tool SEMISEL which is available on the SEMIKRON
homepage www.semikron.com. Load cycles and cooling conditions can be adapted to meet the

application conditions. Measurement of the DCB-sensor temperature (available on the driver

connector as analogue voltage signal) has to be carried out to check that the system works as
®
calculated: if the DCB-temperature value coming from SKiiP 3 V3 during the real operation is close
to the heat sink temperature given in the results of SEMISEL calculation, then the calculated chip
temperature is also very close to the real chip temperature.
2. Gate driver: Although it is fit for operation at 85 C, it is recommended that the average ambient
temperature for the driver board does not exceed 40 C for extended periods of time. For achieving
the lower driver temperature the additional air forced cooling for the driver might be necessary.

7.7 Paralleling of SKiiP®3 V3

For parallel operation the following features are necessary to realize:

®
common error management for all paralleled SKiiP 3 V3
 monitoring of analog signals, e.g. temperature or current
 one power supply should be used for all subsystems
 decoupling reactors
® ®
The easiest way to make the paralleling of SKiiP 3 V3 is to use the Parallel Board SKiiP 3 V3, where all
these points, except of decoupling reactors, are successfully implemented und qualified. For further
® ®
information about Parallel Board SKiiP 3 V3 see Technical Explanation SKiiP 3 Parallel Board.
By using paralleled SKiiPs it has to be made sure that no SKiiP will be overloaded. To ensure this
inhomogeneous current has to be limited. This inhomogeneous current is caused by different output voltages
of the paralleled inverters which could be a consequence of:
 different propagation time of driver boards
 different switching times of power semiconductors
 tolerance of forward voltage drop of IGBT and diodes
 different DC link voltage levels
 different cooling conditions of paralleled half bridges (e.g. in air cooled applications with thermal
stacking)
 different external impedance
To minimize these effects the system designer has to make sure, that there is sufficient inductance between
the AC output terminals of the paralleled SKiiP subsystems. The impedance has two tasks:
 On the one hand it should prevent the divergence of the current during the switching moment. That
could lead to dynamic overload, respectively to oscillations. This is shown in Figure 7.6. The value
®
tjitter is given in the SKiiP 3 V3 data sheet, page 2.
Figure 7.6: Effects of paralleling SKiiP®3 V3

 On the other hand a different root mean square value of the output current should be avoided.
Symmetric effects come from the inductivities (AC choke) and the ohmic resistors (choke resistor,
wiring resistor and path resistance) as shown in Figure 7.7.

Figure 7.7: Schematic Circuit Diagram

Inverter 1 Iout1 Iout2
Iout
Z1

Iout1

Load
Inverter 2
Iout t
Z2

Iout2

The low inductive parallel connection of the AC-terminals can be achieved by an additional flexible cross
connector directly mounted on the SKiiP AC terminals (see Figure 7.8). Please note that the current rating of
this bar must not be very high, because there is no load current flowing in this bar. There are only high
frequency currents flowing. Thus the flexibility can be achieved by using a comparatively thin material.
Figure 7.8: Example of AC cross connector

Tolerance of forward voltage drop of IGBT or diodes

The IGBTs used in the SKiiPs have a positive temperature coefficient. The free wheeling diodes are
produced with a small forward voltage range. Both limit the inhomogeneous current distribution. No further
selection of forward voltage groups is necessary.
Different DC link voltage levels
To avoid different output voltages caused by different DC link voltages levels, the DC link should be
connected in parallel. It has to be avoided that oscillations between the capacitor banks occur. For large
systems fuses between the capacitor banks are recommended. The paralleled systems should have the
same DC link with the same capacitor type and capacitor values.
Different cooling conditions of paralleled half bridges
The cooling system of the paralleled SKiiP units should be designed in way to avoid thermal stacking.
In spite of all the mentioned actions it has to be taken into account that for in-homogenous current sharing a
de-rating of the nominal current of the power section has to be considered.

7.8 Prevention of condensation

Condensation during operation must be prevented. This can be ensured by regulation of the air or water flow
so that the heat sink temperature is always above the environmental temperature. The use of chilled coolant
is therefore not recommended. Condensation may occur because of night/day temperature change as well.
If the power electronic equipment was exposed to humidity or moisture during transport and storage, it
should be dried before commissioning. This can be done by air heater in air cooled systems or by pre-heated
water in water cooled systems.

8. Logistics

8.1 Label
®
For reasons of traceability all SKiiP 3 V3 modules are marked with a system, halfbridge, driver shuttle and a
warranty label.
8.1.1 System Label
The system label of SKiiP (Figure 8.1) is the label which contains all information necessary for customers. In
case of technical inquiries please always name the SKiiP Item number written on this label.
®
Figure 8.1: System Label of SKiiP 3 V3

8.1.2 Half bridge Laser Label

®
Figure 8.2: Half bridge label of SKiiP 3 V3

8.1.3 Warranty Label

The warranty label is presented in the Figure 8.3. The position of the warranty label could be found in the
corresponding data sheet.
®
Figure 8.3: Warranty Label of SKiiP 3
V3

Please note: Removing the warranty label will result in loss of warranty in case of product reclamation

8.1.4 Data Matrix Code

The Data Matrix Code is described as follows
 Cell size: 0,3mm
 Read distance: 60 – 100mm
 Max. angle of 30° (vertical reference line) for reading
®
Figure 8.4: Data Matrix Code of SKiiP 3 V3
20XXXXXX01_0911DE12345601_001_ABCDEFGHIJ

10 digits free for customer information

3 digits continuously module number
2 digits additionally order number
12 digits order number
2 digits
8 digits SKiiP item number

List of figures:
®
Figure 2.1: 4-fold SKiiP 3 V3 ................................................................................................................................. 4
Figure 2.2: Half bridge definition ............................................................................................................................ 4
Figure 2.3: Half bridge “explosion picture” ............................................................................................................. 5
®
Figure 4.3: Implementation of additional basic isolation between SKiiP 3 V3 driver interface and controller
board............................................................................................................................................................. 11
Figure 5.1: Gate Driver Board block diagram ...................................................................................................... 13
Figure 5.2: Gate Driver Interface ......................................................................................................................... 14
®
Figure 5.3: SKiiP 3 V3-connector DIN41651, GB Type, male plug, vertical, top view ....................................... 14
®
Figure 5.4: SKiiP 3 V3-connector DIN41651, GD Type, male plug, vertical, top view ....................................... 15
®
Figure 5.5: Overview schematics SKiiP 3 V3 interface, GB-Topology ............................................................... 18
Figure 5.6: TOP/BOT PWM Signal Input GB-type............................................................................................... 20
Figure 5.7: TOP/BOT PWM Signal Input GD-type .............................................................................................. 20
Figure 5.9: Schematics analogue output signals ................................................................................................. 21
Figure 5.10: Application Example – Symmetric Wired differential Amplifier. Terminal description of pins I ana
out and GND aux for current measurement ................................................................................................. 22
Figure 5.11: SKiiP 3 Open Collector Error Transistor.......................................................................................... 23
Figure 5.12: Ground and shield connection. Principle schematics for switching signal inputs ........................... 24
Figure 5.13: Ground and shield connection. Principle schematics for analogue output signal (Example:
Temperature output) ..................................................................................................................................... 24
Figure 5.14: Short pulse suppression, tpulse<tsis .................................................................................................. 26
Figure 5.15: Short pulse suppression, tpulse>tsis .................................................................................................. 26
®
Figure 5.16: Derating diagram for 2-fold GB-Type SKiiP 3 V3 ........................................................................... 27
®
Figure 5.17: Derating diagram for 3-fold GB-Type SKiiP 3 V3 ........................................................................... 27
®
Figure 5.18: Derating diagram for GD-Type SKiiP 3 V3 ..................................................................................... 28
Figure 5.19: Processing of ERROR out signal ................................................................................................... 29
Figure 5.20: Reference voltage (VCEref) characteristic ......................................................................................... 31
Figure 5.21: Turn on of IGBT too slow* .............................................................................................................. 31
Figure 5.22: Short circuit during operation ......................................................................................................... 31
Figure 5.23: Short circuit during turn on ............................................................................................................. 31
®
Figure 5.24: Compensation principle of SKiiP 3 V3 current sensor .................................................................... 32
Figure 5.25: Characteristic between DCB-sensor temperature and the voltage at TEMP ana out ..................... 34
Figure 7.1: Definition of thermal resistances ....................................................................................................... 36
®
Figure 7.2: Sensor position in SKiiP 3 GB- and GD-Type (2fold, 4fold, 3fold) with proposed cooling (water
inlet) direction ............................................................................................................................................... 37
Figure 7.3: Graphic presentation of the electrical connections by the IVT procedure ......................................... 38
Figure 7.4: Probability of a failure during operation time. .................................................................................... 40
Figure 7.5: SKiiP driver failure rate temperature dependence calculated according to SN29500 ...................... 40
®
Figure 7.6: Effects of paralleling SKiiP 3 V3 ....................................................................................................... 41
Figure 7.7: Schematic Circuit Diagram ................................................................................................................ 42
Figure 7.8: Example of AC cross connector ........................................................................................................ 42
®
Figure 8.1: System Label of SKiiP 3 V3 .............................................................................................................. 44
®
Figure 8.2: Half bridge label of SKiiP 3 V3.......................................................................................................... 44

List of tables:
®
Table 3-1: SKiiP 3 V3 standard product range ..................................................................................................... 7
®
Table 4-1: SKiiP 3 V3 Tests for qualification and re-qualification ......................................................................... 9
®
Table 4-2: SKiiP 3 V3 Electromagnetic compatibility ........................................................................................... 9
®
Table 4-3: Isolation limits SKiiP 3 V3 .................................................................................................................. 10
®
Table 5-1: Pin description SKiiP 3 V3 GB-Type ................................................................................................. 16
®
Table 5-2: Pin description SKiiP 3 V3 GD-Type ................................................................................................. 16
Table 5-3: Requirements to the external power supply ....................................................................................... 19
®
Table 5-4: Ground connections of SKiiP 3 V3 .................................................................................................... 24
Table 5-5: Error management GB-type ............................................................................................................... 29
Table 5-6: Error management GD-type ............................................................................................................... 30
Table 5-7: Signal characteristics of Under Voltage Protection primary side ....................................................... 30
Table 5-8: Signal characteristic of current measurement .................................................................................... 32
®
Table 5-9: Characteristics of the SKiiP 3 V3 current sensor............................................................................... 33

Table 5-10: Characteristics of the DCB-temperature sensor circuit ..................................................................... 33

Table 5-11: VDC characteristics............................................................................................................................. 34
Table 6-1: Maximum allowed forces to terminals ................................................................................................. 35
®
Table 7-1: Snubber capacitors for SKiiP 3 V3 ..................................................................................................... 38

Abbreviations

Abbreviation Meaning
CTE Coefficient of Thermal Expansion
DBC Direct bonded copper
D-Sub D-Subminiature
EMC Electromagnetic compatibility
GB halfbridge configuration
GND Ground
IGBT Insulated Gate Bipolar Transistor
IPM Intelligent Power Module
PCB Printed Circuit Board
PTC Positive Temperature Coefficent
RH Relative Humidity
RoHS Restriction of Hazardous Substances
SCP Short Circuit Protection
SKiiP Semikron intelligent integrated Power
SPS Short Pulse Suppression
UVP Under Voltage Protection

Symbols and Terms

Letter Symbol Term

ICnom Nominal collector current of IGBT
IFnom Nominal forward current of diode
Idigiout Digital output sink current (HALT-signal)
QPD Charge of the Partial Discharge event
RCC´+EE´ Resistance of the interconnections between terminals and die
Rth Thermal resistance
tpReset(OCP) Overcurrent reset time
tjitter Jitter clock time
tSIS Short pulse suppression time
tbl Blanking time
tPOR Power-On Reset time
Ta Ambient temperature
Tj Junction temperature
Tr Temperature at reference position
ULE Line to earth voltage
ULL Line to line voltage
VCEstat Collector-Emitter Threshold Static Monitoring Voltage
Vit+ HALT Input threshold voltage HALT-signal (HIGH)
Vit- HALT Input threshold voltage HALT-signal (LOW)
TDriverTrip Over temperature trip level
f0Uana Bandwidth of DC-voltage measurement @ VDCtrip
f0Iana Bandwidth of current measurement @ ITRIPSC
f0Tana Bandwidth of temperature measurement @ T trip

A detailled explanation of the terms and symbols can be found in the "Application Manual Power
Semiconductors" [2]

References
[1] www.SEMIKRON.com
[2] A. Wintrich, U. Nicolai, W. Tursky, T. Reimann, “Application Manual Power Semiconductors”,
ISLE Verlag 2011, ISBN 978-3-938843-666

HISTORY
SEMIKRON reserves the right to make changes without further notice herein

2.0 Technical documentation revised

3.0 Update Table 4.4 and Chapter 6

DISCLAIMER
SEMIKRON reserves the right to make changes without further notice herein to improve reliability, function
or design. Information furnished in this document is believed to be accurate and reliable. However, no
representation or warranty is given and no liability is assumed with respect to the accuracy or use of such
information, including without limitation, warranties of non-infringement of intellectual property rights of any
third party. SEMIKRON does not assume any liability arising out of the application or use of any product or
circuit described herein. Furthermore, this technical information may not be considered as an assurance of
component characteristics. No warranty or guarantee expressed or implied is made regarding delivery,
performance or suitability. This document supersedes and replaces all information previously supplied and
may be superseded by updates without further notice.

SEMIKRON products are not authorized for use in life support appliances and systems without the express
written approval by SEMIKRON.

SEMIKRON INTERNATIONAL GmbH

P.O. Box 820251 • 90253 Nuremberg • Germany
Tel: +49 911-65 59-234 • Fax: +49 911-65 59-262
[email protected] • www.semikron.com

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