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ELL782: Computer Architecture

This document provides information about the computer architecture course ELL782 at IIT Delhi. It lists the schedule, credits, required and reference textbooks, and papers. It describes the requirements for a mini project involving both theoretical and programming work. Students will be evaluated through minor exams, a mini project, major exam, and attendance. The proposed course outline covers quantitative design and analysis, instruction-level parallelism through pipelining, memory hierarchy and caching, thread and data parallelism, and various modern architectures.

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SIYAB Khan
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86 views

ELL782: Computer Architecture

This document provides information about the computer architecture course ELL782 at IIT Delhi. It lists the schedule, credits, required and reference textbooks, and papers. It describes the requirements for a mini project involving both theoretical and programming work. Students will be evaluated through minor exams, a mini project, major exam, and attendance. The proposed course outline covers quantitative design and analysis, instruction-level parallelism through pipelining, memory hierarchy and caching, thread and data parallelism, and various modern architectures.

Uploaded by

SIYAB Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Architecture-1

ELL782: Computer Architecture


http://www.cse.iitd.ac.in/∼sumantra/courses/arch/arch.html

General Information
No one shall be permitted to audit the course. People are welcome to sit through it,
however. The course is open to all suitably inclined Masters and Doctoral students.
Schedule for classes: [Slot A] Credits: 3 (LTP: 3-0-0)
Mon: 08:00 - 09:30, Thu: 08:00 - 09:30 Room: III-336
Textbook:
• J. L. Hennessey, D. A. Patterson. Computer Architecture: A Quantitative Ap-
proach. Fifth Edition, Elsevier, 2012.
Reference Books:
• D. A. Patterson, J. L. Hennessey. Computer Organization and Design: The
Hardware/Software Interface. Third Edition, Elsevier, 2005.
• J. P. Hayes. Computer Architecture and Organization. Third Edition, WCB/McGraw-
Hill, 1998.
• K. Hwang, F. A. Briggs. Computer Architecture and Parallel Processing. McGraw-
Hill, 1985.
• M. M. Mano. Computer System Architecture. Third Edition, PHI, 1993.
• P. Kogge. Architecture of Pipelined Computers. McGraw-Hill, 1977.
• W. Stallings. Computer Organization and Architecture. Macmillan Publishing
Company, 1986.
• W. Stallings. Computer Organization Architecture: Designing for Performance.
Sixth Edition, Pearson Education, 2003.
• K. Hwang. Advanced Computer Architecture: Parallelism, Scalability, Pro-
grammability. McGraw-Hill, 1993.
• J. D. Carpinelli. Computer Systems Organization & Architecture. Pearson Ed-
ucation Asia, 2001.
• W. Stallings. Reduced Instruction Set Computers. Second Edition, IEEE Com-
puter Society Press, 1990.
• B. Govindarajalu. Computer Architecture and Organization: Design Principles
and Applications. Tata McGraw-Hill, 2004.
• H. S. Stone. (Ed.) Introduction to Computer Architecture. Second Edition,
Galgotia Publications Pvt. Ltd., 1990.
• V. Kumar, A. Grama, A. Gupta, G. Karypis. Introduction to Parallel Comput-
ing. The Benjamin/Cummins Publishing Company, Inc., 1994.
• D. P. Bertsekas, J. N. Tsitsiklis. Parallel and Distributed Computation. Prentice-
Hall International, Inc., 1989.
• C. Hamacher, Z. Vranesic, S. Zaky. Computer Organization. Fifth Edition,
McGraw-Hill, 2002.
• A. S. Tanenbaum. Structured Computer Organization. Fourth Edition, Pearson
Education, 1999.
Papers:
• D. A. Patterson. Reduced Instruction Set Computers. Communications of the
ACM, vol. 28, no. 1, January 1985, pp. 8 – 21.
The above list is (obviously!) not exhaustive. Other reference material will be
announced in the class. The Web has a vast storehouse of tutorial material on
Computer Architecture, and other related areas.
Sumantra Dutta Roy, EE, IITD [email protected]
Computer Architecture-2

Mini Project . . . A combination of theoretical work as well as programming work.


Both will be scrutinized in detail for original work and thoroughness. For the program-
ming part, there will be credit for good coding. Sphagetti coding will be penalized.
Program correctness or good programming alone will not fetch you full credit . . . also
required are results of extensive experimentation with varying various program pa-
rameters, and explaining the results thus obtained. The Mini Project will have to be
submitted on or before the due date and time. Late submissions will not be considered
at all. Unfair means will be result in assigning as marks, the number said to have been
discovered by the ancient Indians, to both parties (un)concerned.
Examinations and Grading Information:
Minor I: 28 Minor II: 28 Mini Project: 16 Major: 28
Attendance Requirements: As per Institute rules. Illness policy: illness to be
certified by the IITD Hospital. Attendance in Examinations is Compulsory.

Proposed Course Outline


1. Quantitative design and analysis; Instruction set samples
2. Instruction-level parallelism; Theory of Pipelining
3. Memory hierarchy design; Cache; Virtual Memory
4. Thread-Level Parallelism
5. Data-Level Parallelism in Vector, SIMD, GPU Architectures
6. Warehouse Scale Comuters; Blade Architecture; Interconnected
Networks
7. Miscellaneous Topics: Hardware and Software for VLIW and
EPIC; Multicore Architectures; Storage Systems

Sumantra Dutta Roy, EE, IITD [email protected]

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