Solid State Electronics xxx (xxxx) xxx–xxx

Contents lists available at ScienceDirect

Solid State Electronics

journal homepage: www.elsevier.com/locate/sse

Lithography for now and the future

M.A. van de Kerkhof, J.P.H. Benschop, V.Y. Banine
⁎

ASML, Veldhoven, the Netherlands

ARTICLE INFO

The review of this paper was arranged by Profs.

S. Luryi, J. M. Xu, and A. Zaslavsky

1. Introduction “Moore’s Law”.

In his 1975 IEEE article [8], Gordon Moore predicted the compo-
Optical lithography has supported multiple generations of scaling of nents per chip would double every two years rather than every year, as
integrated chip production, known as Moore’s law: doubling of the observed from 1959 until 1975.
amount of transistors on the chip about every 1.5–2 years. Though it is not a physical law, and at best can be called an eco-
While state-of-art immersion lithography tools with a numerical nomic law or a conjecture based on a couple of points over a period of
aperture of 1.35 and throughput of > 200 wafers per hour are the main 6 years (see Fig. 2), the prediction of Moore has become the guiding
working horse of the semiconductor industry, multiple patterning is principal for the semiconductor industry for the last 50 years.
required to obtain ∼10–16 nm half-pitch. It is worth mentioning that, in a much later investigation, Ray
Extreme Ultraviolet (EUV, corresponding to 13.5 nm light) scanners Kurzweil [9,10], extended the Moore’s exponential trend retro-
are being introduced in high volume manufacturing and will extend spectively back to 1900 (see Fig. 3).
Moore’s Law for the foreseeable future. As illustrated in [11] a number of paradigm shifts have happened in
After a short introduction of IC making in the past, we will discuss the field of technological employment over the last 60 years:
the present and future of lithography. This includes a demonstration of
the EUV state-of–art systems capabilities, discussion of critical EUV • connecting different locations e.g. land line telephones, to
technologies as well as a view of further extension in the future. • connecting individuals e.g. mobile phones and to
• connecting smart things and devices in the near future e.g. auto-
2. A bit of history motive, home appliances, medical etc.

Lithography in the form of the carved type printing can be dated as Until 2005, making transistors smaller and at the same time in-
far back as the 3rd century CE [1]. creasing the clock speed (so-called Dennard scaling) went hand in hand.
As can be seen from Fig. 1, lithography has always played a major This allowed a simultaneous decrease of the chip cost and a rather
role in information technology. While from the16th to the 19th century straightforward increase of computer performance. The more compu-
it was used for printed books, maps, newspapers etc; in the mid-20th tational technology is embedded in our society, the higher percentage
century, with the invention of the micro- and nano-electronics, it took of power consumption that is dedicated to it.
on a new meaning and became a core process and the basis for the Though evaluations differ, currently server farms alone already
patterning solutions of the modern day semiconductor industry. account for at least a couple of percent the electrical power consump-
For 50 years the progress of the semiconductor industry and thus tion in the US [12,13]. The scalability of power efficiency of compu-
lithography was governed by the law named after one of the founders of tations becomes a significant additional driver for Moore’s law. As has
Fairchild Semiconductors and later co-founder of Intel, Gordon Moore. been shown in [10] the dependence of computations per kWh as a
In his 1965 publication [7], Gordon Moore mentioned that “the function of time also shows a Moore’s-law-like behavior, which is
complexity of the minimum component cost has increased roughly a sometimes called Koomey’s law, see Fig. 4.
factor of two per year” and he predicted this trend would continue for
another decade. Later on this prediction was commonly referred to as

⁎
Corresponding author.
E-mail address: [email protected] (V.Y. Banine).

https://doi.org/10.1016/j.sse.2019.03.006

0038-1101/ © 2019 Published by Elsevier Ltd.

Please cite this article as: M.A. van de Kerkhof, J.P.H. Benschop and V.Y. Banine, Solid State Electronics,
https://doi.org/10.1016/j.sse.2019.03.006
M.A. van de Kerkhof, et al. Solid State Electronics xxx (xxxx) xxx–xxx

Fig. 1. From carved printing [2] through rotary press [3] to Photolithography and EUVL [4–6].

2.1. Lithography for the semiconductor industry

Requirements for and thus the scaling of printable features by a li-

thographic apparatus is determined by the Abbe resolution criterium in
a form similar to the one in [14], as presented in Fig 5. As can be seen,
both the numerical aperture and the radiation wavelength play a major
role in the choice of and methods for scaling.
While the evolution of lithographic machines (see Fig. 6), happens
by the increase of the numerical aperture of the optical system at
constant wavelength, the revolution can be associated with a change of
the wavelength and with this choice of light emitters and optical ma-
terials. Nonetheless, evolutionary part of the scaling does not make the
challenge significantly smaller. An example of this is immersion litho-
graphy. A strong example of revolutionary change in lithography, on
the other hand, is the introduction of Extreme Ultraviolet lithography
(EUVL), where complete system had to be re-thought, starting from a
plasma-based source to a new type of reflective optics in the high va-
cuum environment.

2.2. Extreme Ultraviolet Lithography: technological and scientific revolution

Fig. 2. The famous publication of the graph, which later became known as
Moore’s law [7]. As was stated above lithography is one of the most important
technologies enabling the progress of semiconductor technology.

Fig. 3. Trend of the technological advances of computers according to R. Kurzweil in calculations per s per 1000$ (data are taken from [9]).

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unlike both X-ray and Ultraviolet which have a significantly long ab-
sorption length, EUV only is absorbed in nanometers of any solid ma-
terial and micrometers under normal conditions in gases. This means
that apparatus used in the investigations involving EUV have to use
special and expensive multilayer reflective optics, high vacuum, hot
20–50 eV plasma or accelerator technology for the production of EUV
radiation. Due to these characteristics, applications for EUV were rare
and limited to astrophysics.
This vicious circle of lack of technology leading to lack of interest
and vice versa was broken at the end of the 80 s when an opportunity
presented itself in the form of a new application: EUV lithography. It led
to an explosion of the number of publications at this point in history.
The first paper on the possible application of EUV, or as called at
that time soft X-ray, for lithography was published by Bell Labs [18] in
1985. Already in 1989 Kinoshiba et al. [19] demonstrated EUV imaging
in resist with critical dimensions of ∼0.5 μm, using Schwarzschild
projection optics and a synchrotron as a source. In 1991, EUV images
were shown by prof. Bijkerk’s group [20]. A laser produced plasma
(LPP) source was utilized in order to produce EUV radiation. CDs of
60–80 nm were demonstrated in Japan [21] and the US on the en-
gineering test stand (ETS) tool [22] in 2000 and 2001 respectively. The
EUV lithography program in ASML was launched in 1997. It resulted in
the 2006 shipment of two Alpha Demo Tools to R&D facilities at IMEC
(Belgium) and the University of Albany (NY, USA), which printed on
the critical dimension (CD) of 28 nm. This progressed further towards
Fig. 4. Koomey’s-Moore’s law for computation per kW [13].
the shipment preproduction systems NXE:3100, NXE:3300B, and finally
to the HVM-ready production system NXE:3400B, see e.g. Refs. [23,24].
New challenges for further scaling of semiconductor devices in the
21st century resulted in Extreme Ultraviolet Lithography (EUVL)
3. State-of-the-art EUV lithography
through close collaboration of both hi-tech companies and scientific
institutes.
With the introduction in 2017 of the NXE:3400B [25], with nu-
The number of publications devoted to a certain technological
merical aperture NA = 0.33, EUV lithography is now ready for large
problem by the scientific community can be considered as a sign of
scale production. Offering source power of > 200 W, and a corre-
interest from this community towards a particular problem, see Fig. 7.
sponding throughput of > 125 wph, as well as continuing improve-
As indicated in [15] EUV is one of the last regions of the electro-
ments in overlay, defectivity and availability, this tool is being inserted
magnetic spectrum to be developed and to find practical application. As
for production by leading-edge chip manufacturers worldwide. The
can be seen from the chart in the Fig. 7, the number of published ar-
benefits of the large shift in wavelength to 13.5 nm are multiple: im-
ticles mentioning this part of the spectrum remained relatively low till
proved imaging fidelity improves electrical properties; limiting multiple
the end of the 80 s of the last century. It can be explained by the high
exposures reduces patterning costs and faster cycles-to-yield.
threshold for this technology to be developed due to the fact that,
One of the key features of the NXE:3400B is its flexible illuminator

Fig. 5. Physical limit of optical projection lithography.

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Fig. 6. Lithography roadmap from past to future.

design. It allows setting an illumination mode fitting a particular ima- In parallel, EUV resists have been developed to take advantage of
ging pattern with the highest contrast achievable and without trans- the intrinsic resolution of EUV to push the thresholds of lines/spaces
mission loss. In order to do this, a system of multilayer mirrors con- and contact holes, resulting in a robust printing capability of N5-node-
sisting of several hundreds of facets is applied. This enables aggressive compatible 13 nm Lines/Spaces (k1 = 0.3) and 20 nm Contact Holes,
resolution-enhancing techniques to achieve lower k1-factors (see Fig. 5) with sufficient contrast for large-scale production. Also, work is on-
and thus improved various printed features (see Fig. 8). It goes hand in going to co-optimize lithography with etch to improve bottom-line
hand with the EUV Projection Optics Box (POB) improvement regarding Local CDU (critical dimension uniformity), with promising results [26].
aberrations and distortions to support these low-k1 factors and corre- Although theoretically, EUV resolution can be stretched as low as
sponding overlay requirements (see Fig. 9). ∼11 nm for the current NA = 0.33 (corresponding to a k1 = 0.27), in

Fig. 7. History of Extreme Ultraviolet Lithography (EUVL) [15–17].

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Fig. 8. An example of available illumination setting in the NXE 3400B [25].

Fig. 11. State-of-the-art overlay performance: (a) Single Machine Overlay

0.7 nm, and (b) Matched Machine Overlay at 1.1 nm, exceeding N5-node re-
quirements [25].

demonstrated in a lab setup. In parallel, availability has been con-

Fig. 9. Improvement in wave front error in the EUV projection optics [25]. tinuously improving, although more work is still needed to bring EUV
to the same availability levels as ArFi.
It should be noted that today’s resists are not yet quite sensitive (or
“fast”) enough to support > 125 wph (even for 250 W source power),
practice, it is expected that EUV will also use spacer technology or without sacrificing LCDU (local critical dimension uniformity), a
multiple patterning to go beyond 13 nm, down to 8 nm. Although this parameter, which becomes increasingly important with current scaling
will go at the expense of process complexity, this can be considered as a of critical dimensions to sub-10-nm level. So, while resolution and
viable path for resolution and LWR (line width roughness), similar to overlay requirements are demonstrated by the NXE:3400B, the near
current state-of-the-art ArFi applications, until possible future high-NA future will see the use of mixed DUV and EUV technologies due to the
EUV scanners with an NA > 0.33, e.g. NA = 0.55, become available economical consideration of the complete semiconductor process. For
(see Fig. 10). some applications/layers the imaging resolution advantages of EUV will
In the past few years, significant advances have been demonstrated be decisive, while for other applications/layers the throughput ad-
in EUV source power, from 10 W in 2011 to above 250 W today, re- vantage of ArFi Multi-Patterning will be economically favorable.
sulting in a record 147 wph. Further evolutionary improvements of To enable the best overall economic optimization per layer, the
source power to beyond 300 W are ongoing, with > 400 W already NXE:3400B has been designed for < 2 nm matched-machine overlay
(MMO) with respect to state-of-the-art ArFi scanners, allowing mix-and-
match operation between these lithographic technologies, (see Fig. 11).
Another issue, which is coming up as EUV approaches HVM in-
troduction, is Reticle Defectivity: any particle of size > 50 nm reaching
the reticle frontside will result in imaging defects at the N5 node.
This has been the focus of much effort in recent years, resulting in a
dual-path approach: the NXE:3400B was designed and built for an ab-
solute minimum of particles reaching the sensitive mask surface; in
parallel, an EUV-compatible thin (< 50 nm) free standing membrane in
front of reticle, which is called pellicle has been developed [27]. It
protects the reticle from particles to reach it. At the same time particles
captured by the pellicle will not be imaged on the wafer due to the fact
that it is positioned out of focus of the projection system.
Although an EUV-pellicle gives a guaranteed yield as far as de-
Fig. 10. State-of-the-art EUV imaging results; (a) 13 nm dense lines and spaces,
and (b) contact holes [26,27]. fectivity is concerned, any EUV-pellicle will have a finite transmission
loss and a corresponding throughput loss of up to ∼20%. On the other
hand, running without a pellicle might give highest throughput but

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Fig. 12. Dual path approach to manage defectivity towards HVM requirements [27].

death of Moore’s Law are far from the truth.

4. Concluding remarks

Lithography, as a cornerstone piece of semiconductor manu-

facturing technology, successfully supported major changes in our way
of life for the last several decades. The evolution of lithography tech-
nology from the 90 s of the last century till now, from i-line to ArF
immersion systems was instrumental in this process.
EUV lithography is the next step in this direction. Based on a range
of revolutionary new technologies, it will support cost-effective solu-
tions for semiconductor manufacturing in the foreseeable future.
Pathways to advances in computer power in the further future are
multifold and how lithography will evolve further depends on the
outcome of research of the coming years.

Fig. 13. Layout of NA 0.55 Extreme Ultraviolet (EUV) scanner. References

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[25] Proc. SPIE 10143, Extreme Ultraviolet (EUV) Lithography VIII, 101430D, 2017. Mark van de Kerkhof began his career at ODME, devel-
[26] Proc. SPIE 10143, Extreme Ultraviolet (EUV) Lithography VIII, 1014319, 2017. oping a novel DVD mastering process, and later worked on
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[28] Proc. SPIE 10143, Extreme Ultraviolet (EUV) Lithography VIII, 1014313, 2017. Ray. In 1999 he joined ASML as senior designer, working on
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[30] Holt B. Moore’s law: a path forward, ISSCC, 2016. Product System Engineer. He is currently responsible for
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for_semiconductors_itrs/. authored 25 papers and holds 65 USA patents.
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Vadim Banine joined ASML Department of Metrology in

Jos Benschop started his carrier at Philips Research and 1996 and later in 1997 moved to newly organized Research
joined ASML in 1997. He currently holds the position of Department. Currently, after many years in Research, he
senior vice president technology and is, amongst others, holds a position of director of defectivity department in
responsible for ASML research and system engineering. He development and engineering. He received his PhD in
got a PhD in physics from Twente University, he is currently Eindhoven University of Technology. Next to his job at
a part-time professor at Twente University. He published 30 ASML he is now a part-time professor at the same university
papers and is (co-) inventor of 20 USA patents. He is a for a chair of Extreme Ultraviolet lithography. He has more
member of the Dutch Academy of Technology and than 50 scientific publications and is (co-) inventor of more
Innovation (AcTI) and a fellow of SPIE. than 170 USA patents. He is one of the winners of the
European Inventor Award of 2018.