IRFD113, SiHFD113

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Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
• For Automatic Insertion
VDS (V) 60
RDS(on) (Ω) VGS = 10 V 0.8 • Compact Plastic Package
Qg (Max.) (nC) 7 • End Stackable
Qgs (nC) 2 • Fast Switching
Qgd (nC) 7 • Low Drive Current
Configuration Single • Easily Paralleled
• Excellent Temperature Stability
D • Compliant to RoHS Directive 2002/95/EC
Note
* Pb containing terminations are not RoHS compliant, exemptions
HVMDIP may apply

G DESCRIPTION
The HVMDIP technology is the key to Vishay’s advanced
line of power MOSFET transistors. The efficient geometry
S and unique processing of the HVMDIP design achieves
G
S very low on-state resistance combined with high
D transconductance and extreme device ruggedness.
N-Channel MOSFET HVMDIPs feature all of the established advantages of
MOSFETs such as voltage control, very fast switching, ease
of paralleling, and temperature stability of the electrical
parameters.
The HVMDIP 4 pin, dual-in-line package brings the
advantages of HVMDIPs to high volume applications where
automatic PC board insertion is desireable, such as circuit
boards for computers, printers, telecommunications
equipment, and consumer products. Their compatibility with
automatic insertion equipment, low-profile and end
stackable features represent the stat-of-the-art in power
device packaging.

ORDERING INFORMATION
Package HVMDIP
IRFD113PbF
Lead (Pb)-free
SiHFD113-E3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltagea VDS 60
V
Gate-Source Voltage VGS ± 20
Continuous Drain Current VGS at 10 V TC = 25 °C ID 0.8
A
Pulsed Drain Currentb IDM 6.4
Linear Derating Factor 0.008 W/°C
Inductive Current, Clamped L = 100 μH ILM 6.4 A
Maximum Power Dissipation TC = 25 °C PD 1.0 W
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150
°C
Soldering Recommendations (Peak Temperature) for 10 s 300c
Notes
a. TJ = 25 °C to 150 °C
b. Repetitive rating; pulse width limited by maximum junction temperature.
c. 1.6 mm from case.

S11-2479-Rev. A, 19-Dec-11 1 Document Number: 91487

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 120 °C/W

SPECIFICATIONS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 60 - -
V
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0
Gate-Source Leakage IGSS VGS = ± 20 V - - ± 500 nA
VDS = max. rating, VGS = 0 V - - 250
Zero Gate Voltage Drain Current IDSS μA
VDS = max. rating x 0.8, VGS = 0 V, TC = 125 °C - - 1000
On-State Drain Currentb ID(on) VGS = 10 V VDS > ID(on) x RDS(on) max. 0.8 - - A
Drain-Source On-State Resistanceb RDS(on) VGS = 10 V ID = 0.8 A - 0.6 0.8 Ω
Forward Transconductanceb gfs VDS > ID(on) x RDS(on) max., ID = 0.8 A 0.8 1.2 - S
Dynamic
Input Capacitance Ciss VGS = 0 V, - 135 200
Output Capacitance Coss VDS = 25 V, - 80 100 pF
Reverse Transfer Capacitance Crss f = 1.0 MHz - 20 25
Total Gate Charge Qg - 5 7
ID = 4 A,
Gate-Source Charge Qgs VGS = 10 V - 2 - nC
VDS = 0.8 max. rating
Gate-Drain Charge Qgd - 7 -
Turn-On Delay Time td(on) - 10 20
Rise Time tr - 15 25
VDD = 0.5 VDS , ID = 0.8 A, ns
Turn-Off Delay Time td(off) Rg = 50 Ω - 15 25
Fall Time tf - 10 20
Internal Drain Inductance LD Between lead, D - 4.0 -
2 mm (0.08") from
package and center of nH
Internal Source Inductance LS die contact
G
- 6.0 -
S

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current IS MOSFET symbol D - - 0.8
showing the
integral reverse G
A
Pulsed Diode Forward Current ISM p - n junction diode - - 6.4
S

Body Diode Voltagea VSD TA = 25 °C, IS = 0.8 A, VGS = 0 V - - 2 V

Body Diode Reverse Recovery Time trr - 100 - ns
TJ = 150 °C, IF = 1.0 A, dI/dt = 100 A/μs
Body Diode Reverse Recovery Charge Qrr - 0.2 - μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.

S11-2479-Rev. A, 19-Dec-11 2 Document Number: 91487

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRFD113, SiHFD113
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Saturation Characteristics

Fig. 2 - Typical Transfer Characteristics Fig. 4 - Maximum Safe Operatung Area

S11-2479-Rev. A, 19-Dec-11 3 Document Number: 91487

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRFD113, SiHFD113
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Vishay Siliconix

Fig. 5 - Typical Transconductance vs. Drain Current Fig. 7 - Breakdown Voltage vs. Temperature

Fig. 6 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Normalized On-Resistance vs. Temperature

S11-2479-Rev. A, 19-Dec-11 4 Document Number: 91487

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRFD113, SiHFD113
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Vishay Siliconix

Fig. 9 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 11 - Typical On-Resistance vs. Darin Current

Fig. 10 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 12 - Maximum Darin Current vs. Case Temperature

S11-2479-Rev. A, 19-Dec-11 5 Document Number: 91487

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRFD113, SiHFD113
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Vishay Siliconix

Fig. 17 - Gate Charge Test Circuit

Fig. 13 - Power vs. Temperature Derating

Fig. 14 - Clamped Inductive Test Circuit

EC

VDS
IP
Fig. 18 - Typical Time to Accumulated 1 % Gate Failure
IL
VDD

Fig. 15 - Clamped Inductive Waveforms

Fig. 16 - Switching Time Test Circuit

Fig. 19 - Typical High Temperature Reverse Bias (HTRB) Failure
Rate

S11-2479-Rev. A, 19-Dec-11 6 Document Number: 91487

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRFD113, SiHFD113
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Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 20 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91487.

S11-2479-Rev. A, 19-Dec-11 7 Document Number: 91487

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay
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Revision: 01-Jan-2021 1 Document Number: 91000