Introduction to Modeling MOSFETS in SPICE

ROCHESTER INSTITUTE OF TECHNOLOGY

MICROELECTRONIC ENGINEERING

Introduction to Modeling MOSFETS

in SPICE
Dr. Lynn Fuller
Electrical and Microelectronic Engineering
Rochester Institute of Technology
82 Lomb Memorial Drive
Rochester, NY 14623-5604
Tel (585) 475-2035
Fax (585) 475-5041
Dr. Fuller’s Webpage: http://people.rit.edu/lffeee
Email: [email protected]
Dept Webpage: http://www.microe.rit.edu

Rochester Institute of Technology 1-1-2014 SPICE_MOSFET_Model_Intro.ppt

Microelectronic Engineering

© January 1, 2014 Dr. Lynn Fuller Page 1

 Introduction to Modeling MOSFETS in SPICE

ADOBE PRESENTER

This PowerPoint module has been published using Adobe Presenter. Please click
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Manually advance the slide by clicking on the play arrow or pressing the page
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Introduction to Modeling MOSFETS in SPICE

OUTLINE

Introduction
MOSFET
SPICE
Shichman and Hodges Model
MOSFET Attributes
Changing MOSFET SPICE Model
Ids-Vds Family of Curves
Ids-Vgs
Measured MOSFET Characteristics
AC Attributes
Ring Oscillator
Summary
References
Homework

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© January 1, 2014 Dr. Lynn Fuller Page 3

 Introduction to Modeling MOSFETS in SPICE

INTRODUCTION

PSpice Lite 9.2 is one of the OrCAD family of products, from

Cadence Design Systems, Inc., offering a complete suite of electronic
design tools. It is free and includes limited versions of OrCAD
Capture, for schematic capture, PSpice for analog circuit simulation
and Pspice A/D for mixed analog and digital circuit simulation.
PSpice Lite 9.2 is limited to 64 nodes, 10 transistors, two operational
amplifiers and 65 primitive digital devices. See page 35 (xxxv) of the
PSpice Users Guide.

LT SPICE – is a free SPICE simulator with schematic capture from

Linear Technology. It is quite similar to PSpice Lite but is not limited
in the number of devices or nodes. Linear Technology (LT) is one of
the industry leaders in analog and digital integrated circuits. Linear
Technology provides a complete set of SPICE models for LT
components. Rochester Institute of Technology
Microelectronic Engineering

© January 1, 2014 Dr. Lynn Fuller Page 4

 Introduction to Modeling MOSFETS in SPICE

MOSFET DEVICE MODELS

MOSFET Device models used by SPICE (Simulation Program for

Integrated Circuit Engineering) simulators can be divided into three
classes: First Generation Models (Level 1, Level 2, Level 3 Models),
Second Generation Models (BISM, HSPICE Level 28, BSIM2) and
Third Generation Models (BSIM3, Level 7, Level 8, Level 49, etc.)
The newer generations can do a better job with short channel effects,
local stress, transistors operating in the sub-threshold region, gate
leakage (tunneling), noise calculations, temperature variations and
the equations used are better with respect to convergence during
circuit simulation.
In general first generation models are recommended for MOSFETs
with gate lengths of 10um or more. If not specified most SPICE
MOSFET Models default to level=1 (Shichman and Hodges)

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 Introduction to Modeling MOSFETS in SPICE

SPICE LEVEL-1 MOSFET MODEL

G

CGSO CGDO
S D
COX

p+ p+
RS ID RD
CBD
CBS
CGBO

B
where ID is a dependent current source using
Rochester Institute of Technology
Microelectronic Engineering
the equations on the next page

© January 1, 2014 Dr. Lynn Fuller Page 6

 Introduction to Modeling MOSFETS in SPICE

SPICE LEVEL 1 - SHICHMAN AND HODGES

+Ids
Saturation Region
Non Saturation Region +5
+4 +Vgs
+3
NMOS +2
+Vds

IDsat = µW Cox’ (Vg-Vt)2 ID = µW Cox’ (Vg-Vt-Vd/2)Vd

2L L

Saturation Region Non Saturation Region

where m, Cox’and Vt are given in equations on

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the next pages

© January 1, 2014 Dr. Lynn Fuller Page 7

 Introduction to Modeling MOSFETS in SPICE

SPICE LEVEL-1 EQUATIONS FOR UO, VTO AND COX’

Parameter Arsenic Phosphorous Boron

(µmax-µmin) µmin 52.2 68.5 44.9
Mobility: µ = µ min+ µmax 1417 1414 470.5
(cm2/V-s) Nref 9.68X10^16 9.20X10^16 2.23X10^17
{1 + (N/Nref)}  0.680 0.711 0.719

Threshold Voltage:
+/- VTO = ms - q NSS/Cox’+/ -2[F] +/-2 (qorsi NSUB [F])0.5/Cox’
nmos/pmos
[F] = (KT/q ) ln (NSUB/ni) where ni = 1.45E10 and KT/q = 0.026
Absolute value

PHI = 2 [F]
Gate Capacitance
per unit area Cox’ Cox’= rox o/TOX=3.9 o/TOX

where r si = 11.7 and r ox = 3.9

Rochester Institute of Technology
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o = 8.85E-12 F/m or 8.8eE-14F/cm
q = 1.6E-19
© January 1, 2014 Dr. Lynn Fuller Page 8
 Introduction to Modeling MOSFETS in SPICE

MOBILITY MODEL

1600
Mobility (cm2/ V sec)

1400
1200 electrons Electron and hole mobilities
in silicon at 300 K as
Arsenic
1000 functions of the total dopant
Boron
800 Phosphorus
concentration (N). The
600 values plotted are the results
400 of the curve fitting
holes measurements from several
200 sources. The mobility curves
0 can be generated using the
equation below with the
13

14

15

16

17

18

19

20
parameters shown:
^

^
10

10

10

10

10

10

10

10
Total Impurity Concentration (cm-3) (µmax-µmin)
µ(N) = µ mi+
{1 + (N/Nref)}
Parameter Arsenic Phosphorous Boron
From Muller and Kamins, 3rd Ed., pg 33 µmin 52.2 68.5 44.9
µmax 1417 1414 470.5
Rochester Institute of Technology Nref 9.68X10^16 9.20X10^16 2.23X10^17
Microelectronic Engineering  0.680 0.711 0.719

© January 1, 2014 Dr. Lynn Fuller Page 9

 Introduction to Modeling MOSFETS in SPICE

LONG CHANNEL THRESHOLD VOLTAGE, VT

Xox
Flat-band Voltage VFB = ms - Qss - 1 X (x) dx
C’ox C’ox 0 Xox
p-type substrate n-type substrate
(n-channel) (p-channel) Qss = q Nss
Bulk Potential : p = -KT/q ln (NA /ni) n = +KT/q ln (ND /ni)
Work Function: M S = M - ( X + Eg/2q + [p]) M S = M - ( X + Eg/2q - [n])
Difference
Maximum Depletion Width: 4 s[p] 4 s[n]
(Wdmax) qNa qNd

Threshold Voltage: VT = VFB + 2 [p] + 1 2 s q Na ( 2[p]+Vsb)

p-type substrate C’ox
Threshold Voltage: VT = VFB - 2 [n] - 1 2 s q Nd ( 2[n]+Vbs)
n-type substrate C’ox
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 Introduction to Modeling MOSFETS in SPICE

BACK-BIASING EFFECTS – GAMMA

Body Effect coefficient GAMMA or g :

- Vsb +
Vg
Vd
Vb Vs
Ids VSB=0 VSB=1V
VSB=2V p n n

1
g '
2q Si N Asub
C ox
Vgs
VTO Qss
VTLC   MS  '
 2 F  g 2 F  VSB
C ox

Rochester Institute of Technology where r si = 11.7 and r ox = 3.9

Microelectronic Engineering o = 8.8eE-14F/cm
q = 1.6E-19
© January 1, 2014 Dr. Lynn Fuller Page 11
 Introduction to Modeling MOSFETS in SPICE

VT ADJUST IMPLANT

The threshold voltage can be adjusted with an ion implant. If total

implant dose is shallow (within Wdmax) then the change in Vt is:
+/- Vt = q Dose*/Cox’
where Dose* is the dose that is added to the Si
Boron gives + shift Cox’ is gate oxide capacitance/cm2
Phosphorous gives - shift Cox’ = or / Xox
Vs Vg
Vd
Maximum Depletion Width:
4 s[p]
n n
Wdmax =
qN p
Wdmax
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 Introduction to Modeling MOSFETS in SPICE

CHANNEL LENGTH MODULATION - LAMBDA

Channel Length Modulation
Parameter  NMOS
 = Slope/ Idsat +Ids
Slope Saturation Region
Vg +5
S
Vd +4
Idsat +Vgs
+3
n n +2
p
L - L Vd2 Vd1 Vd2 +Vds
L Vd1

IDsat = µW Cox’ (Vg-Vt)2 (1+ Vds) NMOS Transistor

2L DC Model,  is the channel length modulation
parameter and is different for each channel
Saturation Region length, L. Typical value might be 0.02
ID = µW Cox’ (Vg-Vt-Vd/2)Vd (1+ Vds)
L
Non Rochester
SaturationInstitute of Region
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 Introduction to Modeling MOSFETS in SPICE

TRANSISTOR PROPERTIES OR ATTRIBUTES

2u
L= 2u
W = 8u
Ad = 8u x10u = 80p
As = Ad = 80p
Pd = 8u+10u+8u+10u = 36u
Ps = Pd = 36u
Nrs = 1
Nrd = 1

NMOS 2/8
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 Introduction to Modeling MOSFETS in SPICE

LTSPICE MOSFET ATTRIBUTES

MOSFETS are four terminal devices (Drain, Gate, Source and

Substrate). L and W are channel length and width in meters, Ad and
As are area of drain and source in square meters. If not specified
default values are used. (see next page) Perimeter of Drain and source
(PD and PS) in meters is used to calculate drain and source side wall
capacitance. If PD and PS are not given the default is zero. NRD and
NRS are multiplied by the drain and source sheet resistance to give
series resistance RD and RS. The default value for NRD and NRS is
one.

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 Introduction to Modeling MOSFETS in SPICE

LTSPICE MOSFET ATTRIBUTE DEFAULT VALUES

Name Description Unit Default Example

L Default Length m defl 100u
W Default Width m defw 100u
Ad Default drain area m2 defad 1000p
As Default source area m2 defas 1000p
Pd Default drain perimeter m 0 200u
Ps Default source perimeter m 0 200u
Nrd Default drain squares - 1 1
Nrs Default source squares - 1 1
Nrg Default gate squares - 0 1
Nrb Default bulk squares - 0 1
Lmin Bin length lower limit m 0 10u
Lmax Bin length upper limit m 0 20u
WminRochester Institute
Bin width lower limit
of Technology m 0 10u
Microelectronic Engineering
Wmax Bin width upper limit m 0 20u
© January 1, 2014 Dr. Lynn Fuller Page 16
 Introduction to Modeling MOSFETS in SPICE

MOSFET DEFINITION - LTSPICE

For example:
* SPICE Input File
* MOSFET names start with M…. M2 is the name for the MOSFET below and its drain, gate, source
* and substrate is connected to nodes 3,2,0,0 respectively. The model name is RITSUBN7.
* The parameters/attributes is everything after that.
M2 3 2 0 0 RITSUBN7 L=2U W=16U ad=96e-12 as=96e-12 pd=44e-6 ps=44e-6 nrd=1.0 nrs=1.0
*
*

LTSPICE schematic showing .Include and .dc sweep commands. Properties

dialog box to define L and W values. Note: attributes with no entry field nrs
Rochester Institute of Technology
and nrd are typed
Microelectronic in bottom box. Attribute Editor (CTRL R-click on the
Engineering
transistor) allows attributes with Vis.=X to be displayed on the schematic.
© January 1, 2014 Dr. Lynn Fuller Page 17
 Introduction to Modeling MOSFETS in SPICE

MOSFET DEFINITION - PSPICE

For example:
* SPICE Input File
* MOSFET names start with M…. M2 is the name for the MOSFET below and its drain, gate, source
* and substrate is connected to nodes 3,2,0,0 respectively. The model name is RITSUBN7.
* The parameters/attributes is everything after that.
M2 3 2 0 0 RITSUBN7 L=2U W=16U ad=96e-12 as=96e-12 pd=44e-6 ps=44e-6 nrd=1.0 nrs=1.0
*
*

In PSPICE the Attribute Editor (CTRL R-click on the

transistor) allows attributes values to be set, new attribute
columns toInstitute
Rochester beofcreated,
Technology
Microelectronic Engineering
and attributes can be selected to be
displayed on the schematic..
© January 1, 2014 Dr. Lynn Fuller Page 18
 Introduction to Modeling MOSFETS in SPICE

MOSFET DEFINITION - PSPICE

In SPICE a transistor is defined by its name and associated properties

or attributes and its model. MOSFET names start with M, attributes
(L, W, Ad, As, etc.) are specified by the user and shown in the input file
net list. Some attributes can be displayed on the schematic. The model
is specified in a file in a given location or is defined in a library.

name
attributes
model name

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 Introduction to Modeling MOSFETS in SPICE

CHANGING THE MOSFET SPICE MODEL IN LTSPICE

There a several ways to change the MOSFET SPICE model. A good way to do it
is create a text file on your computer and put your models in that text file and save
it in some folder. You can copy models from Dr. Fuller’s webpage to start your
collection of models.
See: http://people.rit.edu/lffeee/CMOS.htm
Example contents of that file is shown on the page below.
Next you change the model name for your transistor by right click on the model
name shown in your schematic and typing the model name used in the model file.
(for example: RITSUBN7)
Finally you place a SPICE directive on your schematic by clicking on the .op icon
on the top banner and type the following command:
.include Drive:\path\folder\filename
For example .include C:\SPICE\RIT_Models_For_LTSPICE.txt
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 Introduction to Modeling MOSFETS in SPICE

SIMPLE AND ADVANCED SPICE MODELS

* From Electronics II EEEE482 FOR ~100nm Technology

.model EECMOSN NMOS (LEVEL=8
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
* From Electronics II EEEE482 FOR ~100nm Technology
.model EECMOSP PMOS (LEVEL=8
+TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
*
* From Electronics II EEEE482 SIMPLE MODEL
.model EENMOS NMOS (VTO=0.4 KP=432E-6 GAMMA=0.2 PHI=.88)
*
* From Electronics II EEEE482 SIMPLE MODEL
.model EEPMOS PMOS (VTO=-0.4 KP=122E-6 GAMMA=0.2 PHI=.88)
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© January 1, 2014 Dr. Lynn Fuller Page 21

 Introduction to Modeling MOSFETS in SPICE

CHANGING THE MOSFET SPICE MODEL IN PSPICE

View output file to see this

listing of spice model parameters
Right click and select EDIT SPICE including default values for L
MODEL to type in underlined parameters and W

L and W shown on the schematic over

ride default values

Mbreakn

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© January 1, 2014 Dr. Lynn Fuller Page 22

 Introduction to Modeling MOSFETS in SPICE

CHANGING THE MOSFET SPICE MODEL IN PSPICE

In PSPICE models saved in a text file can be included as

a configuration file in the Simulation Settings dialog
box as shown above. Change the component model
name to the model name in the text file.
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 Introduction to Modeling MOSFETS in SPICE

COMPARISON OF MOSFET CHARACTERISTICS

The circuit shown can be used to see the transistor family of Ids-Vds curves, Ids-
Vgs plot and Ids-Vgs (Ids on log scale) Subthreshold plot. We can investigate the
effect of changing attributes, SPICE model and model parameters.

V1 is steped to get
family of curves or is
swept to get Ids-Vgs
and Sub-Vt plots V2 is swept to get
family of curves or is
held constant to get
Ids-Vgs plots

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© January 1, 2014 Dr. Lynn Fuller Page 24

 Introduction to Modeling MOSFETS in SPICE

PSPICE MOSFET MODEL PARAMETERS

95 mosfet model parameters used by 31 mosfet model parameters
cadence PSPICE for Level 8 BSIM used by cadence PSPICE for
Level 1 Shichman and Hodges

View Output File

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© January 1, 2014 Dr. Lynn Fuller Page 25

 Introduction to Modeling MOSFETS in SPICE

LTSPICE CIRCUIT SCHEMATIC

DEEP
SIMPLE RIT SUB-MICRON SUB-MICRON
Three transistor all the same L=2u and W=16u but with different SPICE
models. (SIMPLE, RIT SUB-MICRON and 100nm DEEP SUB-MICRON

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© January 1, 2014 Dr. Lynn Fuller Page 26

 Introduction to Modeling MOSFETS in SPICE

THREE DIFFERENT NMOS SPICE MODELS

* From Sub-Micron CMOS Manufacturing Classes in MicroE
.MODEL RITSUBN7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8
+VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
* From Electronics II EEEE482 FOR ~100nm Technology Deep Sub-Micron
.model EECMOSN NMOS (LEVEL=8
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
* From Electronics II EEEE482 SIMPLE MODEL
Rochester Institute of Technology
.model EENMOS NMOSEngineering
Microelectronic (VTO=0.4 KP=432E-6 GAMMA=0.2 PHI=.88)

© January 1, 2014 Dr. Lynn Fuller Page 27

 Introduction to Modeling MOSFETS in SPICE

LTSPICE OUTPUT FOR ID-VDS AND ID-VG

5.0mA gm Model is EECMOSN

L=2u W=16u
Model not good.
Current low and only
good out to 3 volts.
9.5mA Model is RITSUBN7
gm L=2u W=16u
Model good for RIT
Sub-Micron MOSFETs

160mA gm Model is EENMOS

L=2u W=16u
Model not good current
too large
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 Introduction to Modeling MOSFETS in SPICE

MEASURED MOSFET ID-VDS AND ID-VGS

Imax = 9.5mA

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© January 1, 2014 Dr. Lynn Fuller Page 29

 Introduction to Modeling MOSFETS in SPICE

LTSPICE OUTPUT FOR SUBTHRESHOLD ID-VGS

Model is EECMOSN
L=2u W=16u
Model not good MOSFET does not turn off, Vt too
low
Log10(Id)

Model is RITSUBN7
L=2u W=16u
Model good

Model is EENMOS
L=2u W=16u
Model incorrect in subthreshold region.
Subthreshold slope not possible.
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© January 1, 2014 Dr. Lynn Fuller Page 30

 Introduction to Modeling MOSFETS in SPICE

DEEP SUB-MICRON TRANSISTOR MODELS

440uA Model is EECMOSN

gm
L=0.25u W=1.6u
Model good for Deep
Sub-Micron MOSFETs

660uA gm Model is RITSUBN7

L=0.25u W=1.6u
Model not good too
much short channel
effects

3600uA gm Model is EENMOS

L=0.25u W=1.6u
Model not good current
too large does not show
Rochester Institute of Technology
mobility degradation
Microelectronic Engineering
2V
© January 1, 2014 Dr. Lynn Fuller Page 31
 Introduction to Modeling MOSFETS in SPICE

DEEP SUB-MICRON TRANSISTOR MODELS

Model is EECMOSN
L=0.25u W=1.6u
Model good for Deep Sub-Micron MOSFETs

Model is RITSUBN7
Log10(Id)

L=0.25u W=1.6u
Model not good too much DIBL

Model is EENMOS
L=0.25u W=1.6u
Model incorrect in subthreshold region

Rochester Institute of Technology

Microelectronic Engineering

2V
© January 1, 2014 Dr. Lynn Fuller Page 32
 Introduction to Modeling MOSFETS in SPICE

DEEP SUB-MICRON TRANSISTOR MODELS

Deep sub-micron transistors show punch

through at drain voltages over 3.3 volts.
Which is correct.

Problem is worse in the sub-micron

transistor because the channel is lighter
doped.

Simple model is incorrect.

Rochester Institute of Technology
Microelectronic Engineering
2V 6V
© January 1, 2014 Dr. Lynn Fuller Page 33
 Introduction to Modeling MOSFETS in SPICE

MOSFET MODELS USED BY LTSPICE

LTSPICE uses several different types of MOSFET models including simple, deep
submicrometer, Silicon On Insulator (SOI), Vertical double diffused Power
MOSFET. Level = 1 is the default if a model level is not specified.
Level
1 Shichman and Hodges 1st generation
2 MOS2, Vladimirescu and Liu, UC Berkeley, October 1980 models
3 MOS3, a semi-emperical model, UC Berkeley
4 BSIM UC Berkeley, May 1985
5 BSIM2, UC Berkeley, October 1990 2nd generation models
6 MOS6, UC Berkeley, March 1990
8 BSIM3V3.3.0, UC Berkeley 2005
9 BSIMSOI3.2, Silicon on Insulator (SOI), UC Berkeley 2004 3rd generation
14 BSIM4.6.1, UC Berkeley 2007 models
more….
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© January 1, 2014 Dr. Lynn Fuller Page 34

 Introduction to Modeling MOSFETS in SPICE

SIMPLE AND ADVANCED SPICE MODEL

* From Electronics II EEEE482 FOR ~100nm Technology

.model EECMOSN NMOS (LEVEL=8
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
* From Electronics II EEEE482 FOR ~100nm Technology
.model EECMOSP PMOS (LEVEL=8
+TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
*
* From Electronics II EEEE482 SIMPLE MODEL
.model EENMOS NMOS (VTO=0.4 KP=432E-6 GAMMA=0.2 PHI=.88)
*
* From Electronics II EEEE482 SIMPLE MODEL
.model EEPMOS PMOS (VTO=-0.4 KP=122E-6 GAMMA=0.2 PHI=.88)
Rochester Institute of Technology
Microelectronic Engineering

© January 1, 2014 Dr. Lynn Fuller Page 35

 Introduction to Modeling MOSFETS in SPICE

CMOS INVERTER WITH LEVEL 1 SPICE MODEL

VTC

Rochester Institute of Technology Level = 1 model

Microelectronic Engineering

© January 1, 2014 Dr. Lynn Fuller Page 36

 Introduction to Modeling MOSFETS in SPICE

CMOS INVERTER WITH LEVEL 8 SPICE MODEL

VTC

Rochester Institute of Technology Level = 8 model

Microelectronic Engineering

© January 1, 2014 Dr. Lynn Fuller Page 37

 Introduction to Modeling MOSFETS in SPICE

MEASURED VTC L=2um W=40um CMOS INVERTER

Rochester Institute of Technology

Microelectronic Engineering L=2u and W=40u
© January 1, 2014 Dr. Lynn Fuller Page 38
 Introduction to Modeling MOSFETS in SPICE

ADVANCED LINEAR DEVICES ALD 1103

The Advanced Linear Devices ALD1103 is

a dual NMOS and PMOS matched pair in a
14 pin package. The ALD 1101 is a dual
NMOS matched pair and the ALD 1102 is a
dual PMOS matched pair. The 1101/1102
are in an 8 pin package. One chip design for
all three products.
PMOS NMOS

10um L=10um
W diameter = 35um
W each = Pi D = 110um
W total = 8 x 110 = 880um

Rochester Institute of Technology 8 of the donut shaped MOSFETs

MOSFET
Microelectronic Engineering in parallel form one transistor.
© January 1, 2014 Dr. Lynn Fuller Page 39
Introduction to Modeling MOSFETS in SPICE

ALD1103 LAYOUT

4
V-

4 4
DP1 DP2

ESD
4 4
GP1 GP2

4 4
SP1 SP2
PMOS P2

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Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

ELECTROSTATIC DISCHARGE - INPUT PAD

Vpad Simulation for Vpad sweep from -100 to +100 volts
Vin is between -1 and +6 Volts and I is through M1
and M2 if Vpad exceeds supply voltages
Vdd
100mA
R
M2
PMOS
0 mA
Vin

M1
Vin to Gate
NMOS
-100mA
+5V

0V
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 Introduction to Modeling MOSFETS in SPICE

ALD1103 MATCHED NMOS AND PMOS MOSFETS

Measured Id-Vds Measured Id-Vgs & gm Measured Sub Vt Id-Vgs

.MODEL RITALDN3 NMOS (LEVEL=3
+TPG=1 TOX=6.00E-8 LD=2.08E-6 WD=4.00E-7
+U0= 1215 VTO=0.73 THETA=0.222 RS=0.74 RD=0.74 DELTA=2.5
+NSUB=1.57E16 +XJ=1.3E-6 VMAX=4.38E6 ETA=0.913 KAPPA=0.074 NFS=3E11
+CGSO=5.99E-10 CGDO=5.99E-10 CGBO=4.31E-10 PB=0.90 XQC=0.4)
Using a LEVEL=3 model should give good results since L is long,
LEVEL 1 OR 2 will not work
Rochester Institute of Technology From Dr. Fullers SPICE MOSFET Model
Microelectronic Engineering
Parameter Calculator. xls.
© January 1, 2014 Dr. Lynn Fuller Page 42
 Introduction to Modeling MOSFETS in SPICE

ALD1103 LEVEL=3 NMOS SPICE MODEL AND SIMULATION

40mA

0 mA

2.2mA 1.1mS
gm Id
This SPICE model gives good matching
between measured and simulated curves.

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Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

CD4007 DUAL COMPLEMENTARY PAIR + INVERTER

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Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

CD4007 DUAL COMPLEMENTARY PAIR + INVERTER

4um 20um
SOURCE

DRAIN
Rochester Institute of Technology
Microelectronic Engineering
GATE

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 Introduction to Modeling MOSFETS in SPICE

CD4007 DUAL COMPLEMENTARY PAIR + INVERTER

.MODEL RIT4007N8 NMOS (LEVEL=8

+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8
+VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
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Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

CD4007 DUAL COMPLEMENTARY PAIR + INVERTER

Rochester Institute of Technology

Microelectronic Engineering

© January 1, 2014 Dr. Lynn Fuller Page 47

 Introduction to Modeling MOSFETS in SPICE

SUMMARY

All of these examples are for DC characteristics but similar results would be shown
for examples that depend on internal capacitors and resistors such as a study of rise-
time, fall time, gate delay, oscillators, multi-vibrators, etc.

In general the third generation SPICE models for MOSFETS give better results.
Level=1 models are not good for MOSFETS with L less than 10um.
Large MOSFETS, SUB-MICRON MOSFETS and DEEP SUB MICRON MOSFET
models have been introduced.
Models should be verified by comparing measured ID-VDS, ID-VGS, and Ring
Oscillator output with SPICE simulated results.

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Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

RING OSCILLATOR, td, THEORY

Seven stage ring oscillator

with two output buffers
td = T / 2 N
td = gate delay
N = number of stages Vout
T = period of oscillation Buffer

Vout

T = period of oscillation
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 Introduction to Modeling MOSFETS in SPICE

MEASURED RING OSCILLATOR OUTPUT

73 Stage Ring at 5V td = 104.8ns / 2(73) = 0.718 ns

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Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

AC MODEL FOR MOSFETS

The parameters that effect the AC response of a MOSFET are the resistance
and capacitance values.

RS,RS Source/Drain Series Resistance, ohms

RSH Sheet Resistance of Drain/Source, ohms
CGSO,CGDO Zero Bias Gate-Source/Drain Capacitance, F/m of width
CGBO Zero Bias Gate-Substrate Capacitance, F/m of length
CJ DS Bottom Junction Capacitance, F/m2
CJSW DS Side Wall Junction Capacitance, F/m of perimeter
MJ Junction Grading Coefficient, 0.5
MJSW Side Wall Grading Coefficient, 0.5

These are combined with the transistors

L, W Length and Width
AS,AD Area of the Source/Drain
PS,PD Perimeter of the Source/Drain
Rochester Institute of Technology
NRS,NRDMicroelectronicNumber
Engineering of squares Contact to Channel

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 Introduction to Modeling MOSFETS in SPICE

RING OSCILLATOR LAYOUTS

17 Stage Un-buffered Output L/W=2/30 Buffered Output

L/W 8/16 4/16 2/16 73 Stage 37 Stage

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Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

MOSFETS IN THE INVERTER OF 73 RING OSCILLATOR

nmosfet pmosfet

73 Stage Ring Oscillator

Rochester Institute of Technology
Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

FIND DIMENSIONS OF THE TRANSISTORS

NMOS PMOS 73 Stage

L 2u 2u
W 12u 30u
AD 12ux12u=144p 12ux30u=360p
AS 12ux12u=144p 12ux30u=360p
PD 2x(12u+12u)=48u 2x(12u+30u)=84u
PS 2x(12u+12u)=48u 2x(12u+30u)=84u
NRS 1 0.3
NRD 1 0.3

Use Ctrl Click on all NMOS on OrCad Schematic

Use Ctrl Click on all PMOS on OrCad Schematic
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Then EnterEngineering
Microelectronic Dimensions

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 Introduction to Modeling MOSFETS in SPICE

SIMULATED OUTPUT AT 5 VOLTS

Three Stage Ring Oscillator with Transistor Parameters for 73 Stage Ring
Oscillator and Supply of 5 volts

td = T / 2N = 5.5nsec / 2 / 3
td = 0.92 nsec
Measured td = 0.718 nsec @ 5 V
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 Introduction to Modeling MOSFETS in SPICE

CONCLUSION
Since the measured and the simulated gate delays, td are close to correct, then the
SPICE model must be close to correct. The inverter gate delay depends on the
values of the internal capacitors and resistances of the transistor.

Specifically:
RS, RS, RSH
CGSO, CGDO, CGBO
CJ, CJSW

These are combined with the transistors

L, W Length and Width
AS,AD Area of the Source/Drain
PS,PD Perimeter of the Source/Drain
NRS,NRD Number of squares Contact to Channel

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Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

REFERENCES
1. MOSFET Modeling with SPICE, Daniel Foty, 1997, Prentice Hall,
ISBN-0-13-227935-5
2. Operation and Modeling of the MOS Transistor, 2nd Edition, Yannis Tsividis,
1999, McGraw-Hill, ISBN-0-07-065523-5
3. UTMOST III Modeling Manual-Vol.1. Ch. 5. From Silvaco International.
4. ATHENA USERS Manual, From Silvaco International.
5. ATLAS USERS Manual, From Silvaco International.
6. Device Electronics for Integrated Circuits, Richard Muller and Theodore
Kamins, with Mansun Chan, 3rd Edition, John Wiley, 2003, ISBN 0-471-59398-2
7. ICCAP Manual, Hewlet Packard
8. PSpice Users Guide.

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Microelectronic Engineering

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 Introduction to Modeling MOSFETS in SPICE

HOMEWORK – INTRO TO MOSFET SPICE MODELS

Do SPICE for one of the following:

1. Inverter gate delay is the time it takes for the output voltage to get
to ½ of the supply voltage. Use SPICE to get a value for gate delay
for rising and falling output. Let L=2um and W=40um for both
NMOS and PMOS transistors. State other assumptions. Compare
these values to gate delay measured from a ring oscillator.

2. Do a SPICE simulation for the CMOS inverter shown on page 38

and compare to measured VTC and I vs Vin.

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