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Direct Memory Access (DMA)

Direct Memory Access (DMA) allows I/O devices to access main memory directly without intervention from the CPU. This is done using a DMA controller that is programmed with source/destination addresses and transfer details. The DMA controller then handles the data transfer between memory and I/O device, only interrupting the CPU at the beginning and end of the transfer. This reduces overhead compared to the CPU handling each data transfer.

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115 views3 pages

Direct Memory Access (DMA)

Direct Memory Access (DMA) allows I/O devices to access main memory directly without intervention from the CPU. This is done using a DMA controller that is programmed with source/destination addresses and transfer details. The DMA controller then handles the data transfer between memory and I/O device, only interrupting the CPU at the beginning and end of the transfer. This reduces overhead compared to the CPU handling each data transfer.

Uploaded by

Sabi Chaudry
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Direct Memory Access (DMA)

Slow devices like keyboards will generate an interrupt to the main CPU after each byte
is transferred. If a fast device such as a disk generated an interrupt for each byte, the
operating system would spend most of its time handling these interrupts. So a typical
computer uses direct memory access (DMA) hardware to reduce this overhead.
Direct Memory Access (DMA) means CPU grants I/O module authority to read from or
write to memory without involvement. DMA module itself controls exchange of data
between main memory and the I/O device. CPU is only involved at the beginning and
end of the transfer and interrupted only after entire block has been transferred.
Direct Memory Access needs a special hardware called DMA controller (DMAC) that
manages the data transfers and arbitrates access to the system bus. The controllers
are programmed with source and destination pointers (where to read/write the data),
counters to track the number of transferred bytes, and settings, which includes I/O and
memory types, interrupts and states for the CPU cycles.

The operating system uses the DMA hardware as follows −


Ste Description
p

1 Device driver is instructed to transfer disk data to a buffer address X.

2 Device driver then instruct disk controller to transfer data to buffer.

3 Disk controller starts DMA transfer.

4 Disk controller sends each byte to DMA controller.

5 DMA controller transfers bytes to buffer, increases the memory address, decreases the
counter C until C becomes zero.

6 When C becomes zero, DMA interrupts CPU to signal transfer completion.

Polling vs Interrupts I/O


A computer must have a way of detecting the arrival of any type of input. There are two
ways that this can happen, known as polling and interrupts. Both of these techniques
allow the processor to deal with events that can happen at any time and that are not
related to the process it is currently running.

Polling I/O

Polling is the simplest way for an I/O device to communicate with the processor. The
process of periodically checking status of the device to see if it is time for the next I/O
operation, is called polling. The I/O device simply puts the information in a Status
register, and the processor must come and get the information.
Most of the time, devices will not require attention and when one does it will have to
wait until it is next interrogated by the polling program. This is an inefficient method and
much of the processors time is wasted on unnecessary polls.
Compare this method to a teacher continually asking every student in a class, one after
another, if they need help. Obviously the more efficient method would be for a student
to inform the teacher whenever they require assistance.
Interrupts I/O

An alternative scheme for dealing with I/O is the interrupt-driven method. An interrupt is
a signal to the microprocessor from a device that requires attention.
A device controller puts an interrupt signal on the bus when it needs CPU’s attention
when CPU receives an interrupt, It saves its current state and invokes the appropriate
interrupt handler using the interrupt vector (addresses of OS routines to handle various
events). When the interrupting device has been dealt with, the CPU continues with its
original task as if it had never been interrupted.

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