Power Supply Design Seminar

Control and Design

Challenges for
Synchronous Rectifiers

Reproduced from
2018 Texas Instruments Power Supply Design Seminar
SEM2300,
Topic 2
TI Literature Number: SLUP378
© 2018 Texas Instruments Incorporated

Power Supply Design Seminar resources

are available at:
www.ti.com/psds
 Control and Design Challenges
for Synchronous Rectifiers
Bing Lu

Abstract
Synchronous Rectifiers
To improve power supply efficiency to meet stringent standards, a synchronous rectifier (SR) often replaces
the diode rectifier. Based on loss breakdown, this session explains how to achieve efficiency improvement and

Topic 2
presents design criteria for selecting a suitable SR MOSFET, balancing between conduction and switching
losses. Also, SR control methods are discussed, including VDS sensing, volt-second sensing and self-driven.
The pros and cons of each control method are discussed in detail. Some design challenges, including noise
immunity, fast turn off, high-side and low-side SR and special current shapes, such as LLC converters, are
also discussed.

I. Introduction requirement, the energy efficiency level is clearly

marked on the adapter with a Roman numeral, as
With the development of telecommunication and
shown in Figure 1. The rules of the efficiency marking
mobile technologies, smart phones, tablets and
can be found in [4].
notebook computers became essential parts of
everyday life. The more powerful processors, larger
screen sizes and longer operating times require the
battery sizes to keep increasing. In turn, the power
levels of the AC/DC adapters (chargers) are also
Figure 1 – External power supply marking
increasing. While the power of these adapters keeps
with efficiency level.
increasing, the size of the adapters is expected to
remain the same or become even smaller (for either In the latest DoE efficiency standard (Table 1),
branding reasons or better mobility). Due to the the basic voltage power supply is defined as a rated
smaller size and less surface area, the adapter output voltage larger or equal to 6 V. For the low
efficiency must increase to allow an acceptable surface voltage power supply, which has a rated额定的
output voltage
temperature for safe operation. The power supply less than 6 V, the required efficiencies are lower due to
design industries are searching for different solutions the higher conduction loss challenges for the lower
to obtain higher power density AC/DC adapters output voltage. The regulation has been in effect since
through better semiconductor devices and topologies. February 10, 2016. The efficiency measurement
Meanwhile, different countries and organizations have method is defined as in [3]. The average efficiency is
passed legislation for the efficiency standard for these the average value efficiencies measured at 25%, 50%,
power supplies [1]. The most significant ones are the 75% and 100% of the rated output current. CoC has
US Department of Energy (DoE) [2] and the Code of very similar regulation levels but it also regulates the
Conduct (CoC) [5] from the European Commission. 10% rated load efficiency, which further emphasizes
the light load efficiency requirement. Besides the
A. Efficiency Standards and Power Density average efficiency, the standard also regulates the
Requirements no-load standby power.
Most AC/DC adapters fall into the external power To meet the stringent efficiency standards, the
supply categories of the efficiency standards. Both the power supply industry implemented different
DoE and CoC have regulated the efficiency for many technologies, such as better semiconductor devices as
years. As summarized in [1], different countries and well as better circuit topologies to reduce the
organizations are regulating the power supply conduction and switching losses. Meanwhile, the
efficiency. The expected energy efficiency level is output rectifier is often addressed with a different
becoming higher with the years. According to the DoE method.

2-1
 Single Voltage External AC/DC fixed voltage of Vf, the conduction loss on the
Power Supply, Basic Voltage diode can be calculated using Equation 1.
Minimum Maximum PDIODE = V f ⋅ IOUT
Nameplate
Output Power
Average Efficiency in Power in (1)
Active Mode (Expressed No-Load From this equation, the diode conduction loss
(POUT)
as a Decimal) Mode (W) is directly proportional to the forward voltage
POUT ≤ 1 W ≥ 0.5×POUT + 0.16 ≤ 0.100 drop of the diode rectifier. Lowering the diode’s
1 W < POUT ≥ 0.071×In(POUT) forward voltage drop can help reduce the loss and
≤ 0.100
≤ 49 W -0.0014×POUT + 0.67 improve efficiency. As shown in Figure 3, the
49 W < POUT forward voltage drop for a Schottky diode is much
Topic 2

≥ 0.880 ≤ 0.210
≤ 250 W
lower than the PN junction diode. Therefore, a
POUT > 250 W ≥ 0.875 ≤ 0.500 Schottky diode is often used to reduce the
Single Voltage External AC/DC conduction loss.
Power Supply, Low Voltage
100
Minimum Maximum
Nameplate

Forwad Current (A)

Average Efficiency in Power in
Output Power
Active Mode (Expressed No-Load 10
(POUT)
as a Decimal) Mode (W)
≥ 0.517×POUT
POUT ≤ 1 W ≤ 0.100 1
+ 0.087
PN Diode
1 W < POUT ≥ 0.0834×ln(POUT)
≤ 0.100 Schottky Diode
≤ 49 W -0.0014×POUT + 0.609
0.1
49 W < POUT 0 0.2 0.4 0.6 0.8 1 1.2 1.4
≥ 0.870 ≤ 0.210
≤ 250 W Foward Voltage Drop (V)
POUT > 250 W ≥ 0.875 ≤ 0.500
Figure 3 – Forward voltage drop comparison
Table 1 – DoE efficiency standard for between PN diode and Schottky diode.
external power supply.
Besides the absolute value of the conduction
A simple flyback converter is show in Figure 2. loss, the conduction loss can be normalized with
The secondary side current is rectified and filtered the output power, so the efficiency impact can be
as the load current. The rectifier is directly in series directly calculated. Due to the other losses in the
with the load. converter, the efficiency impact is approximately
+ Vf - IOUT the ratio between the diode loss and the output
power.
P V f ⋅ IOUT Vf
+ ηDIODE ≈ DIODE = = (2)
VOUT
- P V ⋅I V
LOAD OUT OUT OUT
低输出功率效率要求低的原因
According to Equation 2, at lower output
voltage, the diode drop has a higher impact on the
efficiency. This is part of the reason why the
efficiency standard is lower for a low voltage
power supply.
Figure 2 – Flyback converter and Furthermore, beyond the efficiency impact, the
its output rectifier. designers often face the issue of thermal
management. For example, at 10 A output, the 0.5 V
The flyback converter as well as most of the diode drop causes a 5 W loss and the thermal
power conversion topologies have similar management could be an issue. A large and
architecture, such as forward or LLC converters. expensive heatsink is required.
Since the diode forward voltage drop is roughly a

2-2
 Even though the Schottky diode can help reduce 25

the conduction loss, its forward voltage drop is still

Forward Current (A)

20
relatively high. Besides this, the Schottky diodes
are also limited by the voltage ratings. When the 15
breakdown voltage is above 100 V, the improvement 10
of the Schottky diode becomes less significant.
To further reduce the conduction loss, a 5
synchronous rectifier was proposed to replace the
0
diode rectifier and reduce the conduction loss [6]. If 0 0.1 0.2 0.3 0.4 0.5 0.6
a MOSFET is turned on and off in synchronization Forward Voltage Drop (V)

Topic 2
with the diode rectifier, it can be used to replace the (a) Diode conduction loss model
diode. Instead of a fixed voltage drop, when the
MOSFET conducts, its voltage drop is proportional
to its on-state resistance (RDS(ON)) and the 120
instantaneous current. When the resistance is low

Forward Current (A)

100
enough, the MOSFET can achieve much lower
80
conduction loss. As shown in Figure 4, the
MOSFET’s (CSD18532KCS) [8] forward voltage 60
drop is much lower compared to the Schottky diode 40
SBRT20M60SP5 [7]. Much lower conduction loss
20
and heat is generated if the SR is implemented.
0
100 0 0.2 0.4 0.6 0.8
Forward Voltage Drop (V)
10
(b) SR conduction loss model
Forward Current (A)

1
Figure 5 – Conduction loss model of diode and SR.
0.1
ii
0.01
R
REQ
0.001 Schottky Diode EQ

SR
0.0001
0 0.1 0.2 0.3 0.4 0.5 0.6 V
Vff
Forward Voltage Drop (V)

Figure 4 – Forward voltage drop comparison

of MOSFET and Schottky diode. (a) Diode conduction loss

B. Loss Comparison of Diode and SR

The loss improvement can be calculated based ii
on the loss models of the diode and SR. The
conduction loss models of the diode and SR are R
RDS(ON)
DS(ON)
shown in Figure 5.
For the diode, the blue line is its forward
voltage drop versus the forward current. It can be
approximated by a fixed voltage drop with a (b) SR MOSFET conduction loss
straight line as shown with the red line. This
simple piecewise linear approximation models the Figure 6 – Equivalent circuit
diode conduction loss as a fixed voltage drop in for conduction loss.
series with a resistor, as shown in Figure 6(a).

2-3
 diode. With the loss model, the SR conduction loss
VDIODE ( I ) = V f + I ⋅ REQ (3) is calculated for other conditions and topologies.
0.6
As for the SR, if it is ideally controlled in
synchronization with the current flowing, the SR DIODE

Conduction Loss (W)

can be simplified as a resistor and its forward
0.4
voltage drop can be replaced by

VSR ( I ) = RDS( ON ) ⋅ I (4)
0.2
Topic 2

For the previously mentioned Schottky diode SR

(SBRT20M60SP5), its forward voltage drop is
Vf = 0.328 V, while its equivalent series resistance 0
1 1.5 2 2.5 3
is REQ =8.7 mΩ. For the SR (CSD18532KCS), we
Load Current (A)
can set the loss model parameter as RDS(ON) = 5.3 mΩ.
If we use a DCM flyback as the test circuit, the Figure 8 – Conduction loss of diode and SR.
secondary side current waveform is shown in
Figure 7.
ISEC II. SR Control Methods
Even though a diode has higher conduction
loss, it is essentially a passive device. The turn-on
and -off of the diode is automatic, no dedicated
IOUT control is needed. For the SR, the MOSFET needs
to be turned on and off in sync with the diode
DS TS
conduction. Due to the different topologies and
rectifier operation principles, the SR can be
controlled with different methods.
TS
A. Controlled-Driven and Self-Driven
Figure 7 – DCM flyback secondary side current. In some topologies the SR control can be quite
straightforward. For example, in the synchronous
For the diode, the conduction loss is calculated as buck converter, convert the freewheeling diode
2
PDIODE = V f ⋅ I AVG + REQ ⋅ I RMS into the SR, as shown in Figure 9, the SR QSync
can turn on and off in complement to the control
1 I2 switch QControl.
= V f ⋅ I PK ⋅ DS + REQ ⋅ PK

2 3 ⋅ DS (5)

For the SR, the conduction loss is calculated as

2 I2 QControl
PSR (6)
= RDS( ON ) ⋅ I RMS = RDS( ON ) ⋅ PK
3 ⋅ DS
In these equations IPK is the secondary side QSync
peak current and DS is the secondary side
conduction duty-cycle. For a flyback converter
with 50% secondary side conduction duty-cycle, Figure 9 – Synchronous buck converter.
the losses are shown in Figure 8. The conduction
loss of the SR is significantly less than the Schottky

2-4
 As soon as the control switch QControl turns B. VDS Sensing
off, the inductor flows through the body diode of To prevent the negative current, and be useful
SR QSync as the freewheeling diode. The SR is for more topologies, the SR control based on
turned on as soon as its body diode starts drain-to-source voltage sensing (VDS sensing) is
conducting, normally a short delay after turning proposed [12]. The principle of operation for the
off the control switch. Before turning on the VDS sensing SR control can be simplified as in
control switch, the SR needs to turn off so that the Figure 11.
control switch can force the SR body diode to turn
off. Therefore, the control of the synchronous VTH_ON +

buck converter’s SR does not need complicated

Topic 2
–
S Q VGATE
control schemes except to use the simple dead- VDRAIN
times between control and sync switches. To R Q
+
optimize the SR performance, there should be
appropriate dead-time between the two switches VTH_OFF –

to prevent shoot-through current and minimize the

body diode conduction time [9]. Figure 11 – Simplified SR control diagram.
When moving from the non-isolated topologies
into an isolated topology, such as active clamp The VDS control can be illustrated as in Figure
forward, not only is the control straight forward, 12. When the current starts to flow into the SR
SRs might be able to be driven directly from the body diode, the voltage drop across the SR source-
transformer (self-driven). As shown in Figure 10, to-drain is the body diode forward voltage drop of
the SR control is automatic and no extra control IC a few hundreds of mV. A simple turn-on threshold
is required. VTH_ON can be used to detect the body diode
conduction and turn on the SR MOSFET. As
shown in the waveforms, a short turn-on delay is
observed due to the comparator and gate driver
delays. After the SR turns on, its voltage drop
changes from body diode forward voltage drop
into the RDS(ON) voltage drop. Or, in other words,
the MOSFET on-state resistor becomes a current
sense resistor and its voltage drop directly
represents the SR current. Ideally, setting up a
comparator to compare this voltage drop to zero
Figure 10 – Active clamp forward allows the SR to be turned off at exactly the time
with self-driven SR. when the current is at the zero crossing. However,
due to the tolerance on reference, the comparator
Although these controls are simple and straight delay, gate driver delay, etc., SR is always turned
forward, the control method is basically off later than the instance when the voltage crosses
complementary. Therefore, the inductor current is the threshold. Therefore, the turn-off threshold
kept as continuous conduction. At light load, the VTH_OFF is often set slightly below zero. This way
continuous inductor current flows positively and the SR can be turned off slightly earlier than the
negatively to give the equivalent low load current. current zero crossing. In a later section, this paper
This causes large circulating energy, decreasing will cover how the threshold impacts the turn-off
the efficiency. At light load, the circulating current timing of the SR.
causes large conduction loss and decreases the
light load efficiency. As the emphasis is on the
light load efficiency for different efficiency
standards, these simple control methods need to be
improved [10][11].

2-5
 IDS 0
DCM flyback converter operation waveforms
are shown in Figure 13. In each switching cycle, the
transformer inductor current rises from zero to its
peak value and falls back to zero. Because the
flyback transformer is a coupled inductor, its current
represents the volt-second applied to it. Therefore,
VDS
in each switching cycle, the volt-second also starts
from zero and reaches its maximum value when the
primary side switch turns off. During the secondary
side conduction, the volt-second keeps reducing and
Topic 2

0 VTH_OFF turns back to zero when the secondary side current

VTH_ON reaches zero. The transformer volt-second can be
used to detect the turn-off of the SR. The volt-
Figure 12 – SR operation waveforms
second can be captured through the voltage across
based on VDS sensing.
the SR drain to source [13].
By using the volt-second balancing, the SR
The VDS sensing method is the most versatile
can be turned off at its current zero crossing. It
control method, however, it still has many
senses the voltage across the SR drain-to-source
challenges. Firstly, the sensing circuit needs to
during the off state to calculate the volt-second.
handle the high voltage (SR voltage rating) and
Therefore, it does not require sensing of mV levels
measure very low voltage (a few mV of SR
and is much less sensitive to the noise. The
conduction voltage). This makes the sensing
controller design challenges in this case are fewer.
circuit design costly and challenging. Secondly,
However, it also has some limitations. The
the turn-off threshold needs to be very close to
volt-second balance can only be used for certain
zero. The SR voltage sensing and the comparator
topologies, such as the DCM flyback, the
offset voltage have to be designed accurately.
freewheeling diode in a DCM buck or DCM
Furthermore, the comparator speed needs to be
forward converter. In other topologies, such as a
fast. SR needs to operate in sync with the diode
LLC resonant converter or active clamp flyback,
conduction. If the SR turns off too late, there could
the volt-second is not balanced. In addition, the
be shoot-through current or circulating current,
volt-second can only be guaranteed to be balanced
which will decrease the efficiency of the converter.
in DCM operation. In CCM operation, the volt-
second balancing is only achieved in steady state.
C. Based on Volt-Second Balancing During line or load transients, the volt-second is
Instead of sensing very low voltage, some
not balancing and the SR control cannot be
topologies can use volt-second balancing to
guaranteed. Since VDS sensing does not have these
achieve SR control [13]. One example would be a
limitations, it is a much more versatile control
DCM flyback converter.
method.
SR Drain Positive
Voltage Volt-Second

Negative
Volt-Second

Primary
Side Current

Secondary
Side Current

Figure 13 – DCM flyback SR control

based on volt-second sensing.
2-6
D. Adaptive Control To minimize the body diode conduction time,
For VDS sensing control, as mentioned earlier, an adaptive control method is proposed. Reference
to prevent the SR current from flowing negative at [14] gives one example. As shown in Figure 14,
turn-off, the turn-off threshold needs to be set the SR driver measures the body diode conduction
slightly negative. Considering the component time and feeds it back to the digital controller
tolerances, the SR is always turned off before its UCD3138A. The digital controller can adjust the
current reaches zero. After the SR turns off, the SR conduction time according to the body diode
current continues to flow through its body diode. conduction time information and minimize the
Because the body diode voltage drop is time. In this way, the SR is controlled very closely
significantly higher than the SR drop, much higher to the ideal synchronization with the diode

Topic 2
loss is expected. This gets worse for higher conduction and achieves the best efficiency
switching frequency designs, when the total SR possible.
conduction time is short.

VCC VSOURCE
4.5 to 18 V PGND

UCD3138A
3
DPWM 1 IN VCC
VD 5 D

DTC UCD7138
2 DTC
Module
G
OUT 4
Thermal Pad
6 CTRL (GND)
DGND S

PGND

(a) Circuit diagram

VDS

Adjust
SR
Control
Body Diode
Conduction
Minimize Body Minimize Body
SR Diode Conduction Diode Conduction
Gate

Turn on Turn off

Delay Delay

(b) Operation waveforms

Figure 14 – Adaptive control for SR.

2-7
 III. Design Challenges ISR
for SR Control IOFF
SR is an effective way of reducing the
conduction loss of power converters, improving
efficiency and thermal management. Detailed VDRAIN
consideration and trade-offs are required to allow
correct SR operation, optimize the performance
and cost, as well as power management and EMI VTH_OFF
handling. In this section, the design challenges are
Topic 2

discussed in detail. Vf

A. SR MOSFET Selection
From the loss analysis, the conduction loss VGATE
reduction is significant. The SR conduction loss is
proportional to its on-state resistance (R DS(ON)). (a) Lower R DS(ON) SR
Based on the equation, if the SR R DS(ON) becomes
zero, the conduction loss is zero and the converter ISR
efficiency is maximized. Unfortunately, the reality
IOFF
is that this is not the right solution. Not only does
the extremely low R DS(ON) device require much
higher costs, it also introduces other issues and VDRAIN
eventually hurts the efficiency [15].
The first issue is the body diode conduction.
As mentioned earlier, to prevent negative current
VTH_OFF
and in consideration of the component tolerances,
the SR controller often sets the turn-off threshold
slightly lower than zero, instead of right at zero. Vf
This forces the SR to turn off before its current
reaches zero. Without considering other effects, VGATE
the turn-off current can be calculated as

VTH ( OFF ) (b) Higher RDS(ON) SR

(7)
IOFF =
RDS( ON ) Figure 15 – DCM flyback using different SRs.
In this equation, for a selected SR controller,
Let’s use a 3 A DCM flyback design with a
the turn-off threshold VTH(OFF) is a fixed value.
50% secondary side conduction time as an
Lowering the R DS(ON) causes higher turn-off
example. The circuit parameters are summarized
current. Figure 15 is an example of a DCM flyback
in Table 2. The lower R DS(ON) MOSFET causes
converter using different R DS(ON) SRs.
higher conduction loss, even though it gets much
For the lower R DS(ON) SR, with the same turn-
less conduction loss when the SR is on.
off threshold, the turn-off current is much higher
compared to the higher R DS(ON) SR. The
conduction loss at the SR turn-on portion is lower
because of the early turn-off and the body diode
conduction time being longer. The SR overall
conduction loss could be higher.

2-8
 High High
RDS(ON) SR RDS(ON) SR PSR
= PCON + PSW + PDRV (8)
SR peak In this equation, PCON is the conduction loss,
12 A 12 A
current
PSW is the switching loss, including the junction
Turn-off threshold -5 mV -5 mV
capacitor loss and the reverse recovery loss, and
SR RDS(ON) 5 mΩ 1 mΩ PDRV is the driving loss.
Body diode forward The conduction loss portion was discussed
0.5 V 0.5 V
voltage drop
earlier in this paper. The selection of the MOSFET
Turn-off needs to consider both the conduction loss of the
1A 5A
current

Topic 2
SR conduction and body diode conduction.
Body diode conduction
4.2% 20.8% For the switching loss, it includes the capacitive
duty
loss and reverse recovery loss, if the converter is
RDS(ON) conduction loss 0.12 W 0.022 W
operating in CCM. If the converter is operating in
Body diode conduction loss 0.01 W 0.26 W
DCM condition, the loss can be simplified as the
Total conduction loss 0.13 W 0.282 W capacitive loss (COSS loss). For a flyback converter,
Table 2 – Design examples of different due to the hard switching turn-on of the primary
SR for DCM flyback. side switch, every time the switch turns on, it
discharges the switch node capacitor. In the
The curve in Figure 16 shows the relationship meantime, it charges the SR drain-to-source
between the conduction loss and different R DS(ON). voltage to its maximum value. Therefore, the
At the beginning, when reducing the R DS(ON), the switching loss associated with a SR junction
conduction loss gets lower, while the body diode capacitor is calculated as
conduction loss keeps increasing. There should be 1 2
PSW = COSS( eq ) ⋅VDS ⋅ f SW (9)
an optimal design point, based on the minimum 2
conduction loss, that gives the tradeoff between In Equation 9, the worst case is considered
the SR conduction and body diode conduction, for where the SR voltage is charged from zero to full
a given design. drain-to-source voltage. For a flyback converter
0.3 operating in DCM mode, if the DCM ring is
completely damped out, the SR voltage is charged
0.24 from output voltage to its maximum voltage and
Conduction Loss (W)

Equation 9 changes into Equation 10.

0.18 ⎛⎛ V 2 ⎞
1 ⎞
SR Conduction Loss Conduction Loss 2
PSW = COSS( eq ) ⋅ ⎜ ⎜ IN + VOUT ⎟ − VOUT ⎟ ⋅ f SW (10)
by RDS(ON) 2 ⎜⎝ ⎝ N PS ⎠ ⎟⎠
0.12
In this equation, COSS(eq) is the energy based
0.06 equivalent output capacitance, VIN is the flyback
Conduction Loss
by Body Diode
input voltage, N PS is the flyback transformer
0 primary to secondary side turns ratio, VOUT is the
1 2 3 4 5 6 7 8 9 10
output voltage and f SW is the switching frequency.
RDS(ON) (mΩ)
It is clear that the switching loss is directly
Figure 16 – Conduction loss for different R DS(ON) proportional to the SR equivalent output
(assuming 3 A output current, 50% secondary capacitance. Larger SR MOSFETs (lower R DS(ON))
side conduction duty-cycle, -5 mV turn-off have higher capacitance and in turn create higher
threshold and 0.5 V body diode voltage drop). switching losses. Depending on the ratio between
conduction loss and switching loss at heavy loads,
The design optimization shown in Figure 16 often the conduction loss dominates. At lighter
only considers the conduction loss. The overall loads, the switching loss becomes a more significant
loss of the SR can be summarized in Equation 8. portion of the loss. Simply reducing the R DS(ON) of

2-9
 the SR could result in less conduction loss at a B. Handling CCM Operation
heavy load but more switching loss on the lighter Previous discussions have mainly focused on
load. the DCM operation and the reverse recovery loss
Furthermore, the SR loss also includes the is ignored. Converters operating in CCM mode
driving loss. Unlike a diode, the MOSFET needs to help to reduce the conduction loss and achieve a
be turned on and off in each switching cycle as the smaller transformer size, and it is widely used in
SR gate voltage is charged and discharged. The different designs. Before the SR turns off, the
loss associated with a gate driver is calculated in CCM operation mode gives a much higher current
Equation 11. As with the COSS, the input capacitance slew rate in comparison to the DCM operation. As
also gets bigger with a lower R DS(ON) MOSFET. a result, the VDS sensing based SR control often
Topic 2

2 (11) encounters the shoot-through issue.

PDRV = C ISS ⋅VDRV ⋅ f SW
When considering all the losses, conduction, ILM
switching and driving losses as illustrated in
IPRI
Figure 17, the overall performance has higher
efficiency at a heavy load, but less efficiency at a 0
lighter load for the low R DS(ON) MOSFET.
ISEC di
High RDS(ON) SR
dt
0

(a) Flyback converter

Efficiency

Low RDS(ON) SR

IL(OUT)
IOUT

Load
0
Figure 17 – Converter efficiency with different SRs.
ICNTL
When the power supply is designed, efficiency
has two significant constraints, thermal 0
considerations and standards requirements. The ISYNC
di
converter must be efficient enough to manage the
dt
thermals and be higher than the efficiency standard 0
requirement. As described in the introduction, the
efficiency standard regulates the average (b) Forward converter
efficiency, instead of full load efficiency alone.
The power supply designer should optimize the ILR
design to deliver the lowest cost solution while
ILM
meeting the standard. Even though the lower 0
R DS(ON) MOSFET gives better efficiency at a
heavy load, if it results in less efficiency at lighter ISEC
loads and gives similar average efficiency, the di
higher R DS(ON) MOSFET should be chosen to get 0
dt

lower system costs. The selection of the SR is an

iteration process that looks at the trade-off between (c) LLC converter
cost and performance, instead of just simply
assuming the lower R DS(ON) MOSFET gives the Figure 18 – Current slew rate for different
better performance [15]. converters operating in CCM mode.

2-10
 Converter Slew Rate

VIN di VOUT
VO + =
Flyback converter di N PS dt LM / NPS2
=
dt LLK di VOUT +VIN / NPS
=
dt LLK / NPS2
VIN
Forward converter di N PS (a)
=
dt LLK

Topic 2
VIN + VCR (b) (c)
VO +
di N PS
LLC converter =
dt LR
2
N PS
t0 t1
Figure 19 – Zoom in details of
Table 3 – Slew rates for different converters SR operation in CCM.
operating in CCM mode.

Figure 18 summarizes the current slew rating in LLK NP:NS

CCM conditions for different circuit topologies. It is
observed that all the slew rates (di/dt) are determined LM VOUT
by the leakage or the resonant inductance. Normally, VIN
the circuit designer tries to minimize the leakage to di VOUT
improve the transformer efficiency. A smaller leakage =
dt LM / NPS2
inductor forces the di/dt higher and introduces extra
design challenges. Using CCM flyback as an example, (a) t<t0
the issue associated with the high current slew rate is
illustrated in Figure 19. Before the primary side
LLK NP:NS
switch turns on, the SR keeps conducting and the
magnetizing inductor discharges with the slew rate as
shown in Equation 12 and in (a) of Figure 20. In this LM VOUT
equation, LM is the magnetizing inductor and NPS is VIN
the transformer primary to secondary side turns ratio.
di VOUT +VIN / NPS
It should be noted that the current decreasing rate is =
dt LLK / NPS2
determined by the output voltage and the magnetizing
inductor reflected to the secondary side. (b) t0<t<t1
di
V (12)
= OUT2
dt LM / NPS LLK NP:NS
Once the primary side switch turns on, the
secondary current is still positive and it takes time for LM VOUT
the current to reach zero. During this period, the VIN
current slope changes to Equation 13. In this equation,
the voltage increases to the summation of the output di VOUT +VIN / NPS
=
voltage and the reflected input voltage and the inductor dt LLK / NPS2
changes into the leakage inductor reflected on the (c) t>t1
secondary side. Due to the higher voltage and much
lower inductance, the current slew rate is much higher. Figure 20 – Equivalent circuit at different
di VOUT +VIN / NPS (13) stages of SR operation in CCM.
=
dt LLK / NPS2

2-11
 For example, a 15 W, 5 V/3 A output design with QRR is the reverse recovery charge, VST is the
a 1 mH magnetizing inductor and 3% leakage, shoot-through voltage, which in the flyback case
NPS=15, at 165 VDC input, equivalent to the peak of is the output voltage plus the reflected input
the 115 VAC line, at the inductor discharge portion, voltage, and fSW is the switching frequency. To
the current slew rating is only 1.125 A/µs. During the minimize the reverse recovery loss, the only
CCM transition edge, the current slew rate becomes choice is to choose a diode with less reverse
120 A/µs, which is more than 100 times higher than recovery charge or a short reverse recovery time.
the inductor discharge portion.
The issue associated with the high di/dt is the SR PRR
= QRR ⋅VST ⋅ f SW (14)
controller turn-off delay. In CCM operation, during
Topic 2

Since the delayed SR turn-off is equivalent to

the inductor discharge portion, due to the large
the diode reverse recovery, to minimize this effect
conduction current, the SR turn-off threshold is not
there are several choices. As shown in Figure 22(a),
reached yet. SR is turned off at the fast transition
after SR turns off, because the current is still flowing
edge. Because of the comparator and gate driver
in the same direction, the current automatically
propagation delay, the SR can only be turned off 10
shifts from the SR channel to its body diode. This
to 20 ns later after the VDS crosses the turn-off
way, even though it avoids the shoot-through caused
threshold. With 120 A/µs current slew rate, the
by the delayed turn-off, the reverse recovery of the
10~20 ns delay means 1.2 A~2.4 A reverse current.
body diode still introduces a large amount of loss.
This is quite similar to the reverse recovery of a
Another option is to have the SR controller turn off
diode. The reverse recovery behavior of a diode is
the SR as fast as it can, as shown in Figure 21(b). In
shown in Figure 21. During the reverse recovery
this case, the reverse recovery is caused by the SR
time, TRR, diode current flows negatively and causes
turn-off delay. Due to the slow SR body diode, the
the shoot-through current [16]. When the diode
fast turn-off often provides better performance.
current is positive, the voltage drop across the diode
is its forward voltage drop. When the diode current Reverse
crosses zero, it cannot block the voltage immediately. QRR
Recovery Loss
During the tA portion of the reverse recovery time, Diode 1 @ 30 V VDS 127 nC 0.381 W
TRR, the diode voltage drop is still its forward voltage. Diode 2 @ 75 V VDS 385 nC 2.887 W
The diode can only start to block the voltage during
the tB portion of the reverse recovery time. The tA Table 4 – Diode reverse recovery loss estimation.
portion of the diode reverse recovery is equivalent to
the SR turning off late for same amount of time. SR Current

if Body Diode
Current
TRR
If tA tB Body Diode
Reverse Recovery
SR Gate
0 t
25% of IRM
Vf
IRM (a) SR turns off too early
Vf
0 t
SR Current

Figure 21 – Diode reverse recovery current. Body Diode

Current

The loss caused by the diode reverse recovery

can be quantified based on its reverse recovery SR Gate

charge QRR. Table 4 summarizes two different

diodes with different QRR and different voltage
during shoot through. The reverse recovery loss is (b) SR turns off too late
calculated based on Equation 14. In this equation, Figure 22 – Different SR timing in CCM operation.
2-12
C. Dealing with Noise same principle, the turn-off blank time can be used
The VDS sensing-based SR control senses the to avoid false turn-on at the DCM ring. After the SR
voltage across the drain-to-source and detects the is turned off, it cannot turn on again during the turn-
current direction. Because the SR RDS(ON) is used as off blanking time. The turn-off blanking time should
a current sensing resistor, the turn-on and -off be at least one DCM ring cycle to avoid the false
threshold is quite low. The low threshold makes the turn-on. The turn-off blanking time should not be so
controller more sensitive to the noise and some big that it cuts into the SR normal conduction time.
blanking times are required for proper SR operation Some ICs allow the user to adjust this blanking time
[12]. and achieve the balance between noise immunity
Continuing to use a flyback converter as an and normal operation [12].

Topic 2
example, Figure 23 shows that at the SR turn-on
edge the primary side leakage is resetting and large
voltage ringing can be observed on the primary side
switch node and SR drain voltages. Without proper
blanking, the SR voltage could reach the turn-off
threshold with this ringing and cause short SR
conduction.
During the DCM operation, after the SR turns
off, large voltage ringing is observed on both the t (2 µs)
primary side switch node and SR drain. If there is no (a) SR turn-on noise
damping, the SR drain voltage should resonate
centered at the output voltage with the output voltage
as the resonant amplitude. This large resonance
could potentially pass the SR control turn-on
threshold on the first or second resonant ring. If the
SR turned on at the DCM ring, not only does it
discharge the output energy into the transformer,
causing extra efficiency loss, it will also extend the
ringing duration and make the EMI noise worse.
To prevent false turning on and turning off, the t (2 µs)
blanking times are essential. Figure 24 illustrates the (b) SR turn-off noise
operation principles of blanking times. After the SR
turns on, the turn-off of SR is prohibited until after
Primary Switch Node (100 V/div)
the turn-on blanking time expires. If the turn-on SR Drain (10 V/div) SR Gate (5 V/div)
blanking time is longer than the leakage reset time,
or allows the ringing voltage to dampen out, the SR Figure 23 – Noise associated with
control can avoid the false turn-off. Following the SR turning on and off.

(A), (V)
Turn-On Ringing

ISEC

(t)
VDS
Resonant Ringing

Figure 24 – Blanking times for proper SR control.

2-13
 D. Special Current Shape VSENSE = VSR + VLD + VLS
Besides avoiding the false turn-off at the (15)
⎡ dI ⎤
beginning of the SR conduction, the minimum = − ⎢ I SR ⋅ RDS (ON ) + ( LD + LS ) ⋅ SR ⎥
on-time also helps to deal with the special current ⎣ dt ⎦
shape, such as is observed in LLC resonant
coverters. As shown in Figure 25, the SR current VSENSE
has a sinusoidal shape. Following the operation
principle of VDS sensing, after the current flows VSR
through the body diode, the SR control turns on
the SR with a short delay. After that, the SR starts
Topic 2

+ LD - SR + LS -
to conduct and due to the sinusoidal current shape,
the SR current remains low. Since the SR current ISR
is small, the voltage drop could reach the turn-off - +
threshold easily and causes the SR to prematurely (a) SR with parasitic inductor
turn off. To allow SR conduction with a full
conduction angle, the minimum on-time can be
used to force the SR on until the SR current ISR
reaches the high level. In this way, premature turn-
off can be avoided.
IDS 0 VSR

VSENSE ~
~ ~
~ ~
~
VDS SR Gate Drive

0 VTH_OFF (b) SR voltage and controller sensed voltage

VTH_ON

Figure 26 – Parasitic inductor impact

Figure 25 – LLC resonant SR waveforms.
on the VDS sensing.
E. Parasitic Inductor Impact From Equation 15, the effects of the parasitic
In the previous discussion, after the SR turns inductance are seen. When dISR/dt is positive, the
on, the voltage drop across the SR is considered as voltage drop across the inductor is of the same
pure IR drop from the SR MSOFET RDS(ON). polarity as the resistive drop, and the voltage across
Depending on the SR MOSFET package, the SR appears as higher current flowing through the
voltage across the SR not only includes the voltage SR. On the other end, when the dISR/dt is negative,
from the resistive drop, but also from the voltage the voltage drop across the inductor adds onto the
drop across the parasitic inductance. The parasitic offset voltage in reverse polarity, compared to the
inductance can be the contribution from both the resistive drop, and the sensed voltage appears to
trace inductance from the layout and the package have less current flowing through the SR.
inductance. The inductor caused by the trace As illustrated in Figure 26(b), for a LLC
inductance can be eliminated with a proper layout. resonant converter SR, when the current slew rate
However, the package inductance cannot be is positive, the sensed SR voltage appears to have
eliminated [17][18]. more voltage drop and when the current slew rate
Figure 26(a) shows the SR voltage drop with is negative, the sensed SR voltage appears to have
the package inductances. For the SR controller, it less voltage drop. The decreased voltage drop
senses the voltage, VSENSE, which is the could cause the SR controller to make the wrong
combination of voltage across the RDS(ON) (VSR) decision and turn on the SR early.
and the voltage across the drain inductance (LD) Let’s look at an example. For a LLC resonant
and source inductance (LS). The sensed voltage is converter, assuming it operates at the resonant
calculated using Equation 15.

2-14
 VGS-VTH
frequency and the SR current can be approximated 7V
as a sinusoidal waveform, the SR current in each
SR can be written as in Equation 16.

Drain to Source Current

6V
π
I SR ( t ) = ⋅ IOUT ⋅ sin ( 2πt ) (16) 5V
2
For a 10 A output current, at 100 kHz switching 4V
frequency, the current slew rate varies from -10 A/µs 3V
to 10 A/µs. If we choose 5 A/µs as the operation 2V
1V
point, for a typical TO-220 package with an

Topic 2
0 2 4 6 8 10
inductance of about 12 nH, the di/dt could cause Drain to Source Voltage (V)

60 mV offset. This is much higher than the turn-off

Figure 27 – SR MOSFET V-I
threshold and would cause the SR to turn off much
characteristic curves.
too early. This offset gets much worse if the di/dt is
higher, such as in higher power or higher frequency
drop. The SR behaves likes a diode with a much
designs. To avoid the SR early turn-off caused by
lower voltage drop in this period. Since the voltage
the package inductor, a MOSFET package with less
drop is fixed, it becomes higher than the resistive
package inductance is preferred. Besides, the smaller
drop and causes more loss. However, the sacrifice
package inductance MOSFETs can be used in
on the conduction loss brings a few benefits. The
parallel with the high package inductance MOSFET
SR control with proportional gate drive is shown in
as a sensing FET to reduce the impact from the
Figure 28. First, this regulation allows longer
package inductance.
conduction time for the lower RDS(ON) SR MOSFET,
Drain Source even with the offset voltage caused by the package
MOSFET inductance. Because of reduced body diode
Inductance Inductance
Package conduction time, it could help the converter
(LD) (LS)
TO-220 [19] 4.5nH 7.5nH efficiency. Second, during the proportional gate
D2PAK [20] 3.5nH 7.5nH
drive activated region, the SR gate voltage is very
close to its threshold. For CCM operation, this
DPAK [21] 0.0164nH 2.85nH
allows the SR to be turned off fast without
SO-8FL [22] 0.005nH 1nH
considering the time delay from discharging the
Table 5 – Typical SR MOSFET gate voltage to the threshold voltage. This helps to
package inductance. minimize the shoot-through and improve the
performance in CCM operation [23].
F. Proportional Gate Drive VDS
Besides using smaller package inductance, the
early turn-off can also be mitigated by using the ISD
proportional gate drive.
When the SR is driven with voltages much
higher than its threshold voltage, its voltage drop is t
proportional to its on-state resistance. When the gate VTHREG VTHVGOFF
driver voltage is reduced, the voltage drop across the VTHVGON
SR could be much higher for the same drain current,
as shown in Figure 27. VGATE

Instead of fully turning on the SR all the time, 90%

the SR gate voltage can be reduced when the SR
10%
current level is low. The SR gate voltage is
tR_VG t
controlled so that the voltage across the SR tdVGON
becomes a fixed voltage drop, instead of an I-R
Figure 28 – Proportional gate drive.

2-15
 G. EMI Noise Considerations When the rectifier is in the negative path, as
For a simple flyback converter, the output shown in Figure 29(b), there is no current flowing
rectifier can be located on the positive side, as through C1 because both sides of C1 have a stable
shown in Figure 29(a), or the negative side, as voltage potential. In this case, the primary side node
shown in Figure 29(b). From the operational point steps up and the secondary side rectifier cathode
of view, these two rectification methods make no steps down. This causes much higher current flowing
difference, but they have EMI noise behaviors. through C2. With higher capacitor current and no
current to cancel it out, the common mode EMI
LINE
noise is expected to be worse.
0.25 µF
C1 The same analysis can be applied to the SR case
Topic 2

50 Ω and draws the same conclusion. Even though the

INOISE common mode EMI noise performance for the SR
CBULK C2
located in the negative path is worse, because the SR
50 Ω
controller can be easily powered up and drive the SR
0.25 µF
C3 MOSFET, it is still an attractive solution. The power
NEUTRAL supply designers need to use other EMI mitigation
methods, such as the cancelation winding, EMI
(a) Flyback with high-side rectification
filters, etc., to address the EMI noise challenge [24].
LINE

0.25 µF
H. Bias Power Considerations
C1
Unlike the diode rectifier, the SR MOSFET
50 Ω
needs to be actively controlled. How to power up the
INOISE
C2
controller and drive the SR MOSFET becomes a
CBULK
50 Ω new challenge for power supply designers.
0.25 µF
As shown in Figure 30, the SR can be directly
C3
driven when it is on the negative path; this is also
NEUTRAL called low-side configuration since the SR is located
on the low-side. In this way, the SR source, controller
(b) Flyback with low-side rectification
ground and output negative bus are sharing the same
node. Because of the common ground, the IC is less
Figure 29 – Natural EMI noise
sensitive to noise. Furthermore, the SR controller
cancellation of flyback converter.
can be directly powered by the output voltage, if the
output voltage is within the IC power supply range.
The EMI noise, especially the common mode
This provides the most efficient path to power up the
EMI noise, is largely affected by the circuit
controller IC. However, as mentioned in the previous
parameters. As shown in Figure 29(a), the common
section, when SR is located on the positive path
mode noise measured by the LISN 50 Ω resistor is
(high-side configuration), there is some common
generated by the primary side switch node voltage
mode EMI noise benefit.
fluctuation. For the rectifier located on the positive
LLK
side, when the switch node steps high, the positive NP:NS
dv/dt causes a pulse current flowing from the
primary to secondary side through the parasitic LM VOUT
VIN
capacitor C2. At the same time, when the switch
node steps up, the node on the rectifier anode also
steps high. This causes a pulse current flowing from
VD VG VS
the secondary side to primary side through the VDD
parasitic capacitor C1. Since the currents flowing
through C1 and C2 are in reverse polarity, they SR Controller
(UCC246XX)
cancel each other and result in less common mode
EMI noise. Figure 30 – Low-side SR configuration.

2-16
 The first challenge of the high-side configuration The auxiliary winding voltage is basically the
design is the SR controller ground is now connecting output voltage reflected on it. Therefore, the
on the secondary side switch node. The high dv/dt controller operates very similarly to be directly
can cause noise and affect the IC operation. The powered from the output voltage.
design needs to be carefully done and the copper Another method is to power the controller
area of the IC ground path needs to be minimized. from the SR drain. The drain voltage is filtered out
Besides the switch node noise, powering up the as a voltage source and powers up the controller.
IC also becomes a challenge. As illustrated in Figure There are several limitations to this method. First,
31, the SR controller can be powered through the the voltage level changes with the input voltage
auxiliary winding, the RCD circuit or the pulse and load condition. For a flyback converter, the SR

Topic 2
linear regulator. drain voltage is the sum of the output voltage and
SR Controller the reflected input voltage. When the input voltage
(UCC246XX)
VDD
changes, especially for the universal input voltage
VS VG VD range, the drain voltage has large variations. The
LLK NP:NS
RC filter could also get the average voltage across
the SR drain, and reduces the voltage variation. In
LM VOUT the meantime, the average voltage is largely
VIN affected by the converter load condition. Often, the
circuit needs a Zener clamp to help limit the
voltage range. The voltage variation is addressed
through the pulse linear regulator shown in Figure
(a) Aux winding
31(c). Since the pulse linear regulator gate is
clamped by the Zener voltage, its output is a well-
SR Controller
(UCC246XX) regulated voltage regardless of line and load
conditions.
VDD
In addition to the voltage variation, the power
VS VG VD
conversion efficiency is worse when the SR
LLK NP:NS
controller is powered from the SR drain. For a
LM VOUT typical 20 V output flyback converter, assume 4:1
VIN transformer turns ratio, 1 mA of controller current
and 23 nC of gate charge switching at 100 kHz.
When the input voltage is 325 V, which is
equivalent to 230 V AC peak, the total charge
required for the SR operation in each switching
(b) RCD circuit
cycle is
SR Controller
(UCC246XX) I IC 1 mA
QCYC = + QG = + 23 nC = 33 nC (17)
f SW 100 kHz
VDD
VS VG VD The total power consumed from the SR drain is
LLK NP:NS
PCNTL = QCYC ⋅VDS ⋅ f SW
LM VOUT ⎛V ⎞
= QCYC ⋅ ⎜ IN + VOUT ⎟ ⋅ f SW = 0.334W (18)
VIN
⎝ N PS ⎠

At the same time, if the SR is located on the

low-side and the IC is powered from the output,
(c) Pulse linear regulator the IC power consumption is
Figure 31 – Different methods of PCNTL = QCYC ⋅VOUT ⋅ f SW = 66mW (19)
powering high-side SR.

2-17
 Comparing Equations 18 and 19, the low-side No-load consumption score chart
configuration gives much lower power Five stars = most energy efficient
consumption and better efficiency. The power ≤ 0.03 W
supply designers have to pick the trade-off
> 0.03 W to 0.15 W
between EMI noise and the power consumption.
> 0.15 W to 0.25 W
I. Standby Mode > 0.25 W to 0.35 W
As discussed earlier, the efficiency standard not > 0.35 W to 0.5 W
only demands higher average efficiency, it also No Stars > 0.5 W
limits how much power the power supply consumes
Topic 2

in standby mode when there is no load connected. Figure 32 – Five-star standby power.
Even though the standard is quite loose, 75 mW for
CoC and 100 mW for DoE for power supplies less UCC24610. The SR conduction time is compared
than 75 W, some other applications, such as cell with a fixed time. If the SR conduction time is
phone chargers, are demanding much lower standby smaller than the minimum conduction time, the
power. As shown in Figure 32, the cell phone controller detects it as a low load condition and
industry is looking for solutions that provide less puts the SR controller into low power mode,
than 30 mW standby power to achieve a five-star reducing its power consumption. It continuously
rating [25]. In general, when the analog IC is in monitors the SR conduction time and resumes
active mode, it consumes roughly 1~2 mA of current. normal operation when the SR conduction time
With a 5 V output, that is 5~10 mW, which is a big becomes longer than the pre-set minimum
portion of the 30 mW standby power. This is the conduction time. The key design consideration of
same for other applications, such as notebook this control method is that the controller cannot be
adapters: for a 20 V output, 1 mA of IC current woken up in the middle of a switching cycle.
consumption results in a 20 mA load that makes The time-based standby mode detection works
meeting the 75 mW standby power mode a challenge. well when the conduction time is proportional to
To lower the SR controller power consumption, the load. With the higher efficiency requirement
the SR controller needs to have built-in intelligence for the light load, the latest controllers use burst
and enters low power mode during standby mode to mode to improve the light load efficiency. The
consume minimum current. The SR controller needs burst mode forces the converter to operate in the
to maintain its intelligence so that it can resume on/off mode. During the on-period, the converter
normal operation when the load is back to the operates with higher power and higher efficiency.
normal level. During the off-period, the converter consumes no
The load level detection can be implemented power. In this way, the converter maintains higher
through the SR conduction time-based or SR efficiency at a lighter load. The converter power is
switching frequency-based methods. adjusted through the ratio between the on-period
Figure 33 illustrates the SR conduction time- and off-period. Because of the burst mode control,
based standby mode detection, as implemented in the SR conduction time is no longer related to the
load level at burst mode.

(A),
(V)
VDS VDS VDS VDS
ISEC
ISEC ISEC
ISEC
VTH_OFF (t)

GATE Output
TON Blanking
Light-Load Mode

Figure 33 – SR conduction time-based standby mode detection.

2-18
 Low Average Switching Frequency High Average Switching Frequency

SR Drain
at Burst

STB Mode SR Driver Disabled SR Driver Enabled

Topic 2
Figure 34 – Switching frequency-based standby mode detection.

To allow the standby mode detection without Using analysis on different control methods
using the SR conduction time, the switching and design considerations, Figure 35 shows the
frequency-based method was proposed and voltage drop and current for the diode rectifier and
implemented in UCC24630. The control principle the SR rectifier. From these waveforms, the turn-
is based on the average switching frequency of the on ringing, the early turn-off and the loss reduction
converter. When the average switching frequency are observed by comparing the SR with the diode.
is lower than the preset threshold, the converter
power level is low enough to enter the standby
mode. In burst mode, the power level is related
more to the average switching frequency than the
SR conduction. The switching frequency-based
standby mode detection works more reliably for
the burst mode control.

IV. Design Example

The UCC28740 EVM was used to demonstrate
the efficiency improvement by using a synchronous
rectifier. The key circuit parameters of
UCC28740EVM-525 [26] are summarized in Table 6. (a) Diode rectification
The original EVM used two SBR10U45SP5 diodes in
parallel as the output rectifier. The SR MOSFET
CSD19531Q5A has 5.3 mΩ RDS(ON) at 10 V VGS.
Parameter Test Conditions Min Nom Max Units
Input Characteristics
Voltage 85 115/ 265 VRMS
range, VIN 230
Line 47 60/ 63 Hz
frequency 50
Output Characteristics
Output VINmin≤VIN≤VINmax, 4.85 5 5.15 V
voltage, 0 A≤IOUT≤IOUTmax
VOUT
Output load VINmin≤VIN≤VINmax 1.995 2.1 2.205 A (b) SR rectification
current,
IOUTmax
Figure 35 – Voltage and current for different
Table 6 – UCC28740EVM-525 electrical rectification methods.
performance specifications.

2-19
 The efficiency performance using the diode VI. References
rectifier and synchronous rectifier are summarized
in Figure 36. Around a 3% efficiency gain as well [1] CUI Inc., “Efficiency Standards for External
as much higher overall efficiency is observed by Power Supplies,” Aug. 2016, http://www.cui.
using a synchronous rectifier. com/catalog/resource/efficiency-standards-
for-external-power-supplies.pdf.
[2] US Department of Energy, “2014-02-10
Energy Conservation Program: Energy
Conservation Standards for External Power
Supplies; Final Rule,” https://www.
Topic 2

regulations.gov/document?D=EERE-2008-
BT-STD-0005-0219.
[3] US Department of Energy,“2015-08-25
Energy Conservation Program: Test
Procedures for External Power Supplies;
Final rule,” https://www.regulations.gov/
d o c u m e n t ? D = E E R E - 2 0 1 4 - B T-
TP-0043-0023.
(a) Efficiency performance comparison [4] US Department of Energy,“2013-09
International Efficiency Marking Protocol
for External Power Supplies Version 3.0,”
h t t p s : / / w w w. r e g u l a t i o n s . g o v /
d o c u m e n t ? D = E E R E - 2 0 0 8 - B T-
STD-0005-0218.
[5] European Commission, “Code of Conduct
on Energy Efficiency of External Power
Supplies - Version 5,” Oct. 29. 2013,
https://e3p.jrc.ec.europa.eu/sites/default/
files/documents/publications/code_of_
conduct_for_eps_version_5_-_final.pdf.
[6] Blake, C; Kinzer, D; Wood, P, “Synchronous
rectifiers versus Schottky diodes: a
(b) Efficiency gain by using SR
comparison of the losses of a synchronous
Figure 36 – Efficiency performance summary. rectifier versus the losses of a Schottky diode
rectifier,” 9th Annual Applied Power
V. Summary Electronics Conference and Exposition
With the demand for higher efficiency and Conference Proceedings 1994, Vol. 1, pp. 17
higher power density, replacing the rectifier diode - 23, 1994.
with a synchronous rectifier provides an easy and [7] Diodes Inc., SBRT20M60SP5 datasheet,
straight forward method to reduce the conduction https://www.diodes.com/assets/Datasheets/
loss and improve the efficiency. With different SBRT20M60SP5.pdf.
control methods, the VDS sensing-based control [8] Texas Instruments, CSD18532KCS
method is the most popular one. This paper datasheet, www.ti.com/lit/ds/symlink/
discussed the different design challenges of SRs csd18532kcs.pdf.
and SR control, including the SR FET selection, [9] Texas Instruments, UCC27223 datasheet,
noise immunity, standby mode detection, etc. All http://www.ti.com/lit/ds/slus558/slus558.pdf.
this analysis helps to pick the correct SR and SR
control for more efficient power supplies.

2-20
[10] King, Brian and Strassser, David, [19] Vishay Intertechnology, Inc., I R F I Z 4 4 G
“Incorporating Active-Clamp Technology to datasheet, http://www.vishay.com/
Maximize Efficiency in Flyback and Forward docs/91189/91189.pdf.
Designs,” 2010 Texas Instruments Power [20] ON Semiconductor, MTD3055VL datasheet,
Supply Design Seminar, https://www.ti. http://www.onsemi.com/pub/Collateral/
com/seclit/ml/slup262/slup262.pdf. MTD3055VL-D.PDF.
[11] Jovanovic, M. M.; Zhang, M. T.; Lee, F. C., [21] ON Semiconductor, NTD4906N datasheet,
“Evaluation of synchronous-rectification https://www.onsemi.com/pub/Collateral/
efficiency improvement limits in forward NTD4906N-D.PDF.
converters,” IEEE Transactions on Industrial

Topic 2
[22] ON Semiconductor, NTMFS4955N
Electronics, Vol. 42, Issue 4, pp. 387 – 395, datasheet, http://www.onsemi.com/pub/
1995. Collateral/NTMFS4955N-D.PDF.
[12] Texas Instruments, UCC24610 datasheet, [23] Texas Instruments, UCC24612 datasheet,
http://www.ti.com/lit/ds/symlink/ucc24610. http://www.ti.com/lit/ds/symlink/ucc24612.
pdf. pdf.
[13] Texas Instruments, UCC24630 datasheet, [24] Li, Yiming; Zhang, Huan; Wang, Shuo;
http://www.ti.com/lit/ds/symlink/ucc24630. Sheng, Honggang; Lakshmikanthan,
pdf. Srikanth; Chng, Choon Ping, “Techniques of
[14] Texas Instruments, UCD7138 datasheet, the modeling, measurement and reduction of
http://www.ti.com/lit/ds/symlink/ucd7138. common mode noise for a multi-winding
pdf. switching transformer,” 2017 IEEE Applied
[15] Infineon Technologies, “Optimum MOSFET Power Electronics Conference and
Selection for Synchronous Rectification,” Exposition (APEC), pp. 2511 – 2518, 2017.
https://www.infineon.com/dgdl/Infineon+- [25] King, Brian and Valley, Rich, “Control
+Application+Note+-+PowerMOSFETs+- Challenges for Low Power AC/DC
+OptiMOS%e2%84%a2+-+Optimum+MOS Converters,” 2014 Texas Instruments Power
FET+Selection+for+Synchronous+Rectifica Supply Design Seminar SEM2100,
tion.pdf?fileId=db3a30431ff9881501206642 https://www.ti.com/seclit/wp/slup326/
02606c8b. slup326.pdf, 2014.
[16] Widener, Steve, “GaN to the rescue! Part 1: [26] Texas Instruments,
Body-diode reverse recovery,” https://e2e. UCC28740EVM-525 User’s Guide, http://
ti.com/blogs_/b/powerhouse/ www.ti.com/lit/ug/sluual8/sluual8.pdf.
archive/2015/10/28/gan-to-the-rescue-part-
1-body-diode-reverse-recovery, Oct. 28,
2015.
[17] Fu, Dianbo; Lu, Bing; Lee, Fred C., “1MHz
High Efficiency LLC Resonant Converters
with Synchronous Rectifier,” 2007 IEEE
Power Electronics Specialists Conference,
pp. 2404 – 2410, 2007.
[18] Fei, Chao; Li, Qiang; Lee, Fred C., “Digital
Implementation of Adaptive Synchronous
Rectifier (SR) Driving Scheme for High-
frequency LLC Converters with
Microcontroller,” IEEE Transactions on
Power Electronics, Vol. PP, Issue 99, pp. 1-1,
2017.

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