Microelectronics Reliability 50 (2010) 514–521

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Trends of power semiconductor wafer level packaging

Yong Liu *
Fairchild Semiconductor Corp., South Portland, ME 04074, United States

a r t i c l e i n f o a b s t r a c t

Article history: A review of recent advances in power wafer level electronic packaging is presented based on the
Received 18 June 2009 development of power device integration. The paper covers in more detail how advances in both
Received in revised form 25 August 2009 semiconductor content and power advanced wafer level package design and materials have co-enabled
Available online 12 October 2009
significant advances in power device capability during recent years. Extrapolating the same trends in
representative areas for the remainder of the decade serves to highlight where further improvement in
materials and techniques can drive continued enhancements in usability, efficiency, reliability and
overall cost of power semiconductor solutions. Along with next generation wafer level power packaging
development, the role of modeling is a key to assure successful package design. An overview of the power
package modeling is presented. Challenges of wafer level power semiconductor packaging and modeling
in both next generation design and assembly processes are presented and discussed.
Ó 2009 Elsevier Ltd. All rights reserved.

1. Introduction This paper introduces the power wafer level package trends
based on above power device development. A review of recent
Over the last two decades, power semiconductor technology advances in power wafer level electronic packaging which focuses
has made impressive progress, particularly in the increasingly high on monolithic power integrations is presented. It covers in more
power density of monolithic, system multiple function and hybrid detail how advances in both semiconductor content and advanced
designs [1–3], which are the driving forces towards both the mono- wafer level package design and the materials have co-enabled the
lithic package and three dimensional (3D) power solution with significant advances in power device capability during recent years.
heterogeneous functional integration. Extrapolating the same trends in representative areas to the
The development of power packages depends on the develop- remainder of the decade serves to highlight where further improve-
ment of power device integration. Current power devices include ment in materials and techniques can drive continued enhance-
the power integrated circuit (IC)s, high voltage IC (HVIC), discrete ments in usability, efficiency, reliability and overall cost of power
metal oxide semiconductor field effect transistor (MOSFET), intelli- wafer level semiconductor solutions. Challenges of power wafer
gent discrete power device, combined with functional integration level semiconductor packaging in both next generation design and
and the integration of passive elements. Hybrid integration in- assembly process are presented and discussed.
cludes the standard power module and the intelligent power mod- In addition to the forward looking trends it is important to rec-
ule (IPM) for high power application. Today’s power integration ognize that the methods for concurrent engineering of these solu-
solution has covered multiple functions, which is one of major tions (both the semiconductor content and high performance
directions of power wafer level package development. package capability) are becoming more increasingly dependent
The trends are going towards wafer level 3D heterogeneous on rigorous use of proven multi-physics/FEA tools and techniques
integration with high switching frequency and with reduced or for both new power package development and its assembly pro-
eliminated bulky magnetics and capacitances as well as soft cess. The challenges for modeling of power semiconductor package
switching technologies for high efficiency and low harmonics [3]. in new package and assembly process are investigated and
Silicon carbide (SiC) and other wide bandgap (WBG) semiconduc- discussed.
tor devices will ultimately be important elements for hybrid inte-
gration to advance system dynamic characteristics, overload
capability, device ruggedness, and thermal and electrical perfor- 2. Challenges of power wafer level semiconductor packaging
mance [4–8].
Today, providing energy efficient solutions for various products
is becoming increasingly important in our world due to limited
energy resources and climate change. Especially significant is the
* Tel.: +1 (207) 761 3155; fax: +1 (207) 761 6339. fast growth of consumer electronics in both communications and
E-mail address: [email protected] entertainment, industrial power conversion, automotive, and

0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2009.09.002
 Y. Liu / Microelectronics Reliability 50 (2010) 514–521 515

standard power electronics products. Consumer demand for in- As the die shrinks, SOC can add more functions, and SIP can in-
creased mobility with advanced features and for high efficiency en- clude more chips. In SOC, the thermal density will become very
ergy solutions has paved the way for a variety of new products [9], high. Determining how to insulate different functions in one chip
and has driven advances in power electronics technology towards and how to effectively dissipate the heat through the package will
the high power density design of monolithic devices, discrete com- be a challenge [21–25]. Although the cost of SIP is low, there are
ponents and 3D heterogeneous wafer level solutions as well as the challenges due to the assembly of wafer level multiple chips to wa-
wafer level stacking with silicon through vias (TSV) [10]. As com- fer. The internal parasitic effects of SIP, like parasitic inductance
pared to the development in general IC package [11–19], the power [22], are higher than SOC. The impact of heat from the power com-
wafer level package is far behind due to the extremely harsh oper- ponents on the electrical performance of IC drivers will be a con-
ation environment. New modeling methodologies and tools are cern. To build an advanced SIP which has good thermal and
becoming necessary to support new generation power wafer level electrical performance with low cost is the largest challenge of
package development. This paper describes the challenges for to- power wafer level SIP. Modeling and simulation efforts must be
day and the next few years in power wafer level package develop- used to support the SIP development from design, reliability and
ment which should be addressed by the industry. assembly process [26–36].

2.1. Die shrinkage impact

2.3. New power package materials

The development of power semiconductor device has begun to

Development of new materials to support wafer level package
aim at 130 nm technology, while today 180 nm and 250 nm tech-
process, heat transfer and good electrical performance is critical.
nologies is beginning to drive significant die size shrinkage as com-
An example is to develop new molding compound material with
pared to regular 350 nm or 500 nm power technology. As the metal
reasonable content of nano silica fillers to be suitable wafer level
interconnect system inside the die continues to become thinner,
molding and to rapidly dissipate heat from the power die while
current density has significantly increased. The electromigration
keeping the adhesion strength high. At present, both Pb-free sol-
(EM) issues will grow and new interconnect alternatives will be
ders and green epoxy mold compound material (EMC) are used
considered. Current techniques such as the wafer level solder
and accepted by most companies. Thermal stability is a key issue
bumping or Cu-stud bumping will meet the challenges of material
[9], especially in the automotive environment, where current
inter metallic diffusion and mechanical cratering issue for wafer le-
epoxy mold compound materials have difficulties meeting the
vel Cu-stud bumping. As the die shrinks, the pitch of power wafer
requirement of exceeding 180°C continuous operation. The new
level chip scale packages (CSP) will move from current 0.5 mm to-
green EMC will have to withstand such temperatures from the
wards 0.4 mm. The heat dissipation will become a very critical and
power chip. Pb-free solder must have high melting temperatures
significant challenge. Finding a high efficiency heat dissipation
and EMC should not be burnt in high temperature operation.
solution is necessary.
As the chip shrinks, there are two trends in power packages. The
first is the fan-in application for power wafer level packages, which
2.2. Wafer level power system on chip (SOC) vs. system in package
are gaining wider applications without EMC. The second is the fan-
(SIP)
out wafer level package, which use the wafer level molding to
make the interconnect re-distribution. This is particularly useful
The power integration devices allows the state of art smart
for the chip with smaller pitch and shrank die. For this latter trend,
power IC with technology such as integration of bipolar, comple-
the EMC usage is not decreasing [18,21].
mentary metal oxide semiconductor (CMOS) and double diffused
metal oxide semiconductor (DMOS)-BCDMOS, intelligent discrete
power device, and the function integration in both lateral DMOS 3. Trends in discrete wafer level power MOSFET packages
(LDMOS) and vertical DMOS (VDMOS) for power control and pro-
tection as well as other functions. This is so called power semicon- 3.1. Wafer level MOSFET compared to regular discrete power package
ductor system on chip (SOC), which is the integration of several
heterogeneous technologies-analog, digital, MOSFETs, etc. into a Table 1 shows the typical development trends of discrete MOS-
single silicon chip. However, such power SOC technology often is FET package. It gives the representative power transistor package
too expensive and complex. This leads to a wealth of opportunities constituent volumetric percentages. As the package develops from
for system in package (SIP), in which multiple chips with different Fairchild early DPak (TO252) through SO8 to MOSFET BGA and
functions are placed in one package or module [20] which has sim- MOSFET WLCSP, the molding compound decreases as a percentage
ilar function of SOC but with a lower cost. of volume, until it reaches zero with the MOSFET BGA and WLCSP
SIP has evolved as an alternative approach to SOC for electronics packages. At the same time the silicon and interconnect metal in-
integration because this technology provides advantages over SOC creases as a percentage of volume. At DPAk level, leadframe is
in many market segments. In particular SIP provides more integra- about 20% and silicon is about 4%, while EMC is about 75%. At
tion flexibility, faster time to market, lower research and develop- WLCSP level, the silicon is about 82%. There is no EMC in the
ment (R&D) or non-recurring engineering (NRE) cost, and lower WL-CSP.
product cost than SOC for many applications. SIP is not a replace- Fig. 1 shows the discrete wafer level – CSP for schottky diode
ment for high level, single chip, and silicon integration but should and vertical MOSFET from the released products of Vishay and Fair-
be viewed as complementary to SOC. For some very high volume child semiconductor. Those WL-CSPs are called fan-in layout.
applications SOC will be the preferred approach, like a power However, the advantage of EMC is that it can enhance handling
SOC with the integration of LDMOSFETs and IC controller, the cost and mechanical robustness, as it has in the past. It can provide sub-
of the SOC is not expensive due to larger volume of production as stantial protection and mechanical integrity to place components
compared to the SIP with two MOSFET die and an IC controller die. across a wide generational range of pick and place equipment. So
In such case, the electric performance of the SOC is clearly super as the EMC today in discrete power package is still useful as a compo-
compared to the SIP. Some complex SIP products will contain SOC nent ‘‘encapsulant”. For wafer level power package, the EMC can be
components. Wafer level SIP/stack is one major direction for lower used as the re-distribution layer (fan-out) material through the
power application. molding for the fan-out wafer level package. That allows for the
516 Y. Liu / Microelectronics Reliability 50 (2009) 514–521

Table 1
Typical discrete power package constituent volumetric percentages towards WL-CSP [1].

Package type Total volume (mm3) Approximately % EMC Approximately % silicon Approximately % leadframe Approximately % interconnect
TO-252 (wire) 90 75 4 20 1
SO8 (wire) 28 83 6 10 1
SO8 (clip) 28 70 6 20 2
MOSFET BGA 20 0 40 50 10
WL-CSP 20 0 82 0 18

Fig. 3. Trends of low power package development.

Fig. 1. Examples of discrete WL-CSP. there are two approaches: one is to intensify the thermal manage-
ment requirements from the print circuit board (PCB) level and the
larger pitch for a smaller shrank die. Fig. 2 gives the example of other is heat dissipation in multiple directions at the package level
fan-out structure by using wafer level epoxy molding technology. which is advantageous for wafer level discrete power packages.
Bonding the wafer level power discrete package to a metal frame
is an effective approach. Bonding die to metal wafer with pre-
3.2. Higher current carrying capability etched cavity is the wafer level process to get the wafer level pack-
age with multiple direction heat dissipation. Fig. 4 shows the
One trend of the discrete wafer level power package is to in- examples of multiple direction heat transfer of Fairchild MOSFET
crease the current carrying capability per unit area; this is partly BGA and Vishay PolarPAK.
due to the customer’s request for high current capability and partly
due to the die shrinkage. Fig. 3 shows the trends of low power
MOSFET package development in the industry, the data was se- 3.3. Low Rdson resistance and better thermal performance
lected from the released products of Vishay, IR and Fairchild Semi-
conductor, which includes both wafer level power discrete package To get lower Rdson and to improve the thermal performance,
and regular power discrete package. the wafer level MOSFET with vertical metal-oxide can be built on
To better manage the thermal performance with the trend to a silicon substrate thinned to 7 lm and plated with 50 lm copper
higher current carrying capability in wafer level power package,

Fig. 2. EMC as the re-distribution substrate of fan-out wafer level package in

Infineon [21]. Fig. 4. Multiple direction heat transfer packages.
 Y. Liu / Microelectronics Reliability 50 (2010) 514–521 517

Fig. 7. Wafer level integrated power solution.

Fig. 5. (a) Fairchild UMOSFET and (b) regular MOSFET [28].

and ‘‘adaptive” motion control at the high end. For the voltage
range at 100–700 V, next generation of integrated LDMOS struc-
tures reach the limits of Si for breakdown voltage (BVdss) as a
function of geometry, which allows a corresponding increase in
HV monolithic power conversion capability (AC–DC) and results
in an incremental raising of the limit at which multiple die are re-
quested in the actual products.

4.2. Smaller package footprints

As power die size shrinks, the package footprints shrink as well,

Fig. 6. Move the drain to the front side the MOSFET. and maintaining the thermal transfer capacity at the package level
is difficult since the function/unit area of die is increasing with ad-
vanced BCDMOS processes. While the overall package footprint
as its drain, see Ref. [28] Fairchild wafer level UMSFET. This extre- trend is decreasing area, the thermal dissipation capabilities rely
mely reduces the Rdson resistance and improves the thermal per- more on the PCB as part of the system. Therefore insuring mechan-
formance. Fig. 5 shows the internal device structure of the ical integrity of WL-CSP in the form of bare flipped die in conjunc-
UMOSFET and its comparison with regular MOSFET. tion with board level assembly of a heat sink is difficult, see Fig. 8.

3.4. Move the MOSFET drain to front side 4.3. Wafer level micro-channel

For the wafer level discrete MOSFET, another trend which ob- Instead of air cooling for power wafer level package, one trend
tains the attention in the industry is to move the drain of the MOS- is to build the wafer level micro-channel on power chip. This can
FET to the front side of the die so that the drain, source and gate are effectively take the heat out of the power chip. Fig. 9 gives an
at the same side. This would be helpful for the surface mounting example of building the micro-channels on both power die active
application in various PCBs. surface and back side. Due to the high efficiency of cooling through
Fig. 6 shows one of the lateral layouts of the drain for a LDMOS the micro-channels, heat sink is not needed anymore. This may sig-
WL-CSP. Since the drain is in lateral placement, the back metal nificantly reduce the space of heat sink and remove the noise in-
does not contact the drain directly, so its application limits to low- duced by the fans in the cooling system.
er power and lower voltage area. For VDMOS WL-CSP, the trend is
to develop the directly connection to the front side by TSV in
trench area. The advantage of the direct connection the back drain
to front side is its good electrical performance with lower Rdson.
Because this is a vertical DMOS, the application area may be rela-
tive wider in power range as compared to the structure in Fig. 6.

4. Trends in power IC packages

Fig. 8. Example of WL-CSP which is hard to mount the heat sink.
4.1. Higher power density at the wafer level

For the voltage range at 5–100 V, there are a wider range of

inductive loads handled with a monolithic solution and higher le-
vel of functional integration in monolithic solution. The most inter-
esting application is the wafer level integrated system power
conversion solution which combines two power switches (the high
side and lower side) together with an IC driver. Fig. 7 shows an
example of such a wafer level power system on chip. There are also
integrated advanced digital control functions for motion which in-
cludes ‘‘sensorless” positioning and fault detection at the low end Fig. 9. Micro-channels on both active side and back side die [24].
518 Y. Liu / Microelectronics Reliability 50 (2009) 514–521

5. Trends in wafer level passives Current flows across the front side of the die. The die is attached to
the substrate by insulating die attach material.
Although the wafer level passives (resistor, capacitor and Fig. 12 shows a wafer level side by side placement SIP, a new
inductor) in today are only suitable for very low and tiny power, concept of lateral interconnects is proposed for control and com-
it is possible for them to integrate with low power BCDMOS or munication between die [30]. This concept may be used for the
other active IC. Integration of active power switches and passives system power solution with side by side die placement.
in wafer level can greatly improve the electrical performance and In power application, the value of ‘‘SIP” is directly related to
significantly reduce the parasitic effects. For relative larger power reducing board level design complexity and space for power deliv-
products, like buck converter and DrMos with passives, the devel- ery and control and also related to providing reduced parasitic ef-
opment is on going. Fig. 10 gives the development samples of fects in high performance switching applications. One application
wafer level inductors for power application [29], which indicates of the power SIP is to expand ease of point of load (POL) power reg-
the current level with frequency. One significant advantage of ulation and management. As an example of the POL, Fig. 13 shows
the wafer level inductor integration is its frequency can reach from a MOSFET SIP with a high side WL-CSP and a low side WL-CSP
several MHz to 100 MHz, which the regular package level and bumped on a metal substrate for a buck converter. Fig. 14 shows
board integration level are hard to get. the profile of power efficiency (%) vs. current load of the SIP. It
can be seen from the profile that the average efficiency of the SIP
is about 2–5% higher than the individual MOSFETs.
6. Trends in power SIP/3D development

In many power conversion and power management applica- 6.2. Stacked/3D power SIP
tions, the optimized semiconductor solution is a combination of
lateral and vertical conduction devices. This makes a monolithic The above SIP with side by side placed dice has certain draw-
silicon solution with both power switching (VDMOS/IGBT) and backs: its geometry size is not as small as desired, and the electri-
control function (BCDMOS/CMOS IC) impractical. Therefore the cal performance such as the parasitic effect also needs further
Power SIP becomes necessary. Currently there are two major improvement. Ref. [22] discussed a regular SIP (not a wafer level)
trends in power SIP/3D package development: one is the wafer le-
vel CSP bumping on the leadframe to form various stacked die
power package; another one is the fully wafer level 3D package
with TSV.

6.1. Side by side placed multiple die SIP

The SIP as defined here contains at least two die in a package as

shown in Fig. 11. One die is the VDMOS, which is attached to a wa-
fer level metal substrate by a conductive die attach. The current
flows through die and the metal layer. Another die is the driver
IC which uses lateral electric conduction with substrate grounded.

Fig. 12. A wafer level side by side SIP with lateral interconnects [30].

Fig. 10. Wafer level passives [29].

Fig. 11. A two die power SIP. Fig. 13. A SIP of buck converter.
 Y. Liu / Microelectronics Reliability 50 (2010) 514–521 519

Fig. 16. A two phase buck converter SIP with wafer level power CSP bumped on
leadframe.

Fig. 14. Power efficiency (%) vs. current load (I).

of a voltage regulator with component side by side placement and

the stacked SIP and found that the stacked SIP has 55% lower par-
asitic inductance than side by side placed SIP. This is particularly
important for portable applications, and for small size industry
applications.

6.2.1. Power discrete WL-CSP bumped on leadframe

The trend of stacked power package is from simply enhancing Fig. 17. Stacked active die on passive wafer [29].
one function towards systematic function and multiple functions
while reducing the board level complexity and space. Fig. 15 shows
a two phase buck converter circuitry. Fig. 16 shows a stacked SIP
for a two phase buck regulator, which is built by four single wafer
level discrete power CSPs bumped on leadframe and encapsulated
with mold. Such a SIP has inherent advantages of load splitting and
output ripple dividing over its single-phase counterpart and is a
suitable candidate in many applications, given the trends towards
lower supply voltages and greater load–current requirements with Fig. 18. Wafer level stacked power die package with TSVs by two stacked wafers.
low cost. The bottom exposed drains and top exposed source
provide the two way heat dissipation for a better thermal
performance. with wafer 1 source and wafer 2 drain. The common source
(wafer 1)/drain (wafer 2) may be connected to at least one front
6.2.2. Wafer level stack/3D power die SIP side by TSVs. This stacking process can be done through wafer on
There are two stacking wafer level methods for power die SIP. wafer. The advantage of this integration is the very good electrical
One is to stack die on the wafer and the other is to stack two wa- performance for a half bridge with both N channel or P channel
fers. Fig. 17 shows the active IC die is stacked on the passive wafer. MOSFETs for products like liquid crystal display (LCD) back light
The power IC die with two MOSFETs and a IC driver is bonded on inverters. Since the distance between high side die and low side
the passive wafer with inductor L. Fig. 18 shows an example of a die is very short, this greatly reduces the electrical resistance and
wafer level stacked die package of two MOSFETs bonded together parasitic effects.

7. Trends in power package modeling

The power package development today is becoming increas-

ingly dependent on rigorous use of proven multi-physics/FEA tools
and techniques. Correct use of the modeling tools can definitely
save design time and shorten the number of design cycles. The
challenge is, can the modeling tool and methodology be ready to
support the new trends in the development of new wafer level
power package technology? Examples of the challenges include
various designs, reliability and assembly modeling which include
EM simulation; diffusion along the interface of two metal materi-
als; contamination at the interface between different material lay-
ers; thermal resistance definition in SIP; 3D copper stud bumping
Fig. 15. A typical two phase buck converter circuitry. simulation, etc.
520 Y. Liu / Microelectronics Reliability 50 (2009) 514–521

The greatest challenges in modeling for wafer level power pack- Fig. 20 shows an example of thermal simulation automation.
ages today are the multi-physics and multi-scale simulations The user only needs to input the basic information, load the sold
which couple the electrical, thermal and mechanical fields, and model from computer aided design (CAD) Lib, choose the power
the assembly process simulation in a wafer level power package applied, natural convention or forced convention, and then click
system with multi-scale layout from nanometers to millimeters. the button ‘‘solve”, the automation system will automatically mesh
Development of highly efficient modeling algorithms for such a the model, apply the power and thermal boundary condition, and
power WLP system is very critical for virtual prototyping of new solve the problem and out put the results the user needed. For a
products. In some cases, the WLP might have strong thermome- 40,000 degree of freedom model, it will take about 20 minutes to
chanical performance but is weak in electrical function or the get the final result.
WLP has very good electrical performance but is weak in thermo- Another modeling trend of the power package is to develop the
mechanical design. Therefore it is necessary to determine the best advanced methodologies for the challenges due to the new devel-
solution using modeling in design phase. Package measurements opment of power package in design and assembly. Examples are, as
are expensive, time consuming, and cannot provide all of the re- the die size and thickness shrink, die pick up process will become
quired information. very critical, simulating this pick process is helpful to reduce die
ITRS SIP 2008 white paper [23] describes a future vision of chip- cracking [31]. Just as typical wafer level package, the power wafer
package system co-design: (a) One tool for simultaneous design level package needs to go through various reliability tests. Particu-
enabled by a multi-user, cross-functional EDA + system analy- larly EM in power WLCSP in both interconnect and solder balls will
sis + knowledge-based tool. (b) A wizard-like interface, automati- be a serious challenge as the pitch becomes small due to die
cally constructs baseline design for each component based on shrinks. Modeling of EM can help and improve the design of the
series of user questions, analysis and an expert system for technol- WLCSP. Simulation of 3D void generation has been developed in
ogy selection and design rules. These ideas cover stress/mechanical both interconnect and solder bumping level [32,33]. Fig. 21 shows
modeling, thermal chip-package system and electrical chip-pack- the void generation simulation for the EM in a wafer level CSP.
age system. This indicates a modeling trend of the industry is to- Passivation cracking modeling will help for the metal stacking
wards package system design automation. Fig. 19 shows the and layout of passivation layer above the metal [34]. Moisture is
modeling role in all areas of the semiconductor power industry a big impact to the power package at the wet environmental con-
from wafer IC design to final product. dition, a systematic modeling and analysis methodology for mois-
One of the major modeling tools for packages is finite element ture and vapor pressure has been introduced in [35]. Cu-stud
analysis (FEA). Advances in the power package development need bumping in power wafer level CSP will induce the failure such as
the high efficiency, and short design cycles, in which the FEA use the silicon cratering and BPSG crack under the barrier layer. Devel-
will accelerate the further miniaturization of power electronic
components, and accelerate the incorporation of advanced materi-
als and assembly structures. However, most of the power package
design engineers, material engineers, test engineers and the reli-
ability analysis engineers are not familiar with FEA. If they can
run designed experiments using FEA for their product optimization
in co-designed power package efforts and for material selection,
that will really accelerate the power package development. There-
fore, to develop the modeling automation system is one trend of
the power package modeling. This system allows people who
might not know FEA but wish to do design optimization for their
product to run FEA. Engineers just simply input some basic infor-
mation and set the numerical design of experiment (DOE), the sys-
tem will automatically do the meshing, apply boundary conditions
and loads, solving and automatically output the results. Refs. [26]
and [27] have developed the initial modeling automation system
for thermal, moisture and linear thermal–mechanical stress analy- Fig. 20. An example of thermal simulation automation.
sis. The results have shown great efficiency to save modeling time.

Fig. 19. The diagram of the modeling in all areas of power semiconductor. Fig. 21. EM void simulation [33].
 Y. Liu / Microelectronics Reliability 50 (2010) 514–521 521

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