Monolithic Power Systems ®

Reference design –
Xilinx ZU3EG Industrial Networking Solution (using PMIC)

Last update: 1/18/17

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 ZU3EG Industrial Networking Solution

ZU3EG
0.85V @ 3A Rail3 VCCINT 0.85V ZU3EG
VCCBRAM
0.85V
VCCINT_IO
0.85V
1.8V @ 500mA Rail4 VCCAUX
1.8V
VCCAUX_IO
1.8V
VCCADC
1.8V
1.25V@ 1mA Rail10 VREFP 1.25V
Optional

VCC_PSINTLP 0.85V
VCC_PSINTFP
0.85V
VCC_PSINTFP_DDR
1.8V @ 50mA Rail6 0.85V
VCC_PSAUX 1.8V
1.2V @ 50mA Rail7 VCC_PSAMS 1.8V
VCC_PSDDR_PLL
PS_MGTRAVTT
1.8V
1.8V
PS
0.85V @ 300mA Rail5 PS_MGTRAVCC
0.9V
VCC_PSPLL
1.2V
3.3V @ 200mA Rail8 VCC_PSIO[0]
3.3V
CAN PHY / NOR Flash / I2C
NOR
Flash
1.5V @ 1A Rail9 VCCO_PSDDR 1.1V
Share w/ LPDDR4 VDDQ & VDDCA
VDDQ
DDR3

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 ZU3EG Industrial Networking Solution –
MPS solution using PMIC
Optional
MP9457 MP8201
Vin=36-18V 5.0V +/-5% @ 3A max 1.25V@ 1mA
Vin Vo Vin Vo
Rail10
EN PG Accuracy +/-0.5%
1.8V +/-3% @ 50mA Rail6
OUTRTC OUT2 OUT3

10mA LDORTC 300mA LDO2 300mA LDO3

Driver & Driver & Driver &
Control Control Control

2.7V-5.5V VIN2
Vin1 VIN1 DCDC1 SW1 Vout1 0.85V +/-3% @ 3A Rail3
5.5V/4.5A
GND1 I2C VID, 0.6V-2.187V FB1
VIN2 DCDC2 SW2 Vout2 1.8V +/-3% @ 500mA Rail4
5.5V/2.5A
GND2 FB2
I2C VID, 0.8V-3.975V
VIN3 DCDC3 SW3 Vout3 1.5V +/-3% @ 1A Rail9
5.5V/4A
GND3
I2C VID, 0.6V-2.187V FB3
VIN4 SW4 Vout4 3.3V +/-5% @ 200mA Rail8
DCDC4
5.5V/2A
GND4 FB4
I2C VID, 0.8V-3.975V
2.7V-5.5V
AVIN
1uF AVIN Control Logic UVLO
1.5MHz OSC
Phase shift
AGND
SCL VIN5
300mA LDO4
I2C Register & OTP Driver &
Control OUT4 0.85V +/-3% @ 300mA Rail5
SDA
300mA LDO5
nPBIN
Driver &
Control OUT5 1.2V +/-3% @ 50mA Rail7
Power Logic Control
RSTO

AGND

MP5416
Requires factory programming
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 Power specs–
ZU3EG Industrial Networking Solution

Seq MPS part#

Rail # VIN (V) Rail VOUT (V) Load (mA) Footprint
Up/Dwn (Iout max)

TSSOP-20 EP
2 18-36 Intermediate rail 5 ± 5% 3000 MP9457 (3A)
6.6x6.6mm

Vout1
3 5 VCCINT, VCCBRAM, VCCINT_IO 0.85 ± 3% 3000 1/3
(4.5A)

VCCAUX, VCCAUX_IO, VCCADC,

Vout2
4 5 VCC_PSAUX, VCC_PSAMS, 1.8 ± 3% 500 2/2
(2.5A)
VCC_PSDDR_PLL

LDO4
5 5 VPS_MGTRAVCC 0.85 ± 3% 300 3/1
(0.3A)
PMIC QFN-28
MP5416 LDO3 4x4mm
6 5 VPS_MGTRAVTT 1.8 ± 3% 50 3/1
(0.3A)

LDO5
7 5 VCCPSPLL 1.2 ± 3% 50 2/2
(0.3A)

Vout4
8 5 VCC_PSIO 3.3 ± 5% 200 3/1
(2A)

Vout3
9 5 VCCO_PSDDR 1.5 ± 3% 1000 3/1
(4A)

SOT-23
10 5 VREF (optional) 1.25 ± 0.2% 1 3/1 MP8201 (0.002A)
3x2.6mm

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 MP5416
PMIC with 4xBucks and 5xLDOs

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 Recommended Layout MP9457

Schematics (Typical) Layout guidelines

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 MPS design highlights–
(PMIC)
• MP9457
– High Efficiency
– Cost effective
• MP5416
– High integration
• 4x Bucks
• 5x LDOs
– Minimum External Components
– I2C control
– Built in sequencing
– Factory set voltages

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 MPS Contacts

For additional information please contact

MPS Reference Design Team
at [email protected]

For general information

http://www.monolithicpower.com

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