Dabu1mb16e0 Rev e - Quanta - Bu1 - R3a - 20070326 - Schematics

1 2 3 4 5 6 7 8
PCB STACK UP BU1 Block Diagram

LAYER 1 : TOP
LAYER 2 : SGND
Intel
LAYER 3 : IN1
CLOCK GENERATOR
Merom CK505
A A
LAYER 4 : IN2 (35W) ICS9LPR363
Page 2
LAYER 5 : VCC Page 3,4
LAYER 6 : BOT FSB(667/800MHZ)

R.G.B
CRT
Page 18
VCC_CORE 533/ 667 MHZ DDR II DDRII-SODIMM1
LVDS X1
LCD(WXGA 13W) Crestline GM DDRII-SODIMM2
Page 18 Page 12,13
+1.5V
SATA Page 5,7,8,9,10,11
SATA - HDD
Page 19 G SENSOR
+1.05V
PATA
IDE - ODD DMI(x2/x4)
Page 19
B +1.25V B
System 0
Page 24 USB PORT 0
PCI-Express
+1.8VSUS System 1
Page 24 USB PORT 1
ICH8M MINI CARD MINI CARD NEW CARD 100/10 LAN

+3VPCU System 2
WLAN RTL8101E
+3V_S5 Page 24 USB PORT 2 USB 2.0 Page 23 Page 23 (BOT) Page 24 (BOT) Page 20
+3VSUS
+3V WLAN
+5VPCU Page 23 USB PORT 3
+5V_S5 Connector
DAUGHTER Azalia PCI Bus
RJ11/RJ45/USB DAUGHTER BOARD
+5V BORD
Finger Printer (BOT) Page 14,15,16,17
SMDDR_VTERM Page 24 USB PORT 4
SMDDR_VREF PCMCIA Card RJ45 RJ11 USB
Bluetooth (BOT) LPC
32.768KHz
Controller Reader/1394
Page 24 USB PORT 5 (CB 1410) (R5C833)
Page 21 (BOT) Page 22
C New Card (BOT) C
Page 24 USB PORT 6 PCMCIA 1394

(BOT)
5 IN 1 (BOT)
Reserved (BOT)
WPC8763LDG
Page 23 USB PORT 7
PCI ROUTING
Page 26
TABLE IDSEL INTERUPT DEVICE
Camera (BOT)
REQ0# / GNT0# AD17 INTA#,INTB# R5C832
Page 18 USB PORT 8 REQ1# / GNT1# AD20 INTC# CB1410
FAN Touch Key FLASH

AUDIO/FM/USB DAUGHTER BOARD PAD Board ROM
HP HP AMP AUDIO CODEC

(ALC262) Connector
INT SPK SPK AMP BTO BOM OPTION

MDC 1.5 CB@ : CARD BUS
FP@ : FINGER PRINTER
D BT@ : BLUETOOTH D
Page 25 CM@ : CAMERA
GS@ : G-SENSOR
NEW@ : NEW CARD
USB LCD@ : LCD TYPE PANEL
LED@ : LED TYPE PANEL
1394@ : 1394
Quanta Computer Inc.

RJ11 PROJECT : BU1 Santa Rosa
Size Document Number Rev
Block Diagram 1A
Date: Monday, March 26, 2007 Sheet 1 of 33

1 2 3 4 5 6 7 8
5 4 3 2 1
Clock Generator Clock Gen Differential IO power +1.25V_VDD +1.25V
L25
+3V L26 PBY160808T-301Y-N_6 C411 .1U_4 PBY160808T-301Y-N_6
'EMI FILTER BKP1608HS181-T(180,1.5A)'
C426 C427 C428 C422 C425 C424 C419 C420 C416
R90
C414 .1U_4 *10U_810U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
10U_8
D 0_6 C408 10U_8 D
H=1.2mm ICS9LPRS365BGLFT
0.1U close to each VDD_IO Power pin
SLG8SP512T: AL8SP512K05
C43 .1U_4 U22 IC(64P) ICS9LPRS365BGLFT(TSSOP)
VDD_CK_VDD_PCI 2 48
C418 .1U_4 VDD_CK_VDD_48 VDD_PCI IO_VOUT
9 VDD_48
VDD_CK_VDD_PCI 16 64 CGCLK_SMB
VDD_CK_VDD_REF VDD_PLL3 SCLK CGDAT_SMB
61 VDD_REF SDA 63
R404 CK505
C412 .1U_4 VDD_CK_VDD_PCI 39 38 PM_STPPCI# [16]
VDD_CK_VDD_CPU VDD_SRC SRC5/PCI_STOP#
55 VDD_CPU SRC5#/CPU_STOP# 37 PM_STPCPU# [16]
0_6
R68 +1.25V_VDD 12 54 CLK_CPU_BCLK_R RP50 1 2 0X2
VDD_96_IO CPU0 CLK_CPU_BCLK [3]
C415 .1U_4 20 53 CLK_CPU_BCLK#_R 3 4
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# [3]
26 VDD_SRC_IO_1
0_6 45 51 CLK_MCH_BCLK_R RP52 1 2 0X2
VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK [5]
36 50 CLK_MCH_BCLK#_R 3 4
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# [5]
49 VDD_CPU_IO
SRC8/ITP 47
SRC8#/ITP# 46
R85 56_4 PCLK_DEBUG_R 1 35 CLK_PCIE_3GPLL#_R RP58 1 2 0X2

[23,26] PCLK_DEBUG PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# [6]
<check list> 34 CLK_PCIE_3GPLL_R 3 4
SRC10 CLK_PCIE_3GPLL [6]
PCI4/SRC5_EN: PU be used, R81 56_4 PCLK_PCM_R 3
[21] PCLK_PCM PCI1/CR#_B
the CK505 will be configured to +3V R86 10K_4 33 CLK_MCH_OE#_R R410 475_4 CLK_MCH_OE# [6]
R78 56_4 PCLK_R5C833_R SRC11/CR#_H NEW_CLKREQ#_R R412 475_4
use Pin37/38 to SRC5 clock.If [22] PCLK_R5C833 4 32 NEW_CLKREQ# [24]
R82 *10K_4 PCI2/TME SRC11#/CR#_G
PD be detect at powe-on,the
CK505 will setting Pin 37/38 to R405 56_4 PCLK_591_R 5 30 CLK_PCIE_NEW_R RP59 3 4 0X2
[26] PCLK_591 PCI3 SRC9 CLK_PCIE_NEW [24]
PCI_STOP/CUP_SOTP(Default +3V R74 *10K_4 31 CLK_PCIE_NEW_R# 1 2
SRC9# CLK_PCIE_NEW# [24]
is setting to R73 22_4 PCI_CLK_SIO_R 6
R79 10K_4 PCI4/SRC5_EN CLK_PCIE_MINI2_R RP54
PCI_STOP/CUP_SOTP) SRC7/CR#_F 44 1 2 0X2 CLK_PCIE_MINI2 [23]
C R406 56_4 PCLK_ICH_R CLK_PCIE_MINI2#_R C
7 PCIF5/ITP_EN SRC7#/CR#_E 43 3 4 CLK_PCIE_MINI2# [23]
+3V R409 *10K_4
CG_XIN 60 41 CLK_PCIE_MINI_R RP56 1 2 0X2
[15] PCLK_ICH XTAL_IN SRC6 CLK_PCIE_MINI [23]
R407 10K_4 40 CLK_PCIE_MINI#_R 3 4
SRC6# CLK_PCIE_MINI# [23]
<check list> CG_XOUT 59 XTAL_OUT CLK_PCIE_LAN_R RP57
PCIF5/ITP_EN: PU be used,
SRC4 27 3 4 0X2 CLK_PCIE_LAN [20]
the CK505 will be configured R71 33_4 FSA 10 28 CLK_PCIE_LAN#_R 1 2
[16] CLKUSB_48 USB_48/FSA SRC4# CLK_PCIE_LAN# [20]
to use Pin46/47 to CPU ITP CLK_BSEL0 R72 2.2K_4
clock.If PD be detect at CLK_BSEL1 57 24 CLK_PCIE_ICH_R RP55 3 4 0X2
FSB/TEST/MODE SRC3/CR#_C CLK_PCIE_ICH [15]
powe-on,the CK505 will setting 25 CLK_PCIE_ICH#_R 1 2
SRC3#/CR#_D CLK_PCIE_ICH# [15]
Pin 46/47 to SRC8(Default is CLK_BSEL2 R87 2.2K_4 FSC 62 REF0/FSC/TESTSEL CLK_PCIE_SATA_R RP53
setting to SRC8) SRC2/SATA 21 3 4 0X2 CLK_PCIE_SATA [14]
R88 33_4 8 22 CLK_PCIE_SATA#_R 1 2
[16] 14M_ICH VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# [14]
11 VSS_48
15 17 DREFSSCLK_R RP13 1 2 0X2
VSS_IO SRC1/SE1 DREFSSCLK [6]
19 18 DREFSSCLK#_R 3 4
VSS_PLL3 SRC1#/SE2 DREFSSCLK# [6]
52 VSS_CPU
23 13 DREFCLK_R RP51 3 4 0X2
VSS_SRC1 SRC0/DOT96 DREFCLK [6]
29 14 DREFCLK#_R 1 2
VSS_SRC2 SRC0#/DOT96# DREFCLK# [6]
42 VSS_SRC3
58 VSS_REF CKPWRGD/PWRDWN# 56 CK_PWRGD [16]
ICS9LPRS365AGLFT/ SLG8SP512T During initial power-up be used to
sample FSB speed with FSA/B/C
H=1.5mm
C407 30P_4 CG_XIN <check list>
(1)PCI2/TME: PU be used, the CK505 cannot over clock any of the clock for Trust Mode security purposes.
2
Y6
CL=20p (2)PCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock.
14.318MHZ If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP
Clock Gen I2C

(Default is setting to PCI_STOP/CUP_SOTP) +3V
1
B C406 30P_4 CG_XOUT B
<check list> (3)PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock. Q3
XTAL length < 500mils If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8 RHU002N06 R94
2
(Default is setting to SRC8)
10K_4
3 1 CGDAT_SMB
[13,16,19,23,24] SDATA
(4)SLG8SP512 Pin 6 select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M ,
Pin 37, 38 will fixed be use CPU_Stop and PCI_Stop.
(5)SLG505YC64 CK505 Standar parts follow standar setting +3V
Q4
CPU Clock select

RHU002N06 R95
2
BSEL Frequency Select Table [3] CPU_BSEL0
R59 0_4 CLK_BSEL0
MCH_BSEL0 [6]
10K_4
3 1 CGCLK_SMB
[13,16,19,23,24] SCLK
FSC FSB FSA Frequency
+1.05V R66 *56_4
0 0 0 266Mhz
FSA
R65 *1K_4
0 0 1 133Mhz
+3V
0 1 1 166Mhz
R80 0_4 CLK_BSEL1
[3] CPU_BSEL1 MCH_BSEL1 [6]
0 1 0 200Mhz R411 10K_4 NEW_CLKREQ#_R
R77 *0_4
A
1 1 0 400Mhz
A1A: (9/20) Remove 0ohm FSB A
+1.05V R408 *1K_4
1 1 1 Reserved
1 0 1 100Mhz R55 0_4 CLK_BSEL2

[3] CPU_BSEL2 MCH_BSEL2 [6]
R62 *0_4
1 0 0 333Mhz
FSC PROJECT : BU1 Santa Rosa
+1.05V R56 *1K_4 Size Document Number Rev
CLK. GEN./ CK505 1A

5 4 3 2 1
5 4 3 2 1
CPU Thermal monitor

U24A
[5] H_A#[16:3]
H_A#3 J4 H1
A[3]# ADS# H_ADS# [5]
CPU(HOST)
H_A#4
ADDR GROUP 0
L5 A[4]# BNR# E2 H_BNR# [5]
H_A#5 L4 G5 +3V
A[5]# BPRI# H_BPRI# [5]
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# [5]
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# [5]
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# [5]
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BREQ#0 [5]
H_A#12 P2 A[12]#
CONTROL
H_A#13 L2 D20 H_IERR# R16 56.2_4 +1.05V
H_A#14 A[13]# IERR# +3V R431 R432 R437
P4 A[14]# INIT# B3 H_INIT# [14]
H_A#15 P1
H_A#16 A[15]# Q33 10K_4 10K_4 200_6
R1 A[16]# LOCK# H4 H_LOCK# [5]
2
D RHU002N06 LM86VCC D
[5] H_ADSTB0# M1 ADSTB[0]#
[5] H_REQ#[4:0] RESET# C1 H_CPURST# [5]
H_REQ#0 K3 F3 [18,26,27] MBCLK 3 1 C455
REQ[0]# RS[0]# H_RS#0 [5]
H_REQ#1 H2 F4
REQ[1]# RS[1]# H_RS#1 [5]
H_REQ#2 K2 G3 .1U_4
H_REQ#3 J3
REQ[2]# RS[2]#
G2
H_RS#2 [5]
+3V
H=1.75mm
REQ[3]# TRDY# H_TRDY# [5]
H_REQ#4 L1 U23
REQ[4]# Q34 H_THERMDA
[5] H_A#[35:17] HIT# G6 H_HIT# [5]
2
H_A#17 Y2 E4 RHU002N06 8 1
A[17]# HITM# H_HITM# [5] SCLK VCC
H_A#18 U5
H_A#19 A[18]# C454
R3 A[19]# BPM[0]# AD4 [18,26,27] MBDATA 3 1 7 SDA DXP 2
H_A#20
ADDR GROUP 1
W6 A[20]# BPM[1]# AD3
H_A#21 U4 AD1 6 3 2200P_4
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# ALERT# DXN
Y5 A[22]# BPM[3]# AC4
H_A#23 U1 AC2 *10K_4 4 5 H_THERMDC
H_A#24 A[23]# PRDY# R434 OVERT# GND
R4 A[24]# PREQ# AC1 +3V
H_A#25 T5 AC5 XDP_TCK
H_A#26 A[25]# TCK XDP_TDI MAX6657
T3 A[26]# TDI AA6
H_A#27 W2 AB3 [16] THERM_ALERT# R435 *0_4 THERM_ALERT#_R ADDRESS: 98H
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST# +3V R438 10K_4 THER_SHD# <check list>
H_A#30 A[29]# TRST# XDP_DBRESET# R19 0_4
U2 A[30]# DBR# C20 SYS_RST# [16] Layout Note:Routing 10:10 mils and away
H_A#31 V4
H_A#32 W3
A[31]# from noise source with ground gard
H_A#33 A[32]# R17 56.2_4
AA4 A[33]# THERMAL +1.05V
H_A#34 AB2
H_A#35 A[34]#
AA3 A[35]# PROCHOT# D21 H_PROCHOT_R# R18 *2.2K_4
H_PROCHOT# [29]
[5] H_ADSTB1# V1 ADSTB[1]# THERMDA A24 H_THERMDA
CPU FAN
THERMDC B25 H_THERMDC
[14] H_A20M# A6 A20M# <check list> +3V
THERMTRIP#_PWR
ICH
[14] H_FERR# A5 FERR# THERMTRIP# C7 Default PU 56ohm if no use.

[14] H_IGNNE# C4
C IGNNE# Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K R458 C
R26 0_4 H_STPCLK_R# D5 330_4
[14] H_STPCLK# STPCLK#
[14] H_INTR C6 H CLK +3V
LINT0
[14] H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK [2]
[14] H_SMI# A3 A21 Q37
SMI# BCLK[1] CLK_CPU_BCLK# [2]
2
MMBT3904
TP_CPU_RSVD01 M4 R1
T3 RSVD[01]
TP_CPU_RSVD02 N5 THER_SHD# 1 3
T5 RSVD[02] SYS_SHDN# [28]
TP_CPU_RSVD03 T2 10K_4
T8 RSVD[03]
TP_CPU_RSVD04 V3
T1 RSVD[04]
TP_CPU_RSVD05 B2
T146 RSVD[05]
RESERVED
TP_CPU_RSVD06 C3
T7 RSVD[06]
TP_CPU_RSVD07 D2 [26] FANSIG
T6
TP_CPU_RSVD08 D22
RSVD[07] H=1.75mm
T9 RSVD[08] CN34
TP_CPU_RSVD09 D3 U26
T4 RSVD[09]
TP_CPU_RSVD10 F6 2 3 TH_FAN_POWER
T12 RSVD[10] +5V VIN VO 1 4
GND 5 2
C290 .1U_4 1 6
/FON GND C489 C491 C9 3 5
GND 7
Merom Ball-out Rev 1a 4 8 PTI_CWY030-B0G1Z
[5] H_D#[15:0] H_D#[47:32] [5] [26] VFAN VSET GND
U24B 10U_8 .01U_4 *.01U_4
H_D#0 E22 Y22 H_D#32 G995
H_D#1 D[0]# D[32]# H_D#33
F24 D[1]# D[33]# AB24
H_D#2 E26 V24 H_D#34
H_D#3 G22
D[2]# D[34]#
V26 H_D#35 FANPWR = 1.6*VSET
H_D#4 D[3]# D[35]# H_D#36
DATA GRP 0
F23 D[4]# D[36]# V23

H_D#5 G25 T22 H_D#37
H_D#6 D[5]# D[37]# H_D#38
E25 D[6]# D[38]# U25
PU/PD (ITP700) Thermal Trip

H_D#7 E23 U23 H_D#39
H_D#8 D[7]# D[39]# H_D#40
K24 Y25
DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 +1.05V

G24 D[9]# D[41]# W22
H_D#10 J24 Y23 H_D#42
B H_D#11 D[10]# D[42]# H_D#43 B
J23 D[11]# D[43]# W24
H_D#12 H22 W25 H_D#44 +1.05V
D[12]# D[44]#
3
H_D#13 F26 AA23 H_D#45
H_D#14 D[13]# D[45]# H_D#46
K22 D[14]# D[46]# AA24
H_D#15 H23 AB25 H_D#47
D[15]# D[47]# Q1 R23 D3
[5] H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 [5] [6,16,29] DELAY_VR_PWRGOOD 2
[5] H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 [5]
H25 U22 FDV301N *10K_4 *BAS316
[5] H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 [5]
[5] H_D#[31:16] H_D#[63:48] [5]
1
H_D#16 N22 AE24 H_D#48 XDP_TMS R7 39_4 +1.05V C35 *1U_6
H_D#17 D[16]# D[48]# H_D#49
K25 D[17]# D[49]# AD24
H_D#18 P26 AA21 H_D#50
H_D#19 D[18]# D[50]# H_D#51
R23 D[19]# D[51]# AB22
H_D#20 L23 AB21 H_D#52 XDP_TDI R6 150_4
H_D#21 D[20]# D[52]# H_D#53 R25
DATA GRP 1
M24 D[21]# D[53]# AC26

H_D#22 L22 AD20 H_D#54
H_D#23 D[22]# D[54]# H_D#55 56.2_4 Q2
M23 D[23]# D[55]# AE22
2
H_D#24 P25 AF23 H_D#56 MMBT3904
+1.05V H_D#25 D[24]# D[56]# H_D#57
P23 D[25]# D[57]# AC25
H_D#26 P22 AE21 H_D#58 THERMTRIP#_PWR 1 3
DATA GRP 3
D[26]# D[58]# SYS_SHDN# [28]

<Check list & CRB> H_D#27 T24 AD21 H_D#59 <Check list & CRB>
H_D#28 D[27]# D[59]# H_D#60 XDP_TCK R5 27_4
Layout note: Z=55 ohm R24 D[28]# D[60]# AC22 Layout note: L<0.5"
H_D#29 L25 AD23 H_D#61
H_GTLREF<0.5" H_D#30 T25
D[29]# D[61]#
AF22 H_D#62 COMP0/2 Z=27.4ohm
H_D#31 D[30]# D[62]# H_D#63 COMP1/3 Z=54.9 R24 *0_4
N25 D[31]# D[63]# AC23 PM_THRMTRIP# [6,14]
R11 L26 AE25 XDP_TRST# R4 680_4
[5] H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 [5]
1K_4 M26 AF24
[5] H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 [5]
[5] H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 [5] <CRB & Design guide>
Layout Note:Connect from
H_GTLREF AD26
GTLREF COMP[0] R26 COMP0 R14 27.4_6
SB and daisy chain to CPU <CRB & Design guide>
R21 *1K_4 CPU_TEST1 C23 MISC U26 COMP1 R13 54.9_4 Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing
A R20 *1K_4 CPU_TEST2 D25 TEST1 COMP[1] COMP2 R10 27.4_6 CORE VR.Not use T A
AA1
CPU_TEST3 C24 TEST2 COMP[2]
Y1 COMP3 R8 54.9_4 connect.(SB/VR/CPU/NB) (ZS1 default NC)
T10 TEST3 COMP[3]
C14 *.1U_4 CPU_TEST4 AF26
CPU_TEST5 AF1 TEST4
T2 TEST5 DPRSTP# E5 ICH_DPRSTP# [6,14,29]
CPU_TEST6 A26 B5
T11 TEST6 DPSLP# H_DPSLP# [14]
R9 D24
DPWR# H_DPWR# [5]
2K_6 B22 D6
[2] CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD [14]
B23 D7
[2] CPU_BSEL1
[2] CPU_BSEL2 C21
BSEL[1]
BSEL[2]
SLP#
PSI# AE6
H_CPUSLP# [5]
PSI# [29]
Merom Ball-out Rev 1a
PROJECT : BU1 Santa Rosa
CPU(1 of 2)/FAN/Thermal 3A

5 4 3 2 1
5 4 3 2 1
CPU(Power)
VCC_CORE
U24D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
U24C A16 R5
VSS[005] VSS[086]
A7 VCC[001] VCC[068] AB20 <REV.NO. 0.5/REF.NO.19343> A19 VSS[006] VSS[087] R22
C465 C25 C466 C461 C473 C472 C477 C471 C21 C476 A9 AB7 A23 R25
VCC[002] VCC[069] VSS[007] VSS[088]
A10 AC7 AF2 T1
D 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 A12
VCC[003] VCC[070]
AC9
Ivcc Max 52A B6
VSS[008] VSS[089]
T4 D
VCC[004] VCC[071] VSS[009] VSS[090]
A13 VCC[005] VCC[072] AC12 B8 VSS[010] VSS[091] T23
A15 VCC[006] VCC[073] AC13 Ivccp Max 6A(VCCP supply before Vcc stable) B11 VSS[011] VSS[092] T26
A17 VCC[007] VCC[074] AC15 Max 2A(VCCP supply after Vcc stable) B13 VSS[012] VSS[093] U3
A18 VCC[008] VCC[075] AC17 B16 VSS[013] VSS[094] U6
A20 VCC[009] VCC[076] AC18 B19 VSS[014] VSS[095] U21
B7 AD7 Ivcca Max 130mA B21 U24
VCC[010] VCC[077] VSS[015] VSS[096]
B9 VCC[011] VCC[078] AD9 B24 VSS[016] VSS[097] V2
B10 VCC[012] VCC[079] AD10 C5 VSS[017] VSS[098] V5
B12 VCC[013] VCC[080] AD12 C8 VSS[018] VSS[099] V22
C475 C469 C463 C474 C464 C19 C20 C23 C459 C460 B14 AD14 C11 V25
VCC[014] VCC[081] +1.05V VSS[019] VSS[100]
B15 VCC[015] VCC[082] AD15 C14 VSS[020] VSS[101] W1
10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 B17 AD17 C16 W4
VCC[016] VCC[083] VSS[021] VSS[102]
B18 VCC[017] VCC[084] AD18 C19 VSS[022] VSS[103] W23
B20 VCC[018] VCC[085] AE9 C2 VSS[023] VSS[104] W26
C9 VCC[019] VCC[086] AE10 C22 VSS[024] VSS[105] Y3
C10 VCC[020] VCC[087] AE12 C25 VSS[025] VSS[106] Y6
C12 AE13 C16 C18 C17 C456 C15 C22 D1 Y21
VCC[021] VCC[088] VSS[026] VSS[107]
C13 VCC[022] VCC[089] AE15 D4 VSS[027] VSS[108] Y24
C15 AE17 .1U_6 .1U_6 .1U_6 .1U_6 .1U_6 .1U_6 D8 AA2
VCC[023] VCC[090] VSS[028] VSS[109]
C17 VCC[024] VCC[091] AE18 D11 VSS[029] VSS[110] AA5
DESIGN GUIDE C18 VCC[025] VCC[092] AE20 D13 VSS[030] VSS[111] AA8
C31 C28 C470 C462 C30 C467 D9 AF9 D16 AA11
CHANGE FROM 22UF *20 TO 10UF *32 D10
VCC[026] VCC[093]
AF10 D19
VSS[031] VSS[112]
AA14
10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 VCC[027] VCC[094] VSS[032] VSS[113]
D12 VCC[028] VCC[095] AF12 D23 VSS[033] VSS[114] AA16
D14 VCC[029] VCC[096] AF14 D26 VSS[034] VSS[115] AA19
D15 VCC[030] VCC[097] AF15 E3 VSS[035] VSS[116] AA22
D17 VCC[031] VCC[098] AF17 E6 VSS[036] VSS[117] AA25
D18 AF18 <CRB> +1.05V E8 AB1
VCC[032] VCC[099] VSS[037] VSS[118]
E7 VCC[033] VCC[100] AF20 R for test only E11 VSS[038] VSS[119] AB4
E9 VCC[034] E14 VSS[039] VSS[120] AB8
E10 G21 CPU_G21 R15 0_4 E16 AB11
C VCC[035] VCCP[01] CPU_V6 R12 0_4 VSS[040] VSS[121] C
E12 VCC[036] VCCP[02] V6 E19 VSS[041] VSS[122] AB13
E13 VCC[037] VCCP[03] J6 E21 VSS[042] VSS[123] AB16
C468 C27 C458 C24 C26 C457 E15 K6 + C36 E24 AB19
VCC[038] VCCP[04] VSS[043] VSS[124]
10U_8 E17 VCC[039] VCCP[05] M6 <Check list> F5 VSS[044] VSS[125] AB23
10U_8 10U_8 10U_8 10U_8 10U_8 CH6102K9A01 E18 J21 330U_7343 ESR=12m ohm F8 AB26
'CAP CHIP 10U 10V(+-10%,X5R,0805)' VCC[040] VCCP[06] VSS[045] VSS[126]
E20 VCC[041] VCCP[07] K21 F11 VSS[046] VSS[127] AC3
F7 VCC[042] VCCP[08] M21 F13 VSS[047] VSS[128] AC6
F9 VCC[043] VCCP[09] N21 F16 VSS[048] VSS[129] AC8
F10 VCC[044] VCCP[10] N6 F19 VSS[049] VSS[130] AC11
F12 VCC[045] VCCP[11] R21 F2 VSS[050] VSS[131] AC14
F14 VCC[046] VCCP[12] R6 F22 VSS[051] VSS[132] AC16
F15 VCC[047] VCCP[13] T21 F25 VSS[052] VSS[133] AC19
+ C32 + C13 + C29 F17 T6 G4 AC21
VCC[048] VCCP[14] +1.5V VSS[053] VSS[134]
F18 VCC[049] VCCP[15] V21 <CRB> G1 VSS[054] VSS[135] AC24
F20 VCC[050] VCCP[16] W21 .01U near to B26 ball G23 VSS[055] VSS[136] AD2
330U_7343 *330U_7343 330U_7343 AA7 G26 AD5
VCC[051] +VCCA_PROC R22 0_6 VSS[056] VSS[137]
AA9 VCC[052] VCCA[01] B26 H3 VSS[057] VSS[138] AD8
AA10 VCC[053] VCCA[02] C26 H6 VSS[058] VSS[139] AD11
AA12 VCC[054] H21 VSS[059] VSS[140] AD13
AA13 AD6 VCC_CORE C33 C34 H24 AD16
VCC[055] VID[0] H_VID0 [29] VSS[060] VSS[141]
AA15 VCC[056] VID[1] AF5 H_VID1 [29] J2 VSS[061] VSS[142] AD19
<Check list> AA17 VCC[057] VID[2] AE5 H_VID2 [29]
.01U_4 10U_8 J5 VSS[062] VSS[143] AD22
Option1:330U*6(ESR=1.5m ohm aggregate , ESL=0.8nH/6) and 22U*20(ESR=3mohm typ/20 , ESL=0.6nH/20) AA18 VCC[058] VID[3] AF4 H_VID3 [29] J22 VSS[063] VSS[144] AD25
AA20 AE3 R2 J25 AE1
Option2:330U*6(ESR=1.5m ohm aggregate , ESL=1.8nH/6) and 22U*32(ESR=3mohm typ/32 , ESL=0.6nH/32) VCC[059] VID[4] H_VID4 [29] VSS[064] VSS[145]
AB9 VCC[060] VID[5] AF3 H_VID5 [29] K1 VSS[065] VSS[146] AE4
AC10 AE2 100/F_6 K4 AE8
VCC[061] VID[6] H_VID6 [29] VSS[066] VSS[147]
AB10 VCC[062] K23 VSS[067] VSS[148] AE11
AB12 VCC[063] K26 VSS[068] VSS[149] AE14
AB14 VCC[064] VCCSENSE AF7 VCCSENSE [29] L3 VSS[069] VSS[150] AE16
AB15 VCC[065] L6 VSS[070] VSS[151] AE19
AB17 VCC[066] L21 VSS[071] VSS[152] AE23
AB18 VCC[067] VSSSENSE AE7 VSSSENSE [29] L24 VSS[072] VSS[153] AE26
B B
M2 VSS[073] VSS[154] A2
Merom Ball-out Rev 1a M5 AF6
VSS[074] VSS[155]
. <Demo board> M22 VSS[075] VSS[156] AF8
R3 Routing 27.4ohm with 50mils spacing M25 AF11
VSS[076] VSS[157]
N1 AF13
100/F_6 PU/PD near to CPU 1" N4
VSS[077] VSS[158]
AF16
VSS[078] VSS[159]
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
Merom Ball-out Rev 1a

.
A A

CPU(2 of 2) 1A

5 4 3 2 1
5 4 3 2 1
NB(HOST)
H_A#[35:3] [3]
U21A
[3] H_D#[63:0]
J13 H_A#3
H_D#0 H_A#_3 H_A#4
E2 H_D#_0 H_A#_4 B11
+1.05V H_D#1 G2 C11 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
G7 H_D#_2 H_A#_6 M11
H_D#3 M6 C15 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
H7 H_D#_4 H_A#_8 F16
H_D#5 H3 L13 H_A#9
R416 H_D#6 H_D#_5 H_A#_9 H_A#10
D G4 H_D#_6 H_A#_10 G17 D
H_D#7 F3 C14 H_A#11
221/F_4 H_D#8 H_D#_7 H_A#_11 H_A#12
N8 H_D#_8 H_A#_12 K16
H_D#9 H2 B13 H_A#13
H_SWING H_D#10 H_D#_9 H_A#_13 H_A#14
M10 H_D#_10 H_A#_14 L16
H_D#11 N12 J17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
N9 H_D#_12 H_A#_16 B14
R417 C436 <check list> H_D#13 H5 K19 H_A#17
100/F_4 H_D#14 H_D#_13 H_A#_17 H_A#18
0.1U close to B3 P13 H_D#_14 H_A#_18 P15
.1U_4 H_D#15 K9 R17 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
M2 H_D#_16 H_A#_20 B16
H_D#17 W10 H20 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
Y8 H_D#_18 H_A#_22 L19
H_D#19 V4 D17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
M3 H_D#_20 H_A#_24 M17
H_D#21 J1 N16 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
N5 H_D#_22 H_A#_26 J19
H_D#23 N3 B18 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
W6 H_D#_24 H_A#_28 E19
H_D#25 W9 B17 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N2 H_D#_26 H_A#_30 B15
H_RCOMP H_D#27 Y7 E17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
Y9 H_D#_28 H_A#_32 C18 H_A#[35:32] are not supported in
<check list> H_D#29 P4 A19 H_A#33 Calero Interposer
R415 H_D#30 H_D#_29 H_A#_33 H_A#34
10:20 mils(Width:Spacing) W3 B19
C
H_D#31 N1
H_D#_30 H_A#_34
N19 H_A#35 Crestline support 36 bit address C
24.9/F_4 H_D#32 H_D#_31 H_A#_35
AD12 H_D#_32
H_D#33 AE3 G12
H_D#_33 H_ADS# H_ADS# [3]
H_D#34 AD9 H17
HOST
H_D#_34 H_ADSTB#_0 H_ADSTB0# [3]
H_D#35 AC9 G20
H_D#_35 H_ADSTB#_1 H_ADSTB1# [3]
H_D#36 AC7 C8
H_D#_36 H_BNR# H_BNR# [3]
H_D#37 AC14 E8
H_D#_37 H_BPRI# H_BPRI# [3]
H_D#38 AD11 F12
H_D#_38 H_BREQ# H_BREQ#0 [3]
H_D#39 AC11 D6
H_D#_39 H_DEFER# H_DEFER# [3]
H_D#40 AB2 C10
+1.05V H_D#_40 H_DBSY# H_DBSY# [3]
H_D#41 AD7 AM5
H_D#_41 HPLL_CLK CLK_MCH_BCLK [2]
H_D#42 AB1 AM7
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# [2]
H_D#43 Y3 H8
H_D#_43 H_DPWR# H_DPWR# [3]
H_D#44 AC6 K7
H_D#_44 H_DRDY# H_DRDY# [3]
H_D#45 AE2 E4
H_D#_45 H_HIT# H_HIT# [3]
R76 H_D#46 AC5 C6
H_D#_46 H_HITM# H_HITM# [3]
H_D#47 AG3 G10
H_D#_47 H_LOCK# H_LOCK# [3]
54.9/F_4 <check list> H_D#48 AJ9 B7
H_D#_48 H_TRDY# H_TRDY# [3]
Impedance 55ohm H_D#49 AH8
H_SCOMP H_D#50 H_D#_49
AJ14 H_D#_50
H_D#51 AE9
H_D#52 H_D#_51
AE11 H_D#_52 H_DINV#[3:0] [3]
H_D#53 AH12 K5 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AJ5 H_D#_54 H_DINV#_1 L2
B H_D#55 AH5 AD13 H_DINV#2 B
+1.05V H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
AJ6 H_D#_56 H_DINV#_3 AE13
H_D#57 AE7 H_D#_57 H_DSTBN#[3:0] [3]
H_D#58 AJ7 M7 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1
AJ2 H_D#_59 H_DSTBN#_1 K3
H_D#60 AE5 AD2 H_DSTBN#2
R75 H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3
AJ3 H_D#_61 H_DSTBN#_3 AH11
<check list> H_D#62 AH2 H_D#_62 H_DSTBP#[3:0] [3]
54.9/F_4 Impedance 55ohm H_D#63 AH13 L7 H_DSTBP#0
H_D#_63 H_DSTBP#_0 H_DSTBP#1
H_DSTBP#_1 K2
H_SCOMP# AC2 H_DSTBP#2
H_SWING H_DSTBP#_2 H_DSTBP#3
B3 H_SWING H_DSTBP#_3 AJ10
H_RCOMP C2
+1.05V H_RCOMP H_REQ#[4:0] [3]
M14 H_REQ#0
H_SCOMP H_REQ#_0 H_REQ#1
W1 H_SCOMP H_REQ#_1 E13
H_SCOMP# W2 A11 H_REQ#2
H_SCOMP# H_REQ#_2 H_REQ#3
H_REQ#_3 H13
B6 B12 H_REQ#4
[3] H_CPURST# H_CPURST# H_REQ#_4
R418 E5
[3] H_CPUSLP# H_CPUSLP# H_RS#[2:0] [3]
E12 H_RS#0
1K_4 H_RS#_0 H_RS#1
H_RS#_1 D7
D8 H_RS#2
H_AVREF H_RS#_2
B9 H_AVREF
A9 H_DVREF
A A
R422 C432 <check list> CRESTLINE_1p0
0.1U close to B9
2K_4 .1U_4

1A
GMCH HOST(1 of 7)
5 4 3 2 1
5 4 3 2 1
U21B
+VCC_PEG
MCH_RSVD1 P36 U21C
T30 RSVD1
MCH_RSVD2 P37 AV29
T32 RSVD2 SM_CK_0 M_CLK_DDR0 [13]
MCH_RSVD3 R35 BB23 J40
T31 RSVD3 SM_CK_1 M_CLK_DDR1 [13] [18] INT_LVDS_PWM L_BKLT_CTRL
MCH_RSVD4 N35 BA25 H39 N43 EXP_A_COMPX R67 24.9_4
T28 RSVD4 SM_CK_3 M_CLK_DDR3 [13] [18,26] INT_LVDS_BLON L_BKLT_EN PEG_COMPI
MCH_RSVD5 AR12 AV23 +3V R414 10K_4 E39 M43
T40 RSVD5 SM_CK_4 M_CLK_DDR4 [13] L_CTRL_CLK PEG_COMPO
MCH_RSVD6 AR13 R429 10K_4 E40
T41 RSVD6 L_CTRL_DATA
MCH_RSVD7 AM12 AW30 C37
T36 RSVD7 SM_CK#_0 M_CLK_DDR#0 [13] [18] INT_LVDS_EDIDCLK L_DDC_CLK
MCH_RSVD8 AN13 BA23 D35 J51
T37 RSVD8 SM_CK#_1 M_CLK_DDR#1 [13] [18] INT_LVDS_EDIDDATA L_DDC_DATA PEG_RX#_0
MCH_RSVD9 J12 AW25 K40 L51
T22 RSVD9 SM_CK#_3 M_CLK_DDR#3 [13] [18] INT_LVDS_DIGON L_VDD_EN PEG_RX#_1
MCH_RSVD10
RSVD
T39 AR37 RSVD10 SM_CK#_4 AW23 M_CLK_DDR#4 [13] PEG_RX#_2 N47
MCH_RSVD11 AM36 R57 2.4K_4 LVDS_IBG L41 T45
T38 RSVD11 LVDS_IBG PEG_RX#_3
MCH_RSVD12 AL36 BE29 L43 T50
T35 RSVD12 SM_CKE_0 M_CKE0 [12,13] T25 LVDS_VBG PEG_RX#_4
MCH_RSVD13 AM37 AY32 N41 U40
D T34 RSVD13 SM_CKE_1 M_CKE1 [12,13] LVDS_VREFH PEG_RX#_5
MCH_RSVD14 D20 BD39 N40 Y44 D
T14 RSVD14 SM_CKE_3 M_CKE3 [12,13] LVDS_VREFL PEG_RX#_6
SM_CKE_4 BG37 M_CKE4 [12,13] [18] INT_TXLCLKOUT- D46 LVDSA_CLK# PEG_RX#_7 Y40
[18] INT_TXLCLKOUT+ C45 LVDSA_CLK PEG_RX#_8 AB51
C41 .1U_4 BG20 D44 W49
SM_CS#_0 M_CS#0 [12,13] LVDSB_CLK# PEG_RX#_9
SM_CS#_1 BK16 M_CS#1 [12,13] E42 LVDSB_CLK PEG_RX#_10 AD44
LVDS
SM_CS#_2 BG16 M_CS#2 [12,13] PEG_RX#_11 AD40
MCH_RSVD20 H10 BE13 G51 AG46
T18 RSVD20 SM_CS#_3 M_CS#3 [12,13] [18] INT_TXLOUT0- LVDSA_DATA#_0 PEG_RX#_12
MCH_RSVD21 B51 E51 AH49
MUXING
T125 RSVD21 [18] INT_TXLOUT1- LVDSA_DATA#_1 PEG_RX#_13
MCH_RSVD22 BJ20 BH18 F49 AG45
T112 RSVD22 SM_ODT_0 M_ODT0 [12,13] [18] INT_TXLOUT2- LVDSA_DATA#_2 PEG_RX#_14
MCH_RSVD23 BK22 BJ15 AG41
T113 RSVD23 SM_ODT_1 M_ODT1 [12,13] PEG_RX#_15
GRAPHICS
MCH_RSVD24 BF19 BJ14
T47 RSVD24 SM_ODT_2 M_ODT2 [12,13]
MCH_RSVD25 BH20 BE16 G50 J50
T51 RSVD25 SM_ODT_3 M_ODT3 [12,13] [18] INT_TXLOUT0+ LVDSA_DATA_0 PEG_RX_0
MCH_RSVD26 BK18 E50 L50
T116 RSVD26 [18] INT_TXLOUT1+ LVDSA_DATA_1 PEG_RX_1
MCH_RSVD27 BJ18 BL15 M_RCOMP F48 M47
T53 RSVD27 SM_RCOMP [18] INT_TXLOUT2+ LVDSA_DATA_2 PEG_RX_2
MCH_RSVD28 BF23 BK14 M_RCOMP# U44
T49 RSVD28 SM_RCOMP# SMDDR_VREF PEG_RX_3
MCH_RSVD29 BG23 T49
T50 RSVD29 PEG_RX_4
MCH_RSVD30 BC23 BK31 SM_RCOMP_VOH G44 T41
T48 RSVD30 SM_RCOMP_VOH LVDSB_DATA#_0 PEG_RX_5
MCH_RSVD31 BD24 BL31 SM_RCOMP_VOL B47 W45
T46
DDR
RSVD31 SM_RCOMP_VOL LVDSB_DATA#_1 PEG_RX_6
[12,13] M_A_A14 BJ29 RSVD32 B45 LVDSB_DATA#_2 PEG_RX_7 W41
BE24 AR49 SMDDR_VREF_MCH R108 0_6 AB50
[12,13] M_B_A14 RSVD33 SM_VREF_0 PEG_RX_8
MCH_RSVD34 BH39 AW4 Y48
T45 RSVD34 SM_VREF_1 PEG_RX_9
MCH_RSVD35 AW20 R107 *10K_6 +1.8VSUS E44 AC45
T44 RSVD35 LVDSB_DATA_0 PEG_RX_10
MCH_RSVD36 BK20 R98 *10K_6 A47 AC41
MCH_RSVD37 C48 A45 AH47
MCH_RSVD38 DREFCLK
PCI-EXPRESS
T15 D47 RSVD38 DPLL_REF_CLK B42 DREFCLK [2] PEG_RX_13 AG49
MCH_RSVD39 B44 C42 DREFCLK# AH45
T132 RSVD39 DPLL_REF_CLK# DREFCLK# [2] PEG_RX_14
MCH_RSVD40 C44 H48 DREFSSCLK AG42
T135 RSVD40 DPLL_REF_SSCLK DREFSSCLK [2] PEG_RX_15
MCH_RSVD41 A35 H47 DREFSSCLK#
T142 RSVD41 DPLL_REF_SSCLK# DREFSSCLK# [2]
MCH_RSVD42 B37 E27 N45
T145 RSVD42 TVA_DAC PEG_TX#_0
MCH_RSVD43 B36 K44 G27 U39
T129 RSVD43 PEG_CLK CLK_PCIE_3GPLL [2] TVB_DAC PEG_TX#_1
CLK
MCH_RSVD44 B34 K45 K27 U47
T138 RSVD44 PEG_CLK# CLK_PCIE_3GPLL# [2] TVC_DAC PEG_TX#_2
MCH_RSVD45
TV
T131 C34 RSVD45 PEG_TX#_3 N51
C C
DMI_TXN[3:0] [15] F27 TVA_RTN PEG_TX#_4 R50
J27 TVB_RTN PEG_TX#_5 T42
AN47 DMI_TXN0 L27 Y43
DMI_RXN_0 DMI_TXN1 TVC_RTN PEG_TX#_6
DMI_RXN_1 AJ38 PEG_TX#_7 W46
AN42 DMI_TXN2 M35 W38
DMI_RXN_2 DMI_TXN3 TV_DCONSEL_0 PEG_TX#_8
DMI_RXN_3 AN46 DMI_TXP[3:0] [15] P33 TV_DCONSEL_1 PEG_TX#_9 AD39
PEG_TX#_10 AC46
AM47 DMI_TXP0 R34 *0_4 AC49
DMI_RXP_0 DMI_TXP1 R37 *0_4 PEG_TX#_11
[2] MCH_BSEL0 P27 CFG_0 DMI_RXP_1 AJ39 PEG_TX#_12 AC42
N27 AN41 DMI_TXP2 AH39
[2] MCH_BSEL1 CFG_1 DMI_RXP_2 PEG_TX#_13
N24 AN45 DMI_TXP3 AE49
[2] MCH_BSEL2 CFG_2 DMI_RXP_3 DMI_RXN[3:0] [15] PEG_TX#_14
MCH_CFG_3 C21 AH44
T130 CFG_3 PEG_TX#_15
MCH_CFG_4 C23 AJ46 DMI_RXN0
T134 CFG_4 DMI_TXN_0
[11] MCH_CFG_5 F23 CFG_5 DMI_TXN_1 AJ41 DMI_RXN1 [18] CRT_B
CRT_B H32 CRT_BLUE PEG_TX_0 M45
MCH_CFG_6 N23 AM40 DMI_RXN2 G32 T38
T29 CFG_6 DMI_TXN_2 CRT_BLUE# PEG_TX_1
MCH_CFG_7 G23 AM44 DMI_RXN3 CRT_G K29 T46
T19 CFG_7 DMI_TXN_3 DMI_RXP[3:0] [15] [18] CRT_G CRT_GREEN PEG_TX_2
MCH_CFG_8 J20 J29 N50
T20
DMI
CFG_8 CRT_GREEN# PEG_TX_3

AJ47 DMI_RXP0 CRT_R
CFG
[11] MCH_CFG_9 C20 CFG_9 DMI_TXP_0 [18] CRT_R F29 CRT_RED PEG_TX_4 R51
MCH_CFG_10 AJ42 DMI_RXP1
VGA
T33 R24 CFG_10 DMI_TXP_1 E29 CRT_RED# PEG_TX_5 U43
MCH_CFG_11 L23 AM39 DMI_RXP2 W42
T27 CFG_11 DMI_TXP_2 PEG_TX_6
[11] MCH_CFG_12 J23 CFG_12 DMI_TXP_3 AM43 DMI_RXP3 PEG_TX_7 Y47
[11] MCH_CFG_13 E23 DDCCLK K33 Y39
CFG_13 [18] DDCCLK CRT_DDC_CLK PEG_TX_8
MCH_CFG_14 E20 DDCDAT G35 AC38
T13 CFG_14 [18] DDCDAT CRT_DDC_DATA PEG_TX_9
MCH_CFG_15 K23 R41 30_4 HSYNC_A F33 AD47
T23 CFG_15 [18] HSYNC CRT_HSYNC PEG_TX_10
[11] MCH_CFG_16 M20 R419 1.3K_6 CRTIREF C32 AC50
MCH_CFG_17 CFG_16 R40 30_4 VSYNC_A CRT_TVO_IREF PEG_TX_11
T26 M24 CFG_17 [18] VSYNC E33 CRT_VSYNC PEG_TX_12 AD43
GRAPHICS VID
MCH_CFG_18 L32 AG39

T21 CFG_18 PEG_TX_13
[11] MCH_CFG_19 N33 CFG_19 PEG_TX_14 AE50
[11] MCH_CFG_20 L35 CFG_20 PEG_TX_15 AH43
E35 T16 CRESTLINE_1p0

B R50 0_4 PM_BMBUSY#_R GFX_VID_0 T144 B
[16] PM_BMBUSY# G41 PM_BM_BUSY# GFX_VID_1 A39
[3,14,29] ICH_DPRSTP# R45 0_4 ICH_DPRSTP#_R L39 C38 T133
PM_EXTTS#0 PM_DPRSTP# GFX_VID_2 T140
[13] PM_EXTTS#0 L36 PM_EXT_TS#_0 GFX_VID_3 B39
R38 0_4 PM_EXTTS#1_R T143 R46 150_4 CRT_B
PM
[13] PM_EXTTS#1 J36 PM_EXT_TS#_1 GFX_VR_EN E36

3,16,29] DELAY_VR_PWRGOOD AW49 PWROK
R97 100_4RST_IN#_MCH AV20 R52 150_4 CRT_G
[15] PLTRST#_NB RSTIN# +1.25V_AXD
[3,14] PM_THRMTRIP# R64 PM_THRMTRIP#_GMCH N20
*0_4
R42 0_4PM_DPRSLPVR_GMCH G36 THERMTRIP# R49 150_4 CRT_R
[16,29] PM_DPRSLPVR DPRSLPVR
AM49 R84
CL_CLK CL_CLK0 [16]
CL_DATA AK50 CL_DATA0 [16]
T122 TP_MCH_NC1 BJ51 AT43 1K_4
NC_1 CL_PWROK MPWROK [16]
T123 TP_MCH_NC2 BK51 AN49
ME
NC_2 CL_RST# CL_RST#0 [16]

T120 TP_MCH_NC3 BK50 AM50 +1.25V_CL_VREF
TP_MCH_NC4 NC_3 CL_VREF
T118 BL50
TP_MCH_NC5 NC_4
T114 BL49
TP_MCH_NC6 NC_5 C67 R83
T117 BL3
TP_MCH_NC7 NC_6
T115 BL2
TP_MCH_NC8 NC_7 .1U_4 392_6
NC
T121 BK1
TP_MCH_NC9 NC_8 T17
T124 BJ1 H35
TP_MCH_NC10 NC_9 SDVO_CTRL_CLK T24
T126 E1 K36
MISC
TP_MCH_NC11 NC_10 SDVO_CTRL_DATA

T139 A5 NC_11 CLK_REQ# G39 CLK_MCH_OE# CLK_MCH_OE# [2]
T127 TP_MCH_NC12 C51 G40
NC_12 ICH_SYNC# MCH_ICH_SYNC# [16]
T128 TP_MCH_NC13 B50
TP_MCH_NC14 NC_13
T137 A50
TP_MCH_NC15 NC_14
T136 A49 NC_15 TEST_1 A37 GMCH_TEST1 R428 0_4
T119 TP_MCH_NC16 BK2 R32 GMCH_TEST2 R70 20K_4
NC_16 TEST_2
CRESTLINE_1p0
+1.8VSUS R106 1K_4 SM_RCOMP_VOH
A R104 C93 C95 A
3.01K_4 .01U_4 2.2U_6

M_RCOMP# +1.8VSUS +3V
R102 SM_RCOMP_VOL
R105 R44 10K_4 CLK_MCH_OE#
20_4
20_4 R39 10K_4 PM_EXTTS#0
R103 C97 C98
M_RCOMP R32 10K_4 PM_EXTTS#1 PROJECT : BU1 Santa Rosa
1K_4 .01U_4 2.2U_6 Size Document Number Rev
GMCH DMI/VIDEO(2 of 7) 1A

5 4 3 2 1
5 4 3 2 1
NB(Memory controller)
[13] M_A_DQ[63:0] [13] M_B_DQ[63:0]

U21D U21E
D M_A_DQ0 AR43 BB19 M_B_DQ0 AP49 AY17 D
SA_DQ_0 SA_BS_0 M_A_BS#0 [12,13] SB_DQ_0 SB_BS_0 M_B_BS#0 [12,13]
M_A_DQ1 AW44 BK19 M_B_DQ1 AR51 BG18
M_A_DQ2 BA45 BF29 M_B_DQ2 AW50 BG36
M_A_DQ3 AY46 M_B_DQ3 AW51
SA_DQ_3 M_A_CAS# [12,13] SB_DQ_3 M_B_CAS# [12,13]
M_A_DQ4 AR41 BL17 M_B_DQ4 AN51 BE17
M_A_DQ5 SA_DQ_4 SA_CAS# M_B_DQ5 SB_DQ_4 SB_CAS#
AR45 SA_DQ_5 M_A_DM[7:0] [13] AN50 SB_DQ_5 M_B_DM[7:0] [13]
M_A_DQ6 AT42 AT45 M_A_DM0 M_B_DQ6 AV50 AR50 M_B_DM0
M_A_DQ7 SA_DQ_6 SA_DM_0 M_A_DM1 M_B_DQ7 SB_DQ_6 SB_DM_0 M_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
M_A_DQ8 BB45 BD42 M_A_DM2 M_B_DQ8 BA50 BK45 M_B_DM2
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
M_A_DQ10 BG47 AW13 M_A_DM4 M_B_DQ10 BA49 BH12 M_B_DM4
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
M_A_DQ12 BB47 AY5 M_A_DM6 M_B_DQ12 BA51 BF3 M_B_DM6
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
M_A_DQ14 BH49 M_B_DQ14 BF50
SA_DQ_14 M_A_DQS[7:0] [13] SB_DQ_14 M_B_DQS[7:0] [13]
M_A_DQ15 BE45 AT46 M_A_DQS0 M_B_DQ15 BF49 AT50 M_B_DQS0
A
SA_DQ_15 SA_DQS_0 SB_DQ_15 SB_DQS_0
B
M_A_DQ16 AW43 BE48 M_A_DQS1 M_B_DQ16 BJ50 BD50 M_B_DQS1
M_A_DQ17 SA_DQ_16 SA_DQS_1 M_A_DQS2 M_B_DQ17 SB_DQ_16 SB_DQS_1 M_B_DQS2
BE44 SA_DQ_17 SA_DQS_2 BB43 BJ44 SB_DQ_17 SB_DQS_2 BK46
M_A_DQ18 BG42 BC37 M_A_DQS3 M_B_DQ18 BJ43 BK39 M_B_DQS3
BE40 SA_DQ_19 SA_DQS_4 BB16 BL43 SB_DQ_19 SB_DQS_4 BJ12
M_A_DQ20 BF44 BH6 M_A_DQS5 M_B_DQ20 BK47 BL7 M_B_DQS5
MEMORY
SA_DQ_20 SA_DQS_5 SB_DQ_20 SB_DQS_5
MEMORY
M_A_DQ21 BH45 BB2 M_A_DQS6 M_B_DQ21 BK49 BE2 M_B_DQS6
BG40 SA_DQ_22 SA_DQS_7 AP3 M_A_DQS#[7:0] [13] BK43 SB_DQ_22 SB_DQS_7 AV2 M_B_DQS#[7:0] [13]
M_A_DQ23 BF40 AT47 M_A_DQS#0 M_B_DQ23 BK42 AU50 M_B_DQS#0
M_A_DQ24 SA_DQ_23 SA_DQS#_0 M_A_DQS#1 M_B_DQ24 SB_DQ_23 SB_DQS#_0 M_B_DQS#1
C
AR40 SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50 C
M_A_DQ25 AW40 BC41 M_A_DQS#2 M_B_DQ25 BL41 BL45 M_B_DQS#2
AT39 SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
M_A_DQ27 AW36 BA16 M_A_DQS#4 M_B_DQ27 BJ36 BK12 M_B_DQS#4
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
M_A_DQ29 AY41 BC1 M_A_DQS#6 M_B_DQ29 BJ40 BF2 M_B_DQS#6
AV38 SA_DQ_30 SA_DQS#_7 AP2 BL35 SB_DQ_30 SB_DQS#_7 AV3
M_A_DQ31 AT38 M_B_DQ31 BK37
SA_DQ_31 M_A_A[13:0] [12,13] SB_DQ_31 M_B_A[13:0] [12,13]
M_A_DQ32 AV13 BJ19 M_A_A0 M_B_DQ32 BK13 BC18 M_B_A0
M_A_DQ33 SA_DQ_32 SA_MA_0 M_A_A1 M_B_DQ33 SB_DQ_32 SB_MA_0 M_B_A1
SYSTEM
AT13 SA_DQ_33 SA_MA_1 BD20 BE11 SB_DQ_33 SB_MA_1 BG28
SYSTEM
M_A_DQ34 AW11 BK27 M_A_A2 M_B_DQ34 BK11 BG25 M_B_A2
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
M_A_DQ36 AU15 BL24 M_A_A4 M_B_DQ36 BC13 BF25 M_B_A4
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
M_A_DQ38 BA13 BJ27 M_A_A6 M_B_DQ38 BC12 BA29 M_B_A6
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
M_A_DQ40 BE10 BL28 M_A_A8 M_B_DQ40 BJ10 AY28 M_B_A8
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
M_A_DQ42 BD8 BC19 M_A_A10 M_B_DQ42 BK5 BG17 M_B_A10
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
M_A_DQ44 BG10 BG30 M_A_A12 M_B_DQ44 BK9 BA39 M_B_A12
AW9 SA_DQ_45 SA_MA_13 BJ16 BK10 SB_DQ_45 SB_MA_13 BG13
DDR
M_A_DQ46 BD7 M_B_DQ46 BJ8

SA_DQ_46 SB_DQ_46
DDR
M_A_DQ47 BB9 M_B_DQ47 BJ6 AV16
SA_DQ_47 SB_DQ_47 SB_RAS# M_B_RAS# [12,13]
M_A_DQ48 BB5 BE18 M_B_DQ48 BF4 AY18 TP_SB_RCVEN#
SA_DQ_48 SA_RAS# M_A_RAS# [12,13] SB_DQ_48 SB_RCVEN# T42
B M_A_DQ49 AY7 AY20 TP_SA_RCVEN# M_B_DQ49 BH5 B
SA_DQ_49 SA_RCVEN# T43 SB_DQ_49
M_A_DQ50 AT5 M_B_DQ50 BG1 BC17
SA_DQ_50 SB_DQ_50 SB_WE# M_B_WE# [12,13]
M_A_DQ51 AT7 BA19 M_B_DQ51 BC2
SA_DQ_51 SA_WE# M_A_WE# [12,13] SB_DQ_51
M_A_DQ52 AY6 M_B_DQ52 BK3
M_A_DQ53 SA_DQ_52 M_B_DQ53 SB_DQ_52
BB7 SA_DQ_53 BE4 SB_DQ_53
M_A_DQ54 AR5 M_B_DQ54 BD3
AR8 SA_DQ_55 BJ2 SB_DQ_55
M_A_DQ56 AR9 M_B_DQ56 BA3
AN3 SA_DQ_57 BB3 SB_DQ_57
M_A_DQ58 AM8 M_B_DQ58 AR1
AN10 SA_DQ_59 AT3 SB_DQ_59
M_A_DQ60 AT9 M_B_DQ60 AY2
AN9 SA_DQ_61 AY3 SB_DQ_61
M_A_DQ62 AM9 M_B_DQ62 AU2
AN11 SA_DQ_63 AT2 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0
A A

MCH DDR(3 of 7) 1A

5 4 3 2 1
5 4 3 2 1
+3V_VCCSYNC +1.05V
NB(Power-1) R61 10_4 VCCGFPLLOW D4 1 2 PDZ5.6B
+1.05V
+1.05V ADD 10ohm
U21G THEY ONLY USE IN UMA (GM OR GML)
AT35 U21F
VCC_1
AT34 VCC_2 VCC_AXG_NCTF_1 T17
AH28 VCC_3 VCC_AXG_NCTF_2 T18 +1.05V AB33 VCC_NCTF_1
AC32 VCC_5 VCC_AXG_NCTF_3 T19 AB36 VCC_NCTF_2
D
AC31 VCC_4 VCC_AXG_NCTF_4 T21 AB37 VCC_NCTF_3 D
AK32 T22 + C423 C74 C59 C73 C63 AC33 T27
VCC_6 VCC_AXG_NCTF_5 VCC_NCTF_4 VSS_NCTF_1
AJ31 VCC_7 VCC_AXG_NCTF_6 T23 AC35 VCC_NCTF_5 VSS_NCTF_2 T37
AJ28 T25 330U_3528 22U_8 .22U_4 .22U_4 .1U_4 AC36 U24
AH32 VCC_9 VCC_AXG_NCTF_8 U15 AD35 VCC_NCTF_7 VSS_NCTF_4 U28
VCC CORE
AH31 VCC_10 VCC_AXG_NCTF_9 U16 AD36 VCC_NCTF_8 VSS_NCTF_5 V31
AH29 VCC_11 VCC_AXG_NCTF_10 U17 AF33 VCC_NCTF_9 VSS_NCTF_6 V35
AF32 VCC_12 VCC_AXG_NCTF_11 U19 AF36 VCC_NCTF_10 VSS_NCTF_7 AA19
VCC_AXG_NCTF_12 U20 AH33 VCC_NCTF_11 VSS_NCTF_8 AB17
VSS NCTF
VCC_AXG_NCTF_13 U21 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35
VCC_AXG_NCTF_14 U23 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19
R69 0_4 +1.05V_VCC_GMCH_VCC13 R30 U26 AH37 AD37
VCC_AXG_NCTF_16 V16 AJ33 VCC_NCTF_15 VSS_NCTF_12 AF17
VCC_AXG_NCTF_17 V17 AJ35 VCC_NCTF_16 VSS_NCTF_13 AF35
VCC_AXG_NCTF_18 V19 AK33 VCC_NCTF_17 VSS_NCTF_14 AK17
VCC_AXG_NCTF_19 V20 AK35 VCC_NCTF_18 VSS_NCTF_15 AM17
VCC_AXG_NCTF_20 V21 AK36 VCC_NCTF_19 VSS_NCTF_16 AM24
V23 +1.05V AK37 AP26
VCC_AXG_NCTF_21 VCC_NCTF_20 VSS_NCTF_17
VCC_AXG_NCTF_22 V24 AD33 VCC_NCTF_21 VSS_NCTF_18 AP28
+1.8VSUS +1.8VSUS Y15 AJ36 AR15
POWER VCC_AXG_NCTF_23 VCC_NCTF_22 VSS_NCTF_19
VCC NCTF
VCC_AXG_NCTF_24 Y16 AM35 VCC_NCTF_23 VSS_NCTF_20 AR19
VCC_AXG_NCTF_25 Y17 AL33 VCC_NCTF_24 VSS_NCTF_21 AR28
AU32 Y19 + C413 + C417 C81 C61 C57 C58 C76 C60 AL35
VCC_SM_1 VCC_AXG_NCTF_26 VCC_NCTF_25
AU33 VCC_SM_2 VCC_AXG_NCTF_27 Y20 AA33 VCC_NCTF_26
AU35 Y21 330U_3528 .47U_6 1U_6 10U_8 22U_8 .1U_4 .1U_4 AA35
VCC_SM_3 VCC_AXG_NCTF_28 330U_3528 VCC_NCTF_27
AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23 AA36 VCC_NCTF_28
C89 C102 C108 AW33 Y24 AP35
AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26 AP36 VCC_NCTF_30
.1U_4 22U_8 22U_8 AY35 Y28 AR35
BA32 VCC_SM_8 VCC_AXG_NCTF_33 Y29 AR36 VCC_NCTF_32
C BA33 VCC_SM_9 VCC_AXG_NCTF_34 AA16 Y32 VCC_NCTF_33
C
BA35 AA17 Y33
BB33
BC32
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
AB16
AB19
Y35
Y36
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
POWER
BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16 Y37 VCC_NCTF_37 VSS_SCB1 A3
BC35 VCC_SM_14 VCC SM VCC_AXG_NCTF_39 AC17 T30 VCC_NCTF_38 VSS_SCB2 B2
VSS SCB
BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19 T34 VCC_NCTF_39 VSS_SCB3 C1
BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15 T35 VCC_NCTF_40 VSS_SCB4 BL1
BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16 U29 VCC_NCTF_41 VSS_SCB5 BL51
BE33 VCC_SM_18 VCC_AXG_NCTF_43 AD17 U31 VCC_NCTF_42 VSS_SCB6 A51
BE35
BF33
VCC_SM_19 VCC GFX NCTF VCC_AXG_NCTF_44 AF16
AF19
U32
U33
VCC_NCTF_43
BF34 VCC_SM_21 VCC_AXG_NCTF_46 AH15 U35 VCC_NCTF_45
BG32 VCC_SM_22 VCC_AXG_NCTF_47 AH16 U36 VCC_NCTF_46
BG33 AH17 V32 +1.05V
BG35 VCC_SM_24 VCC_AXG_NCTF_49 AH19 V33 VCC_NCTF_48
BH32 AJ16 V36 R89
BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17 V37 VCC_NCTF_50
BH35 VCC_SM_27 VCC_AXG_NCTF_52 AJ19
BJ32 AK16 AT33 0_6
VCC_SM_28 VCC_AXG_NCTF_53 VCC_AXM_1
BJ33 VCC_SM_29 VCC_AXG_NCTF_54 AK19 VCC_AXM_2 AT31
+1.05V
VCC AXM
BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16 VCC_AXM_3 AK29
BK32 VCC_SM_31 VCC_AXG_NCTF_56 AL17 VCC_AXM_4 AK24
BK33 VCC_SM_32 VCC_AXG_NCTF_57 AL19 VCC_AXM_5 AK23
BK34 VCC_SM_33 VCC_AXG_NCTF_58 AL20 AL24 VCC_AXM_NCTF_1 VCC_AXM_6 AJ26
BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21 AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23
BL33 VCC_SM_35 VCC_AXG_NCTF_60 AL23 AL28 VCC_AXM_NCTF_3
AU30 AM15 C66 C70 C71 C62 C69 C64 AM26
VCC_SM_36 VCC_AXG_NCTF_61 VCC_AXM_NCTF_4
VCC AXM NCTF

VCC_AXG_NCTF_62 AM16 AM28 VCC_AXM_NCTF_5
+1.05V AM19 22U_8 .22U_4 .22U_4 .1U_4 .1U_4 .1U_4 AM29
B VCC_AXG_NCTF_63 VCC_AXM_NCTF_6 B
R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23 AM33 VCC_AXM_NCTF_9
T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15 AP29 VCC_AXM_NCTF_10
W13 VCC_AXG_3 VCC_AXG_NCTF_68 AP16 AP31 VCC_AXM_NCTF_11
W14 VCC_AXG_4 VCC_AXG_NCTF_69 AP17 AP32 VCC_AXM_NCTF_12
Y12 VCC_AXG_5 VCC_AXG_NCTF_70 AP19 AP33 VCC_AXM_NCTF_13
AA20 VCC_AXG_6 VCC_AXG_NCTF_71 AP20 AL29 VCC_AXM_NCTF_14
AA28 VCC_AXG_9 VCC_AXG_NCTF_74 AP24 AR31 VCC_AXM_NCTF_17
AB21 VCC_AXG_10 VCC_AXG_NCTF_75 AR20 AR32 VCC_AXM_NCTF_18
AB24 VCC_AXG_11 VCC_AXG_NCTF_76 AR21 AR33 VCC_AXM_NCTF_19
AB29 VCC_AXG_12 VCC_AXG_NCTF_77 AR23
AC20 VCC_AXG_13 VCC_AXG_NCTF_78 AR24
VCC GFX
AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26

AC23 VCC_AXG_15 VCC_AXG_NCTF_80 V26
AC24 V28 CRESTLINE_1p0
VCC_AXG_16 VCC_AXG_NCTF_81
AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
AC28 VCC_AXG_18 VCC_AXG_NCTF_83 Y31
AC29 VCC_AXG_19
AD20 VCC_AXG_20
AD23 VCC_AXG_21
AD24 AW45 VCCSM_LF1
VCC_AXG_22 VCC_SM_LF1 VCCSM_LF2
AD28 VCC_AXG_23 VCC_SM_LF2 BC39
VCCSM_LF3
VCC SM LF
AF21 VCC_AXG_24 VCC_SM_LF3 BE39

AF26 BD17 VCCSM_LF4
AA31 VCC_AXG_26 VCC_SM_LF5 BD4
AH20 AW8 VCCSM_LF6
A AH21 VCC_AXG_28 VCC_SM_LF7 AT6 A
AH23 VCC_AXG_29
AH24 C82 C84 C90 C88 C92 C86 C85
VCC_AXG_30
AH26 VCC_AXG_31
AD31 .1U_4 .1U_4 .22U_4 .22U_4 .47U_6 1U_6 1U_6
VCC_AXG_32
AJ20 VCC_AXG_33
AN14 VCC_AXG_34 Quanta Computer Inc.
CRESTLINE_1p0
GMCH Power-1(4 of 7) 1A
Date: Thursday, February 01, 2007 Sheet 8 of 33

5 4 3 2 1
5 4 3 2 1
NB(Power-2) +3V_VCCSYNC
CRT/TV Disable/Enable guideline
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
+3V R33 0_6
If SDVO Disable If SDVO enable If SDVO enable
'IND CHIP 10UH(20%,100MA,LB2012T100MR)' C45 Ball Enable Disable Ball Enable Disable Signal LVDS Disable LVDS Disable LVDS enable
<FAE>
INT VGA disable .1U_4 VCCA_CRT 3.3V GND VCCA_C_TVO 3.3V GND VCCD_LVDS GND 1.8V 1.8V
+1.25V L1 10UH_8
VCCSYNC connect to GND VCCD_CRT 1.5V GND VCCD_TVO 1.5V 1.5V VCCA_LVDS GND GND 1.8V
+ C451 C39 VCCDQ_CRT 1.5V GND VCCABG_DAC 3.3V GND VCCTX_LVDS GND GND 1.8V
+3V L29 PBY160808T-301Y-N_6
470U_7343 .1U_4 VCCA_A_TVO 3.3V GND VSSABG_DAC GND GND
C446 C430 C448 R421 EXTERNAL INTERNAL
D VCCA_B_TVO 3.3V GND VCC_SYNC 3.3V GND D
*22U_8 .1U_4 22N_4 *0_4
+1.05V
U21H
+1.05V
J32 VCCSYNC VTT_1 U13
+1.25V L2 10UH_8 +3V_TV_DAC R426 0_6 U12
+3V_VCCA_CRT_DAC VTT_2
A33 VCCA_CRT_DAC_1 VTT_3 U11
C429 C438 R425 B33 U9 C53 C51 C52 C56 + C421
+ C452 C44 VCCA_CRT_DAC_2 VTT_4
VTT_5 U8
.1U_4 22N_4 *0_4 4.7U_8 4.7U_8 2.2U_8 .47U_6 330U_3528
CRT
VTT_6 U7
470U_7343 .1U_4 +3V_VCCA_DAC_BG A30 U5
VCCA_DAC_BG VTT_7
VTT_8 U3
B32 U2 +1.25V_AXD
VSSA_DAC_BG VTT_9
VTT_10 U1
VTT_11 T13
+1.25V_VCCA_DPLLA R93 0_6
VTT
B49 VCCA_DPLLA VTT_12 T11 +1.25V
VTT_13 T10
+1.25V_VCCA_DPLLB H49 T9
'EMI FILTER BKP1608HS181-T(180,1.5A)' VCCA_DPLLB VTT_14 C83 C77
VTT_15 T7
L23 PBY160808T-301Y-N_6 +1.25VM_VCCA_HPLL
PLL
+1.25V AL2 VCCA_HPLL VTT_16 T6
T5 1U_6 *22U_8
C410 C72 +1.25VM_VCCA_MPLL VTT_17
AM2 VCCA_MPLL VTT_18 T3
VTT_19 T2
22U_8 .1U_4 R3
+1.8VSUS_VCC_TX_LVDS VTT_20 R424 0_6
A LVDS
A41 VCCA_LVDS VTT_21 R2 +1.25V
VTT_22 R1
B41 VSSA_LVDS
L24 PBY160808T-301Y-N_6 C435 C443 C442
VCC_AXD_1 AT23
1000P_4 AU28 1U_6 10U_8
C75 VCC_AXD_2
K50 VCCA_PEG_BG VCC_AXD_3 AU24
C R403 R53 0_8 +3V_VCCA_PEG_BG C
AXD
+3V VCC_AXD_4 AT29
0.5_6 .1U_4 K49 AT25
C48 VSSA_PEG_BG VCC_AXD_5
A PEG
VCC_AXD_6 AT30
C409 22U_8 V1.25M_MPLL_RC R91 0_6 +1.25V
.1U_4 +1.25V_VCCD_PEG_PLL U51 AR29
VCCA_PEG_PLL VCC_AXD_NCTF C68
+1.25V R118 0_6 +1.25VM_VCCA_SM AW18 B23 +1.25V_VCC_AXF .1U_4

VCCA_SM_1 VCC_AXF_1
AV19 B21
C399 C103 C79 C110 C80 VCCA_SM_2
POWER VCC_AXF_2
AXF
AU19 VCCA_SM_3 VCC_AXF_3 A21
+ AU18 L5 1UH_8 +1.8VSUS
100U_3528 *22U_8 4.7U_6 22U_8 1U_6 VCCA_SM_4
AU17 VCCA_SM_5 VCC_DMI AJ50 +1.25V_VCC_DMI
C94 C96
R109 1_6 +V1.8_SMCK_RC C119 22U_8
A SM
AT22 VCCA_SM_7
AT21 VCCA_SM_8 VCC_SM_CK_1 BK24 +1.8VSUS_VCC_SM_CK .1U_4 22U_8
SM CK
AT19 VCCA_SM_9 VCC_SM_CK_2 BK23
AT18 VCCA_SM_10 VCC_SM_CK_3 BJ24
+1.25V R110 0_6 AT17 BJ23
VCCA_SM_11 VCC_SM_CK_4
AR17 VCCA_SM_NCTF_1
C105 C106 C107 C87 AR16 VCCA_SM_NCTF_2
+3V_TV_DAC +1.8VSUS
L28 *1U_6 *1U_6 22U_8 .1U_4 A43 +1.8VSUS_VCC_TX_LVDS L27 1UH_8
PBY160808T-301Y-N_6 +1.25VM_VCCA_SM_CK VCC_TX_LVDS
A CK
BC29 VCCA_SM_CK_1
+3V BB29 VCCA_SM_CK_2
C40 +3V_VCC_HV C434 + C450
C433 C447 R413 VCC_HV_1
C25 VCCA_TVA_DAC_1 VCC_HV_2 B40
1000P_4 220U_7343
HV
B25 VCCA_TVA_DAC_2
.1U_4 22N_4 *0_4 C27 VCCA_TVB_DAC_1
B27 VCCA_TVB_DAC_2 VCC_PEG_1 AD51
TV
B28 VCCA_TVC_DAC_1 VCC_PEG_2 W50
+VCC_PEG
PEG
A28 VCCA_TVC_DAC_2 VCC_PEG_3 W51
R60 *0_4 V49
B VCC_PEG_4 B
VCC_PEG_5 V50
R31 0_6 +1.5V_VCCD_CRT
D TV/CRT
M32 VCCD_CRT
+1.5V_VCCD_TVDAC L29
C441 C444 R427 VCCD_TVDAC
VCC_RXR_DMI_1 AH50
+1.5V_VCCD_QDAC
DMI
N28 VCCD_QDAC VCC_RXR_DMI_2 AH51
.1U_4 22N_4 *0_4
+1.25V R92 0_6 +1.25VM_MCH_VCCD_HPLL AN2 VCCD_HPLL L22 91nH
VTTLF1 A7 +1.05V
C78 +1.25V_VCCD_PEG_PLL
VTTLF
U48 VCCD_PEG_PLL VTTLF2 F2
VTTLF3 AH1
.1U_4 C54 J41 C405 + C400
VCCD_LVDS_1 LVDS C65 C42 C437
H42 VCCD_LVDS_2
C445 C449 C439 C431 R423 .1U_4 10U_8
.47U_4 .47U_4 .47U_4 330U_3528
22U_8 10U_8 .1U_4 22N_4 *0_4 +1.25V L3 PBY160808T-301Y-N_6
CRESTLINE_1p0 <FAE>
VCC_RXR_DMI and VCC_PEG
R43 C55 connect to+1.05V
1_8 .1U_4
+V1.25S_PEGPLL_FB
C40
10U_8
+1.5V R30 0_6
C47 C38
.1U_4 22N_4 +1.05V D26 2 1 PDZ5.6B +1.05V_SD

A A
+3V_VCC_HV
+1.8VSUS R420 0_6 +1.8V_VCCD_LVDS R436
10_4
R29 100/F_6 C46 C440
+3V R433 0_4
1U_6 *10U_8
C50 C37 C49
C453
.1U_4 22N_4 1U_6 <CRB> PROJECT : BU1 Santa Rosa
+1.25V AND +1.25M shall be .1U_4
+1.5V for Calero Interposer
Date: Tuesday, February 06, 2007 Sheet 9 of 33

5 4 3 2 1
5 4 3 2 1
NB(Power-3)
U21I
U21J
A13 VSS_1 VSS_100 AW24 C46 VSS_199 VSS_287 W11
A24 VSS_4 VSS_103 AW5 D13 VSS_202 VSS_290 W47
AA21 VSS_5 VSS_104 AW7 D24 VSS_203 VSS_291 W5
AA24 VSS_6 VSS_105 AY10 D3 VSS_204 VSS_292 W7
AA29 VSS_7 VSS_106 AY24 D32 VSS_205 VSS_293 Y13
AB20 VSS_8 VSS_107 AY37 D39 VSS_206 VSS_294 Y2
D AB23 AY42 D45 Y41 D
VSS_9 VSS_108 VSS_207 VSS_295
AB26 VSS_10 VSS_109 AY43 D49 VSS_208 VSS_296 Y45
AB28 VSS_11 VSS_110 AY45 E10 VSS_209 VSS_297 Y49
AB31 VSS_12 VSS_111 AY47 E16 VSS_210 VSS_298 Y5
AC10 VSS_13 VSS_112 AY50 E24 VSS_211 VSS_299 Y50
AC13 VSS_14 VSS_113 B10 E28 VSS_212 VSS_300 Y11
AC3 VSS_15 VSS_114 B20 E32 VSS_213 VSS_301 P29
AC39 B24 E47 T29 VSS_GMCH_T29 R35 0_4
VSS_16 VSS_115 VSS_214 VSS_302 VSS_GMCH_T31 R27 0_4
AC43 VSS_17 VSS_116 B29 F19 VSS_215 VSS_303 T31
AC47 B30 F36 T33 VSS_GMCH_T33 R28 0_4
VSS_18 VSS_117 VSS_216 VSS_304 VSS_GMCH_R28 R63 0_4
AD1 VSS_19 VSS_118 B35 F4 VSS_217 VSS_305 R28
AD21 VSS_20 VSS_119 B38 F40 VSS_218
AD26 VSS_21 VSS_120 B43 F50 VSS_219
AD29 VSS_22 VSS_121 B46 G1 VSS_220
AD3 VSS_23 VSS_122 B5 G13 VSS_221 VSS_306 AA32
AD41 VSS_24 VSS_123 B8 G16 VSS_222 VSS_307 AB32
AD45 VSS_25 VSS_124 BA1 G19 VSS_223 VSS_308 AD32
AD49 VSS_26 VSS_125 BA17 G24 VSS_224 VSS_309 AF28
AD5 VSS_27 VSS_126 BA18 G28 VSS_225 VSS_310 AF29
AD50 VSS_28 VSS_127 BA2 G29 VSS_226 VSS_311 AT27
AD8 VSS_29 VSS_128 BA24 G33 VSS_227 VSS_312 AV25
AE10 VSS_30 VSS_129 BB12 G42 VSS_228 VSS_313 H50
AE14 VSS_31 VSS_130 BB25 G45 VSS_229
AE6 VSS_32 VSS_131 BB40 G48 VSS_230
AF20 BB44 G8
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
H24
H28
VSS_231
VSS_232
VSS_233
AF31 VSS_36 VSS_135 BC16 H4 VSS_234
C AG2 VSS_37 VSS_136 BC24 H45 VSS_235 C
AG38 VSS_38 VSS_137 BC25 J11 VSS_236
AG43 VSS_39 VSS_138 BC36 J16 VSS_237
AG47 VSS_40 VSS_139 BC40 J2 VSS_238
AG50 VSS_41 VSS_140 BC51 J24 VSS_239
AH3 VSS_42 VSS_141 BD13 J28 VSS_240
AH40 BD2 J33
AH41
AH7
VSS_43
VSS_44
VSS_45
VSS_142
VSS_143
VSS_144
BD28
BD45
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AH9 VSS_46 VSS_145 BD48
AJ11 VSS_47 VSS_146 BD5 K12 VSS_245
AJ13 VSS_48 VSS_147 BE1 K47 VSS_246
AJ21 VSS_49 VSS_148 BE19 K8 VSS_247
AJ24 VSS_50 VSS_149 BE23 L1 VSS_248
AJ29 VSS_51 VSS_150 BE30 L17 VSS_249
AJ32 VSS_52 VSS_151 BE42 L20 VSS_250
AJ43 VSS_53 VSS_152 BE51 L24 VSS_251
AJ45 VSS_54 VSS_153 BE8 L28 VSS_252
AJ49 VSS_55 VSS_154 BF12 L3 VSS_253
AK20 VSS_56 VSS_155 BF16 L33 VSS_254
AK21 VSS_57 VSS_156 BF36 L49 VSS_255
AK26 VSS_58 VSS_157 BG19 M28 VSS_256
AK28 VSS_59 VSS_158 BG2 M42 VSS_257
AK31 VSS_60 VSS_159 BG24 M46 VSS_258
AK51 VSS_61 VSS_160 BG29 M49 VSS_259
AL1 VSS_62 VSS_161 BG39 M5 VSS_260
AM11 VSS_63 VSS_162 BG48 M50 VSS_261
AM13 VSS_64 VSS_163 BG5 M9 VSS_262
B AM3 VSS_65 VSS_164 BG51 N11 VSS_263 B
AM4 VSS_66 VSS_165 BH17 N14 VSS_264
AM41 VSS_67 VSS_166 BH30 N17 VSS_265
AM45 VSS_68 VSS_167 BH44 N29 VSS_266
AN1 VSS_69 VSS_168 BH46 N32 VSS_267
AN38 VSS_70 VSS_169 BH8 N36 VSS_268
AN39 VSS_71 VSS_170 BJ11 N39 VSS_269
AN43 VSS_72 VSS_171 BJ13 N44 VSS_270
AN5 VSS_73 VSS_172 BJ38 N49 VSS_271
AN7 VSS_74 VSS_173 BJ4 N7 VSS_272
AP4 VSS_75 VSS_174 BJ42 P19 VSS_273
AP48 VSS_76 VSS_175 BJ46 P2 VSS_274
AP50 VSS_77 VSS_176 BK15 P23 VSS_275
AR11 VSS_78 VSS_177 BK17 P3 VSS_276
AR2 VSS_79 VSS_178 BK25 P50 VSS_277
AR39 VSS_80 VSS_179 BK29 R49 VSS_278
AR44 VSS_81 VSS_180 BK36 T39 VSS_279
AR47 VSS_82 VSS_181 BK40 T43 VSS_280
AR7 VSS_83 VSS_182 BK44 T47 VSS_281
AT10 VSS_84 VSS_183 BK6 U41 VSS_282
AT14 VSS_85 VSS_184 BK8 U45 VSS_283
AT41 VSS_86 VSS_185 BL11 U50 VSS_284
AT49 VSS_87 VSS_186 BL13 V2 VSS_285
AU1 VSS_88 VSS_187 BL19 V3 VSS_286
AU23 VSS_89 VSS_188 BL22
AU29 VSS_90 VSS_189 BL37
AU3 BL47 CRESTLINE_1p0
VSS_91 VSS_190
AU36 VSS_92 VSS_191 C12
AU49 VSS_93 VSS_192 C16
A A
AU51 VSS_94 VSS_193 C19
AV39 VSS_95 VSS_194 C28
AV48 VSS_96 VSS_195 C29
AW1 VSS_97 VSS_196 C33
AW12 VSS_98 VSS_197 C36
AW16 C41
VSS_99 VSS_198 Quanta Computer Inc.
CRESTLINE_1p0
Date: Thursday, February 01, 2007 Sheet 10 of 33

5 4 3 2 1
5 4 3 2 1
Strap table
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin
Pin Name Strap description Configuration
CFG[2:0] FSB Frequency Select 010 = FSB 800MHz

D 011 = FSB 667MHz D
CFG[4:3] Reserved
CFG5 DMI X2 Select 0 = DMI X2

1 = DMI X4(Default)
CFG6 Reserved
CFG7 CPU Strap 0 = Reserved

1 = Mobile CPU(Default)
CFG8 Low power PCI Express 0 = Normal mode

1 = Low Power mode
CFG9 PCI Express Graphics Lane Reversal 0 = Reverse Lanes

1 = Normal operation(Default)
CFG[11:10] Reserved
C C
CFG[13:12] XOR/ALLZ 00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)
CFG[15:14] Reserved
CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable

1 = Dynamic ODT Enable(Default)
CFG[18:17] Reserved
SDVO_CTRLDATA SDVO Present 0 = No SDVO Card present(Default)

1 = SDVO Card Present
CFG19 DMI Lane Reversal 0 = Normal operation(Default)

1 = Reverse Lanes
CFG20 SDVO/PCIe concurrent 0 = Only SDVO or PCIE x1 is operation(Default)

1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
B B
DMI X2 Select DMI Lane Reversal XOR /ALLz /Clock Un-gating PCI Express Graphics SDVO Present
MCH_CFG_5 Low = DMIX2 MCH_CFG_19 Low = Normal operation(Default) MCH_CFG_12MCH_CFG_13 Configuration MCH_CFG_9 Low = Reverse Lane Strap define at External
High = IDMIX4(Default) High = Reverse Lane High = Normal operation(Default)
DVI control page
0 0 Clock gating disable
+3V
[6] MCH_CFG_5 [6] MCH_CFG_9
0 1 XOR Mode Enable
1 0 ALL-z Mode Enable

R51 R47
R36
*4.02K_4 1 1 Normal operation(Default) *4.02K_4
*4.02K_4
[6] MCH_CFG_19
FSB Dynamic ODT SDVO/PCIE Concurrent operation
Low = Only SDVO or PCIE X1 is
MCH_CFG_16 Low = ODT Disable MCH_CFG_20 operational(Default)
High = ODT Enable(Default) High = SDVO andPCIE X1 are operating
simultaneously via the PEG port
[6] MCH_CFG_12
A [6] MCH_CFG_13 A
[6] MCH_CFG_16 +3V
R48 R54
R58
*4.02K_4 *4.02K_4
*4.02K_4 R430
*4.02K_4
[6] MCH_CFG_20 GMCH Strap(7 of 7) 1A

5 4 3 2 1
1 2 3 4 5 6 7 8
DDR2 Dual channel A/B PU
A A
M_A_A[13..0]
M_A_A[13..0] [7,13]
M_B_A[13..0]
M_B_A[13..0] [7,13]
DDRII A CHANNEL DDRII B CHANNEL
SMDDR_VTERM SMDDR_VTERM
C176 C145 C143 C148 C195 C146 C230 C201 C228 C227 C142 C173 C200 C174 C172 C177 C175 C231 C196 C197 C199 C171 C144 C226 C147 C225
.1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM
B B
M_A_A3 RP16 1 2 56X2 SMDDR_VTERM

M_A_A1 3 4
M_A_A9 RP18 1 2 56X2 M_A_A7 RP22 1 2 56X2 SMDDR_VTERM

M_A_A5 3 4 M_A_A6 3 4
M_A_A2 RP21 1 2 56X2 RP32 1 2 56X2

[6,13] M_CKE3
M_A_A4 3 4 [7,13] M_B_BS#2 3 4
M_A_A11 RP23 1 2 56X2 RP14 1 2 56X2

[6,13] M_ODT1
[6,13] M_CKE1 3 4 [6,13] M_CS#1 3 4
RP19 1 2 56X2
[6,13] M_CKE0
M_A_A8 3 4 [6,13] M_ODT3 RP33 1 2 56X2
[7,13] M_B_BS#0 3 4
M_A_A12 RP20 1 2 56X2

3 4 M_A_A10 RP17 1 2 56X2
[7,13] M_A_BS#2
[7,13] M_A_BS#0 3 4
RP25 1 2 56X2
[7,13] M_A_BS#1
M_A_A0 3 4 RP15 1 2 56X2
[7,13] M_A_CAS#
[7,13] M_A_WE# 3 4
C C
RP26 1 2 56X2
[6,13] M_CS#0
[7,13] M_A_RAS# 3 4
M_B_A10 RP30 1 2 56X2 SMDDR_VTERM

[7,13] M_B_WE# 3 4 [7,13] M_B_CAS# RP29 1 2 56X2
[6,13] M_CS#3 3 4
M_B_A3 RP31 1 2 56X2

M_B_A1 3 4 M_B_A6 RP39 1 2 56X2
[6,13] M_CKE4 3 4
RP38 1 2 56X2
[7,13] M_B_BS#1
M_B_A0 3 4 [6,13] M_ODT2 RP37 1 2 56X2
[7,13] M_B_RAS# 3 4
M_B_A7 RP35 1 2 56X2

M_B_A11 3 4 [6,13] M_ODT0 RP24 1 2 56X2
M_A_A13 3 4
M_B_A8 RP27 1 2 56X2

M_B_A5 3 4 M_B_A13 RP36 1 2 56X2
[6,13] M_CS#2 3 4
M_B_A2 RP34 1 2 56X2

M_B_A4 3 4
M_B_A9 RP28 1 2 56X2

D M_B_A12 3 4 D
INTEL FAE (08/17)

ADD MA14 FOR DUAL LAYERS RAM
R199 56_4 SMDDR_VTERM

[6,13] M_A_A14
R219 56_4
[6,13] M_B_A14 PROJECT : BU1 Santa Rosa
DDR RES. ARRAY 1A

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
DDR2 Dual channel A/B CONN

SMDDR_VREF_DIMM
M_A_DM[0..7] [7]
SMDDR_VREF_DIMM
M_B_DM[0..7] [7]
M_A_DQ[0..63] [7] M_B_DQ[0..63] [7]
+1.8VSUS
M_A_DQS[0..7] [7] M_B_DQS[0..7] [7]
+1.8VSUS +1.8VSUS +1.8VSUS +1.8VSUS
M_A_DQS#[0..7] [7] M_B_DQS#[0..7] [7]
CN25
M_A_A[0..13] [7,12] M_B_A[0..13] [7,12]
CN30 1 2
VREF VSS46 M_B_DQ4
1 VREF VSS46 2 3 VSS47 DQ4 4
3 4 M_A_DQ4 M_B_DQ0 5 6 M_B_DQ1
M_A_DQ6 VSS47 DQ4 M_A_DQ0 M_B_DQ5 DQ0 DQ5 + C370 C376 C379 C367 C368 C380
5 DQ0 DQ5 6 7 DQ1 VSS15 8
M_A_DQ5 7 8 9 10 M_B_DM0
DQ1 VSS15 M_A_DM0 M_B_DQS#0 VSS37 DM0 330U_3528 2.2U_6 2.2U_6 2.2U_6 2.2U_6 2.2U_6
9 VSS37 DM0 10 11 DQS#0 VSS5 12
M_A_DQS#0 11 12 M_B_DQS0 13 14 M_B_DQ2
M_A_DQS0 DQS#0 VSS5 M_A_DQ7 DQS0 DQ6 M_B_DQ6
13 DQS0 DQ6 14 15 VSS48 DQ7 16
15 16 M_A_DQ1 M_B_DQ7 17 18
M_A_DQ2 VSS48 DQ7 M_B_DQ3 DQ2 VSS16 M_B_DQ12
17 DQ2 VSS16 18 19 DQ3 DQ12 20
A M_A_DQ3 M_A_DQ13 M_B_DQ13 A
19 DQ3 DQ12 20 21 VSS38 DQ13 22
21 22 M_A_DQ12 M_B_DQ9 23 24
M_A_DQ9 VSS38 DQ13 M_B_DQ8 DQ8 VSS17 M_B_DM1
23 DQ8 VSS17 24 25 DQ9 DM1 26
M_A_DQ8 25 26 M_A_DM1 27 28
DQ9 DM1 M_B_DQS#1 VSS49 VSS53 +1.8VSUS SMDDR_VREF_DIMM +3V
27 VSS49 VSS53 28 29 DQS#1 CK0 30 M_CLK_DDR3 [6]
M_A_DQS#1 29 30 M_B_DQS1 31 32
DQS#1 CK0 M_CLK_DDR0 [6] DQS1 CK0# M_CLK_DDR#3 [6]
M_A_DQS1 31 32 33 34
DQS1 CK0# M_CLK_DDR#0 [6] VSS39 VSS41
33 34 M_B_DQ11 35 36 M_B_DQ14
M_A_DQ14 VSS39 VSS41 M_A_DQ10 M_B_DQ10 DQ10 DQ14 M_B_DQ15 C185 C183 C369 C182 C202 C198 C141 C150
35 DQ10 DQ14 36 37 DQ11 DQ15 38
M_A_DQ11 37 38 M_A_DQ15 39 40
DQ11 DQ15 VSS50 VSS54 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 2.2U_6 2.2U_6 .1U_4
39 VSS50 VSS54 40
41 VSS18 VSS20 42
41 42 M_B_DQ20 43 44 M_B_DQ16
PC4800 DDR2 SDRAM

M_A_DQ17 VSS18 VSS20 M_A_DQ16 M_B_DQ17 DQ16 DQ20 M_B_DQ21
43 DQ16 DQ20 44 45 DQ17 DQ21 46
M_A_DQ20 45 46 M_A_DQ21 47 48
DQ17 DQ21 M_B_DQS#2 VSS1 VSS6
PC4800 DDR2 SDRAM

47 VSS1 VSS6 48 49 DQS#2 NC3 50 PM_EXTTS#1 [6]
M_A_DQS#2 49 DQS#2 NC3 50 PM_EXTTS#0 [6] M_B_DQS2 51 DQS2 DM2 52 M_B_DM2 Close to DIMM0
M_A_DQS2 51 52 M_A_DM2 53 54
SO-DIMM (200P)
DQS2 DM2 M_B_DQ22 VSS19 VSS21 M_B_DQ18
53 VSS19 VSS21 54 55 DQ18 DQ22 56
M_A_DQ23 55 56 M_A_DQ18 M_B_DQ23 57 58 M_B_DQ19
M_A_DQ19 DQ18 DQ22 M_A_DQ22 DQ19 DQ23
SO-DIMM (200P)
57 DQ19 DQ23 58 59 VSS22 VSS24 60
59 60 M_B_DQ29 61 62 M_B_DQ24
61 DQ24 DQ28 62 63 DQ25 DQ29 64
M_A_DQ25 63 64 M_A_DQ24 65 66 +1.8VSUS
DQ25 DQ29 M_B_DM3 VSS23 VSS25 M_B_DQS#3
65 VSS23 VSS25 66 67 DM3 DQS#3 68
M_A_DM3 67 68 M_A_DQS#3 69 70 M_B_DQS3
DM3 DQS#3 M_A_DQS3 NC4 DQS3
69 NC4 DQS3 70 71 VSS9 VSS10 72
71 72 M_B_DQ26 73 74 M_B_DQ30
M_A_DQ26 VSS9 VSS10 M_A_DQ30 M_B_DQ27 DQ26 DQ30 M_B_DQ31 + C364 C375 C365 C377 C366 C378
73 DQ26 DQ30 74 75 DQ27 DQ31 76
M_A_DQ27 75 76 M_A_DQ31 77 78
DQ27 DQ31 VSS4 VSS8 330U_3528 2.2U_6 2.2U_6 2.2U_6 2.2U_6 2.2U_6
77 VSS4 VSS8 78 [6,12] M_CKE3 79 CKE0 CKE1 80 M_CKE4 [6,12]
[6,12] M_CKE0 79 CKE0 CKE1 80 M_CKE1 [6,12] 81 VDD7 VDD8 82
B B
81 VDD7 VDD8 82 83 NC1 A15 84
83 NC1 A15 84 [7,12] M_B_BS#2 85 A16_BA2 A14 86 M_B_A14 [6,12] INTEL FAE (08/17)
[7,12] M_A_BS#2 85 86 M_A_A14 [6,12] 87 88
87
A16_BA2 A14
88 M_B_A12 89
VDD9 VDD11
90 M_B_A11 ADD MA14 FOR DUAL LAYERS RAM
M_A_A12 VDD9 VDD11 M_A_A11 M_B_A9 A12 A11 M_B_A7
89 A12 A11 90 91 A9 A7 92
M_A_A9 91 92 M_A_A7 M_B_A8 93 94 M_B_A6 +1.8VSUS SMDDR_VREF_DIMM +3V
A9 A7 INTEL FAE (08/17) A8 A6
M_A_A8 93 94 M_A_A6 95 96
95
A8 A6
96
ADD MA14 FOR DUAL LAYERS RAM M_B_A5 97
VDD5 VDD4
98 M_B_A4
M_A_A5 VDD5 VDD4 M_A_A4 M_B_A3 A5 A4 M_B_A2
97 A5 A4 98 99 A3 A2 100
M_A_A3 99 100 M_A_A2 M_B_A1 101 102 M_B_A0 C184 C187 C181 C186 C149 C140 C193 C194
M_A_A1 A3 A2 M_A_A0 A1 A0
101 A1 A0 102 103 VDD10 VDD12 104
103 104 M_B_A10 105 106 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 2.2U_6 2.2U_6 .1U_4
VDD10 VDD12 A10/AP BA1 M_B_BS#1 [7,12]
M_A_A10 105 106 [7,12] M_B_BS#0 107 108
A10/AP BA1 M_A_BS#1 [7,12] BA0 RAS# M_B_RAS# [7,12]
[7,12] M_A_BS#0 107 BA0 RAS# 108 M_A_RAS# [7,12] [7,12] M_B_WE# 109 WE# S0# 110 M_CS#2 [6,12]
[7,12] M_A_WE# 109 WE# S0# 110 M_CS#0 [6,12] 111 VDD2 VDD1 112
111 VDD2 VDD1 112 [7,12] M_B_CAS# 113 CAS# ODT0 114 M_ODT2 [6,12]
113 114 115 116 M_B_A13
[7,12] M_A_CAS# CAS# ODT0 M_ODT0 [6,12] [6,12] M_CS#3 S1# A13
[6,12] M_CS#1 115 S1# A13 116 M_A_A13 117 VDD3 VDD6 118 Close to DIMM1
117 VDD3 VDD6 118 [6,12] M_ODT3 119 ODT1 NC2 120
[6,12] M_ODT1 119 ODT1 NC2 120 121 VSS11 VSS12 122
121 122 M_B_DQ37 123 124 M_B_DQ32
123 DQ32 DQ36 124 125 DQ33 DQ37 126
M_A_DQ37 125 126 M_A_DQ33 127 128
DQ33 DQ37 M_B_DQS#4 VSS26 VSS28 M_B_DM4
127 VSS26 VSS28 128 129 DQS#4 DM4 130
M_A_DQS#4 129 130 M_A_DM4 M_B_DQS4 131 132
M_A_DQS4 DQS#4 DM4 DQS4 VSS42 M_B_DQ39
131 DQS4 VSS42 132 133 VSS2 DQ38 134
133 134 M_A_DQ35 M_B_DQ34 135 136 M_B_DQ33 +3V
M_A_DQ39 VSS2 DQ38 M_A_DQ38 M_B_DQ35 DQ34 DQ39
135 DQ34 DQ39 136 137 DQ35 VSS55 138
M_A_DQ34 137 138 139 140 M_B_DQ44
DQ35 VSS55 M_A_DQ44 M_B_DQ40 VSS27 DQ44 M_B_DQ45
139 VSS27 DQ44 140 141 DQ40 DQ45 142
M_A_DQ40 141 142 M_A_DQ45 M_B_DQ41 143 144
M_A_DQ41 DQ40 DQ45 DQ41 VSS43 M_B_DQS#5 Q9 R225 R224
143 DQ41 VSS43 144 145 VSS29 DQS#5 146
C M_A_DQS#5 M_B_DM5 M_B_DQS5 C
145 VSS29 DQS#5 146 147 DM5 DQS5 148
2
M_A_DM5 147 148 M_A_DQS5 149 150 RHU002N06 10K_4 10K_4
DM5 DQS5 M_B_DQ46 VSS51 VSS56 M_B_DQ42
149 VSS51 VSS56 150 151 DQ42 DQ46 152
M_A_DQ42 151 152 M_A_DQ43 M_B_DQ43 153 154 M_B_DQ47 3 1 DDRDAT_SMB
DQ42 DQ46 DQ43 DQ47 [2,16,19,23,24] SDATA
M_A_DQ46 153 154 M_A_DQ47 155 156
DQ43 DQ47 M_B_DQ53 VSS40 VSS44 M_B_DQ52
155 VSS40 VSS44 156 157 DQ48 DQ52 158
M_A_DQ49 DQ48 DQ52 M_A_DQ52 DQ49 DQ53 +3V
159 DQ49 DQ53 160 161 VSS52 VSS57 162
161 VSS52 VSS57 162 163 NCTEST CK1 164 M_CLK_DDR4 [6]
163 164 165 166 Q8
NCTEST CK1 M_CLK_DDR1 [6] VSS30 CK1# M_CLK_DDR#4 [6]
165 166 M_B_DQS#6 167 168
VSS30 CK1# M_CLK_DDR#1 [6] DQS#6 VSS45
2
M_A_DQS#6 167 168 M_B_DQS6 169 170 M_B_DM6 RHU002N06
M_A_DQS6 DQS#6 VSS45 M_A_DM6 DQS6 DM6
169 DQS6 DM6 170 171 VSS31 VSS32 172
171 172 M_B_DQ51 173 174 M_B_DQ55 3 1 DDRCLK_SMB
VSS31 VSS32 DQ50 DQ54 [2,16,19,23,24] SCLK
M_A_DQ51 DQ50 DQ54 M_A_DQ55 DQ51 DQ55
175 DQ51 DQ55 176 177 VSS33 VSS35 178
177 178 M_B_DQ56 179 180 M_B_DQ60
179 DQ56 DQ60 180 181 DQ57 DQ61 182
M_A_DQ60 181 182 M_A_DQ57 183 184
DQ57 DQ61 M_B_DM7 VSS3 VSS7 M_B_DQS#7
183 VSS3 VSS7 184 185 DM7 DQS#7 186
M_A_DM7 185 186 M_A_DQS#7 187 188 M_B_DQS7
DM7 DQS#7 M_A_DQS7 M_B_DQ59 VSS34 DQS7
187 VSS34 DQS7 188 189 DQ58 VSS36 190
M_A_DQ62 189 190 M_B_DQ62 191 192 M_B_DQ63
M_A_DQ63 DQ58 VSS36 M_A_DQ58 DQ59 DQ62 M_B_DQ58 SMDDR_VREF_DIMM
191 DQ59 DQ62 192 193 VSS14 DQ63 194
193 194 M_A_DQ59 DDRDAT_SMB 195 196
DDRDAT_SMB VSS14 DQ63 DDRCLK_SMB SDA VSS13 R217 10K_4
195 SDA VSS13 196 197 SCL SA0 198
DDRCLK_SMB 197 198 R202 10K_4 +3V 199 200 R216 10K_4
+3V SCL SA0 R201 10K_4 VDD(SPD) SA1
+3V 199 VDD(SPD) SA1 200
TYCO_292564-4 +3V R208 0_6 SMDDR_VREF
TYCO_1-1734071-1
SO-DIMM0 SPD Address is 0xA0 SO-DIMM1 SPD Address is 0xA4
SO-DIMM0 TS Address is 0x30 SO-DIMM1 TS Address is 0x34 R209 *10K_4 R117 *10K_4 +1.8VSUS
D D
H: 5.6mm H: 10.1mm
CLOCK 0,1 CLOCK 3,4
CKE 0,1 CKE 2,3 Quanta Computer Inc.
DDR SO-DIMM(200P) 3A

1 2 3 4 5 6 7 8
5 4 3 2 1
RTC VCCRTC
D11 CH500H-40 VCCRTC C247 1U_6

+3VPCU
<check list>
Delay 18~25ms C383 15P_4
VCCRTC_4 D12 CH500H-40 R232 20K_6
1
R246 R226 G1 C237 Y4 R375
1K_4 1U_6 32.768KHZ 10M_6

U16A
2
D 1M_6 *SHORT_PAD D
CLK_32KX1 AG25 E5
RTCX1 FWH0/LAD0 LAD0 [23,26]
C386 15P_4 CLK_32KX2 AF24 F5
RTCX2 FWH1/LAD1 LAD1 [23,26] +1.05V_V_CPU_IO
CN24 G8
FWH2/LAD2 LAD2 [23,26]
1 1 RTCRST# AF23 F6
RTCRST# FWH3/LAD3 LAD3 [23,26]
2 2
SM_INTRUDER# AD22 C4 +1.05V_V_CPU_IO
INTRUDER# FWH4/LFRAME# LFRAME# [23,26]
ACS_85204-0200L
ICH_INTVRMEN
RTC
LPC
AF25 INTVRMEN LDRQ0# G9 T68
CMOS Setting G1 LAN100_SLP AD21 LAN100_SLP LDRQ1#/GPIO23 E6 LDRQ#1
LDRQ#1 [23]
R165 R164
Clear CMOS Short B24 AF13 GATEA20 *56.2_4 *56.2_4 R175
GLAN_CLK A20GATE GATEA20 [26]
Keep CMOS Open AG26 H_A20M# [3]
A20M# 56.2_4
D22 LAN_RSTSYNC
AF26 H_DPRSTP#_R R161 0_4
DPRSTP# ICH_DPRSTP# [3,6,29]
C21 AE26 H_DPSLP#_R R169 0_4
LAN_RXD0 DPSLP# H_DPSLP# [3]
B21 LAN_RXD1
C22 LAN_RXD2 FERR# AD24 H_FERR# [3]
VCCRTC_3
LAN / GLAN
D21 AG29 H_PWRGD_R R153 0_4
LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGD [3]
E20 LAN_TXD1
C20 LAN_TXD2 IGNNE# AF27 H_IGNNE# [3]
+5VPCU AH21 AE24
GLAN_DOCK#/GPIO13 INIT# H_INIT# [3]
INTR AC20 H_INTR [3]
R222 *24.9_4 GLAN_COMP_SB RCIN# +1.05V_V_CPU_IO
CPU
+1.5V_PCIE D25 GLAN_COMPI RCIN# AH14 RCIN# [26]
R245 8.66K/F_4 VCCRTC_1 R240 8.66K/F_4 VCCRTC_2 3 1 C25 GLAN_COMPO
NMI AD23 H_NMI [3]
ACZ_BCLK AJ16 AG28 H_SMI#_R R154 0_4 R206
HDA_BIT_CLK SMI# H_SMI# [3]
R248 Q10 ACZ_SYNC AJ15 HDA_SYNC
2
STPCLK# AA24 H_STPCLK# [3]

56.2_4 Placement close SB L<2"
4.7K_4 MMBT3904 ACZ_RST# AE14
C HDA_RST# H_THERMTRIP_R R203 24_6 R205 *0_4 C
THRMTRIP# AE27 PM_THRMTRIP# [3,6]
[24] ACZ_SDIN0 AJ17 HDA_SDIN0
AH17 AA23 ICH_TP8
[25] ACZ_SDIN1 HDA_SDIN1 TP8 T63
ACZ_SDIN2 AH15 HDA_SDIN2 PDD[15:0] [19]
R247 T109 ACZ_SDIN3 AD13 V1 PDD0
IHDA
T58 HDA_SDIN3 DD0 PDD1
+3V DD1 U2
15K_4 R480 ACZ_SDOUT AE13 V3 PDD2
*10K_4 HDA_SDOUT DD2 PDD3 +3V +3V
DD3 T1
AE10 V4 PDD4
T56 HDA_DOCK_EN#/GPIO33 DD4 PDD5
AG14 HDA_DOCK_RST#/GPIO34 DD5 T5
T54 AB2 PDD6
DD6
[25] SATA_LED#
SATA_LED# AF10 SATALED# DD7 T6 PDD7 0810 UR FAE: R131 R379
T3 PDD8
C136 3900P_4 SATA_RXN0_C AF6
DD8
R2 PDD9 RCIN# DOESN'T NEED PU 10K_4 8.2K_4
[19] SATA_RXN0 SATA0RXN DD9
C138 3900P_4 SATA_RXP0_C AF5 T4 PDD10
[19] SATA_RXP0 SATA0RXP DD10
C135 3900P_4 SATA_TXN0_C AH5 V6 PDD11 RCIN#
[19] SATA_TXN0 SATA0TXN DD11
C132 3900P_4 SATA_TXP0_C AH6 V5 PDD12 GATEA20
[19] SATA_TXP0 SATA0TXP DD12
U1 PDD13
DD13 PDD14
AG3 SATA1RXN DD14 V2
AG4 U6 PDD15
SATA1RXP DD15
IDE
AJ4 SATA1TXN PDA[2:0] [19]
AJ3 AA4 PDA0
SATA1TXP DA0 PDA1
DA1 AA1
PDA2
SATA
AF2 SATA2RXN DA2 AB3
AF1 SATA2RXP
AE4 SATA2TXN DCS1# Y6 PDCS1# [19]
AE3 Y5
SATA Disable SATA2TXP DCS3# PDCS3# [19]
[2] CLK_PCIE_SATA# AB7 SATA_CLKN DIOR# W4 PDIOR# [19]

1.Connect to GND: SATA[2:0]RXp/n , SATARBIAS , SATARBIAS# , SATA_CLKP , SATACLKN [2] CLK_PCIE_SATA AC6 SATA_CLKP DIOW# W3 PDIOW# [19]
2.NC: SATA[2:0]TXp/n , SATALED# DDACK# Y2 PDDACK# [19]
AG1 Y3 IRQ14 [19]
B 3.VccSATAPLL should be connected directly to Vcc1_5,Filter cap are not required R139 24.9_4 SATA_BIAS AG2
SATARBIAS# IDEIRQ
Y1 B
4.BIOS disable SATARBIAS IORDY PDIORDY [19]
DDREQ W5 PDDREQ [19]
<check list>
L<500mils ICH8M REV 1.0
SB Strap HDA
XOR Chain Entrance Strap
ICH8-M Internal VR Enable strap ICH8-M LAN100_SLP Strap ACZ_SDOUT R392 33_4
(Internal VR for Vccsus1_05,VccSus1_5 and VccCL1_5) (Internal VR for VccLAN1_05 and VccCL1.05) ACZ_SDOUT_AUDIO [24]
ICH_RSV0 HDA_SDOUT Description
R393 33_4
ACZ_SDOUT_MDC [25]
INTVRMEN Low = Internal VR disable LAN100_SLP Low = Internal VR disable 0 0 RSVD
High = Internal VR enable(Default) High = Internal VR enable(Default)
0 1 Enter XOR Chain ACZ_SYNC R130 33_4

ACZ_SYNC_AUDIO [24]
1 0 Normal opration(Default) R129 33_4

ACZ_SYNC_MDC [25]
1 1 Set PCIE port config bit 1

ACZ_BCLK R364 33_4
BIT_CLK_AUDIO [24]
R365 33_4
VCCRTC +3V BIT_CLK_MDC [25]
VCCRTC
ACZ_RST# R172 33_4

A ACZ_RST#_AUDIO [24] A
R149 R394 R167 33_4
ACZ_RST#_MDC [25]
332K_6 R147 *1K_6
332K_6
ICH_INTVRMEN ACZ_SDOUT
LAN100_SLP
ICH_TP3 [16]
R162
*0_4 R150
*0_4 R361
*1K_4 PROJECT : BU1 Santa Rosa
ICH8M HOST(1 of 4) 2A
Date: Tuesday, March 27, 2007 Sheet 14 of 33

5 4 3 2 1
5 4 3 2 1
SB-PCIE/USB/DMI
U16D
[23] PCIE_RXN1 P27 PERN1 DMI0RXN V27 DMI_RXN0 [6] A16 SWAP Override strap
To WLAN [23] PCIE_RXP1 P26 PERP1 DMI0RXP V26 DMI_RXP0 [6]
C204 .1U_4 PCIE_TXN1_C N29 U29
[23] PCIE_TXN1 PETN1 DMI0TXN DMI_TXN0 [6]
C192 .1U_4 PCIE_TXP1_C N28 U28 PCI_GNT#3 Low = A16 swap override enabled
[23] PCIE_TXP1 PETP1 DMI0TXP DMI_TXP0 [6]
Direct Media Interface

High = Default
[20] PCIE_RXN4 M27 PERN2 DMI1RXN Y27 DMI_RXN1 [6]
To LAN [20] PCIE_RXP4 M26 PERP2 DMI1RXP Y26 DMI_RXP1 [6]
C222 .1U_4 PCIE_TXN4_C L29 W29 GNT3# R227 *1K_4
C219 .1U_4 PCIE_TXP4_C L28 W28
D [20] PCIE_TXP4 PETP2 DMI1TXP DMI_TXP1 [6] D
PCI-Express
[23] PCIE_RXN3 K27 PERN3 DMI2RXN AB26 DMI_RXN2 [6] ICH8 Boot BIOS select
To 3G [23] PCIE_RXP3 K26 PERP3 DMI2RXP AB25 DMI_RXP2 [6]
C214 .1U_4 PCIE_TXN3_C J29 AA29
C209 .1U_4 PCIE_TXP3_C J28 AA28 PCI_GNT#0 SPI_CS#1 Boot BIOS Location
[24] PCIE_RXN2 H27 PERN4 DMI3RXN AD27 DMI_RXN3 [6]

To New Card H26 AD26 +1.5V_PCIE 0 1 SPI(Default)
[24] PCIE_RXP2 PERP4 DMI3RXP DMI_RXP3 [6]
C229 .1U_4 PCIE_TXN2_C G29 AC29
C234 .1U_4 PCIE_TXP2_C G28 AC28
1 0 PCI
F27 T26 R186
T71 PERN5 DMI_CLKN CLK_PCIE_ICH# [2]
T69 F26 PERP5 DMI_CLKP T25 CLK_PCIE_ICH [2]
E29 24.9_4 1 1 LPC
T103 PETN5
T102 E28 PETP5 DMI_ZCOMP Y23
Y24 DMI_IRCOMP_R
DMI_IRCOMP
T76 D27 PERN6/GLAN_RXN
D26 G3 SPI_CS1# R220 *1K_4
T72 PERP6/GLAN_RXP USBP0N USBP0- [24]
T78 C29 PETN6/GLAN_TXN USBP0P G2 USBP0+ [24] To USB BOARD(Audio)
C28 H5 GNT0# R223 *1K_4
T74 PETP6/GLAN_TXP USBP1N USBP1- [24]
USBP1P H4 USBP1+ [24] To USB BOARD(Audio)
T77 C23 SPI_CLK USBP2N H2 USBP8- [18]
T101 B23 SPI_CS0# USBP2P H1 USBP8+ [18] To Camera
SPI_CS1# E22 J3
T75 SPI_CS1# USBP3N USBP3- [23]
SPI
USBP3P J2 USBP3+ [23] To WLAN
T73 D23 SPI_MOSI USBP4N K5 USBP4- [24]
T70 F21 SPI_MISO USBP4P K4 USBP4+ [24] To Finger Printer
USBP5N K2 USBP5- [24]
USBOC#0 AJ19 K1 To Bluetooth
OC0# USBP5P USBP5+ [24]
C USBOC#1 AG16 L3 C
OC1#/GPIO40 USBP6N USBP6- [24]
USBOC#2 AG15 L2 To New Card
USBOC#3 AE15
OC2#/GPIO41 USB USBP6P
M5
USBP6+ [24]
USBOC#4 AF15 M4 To 3G
OC4#/GPIO43 USBP7P USBP7+ [23]
USBOC#5 AG17 M2
USBOC#6 AD12 M1 To USB BOARD(LAN)
OC6#/GPIO30 USBP8P USBP2+ [24]
USBOC#7 AJ18 N3 +3V
OC7#/GPIO31 USBP9N T64
USBOC#8 AD14 N2
OC8# USBP9P T65 RP42
USBOC#9 AH18 OC9#
USBRBIAS# F2 6 5
F3 USB_RBIAS_PN SERR# 7 4
USBRBIAS REQ0# 8 3
ICH8M REV 1.0 INTH# 9 2 INTC#
R351 +3V 10 1 INTB#
<CRB>
USB_RBIAS_PN<500mils 22.6_6 8.2KX8
+3V_S5
RP47
SB-PCI USBOC#0
USBOC#7
6
7
5
4 USBOC#2
USBOC#5 8 3 USBOC#3
U16B USBOC#1 9 2 USBOC#4
[21,22] AD[0..31]
AD0 D20 A4 REQ0# +3V_S5 10 1 USBOC#6
AD0 REQ0# REQ0# [22]
AD1 E19 D7 GNT0#
AD2 D19
AD1 PCI GNT0#
E18 REQ1#
GNT0# [22]
8.2KX8
AD2 REQ1#/GPIO50 REQ1# [21]
AD3 A20 C18 GNT1#
AD3 GNT1#/GPIO51 GNT1# [21]
AD4 D17 B19 REQ2# USBOC#8 R188 8.2K_4 +3V_S5
AD5 AD4 REQ2#/GPIO52 GNT2#
A21 AD5 GNT2#/GPIO53 F18 T80
AD6 A19 A11 REQ3# USBOC#9 R363 8.2K_4 +3V_S5
B
AD7 AD6 REQ3#/GPIO54 GNT3# B
C19 AD7 GNT3#/GPIO55 C10 T81
AD8 A18 +3V
AD9 AD8
B16 AD9 C/BE0# C17 CBE0# [21,22] RP40
AD10 A12 E15
AD10 C/BE1# CBE1# [21,22]
AD11 E16 F16 REQ1# 6 5
AD11 C/BE2# CBE2# [21,22]
AD12 A14 E17 DEVSEL# 7 4 REQ2#
AD12 C/BE3# CBE3# [21,22]
AD13 G16 FRAME# 8 3 TRDY#
AD14 AD13 IRDY# STOP# INTG#
A15 AD14 IRDY# C8 IRDY# [21,22] 9 2
AD15 B6 D9 +3V 10 1
AD15 PAR PAR [21,22]
AD16 C11 G6
AD16 PCIRST# PCIRST# [21,22]
AD17 A9 D16 DEVSEL# 8.2KX8 +3V
AD17 DEVSEL# DEVSEL# [21,22]
AD18 D11 A7 PERR#
AD18 PERR# PERR# [21,22] RP41
AD19 B12 B7 LOCK#
AD20 AD19 PLOCK# SERR# LOCK#
C12 AD20 SERR# F10 SERR# [21,22] 6 5
AD21 D10 C16 STOP# IRDY# 7 4 INTE#
AD21 STOP# STOP# [21,22]
AD22 C7 C9 TRDY# PERR# 8 3 INTD#
AD22 TRDY# TRDY# [21,22]
AD23 F13 A17 FRAME# INTF# 9 2 REQ3#
AD23 FRAME# FRAME# [21,22]
AD24 E11 +3V 10 1 INTA#
AD25 AD24 PLT_RST-R# R148 0_6
E13 AD25 PLTRST# AG24 PLTRST#_NB [6]
AD26 E12 B10 PCLK_ICH 8.2KX8
AD26 PCICLK PCLK_ICH [2]
AD27 D8 G7
AD27 PME# PCI_PME# [21,22]
AD28 A6
AD29 AD28
E8 AD29
AD30 D6 +3V
AD31 AD30
A3 AD31
INTA# F9
Interrupt I/F F8 INTE# C382
[22] INTA# PIRQA# PIRQE#/GPIO2
INTB# B5 G11 INTF#
[22] INTB# PIRQB# PIRQF#/GPIO3
A INTC# C5 F12 INTG# .1U_4 A
[21] INTC# PIRQC# PIRQG#/GPIO4
INTD# A10 B3 INTH# R241 0_4 U3
T79 PIRQD# PIRQH#/GPIO5 CRT_SENSE# [18,26]
5
ICH8M REV 1.0 PLT_RST-R# 2
4 PLTRST# [16,19,20,23,24,26]
1
PCI ROUTING Quanta Computer Inc.
TABLE IDSEL INTERUPT DEVICE TC7SH08FU R384
3
REQ0# / GNT0# AD17 INTA#,INTB# R5C833 100K_6
REQ1# / GNT1# AD20 INTC# CB1410 Size Document Number Rev
ICH8M PCIE(2 of 4)/ BIOS 1A

5 4 3 2 1
5 4 3 2 1
SB-GPIO SCLK AJ26

U16C
AJ12 BOARD_ID4
[2,13,19,23,24] SCLK SMBCLK SATA0GP/GPIO21
SDATA AD19 AJ10 BOARD_ID2 CLKUSB_48 14M_ICH
[2,13,19,23,24] SDATA SMBDATA SATA1GP/GPIO19
CL_RST#1 AG21 AF11 GPIO36
SATA
GPIO
[23] CL_RST#1 LINKALERT# SATA2GP/GPIO36
T60 SMLINK0 GPIO37 R211 R160
SMB
AC17 SMLINK0 SATA3GP/GPIO37 AG11
T59 SMLINK1 AE19
+3V SMLINK1 14M_ICH *10_4 *33_4
CLK14 AG9 14M_ICH [2]
RI# AF17 G5 CLKUSB_48
Clocks
RI# CLK48 CLKUSB_48 [2]
[22] LPC_PD# F4 SUS_STAT#/LPCPD# SUSCLK D3

SYS_RST# AD15 T94 C208 C128
[3] SYS_RST# SYS_RESET#
AG23 SLP_S3# R168 100_4
SLP_S3# SUSB# [26]
AG12 AF21 SLP_S4# R385 100_4 *10P_4 *10P_4
[6] PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# SUSC# [26]
R127 R124 AD18 SLP_S5#
*10K_4 *10K_4 SMB_ALERT# SLP_S5# T61 <FAE>
AG22 SMBALERT#/GPIO11
D Since your CPU VRM has no D
S4_STATE#/GPIO26 AH27
R125 0_4 PM_STPPCI_ICH# AE20 T104 DPRSTP# pin, connect
GPIO
[2] PM_STPPCI# STP_PCI#/GPIO15
R126 0_4 PM_STPCPU_ICH# ICH_PWROK PM_DPRSLPVR to IMVP6 is correct
SYS
[2] PM_STPCPU# AG18 STP_CPU#/GPIO25 PWROK AE23
<FAE> CLKRUN# AH11 AJ14 PM_DPRSLPVR_R R367 100_4 PM_DPRSLPVR

[22,26] CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR [6,29]
CRB STP_PCI# PU is no stuff.
Power MGT
CRB STP_CPU# always keeps high to PCIE_WAKE# AE17 AE21 PM_BATLOW#_R If no use internal LAN MAC connect
[20,23,24] PCIE_WAKE# WAKE# BATLOW#
ensure ME alive in M1 state. SERIRQ AF12 LAN_RST# to PLTRST#
[21,22,23,26] SERIRQ SERIRQ
(CLK_MCH_BCLK/# must keep alive to THERM_ALERT# AC13 C2 DNBSWON# Use internal LAN MAC connect
[3] THERM_ALERT# THRM# PWRBTN# DNBSWON# [26]
make ME work) LAN_RST# to RSMRST#
VR_PWRGD_CLKEN PM_LAN_ENABLE_R R123 *0_4 PLTRST#
I think there will be update for this design, AJ20 VRMPWRGD LAN_RST# AH20 PLTRST# [15,19,20,23,24,26] should go high no sooner than 10
I suggest you to keep PU and 0Ω ms after both VccLAN3_3 and
isolation resistors for this signal. T106 ICH_TP7 AJ22 AG27 RSMRST#_R VccLAN1_5 have reached their
TP7 RSMRST#
nominal voltages.
D25 BAS316 KBSMI#_ICH AJ8 E1
[26] KBSMI# TACH1/GPIO1 CK_PWRGD CK_PWRGD [2]
T107 AJ9 TACH2/GPIO6 ECPWROK [26]
T108 AH9 E3 ECPWROK R221 0_4
TACH3/GPIO7 CLPWROK MPWROK [6]
SCI# AE16 +3V_S5 +3V
[26] SCI# GPIO8
GPIO12 AC19 AJ25
BOARD_ID0 GPIO12 SLP_M# T105
AG8 TACH0/GPIO17
BOARD_ID1 AH12 F23
GPIO18 CL_CLK0 CL_CLK0 [6]
BOARD_ID3 AE11 AE18
GPIO20 CL_CLK1 CL_CLK1 [23]
ICH_GPIO22 R378 R229
GPIO
Controller Link
AG10 SCLOCK/GPIO22
T111 ICH_GPIO27 AH25 F22 3.24K_6 3.24K_6
QRT_STATE0/GPIO27 CL_DATA0 CL_DATA0 [6]
T149 ICH_GPIO28 AD16 AF19
QRT_STATE1/GPIO28 CL_DATA1 CL_DATA1 [23]
GPIO35 AG13
RST_HDD# SATACLKREQ#/GPIO35 CL_VREF0_SB
[19] RST_HDD# AF9 SLOAD/GPIO38 CL_VREF0 D24
ICH_GPIO39 AJ11 AH23 CL_VREF1_SB C235
ICH_GPIO48 SDATAOUT0/GPIO39 CL_VREF1
AD10 SDATAOUT1/GPIO48
AJ23 C134 .1U_4
CL_RST# CL_RST#0 [6]
SPKR AD9
[24] SPKR SPKR
AJ27 ICH_GPIO24 .1U_4
C R369 0_4 MCH_ICH_SYNC#_R MEM_LED/GPIO24 HDPACT R377 R230 C
MISC
[6] MCH_ICH_SYNC# AJ13 MCH_SYNC# ME_EC_ALERT/GPIO10 AJ24 HDPACT [19,26]
AF22 ICH_GPIO14 453_4 453_4
EC_ME_ALERT/GPIO14 HDPINT
[14] ICH_TP3 AJ21 TP3 WOL_EN/GPIO9 AG19 HDPINT [19,26]
ICH8M REV 1.0
+3VSUS Controller Link 1 VREF for IAMT support only
C250 .1U_4
5
DELAY_VR_PWRGOOD 1 U5
+3V [3,6,29] DELAY_VR_PWRGOOD
4 ICH_PWROK
ECPWROK 2
C130 .1U_4 +3V
3
U17 R233 100K_4 INTEL CRB NEED THOSE PU & PD. INTEL FAE (08/17)
1 5 TC7SH08FU
2
"Add RSMRST# isolation (important!!! See ww22 Santa Rosa MoW)"
[29] VR_PWRGD_CK410#
3 4 VR_PWRGD_CLKEN
NC7SZ04
R362 100K_4 +3V_S5
PM_LAN_ENABLE_R R122 10K_4 Q5

MMBT3906
No Reboot strap SMLINK0 R185 10K_4 INTEL CRB SHOW IT
RSMRST#_R 3 1 RSMRST# [26]
SMLINK1 R184 10K_4
B SPKR Low = Default B
TO ICH8 FROM uR(EC)
High = No Reboot +3V SYS_RST# R179 10K_4
2
R155
BIOS/ ERIC: UNSTUFF 10K_4 R200 4.7K_4 +3VSUS
DNBSWON# R239 *10K_4
2
SPKR R178 *10K_4
Internal Pull up D8
GPIO35 R380 10K_4 ICH_GPIO24 R358 *10K_4 3 BAV99
THERM_ALERT# R187 8.2K_4 HDPACT R140 *10K_4
1
SERIRQ R157 10K_4 RI# R145 10K_4
ICH_GPIO39 R372 10K_4
2
CLKRUN# R371 8.2K_4
INTEL CRB SHOW IT D9
MCH_ICH_SYNC#_R R381 *10K_4 SCLK R359 2.2K_4 3 BAV99
CL_RST#1 R151 10K_4 SDATA R128 2.2K_4
PM_LAN_ENABLE_R R121 *0_4 R210
1
KBSMI#_ICH R390 10K_4 SMB_ALERT# R360 10K_4 2.2K_4
SCI# R366 10K_4 PCIE_WAKE# R146 1K_4 DISABLE LAN: STUFF
ICH_GPIO22 R134 10K_4 PM_BATLOW#_R R158 8.2K_4
ICH_GPIO48 R138 10K_4 GPIO12 R183 10K_4
RST_HDD# R137 10K_4

+3V +3V +3V +3V +3V
GPIO36 R133 8.2K_4
Board ID ID4 ID3 ID2 ID1 ID0
GPIO37 R132 8.2K_4
A R290 R120 R136 R382 R373 A
NEW CARD 0 0 0 0 1
*10K_4 *10K_4 *10K_4 *10K_4 *10K_4
PM_DPRSLPVR R368 100K_4
CARD BUS 0 0 0 1 0 BOARD_ID4 BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0
ICH_PWROK R170 10K_4
ICH_GPIO14 R166 10K_4 G-SENSOR 0 0 1 0 0

HDPINT R468 *10K_4
R269 R141 R135 R370 R374 Quanta Computer Inc.
CCD 0 1 0 0 0 10K_4 10K_4 10K_4 10K_4 10K_4
ROBSON 1 0 0 0 0 ICH8M GPIO(3 of 4) 2A

5 4 3 2 1
5 4 3 2 1
+3V_S5 +3V
VCCRTC
C153 C154 C152 +1.05V
2
D24 D10
1U_4 .1U_4 .1U_4 U16F
AD25 A13 +1.05V_SB R238 0_1206
PDZ5.6B PDZ5.6B VCCRTC VCC1_05[01] U16E
VCC1_05[02] B13
A16 V5REF[1] VCC1_05[03] C13 A23 VSS[001] VSS[099] K7
1
+5V_S5 R353 10_6 +5V R235 100/F_6 +5VREF_SB T7 C14 C190 A5 L1
V5REF[2] VCC1_05[04] C180 VSS[002] VSS[100]
VCC1_05[05] D14 AA2 VSS[003] VSS[101] L13
C218 C191 +5VREF_SUS_SB G4 E14 .1U_4 AA7 L15
V5REF_SUS VCC1_05[06] 10U_8 VSS[004] VSS[102]
VCC1_05[07] F14 A25 VSS[005] VSS[103] L26
.1U_4 .1U_4 AA25 G14 AB1 L27
VCC1_5_B[01] VCC1_05[08] +1.5V VSS[006] VSS[104]
AA26 VCC1_5_B[02] VCC1_05[09] L11 AB24 VSS[007] VSS[105] L4
AA27 VCC1_5_B[03] VCC1_05[10] L12 AC11 VSS[008] VSS[106] L5
D D
AB27 VCC1_5_B[04] VCC1_05[11] L14 AC14 VSS[009] VSS[107] M12
AB28 L16 VCCDMIPLL_ICH L6 R204 1_8 AC25 M13
+1.5V_PCIE VCC1_5_B[05] VCC1_05[12] VSS[010] VSS[108]
AB29 VCC1_5_B[06] VCC1_05[13] L17 AC26 VSS[011] VSS[109] M14
D28 L18 PBY160808T-301Y-N_6 AC27 M15
VCC1_5_B[07] VCC1_05[14] C188 C189 VSS[012] VSS[110]
D29 VCC1_5_B[08] VCC1_05[15] M11 AD17 VSS[013] VSS[111] M16
L18
CORE
+1.5V E25 VCC1_5_B[09] VCC1_05[16] M18 AD20 VSS[014] VSS[112] M17
FBMJ2125HS420-T_8 E26 P11 .01U_4 10U_6 AD28 M23
VCC1_5_B[10] VCC1_05[17] VSS[015] VSS[113]
E27 VCC1_5_B[11] VCC1_05[18] P18 AD29 VSS[016] VSS[114] M28
Intel use 0.5UH inductor + C372 C210 C203 C167 F24 VCC1_5_B[12] VCC1_05[19] T11
+1.25V
AD3 VSS[017] VSS[115] M29
F25 VCC1_5_B[13] VCC1_05[20] T18 AD4 VSS[018] VSS[116] M3
330U_3528 22U_8 22U_8 2.2U_6 G24 U11 AD6 N1
VCC1_5_B[14] VCC1_05[21] VSS[019] VSS[117]
H23 VCC1_5_B[15] VCC1_05[22] U18 AE1 VSS[020] VSS[118] N11
H24 V11 +1.25V_DMI R356 0_8 +1.05V AE12 N12
VCC1_5_B[16] VCC1_05[23] VSS[021] VSS[119]
J23 VCC1_5_B[17] VCC1_05[24] V12 AE2 VSS[022] VSS[120] N13
J24 VCC1_5_B[18] VCC1_05[25] V14 AE22 VSS[023] VSS[121] N14
+1.5V K24 V16 C374 R192 0_6 AD1 N15
VCC1_5_B[19] VCC1_05[26] VSS[024] VSS[122]
K25 VCC1_5_B[20] VCC1_05[27] V17 AE25 VSS[025] VSS[123] N16
L23 V18 22U_8 AE5 N17
VCC1_5_B[21] VCC1_05[28] C159 C164 C165 VSS[026] VSS[124]
L24 VCC1_5_B[22] AE6 VSS[027] VSS[125] N18
R388 0_8+1.5V_SATA R383 0_8+1.5V_APLL_RR +1.5V_APLL
VCCA3GP
L25 VCC1_5_B[23] VCCDMIPLL R29 AE9 VSS[028] VSS[126] N26
M24 .1U_4 .1U_4 4.7U_6 AF14 N27
L19 C385 C384 VCC1_5_B[24] VSS[029] VSS[127]
M25 VCC1_5_B[25] VCC_DMI[1] AE28 AF16 VSS[030] VSS[128] N4
10UH_8 N23 AE29 +1.05V_V_CPU_IO AF18 N5
CV01001MN08 10U_6 1U_6 VCC1_5_B[26] VCC_DMI[2] +3V VSS[031] VSS[129]
N24 VCC1_5_B[27] AF3 VSS[032] VSS[130] N6
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AF4 VSS[033] VSS[131] P12
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AG5 VSS[034] VSS[132] P13
P25 VCC1_5_B[30] AG6 VSS[035] VSS[133] P14
R24 AF29 +V3.3_DMI_ICH R357 0_6 AH10 P15
VCC1_5_B[31] VCC3_3[01] VSS[036] VSS[134]
R25 VCC1_5_B[32] AH13 VSS[037] VSS[135] P16
R26 AD2 +V3.3_SATA_ICH R176 0_6 AH16 P17
VCC1_5_B[33] VCC3_3[02] VSS[038] VSS[136]
R27 VCC1_5_B[34] AH19 VSS[039] VSS[137] P23
T23 AC8 +V3.3S_VCCPCORE_ICH AH2 P28
C VCC1_5_B[35] VCC3_3[03] VSS[040] VSS[138] C
T24 VCC1_5_B[36] VCC3_3[04] AD8 AF28 VSS[041] VSS[139] P29
VCCP_CORE
T27 AE8 C155 C381 AH22 R11
VCC1_5_B[37] VCC3_3[05] VSS[042] VSS[140]
T28 VCC1_5_B[38] VCC3_3[06] AF8 AH24 VSS[043] VSS[141] R12
T29 .1U_4 .1U_4 AH26 R13
C217 VCC1_5_B[39] +V3.3S_IDE_ICH VSS[044] VSS[142]
U24 VCC1_5_B[40] VCC3_3[07] AA3 AH3 VSS[045] VSS[143] R14
U25 VCC1_5_B[41] VCC3_3[08] U7 AH4 VSS[046] VSS[144] R15
1U_6 V23 V7 C168 AH8 R16
VCC1_5_B[42] VCC3_3[09] VSS[047] VSS[145]
V24 VCC1_5_B[43] VCC3_3[10] W1 AJ5 VSS[048] VSS[146] R17
V25 W6 .1U_4 R173 0_6 B11 R18
VCC1_5_B[44] VCC3_3[11] VSS[049] VSS[147]
IDE
W25 VCC1_5_B[45] VCC3_3[12] W7 B14 VSS[050] VSS[148] R28
Y25 Y7 R190 0_6 B17 R4
VCC1_5_B[46] VCC3_3[13] VSS[051] VSS[149]
B2 VSS[052] VSS[150] T12
AJ6 A8 +V3.3S_PCI_ICH R234 0_6 B20 T13
VCCSATAPLL VCC3_3[14] VSS[053] VSS[151]
VCC3_3[15] B15 B22 VSS[054] VSS[152] T14
AE7 VCC1_5_A[01] VCC3_3[16] B18 B8 VSS[055] VSS[153] T15
C212 AF7 B4 C24 T16
VCC1_5_A[02] VCC3_3[17] VSS[056] VSS[154]
ARX
AG7 VCC1_5_A[03] VCC3_3[18] B9 C26 VSS[057] VSS[155] T17
1U_6 AH7 C15 C236 C223 C233 C27 T2
VCC1_5_A[04] VCC3_3[19] VSS[058] VSS[156]
AJ7 VCC1_5_A[05] VCC3_3[20] D13 C6 VSS[059] VSS[157] U12
PCI
D5 .1U_4 .1U_4 .1U_4 D12 U13
VCC3_3[21] VSS[060] VSS[158]
AC1 VCC1_5_A[06] VCC3_3[22] E10 D15 VSS[061] VSS[159] U14
AC2 VCC1_5_A[07] VCC3_3[23] E7 D18 VSS[062] VSS[160] U15
ATX
AC3 VCC1_5_A[08] VCC3_3[24] F11 D2 VSS[063] VSS[161] U16

AC4 VCC1_5_A[09] D4 VSS[064] VSS[162] U17
AC5 AC12 +3V_1.5V_HDA_IO_ICH R386 0_6 +3V E21 U23
VCC1_5_A[10] VCCHDA R391 *0_6 VSS[065] VSS[163]
+1.5V E24 VSS[066] VSS[164] U26
AC10 AD11 +VCCSUSHDA R189 0_6 +3V_S5 E4 U27
VCC1_5_A[11] VCCSUSHDA C161 VSS[067] VSS[165]
AC9 VCC1_5_A[12] E9 VSS[068] VSS[166] U3
J6 TP_VCCSUS1_05_ICH_1 C166 F15 U5
VCCSUS1_05[1] TP_VCCSUS1_05_ICH_2 .1U_4 VSS[069] VSS[167]
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 E23 VSS[070] VSS[168] V13
AA6 .1U_6 F28 V15
R349 0_6 +1.5V_USB VCC1_5_A[14] TP_VCCSUS1_5_ICH_1 VSS[071] VSS[169]
VCCSUS1_5[1] AC16 F29 VSS[072] VSS[170] V28
B B
G12 VCC1_5_A[15] F7 VSS[073] VSS[171] V29
C205 G17 J7 TP_VCCSUS1_5_ICH_2 +3V_S5 G1 W2
VCC1_5_A[16] VCCSUS1_5[2] VSS[074] VSS[172]
H7 VCC1_5_A[17] E2 VSS[075] VSS[173] W26
.1U_4 C3 +V3.3A_ICH R228 0_6 G10 W27
VCCSUS3_3[01] VSS[076] VSS[174]
AC7 VCC1_5_A[18] G13 VSS[077] VSS[175] Y28
AD7 VCC1_5_A[19] VCCSUS3_3[02] AC18 G19 VSS[078] VSS[176] Y29
AC21 C127 C163 G23 Y4
VCCSUS3_3[03] VSS[079] VSS[177]
D1 VCCUSBPLL VCCSUS3_3[04] AC22 G25 VSS[080] VSS[178] AB4
VCCPSUS
AG20 .1U_4 22N_4 G26 AB23

VCCSUS3_3[05] VSS[081] VSS[179]
F1 VCC1_5_A[20] VCCSUS3_3[06] AH28 G27 VSS[082] VSS[180] AB5
USB CORE
L6 VCC1_5_A[21] H25 VSS[083] VSS[181] AB6

C371 L7 P6 H28 AD5
VCC1_5_A[22] VCCSUS3_3[07] VSS[084] VSS[182]
M6 VCC1_5_A[23] VCCSUS3_3[08] P7 H29 VSS[085] VSS[183] U4
.1U_4 M7 C1 H3 W24
VCC1_5_A[24] VCCSUS3_3[09] +V3.3A_USB_ICH R352 0_8 VSS[086] VSS[184]
VCCSUS3_3[10] N7 H6 VSS[087]
+1.5V_SATA W23 P1 J1 A1
VCC1_5_A[25] VCCSUS3_3[11] VSS[088] VSS_NCTF[01]
VCCSUS3_3[12] P2 J25 VSS[089] VSS_NCTF[02] A2
TP_VCCLAN1_05_ICH_1 F17 P3 C373 J26 A28
VCCLAN1_05[1] VCCSUS3_3[13] VSS[090] VSS_NCTF[03]
VCCPUSB
TP_VCCLAN1_05_ICH_2 G18 P4 J27 A29

VCCLAN1_05[2] VCCSUS3_3[14] 4.7U_6 TP_VCCLAN1_05_ICH_1 C216 .1U_6 VSS[091] VSS_NCTF[04]
VCCSUS3_3[15] P5 J4 VSS[092] VSS_NCTF[05] AH1
+3V R213 0_6 +3V_VCCLAN F19 R1 TP_VCCLAN1_05_ICH_2 C215 .1U_6 J5 AH29
VCCLAN3_3[1] VCCSUS3_3[16] VSS[093] VSS_NCTF[06]
G20 VCCLAN3_3[2] VCCSUS3_3[17] R3 K23 VSS[094] VSS_NCTF[07] AJ1
C221 R5 TP_VCCSUS1_05_ICH_1 C211 .1U_6 K28 AJ2
+1.5V_VCCGLANPLL VCCSUS3_3[18] TP_VCCSUS1_05_ICH_2 C157 .1U_6 VSS[095] VSS_NCTF[08]
A24 VCCGLANPLL VCCSUS3_3[19] R6 K29 VSS[096] VSS_NCTF[09] AJ28
.1U_4 K3 AJ29
TP_VCCCL1_05_ICH TP_VCCSUS1_5_ICH_1 VSS[097] VSS_NCTF[10]
GLAN POWER
A26 VCCGLAN1_5[1] VCCCL1_05 G22 T62 K6 VSS[098] VSS_NCTF[11] B1

A27 TP_VCCSUS1_5_ICH_2 B29
VCCGLAN1_5[2] T66 VSS_NCTF[12]
B26 A22 VCCCL1_5_INT_ICH TP_VCCCL1_05_ICH
VCCGLAN1_5[3] VCCCL1_5 T67
+1.5V R244 1_8 L7 B27 ICH8M REV 1.0
VCCGLAN1_5[4] +V3.3M_ICH C240 C239
B28 VCCGLAN1_5[5] VCCCL3_3[1] F20
PBY160808T-301Y-N_6 C238 C241 G21
VCCCL3_3[2] 1U_6 *.1U_4
B25 VCCGLAN3_3
A 10U_6 2.2U_6 A
ICH8M REV 1.0
+1.5V_PCIE
C220
R212 0_6 +3V
4.7U_6
R231 0_6 +3V_GLAN
+3V
ICH8M Power(4 of 4) 3A

5 4 3 2 1
5 4 3 2 1
+3V +3V +3V
CRT PORT C527 C485 C486 U25
*.1U_4 1000P_4 .1U_4 6 1 LCDVCC_1 R440 0_8 LCDVCC

IN OUT
1A C3 .1U_4 4 2
D1 SSM14 F2 IN GND C481 C484 C479 C478 C480 C526
2 1 2 1 5V_CRT2 CN35 3 5
16
+5V [6] INT_LVDS_DIGON ON/OFF GND .1U_4 10U_8 .1U_4 .01U_4 10U_8 .1U_4
FUSE1A6V_POLY-1A-6V 25 MIL CRT_DSUB-070546FR015SX05ZX-
6 AAT4280
CRT_R L34 BLM18BA220SN1D_6 CRT_R1 1 11 D2 MTW355 CRT_SENSE# [15,26] <demo circuit> R441
[6] CRT_R
7 Crestline suggest 100K
CRT_G L33 BLM18BA220SN1D_6 CRT_G1 2 12 100K_4
D [6] CRT_G G73 suggest 10K(ZS1 Default) D
8
[6] CRT_B
CRT_B L32 BLM18BA220SN1D_6 CRT_B1 3 13 8/27 change back to 100K
9
4 14
R453 C12 R452 C11 R451 C10 C5 C6 C8 10
150_4 10P_4 150_4 10P_4 150_4 10P_4 10P_4 10P_4 10P_4 5 15
LCD/LED TYPE CONNECTOR
17
+3V R445 2.2K_4 INT_LVDS_EDIDDATA
R447 2.2K_4 INT_LVDS_EDIDCLK

U27
5V_CRT2 1 16 VSYNC1 R449 39_4 VSYNC1_CRT L30 BLM18BA220SN1 CRTVSYNC
VCC_SYNC SYNC_OUT2 HSYNC1 R448 39_4 HSYNC1_CRT L31 CRTHSYNC RP2 LCD@0_4P2R_S RP10 LCD@0_4P2R_S
+5V SYNC_OUT1 14
7 BLM18BA220SN1 LCD_EDIDCLK 4 3 INT_LVDS_EDIDCLK LCD_TXLOUT2- 4 3 INT_TXLOUT2-
VCC_DDC INT_LVDS_EDIDCLK [6] INT_TXLOUT2- [6]
C492 .22U_6 8 C2 C4 LCD_EDIDDATA 2 1 INT_LVDS_EDIDDATA LCD_TXLOUT2+ 2 1 INT_TXLOUT2+
BYP INT_LVDS_EDIDDATA [6] INT_TXLOUT2+ [6]
15 VSYNC
SYNC_IN2 VSYNC [6]
2 13 HSYNC 5V_CRT2 10P_4 10P_4 RP1 LED@0_4P2R_S RP9 LED@0_4P2R_S
+3V VCC_VIDEO SYNC_IN1 HSYNC [6]
LED_EDIDDATA 4 3 LED_TXLOUT2+ 4 3
R454 R455 LED_EDIDCLK 2 1 LED_TXLOUT2- 2 1
CRT_R1 3 10 DDCCLK
VIDEO_1 DDC_IN1 DDCCLK [6]
CRT_G1 4 11 DDCDAT 2.7K_4 2.7K_4 RP4 LCD@0_4P2R_S RP8 LCD@0_4P2R_S
VIDEO_2 DDC_IN2 DDCDAT [6]
CRT_B1 5 LCD_TXLCLKOUT- 4 3 INT_TXLCLKOUT- LCD_TXLOUT1- 4 3 INT_TXLOUT1-
VIDEO_3 INT_TXLCLKOUT- [6] INT_TXLOUT1- [6]
9 CRTDCLK LCD_TXLCLKOUT+ 2 1 INT_TXLCLKOUT+ LCD_TXLOUT1+ 2 1 INT_TXLOUT1+
DDC_OUT1 INT_TXLCLKOUT+ [6] INT_TXLOUT1+ [6]
6 12 CRTDDAT
GND DDC_OUT2 RP3 LED@0_4P2R_S RP7 LED@0_4P2R_S
CM2009 LED_TXLCLKOUT+ 4 3 LED_TXLOUT1+ 4 3
C1 C7 LED_TXLCLKOUT- 2 1 LED_TXLOUT1- 2 1
H=1.75mm 10P_4 10P_4 LCD@0_4P2R_S RP6 LCD@0_4P2R_S
DDCCLK R446 2.2K_4 USBP8-_LCD RP12 2 1 USBP8- LCD_TXLOUT0- 4 3 INT_TXLOUT0-
+5V +3V +3V USBP8- [15] INT_TXLOUT0- [6]
USBP8+_LCD 4 3 USBP8+ LCD_TXLOUT0+ 2 1 INT_TXLOUT0+
USBP8+ [15] INT_TXLOUT0+ [6]
DDCDAT R450 2.2K_4
RP11 LED@0_4P2R_S RP5 LED@0_4P2R_S
C USBP8-_LED 4 3 LED_TXLOUT0+ 4 3 C
C494 C493 USBP8+_LED 2 1 LED_TXLOUT0- 2 1
.1U_4 .1U_4
CN1
TOSHIBA LED PANEL MODULE CHI MEI LED PANEL MODULE +3V 1 1
3 3
5 5
USBP8-_LCD 7
CCD_POWER USBP8+_LCD 7
9
46
45
R268 100K_4 VIN 44 40 9
43 39 +3V 11 11
+3VPCU 0_8 R444 INVCC0 LCDVCC LCD_VADJ 13
42 38 LCDVCC DISPON 13
41 37 15 15
1
C488 C490 CCD_POWER 17

36 USBP8-_LED LCDVCC 17
+
35 19 19
DLW21HN900SQ2L USBP8+_LED LCDVCC 21
10U-25V_1210 1000P_4 USBP8-_LCD USBP8- 34 INVCC0 21
4 4 3 3 33 23 23
2
1 2 LID591# USBP8+_LCD 1 2 USBP8+ LED_TXLOUT2+ INVCC0 25

1 2 32 LED_TXLOUT2- D-MIC_CLK_LCD 25
31 27 27
+3V MR1 L37 D-MIC_DATA_LCD 29
C495 EC2648-B3-F 30 LED_TXLOUT1+ LCD_EDIDCLK 29
29 2 2
L38 LED_TXLOUT1- LCD_EDIDDATA 4
28 4
3
.1U_4 USBP8-_LED 1 2 6
R253 USBP8+_LED 1 2 27 LED_TXLOUT0+ LCD_TXLCLKOUT- 6
4 4 3 3 26 8 8
1K_4 LED_TXLOUT0- LCD_TXLCLKOUT+ 10
DLW21HN900SQ2L 25 10
24 12 12
LED_TXLCLKOUT+ LCD_TXLOUT0- 14
23 LED_TXLCLKOUT- LCD_TXLOUT0+ 14
22 16 16
DISPON D15 BAS316 R442 *0_4 LCD_VADJ 18
LID591# [26] [6] INT_LVDS_PWM 21 18
LED_EDIDDATA LCD_TXLOUT1- 20
R439 0_4 20 LED_EDIDCLK LCD_TXLOUT1+ 20
[26] CONTRAST 19 22 22
18 24 24
D13 BAS316 R250 0_4 C483 *.1U_4 LED_GND1 LCD_TXLOUT2- 26
INT_LVDS_BLON [6,26] 17 26
LED_GND2 LCD_TXLOUT2+ 28 31
16 LED_GND3 28 31
15 30 30 32 32
B LED_GND4 B
R243 14 LED_GND5 LCD@ACS_88242-3001
R251 *1K_4 13 LED_GND6
100K_4 LCD_VADJ R483 10K_4 LCD_VADJ_O2 12
11 LED_PWR
VIN 10 LCD PANEL MODULE
3
C531 1n_4
9
8
2 EC_FPBACK# [26] 7
DISPON R487 10K_4 DISPON_O2
6
2
Q24 F1 C532 10n_4 5

4
1
LITTLE-0603-2A-32V INT_MIC
DTC144EU 3 D-MIC_CLK_LCD D-MIC_CLK_LCD
2 D-MIC_DATA_LCD D-MIC_DATA_LCD 2
D27 1 1
1
HALL SENSOR C496

L35
10UH-88mR
LED_SW
C497
LED_PWR
C498
CN4
LVC-C40SFYG-40P
C529 C530 CN2
B140 *1000P_4 *1000P_4

10U/X6S-25V_1206 10U/Y5V-50V_1210 10U/Y5V-50V_1210
LCD_VADJ_O2 ISEN6 R469 10/F_4 LED_GND6
CAMERA MODULE
LED_VIN
20
19
18
17
16
U28
PWM
NC
SW
ISEN6
NC
DISPON_O2 1 15 ISEN5 R470 10/F_4 LED_GND5

ENA ISEN5 ISEN4 R471 10/F_4 LED_GND4
2 NC ISEN4 14
+5V 3 13 GND
VREF GNDA ISEN3 R472 10/F_4 LED_GND3
4 12
LED_VREF
VIN ISEN3
SSTCMP
5 11 ISEN2 R473 10/F_4 LED_GND2

RT ISEN2
ISEN1
+5V 1 3 CCD_POWER
ISET
OVP
21
NC
C482 CM@10U_8 R474 PAD

+
Q35 R443 OZ9956

2
6
7
8
9
10
CM@AO3413 C487 CM@1000P_4 [email protected]_4 51K_4

2
ISEN1 R475 10/F_4 LED_GND1

A C525 .1U_4 C499 A
1U/X7R-25V_6
1
LED_PWR
C500 C501 C502 C503 C504 C505
R476 SSTCMP 1n_4 1n_4 1n_4 1n_4 1n_4 1n_4
3
1M_6
2 R477 R478
CCD_POWERON [26]
OVP
75K_4 10K/F_6
Q36 C506
1
CM@DTC144EU R479 1n_4
75K_4 C507
10n_4
LCD/CRT/LID/CAMERA 3A
Date: Sunday, April 01, 2007 Sheet 18 of 33

5 4 3 2 1
5 4 3 2 1
ODD
-IDERST
CN23
1
3
2
4 PDD8
SATA HDD
PDD7 5 6 PDD9
PDD6 7 8 PDD10
PDD[0..15] PDD5 9 10 PDD11
[14] PDD[0..15] 11 12
PDD4 PDD12
PDDREQ PDD3 13 14 PDD13
[14] PDDREQ 15 16
PDIOW# PDD2 PDD14
[14] PDIOW# 17 18 CN33
PDIOR# PDD1 PDD15
[14] PDIOR# 19 20
PDIORDY PDD0 PDDREQ 23
[14] PDIORDY 21 22 GND23
D PDDACK# PDIOR# D
[14] PDDACK# 23 24
IRQ14 PDIOW# 1
[14] IRQ14 25 26 GND1
PDA1 PDIORDY PDDACK# 2 SATA_TXP0
[14] PDA1 27 28 RXP SATA_TXP0 [14]
PDA0 IRQ14 3 SATA_TXN0
[14] PDA0 29 30 RXN SATA_TXN0 [14]
PDCS1# PDA1 DIAG# R350 *10K_4 +5V 4
[14] PDCS1# 31 32 GND2
PDA2 PDA0 PDA2 5 SATA_RXN0 SATA_RXN0 [14]
[14] PDA2 33 34 TXN
PDCS3# PDCS1# PDCS3# 6 SATA_RXP0 SATA_RXP0 [14]
[14] PDCS3# 35 36 TXP
ODD_LED# 7
37 38 +5V GND3
[25] ODD_LED#
ODD_LED# +5V 39 40 80 mils
41 42 +3.3VSATA R395 *0_8
43 44 3.3V 8 +3V
C248 C246 C249 C252 9
R345 470_6 45 46 C254 3.3V
47 48 3.3V 10
.1U_4 1000P_6 .1U_4 10U_8 150U/6.3V_7343 11 C388 C391
51
52
49 50 GND
GND 12
13 *4.7U_8 *.1U_4
GND
51
52
IN for Master ODD_CONN
5V 14
5V 15
NC for Slave 5V 16 +5VSATA R387 0_8 +5V
GND 17
RSVD 18
19 C100 C101 C389 C387
RES-TYPE GND
20
12V
<check list & FAE> 12V 21 .1U_4 .1U_4 10U_8 150U/6.3V_7343
Must be PU even when IDE device is not use 12V 22
+3V +5V
GND24 24
R215 4.7K_4 PDIORDY
+3V
Q25 SA@Serial_ATA
2
DTC144EU R346 R214 8.2K_4 IRQ14

C +3V C
10K_4
R347 *0_4
[16] RST_HDD#
R348 0_4 1 3 -IDERST
[15,16,20,23,24,26] PLTRST#
+3V_HDP
G SENSOR U19
+3V_HDP
ADDRESS: 32H
Q32
GS@2N7002
+3V_HDP +3V_HDP
2
[26,30,31,32] MAINON 1 SHDN VO 4
+5V_S5 2 C398 R484 0_4 3 1 KXP84_SDA C403 C397
GND [26] 2ND_MBDATA
GS@10U_8
3 5 R485 *0_4 +3V_HDP [email protected]_4 [email protected]_4
VIN SET [2,13,16,23,24] SDATA
RP49
C396 GS@G913-C
+3V_HDP 3 4
[email protected]_4 1 2
Q31
GS@2N7002 [email protected]_4P2R_S
2
U1 R486 0_4 3 1 KXP84_SCL XIN_G C394 GS*22P_6
34
35
36
37
38
39
40
41
42
43
44
[26] 2ND_MBCLK
1
R488 *0_4 Y5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
[2,13,16,23,24] SCLK
+3V_HDP GS*8 MHz
B 33 1 G691L308T73UF-SOT23 B
NC NC
2
3 XOUT_G C395 GS*22P_6
Vcc G-RESET# +3V_HDP
32 NC NC 2 Reset# 1
2 U20
GND
31 NC NC 3
U29 16 1 KXP84_SCL +3V_HDP
VCC HDPSCL KXP84_SDA
30 NC GND 4 7 VCC HDPSDA 20
29 5 +3V_HDP ACCELX 18 3 G-RESET# R399 GS@10K_4

NC VDD ACCELY ACCELX RESET R401 GS@10K_4
17 ACCELY MODE 8
28 GS@LIS3L02AQ3 6 ACCELY ACCELZ 15
Reserved Vouty C91 AXSTST ACCELZ XIN_G R99 GS@10K_4
2 AXSTST Reserved 4
+3V_HDP 27 7 AXSTST 6 XOUT_G R400 GS@10K_4
Reserved ST [email protected]_4 Reserved
[16,26] HDPACT 11 HDPACT Reserved 12
26 8 ACCELX GND 10 13
Reserved Voutx HD_PINT HDPPD Reserved
[16,26] HDPINT 9 HDPINT Reserved 14
25 9 R398 GS@1K_4 19
NC NC R96 Reserved
5 VSS HDPPD selection
24 10 GS@47K/F_6
+3V_HDP NC NC
GS@R5F211B4D11SP 0 1
23 Reserved NC 11 FS (Full Scale) selection HDPPD
Reserved
Reserved
Reserved
Reserved
Reserved
ACCELX Normal Mode Power-down mode

Voutz
0 1
R100 ACCELY
NC
NC
NC
FS
PD
FS
GS@*10K_4 2g Full-Scale 6g Full-Scale

ACCELZ
22
21
20
19
18
17
16
15
14
13
12
PD (Power Down) selection C401 C402 C404
R101 0 1 GS@33n-16V_4 GS@33n-16V_4 GS@33n-16V_4

A GS@10K_4 A
PD
FS Normal Mode Power-down mode
ACCELZ Close Chipset

Close Chipset PATA/ODD/G SENSOR 2A

5 4 3 2 1
5 4 3 2 1
DVDD15 LAN_ACT#
DVDD15 LAN_ACT# [24] 93C56: STUFF
AVDD33 LAN_LINK#
AVDD33 LAN_LINK# [24] 93C46: NOSTUFF
XTAL1 T87
Y2 VDD33
1 2 XTAL2 T86
U11
EECS 1 8
D GVDD VDD33 R313 *10K_4 EESK CS VCC C355 D
25.0000 MHz VDD33 VDD33 2 7
R312 2 SK DC
+3V_S5 1 3.6K_6 EEDI 3 DI ORG 6
C323 C314 CTRL15 CTRL15 DVDD15 DVDD15 EEDO 4 5 .1U/16V_4
C316 C318 DO GND
33P_6 33P_6 R304 2K/F_4 RSET DVDD15 DVDD15 93C46-3GR
0.1U/10V_4 0.1U/10V_4
U10
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
GND
RSET
VCTRL15
GVDD
CKTAL2
CKTAL1
AVDD33
VDD15
LED0
LED1
LED2
LED3
VDD33
VDD15
NC
NC
VDD15
CTRL18 CTRL18 1 48 EESK
AVDD33 VCTRL18 EESK EEDI
AVDD33 2 AVDD33 EEDI 47
MDI0+ 3 46 VDD33 VDD33
[24] MDI0+ MDIP0 VDD33 +3V
MDI0- 4 45 EEDO
[24] MDI0- MDIN0 EEDO
100Ohm
AVDD18 AVDD18 5 44 EECS close chipset
MDI1+ AVDD18 EECS DVDD15
[24] MDI1+ 6 MDIP1 VDD15 43 DVDD15
MDI1- 7 42 MDI0+ R298 49.9/F_4 C295 .01U/16V_4
[24] MDI1- MDIN1 NC
AVDD18 AVDD18 8 41 DVDD15 DVDD15 R330
AVDD18
T93 MDI2+ 9 MDIP2
RTL8111B/8111C/8101E VDD1NC 40 MDI0- R299 49.9/F_4
T89 MDI2- 10 39 1K_4
AVDD18 MDIN2 NC DVDD15
AVDD18 11 AVDD18 VDD15 38 DVDD15
T90 MDI3+ 12 37 VDD33 VDD33 MDI1+ R335 49.9/F_4 C353 .01U/16V_4
MDI3- MDIP3 VDD33 ISOLATEB
T92 13 MDIN3 ISOLATEB# 36
AVDD18 AVDD18 14 35 MDI1- R334 49.9/F_4
DVDD15 AVDD18 NC
LANWAKEB#
DVDD15 15 VDD15 NC 34
PDAT_SMB
PCLK_SMB
1
REFCLK_N
REFCLK_P
VDD33 VDD33 16 33 DVDD15 DVDD15 close connector
PERSTB#
VDD33 VDD15 R329
EVDD18
EVDD18
VDD15
VDD15
EGND
HSON
EGND
HSOP
C C
MDI0 Pair Tx
HSIN
HSIP
15K_4
2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MDI1 Pair Rx
T91 DVDD15 DVDD15

T88 EGND
PCIE_WAKE# PCIE_RXN4_R C328 .1U_4 EGND
[16,23,24] PCIE_WAKE# PCIE_RXN4 [15]
R302 0_4 PERSTB PCIE_RXP4_R C326 .1U_4 To SB RX
[15,16,19,23,24,26] PLTRST# PCIE_RXP4 [15]
DVDD15 DVDD15 EVDD18 EVDD18
EVDD18 EVDD18 CLK_PCIE_LAN#
CLK_PCIE_LAN# [2]
PCIE_TXP4 CLK_PCIE_LAN
[15] PCIE_TXP4 CLK_PCIE_LAN [2]
To SB TX [15] PCIE_TXN4
PCIE_TXN4 EGND
EGND
R488 0_6 L16

+3V_S5 LANVCC VDD33 VDD33
PBY160808T-301Y-N_6
C352 C305 C322 C325 C341 C345
22U/10V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
B AVDD18 [23,24] B
L13
CTRL18 CTRL18 AVDD18 AVDD18
PBY160808T-301Y-N_6
L12 C308 C294 C300 C301 C302 C296 C303

AVDD33 AVDD33
+3VPCU 22U_8 22U_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
BK1608HS220_6
C312 C320
0.1U/10V_4 0.1U/10V_4
C538
R306 0_6
1
2
5
6
*0.1U/X7R-50V_6 EVDD18 EVDD18

3 Q40
[26] LANVCC_EN
*AO6402 C324 C317
0.1U/10V_4 0.1U/10V_4
4
LANVCC L14
BK1608HS220_6
C539 L15
*0.1U/X7R-50V_6 BK1608HS220_6
EGND
A A
L17
CTRL15 CTRL15 DVDD15 DVDD15
PBY160808T-301Y-N_6
C354 C340 C347 C304 C333 C315 C346 C344 C343 C342 C332 C327 C321
22U_8 22U_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
PCIE LAN 10/100M RTL8101E 3A
Date: Thursday, March 29, 2007 Sheet 20 of 33

5 4 3 2 1
5 4 3 2 1
PCLK_PCM R237 CB@*22_4 PCLK_PCM_R C244 CB@*10p_4

+3V
A_CCD1#
C245 C263 C253 C258 C363 CB_RSMRST# R340 CB@*0_6 PCIRST# A_CCD2#
R338 CB@100K_6
+3V
[email protected]_4 [email protected]_4 [email protected]_4 [email protected]_4 [email protected]_4 C359 C255 C357
[email protected]_6
delay 10ms at least CB@10P_4 CB@10P_4
+3V
D D
INTC# VCCD1#
[15] INTC#
PCMCIA SOCKET
C361 C242 C256 C360 C243 SERIRQ VCCD0#
[16,22,23,26] SERIRQ
PCI_PME# R344 CB@0_4 PCM_PME# CN15
[15,22] PCI_PME#
[email protected]_4 [email protected]_4 [email protected]_4 [email protected]_4 [email protected]_4 PCMSPK VPPD1
[24] PCMSPK
CB_RSMRST# VPPD0 1
REQ1# +3V AVCC A_CAD0 GND
[15] REQ1# 2 D3 - CAD0
GNT1# A_CRSVD/D2 A_CAD1 3
[15] GNT1# D4 - CAD1
AD20 R236 CB@47_4 PCM_IDSEL A_CRSVD/D14 A_CAD3 4
PCIRST# R337 A_CRSVD/A18 R284 A_CAD5 D5 - CAD3
[15,22] PCIRST# 5 D6 - CAD5
PCLK_PCM A_CAD7 6
[2] PCLK_PCM D7 - CAD7
A_CCD1# CB@43K_6 A_CC/BE0# 7
FRAME# A_CCD2# A_CAD9 CE1- CCBE0
[15,22] FRAME# 8 A10- CAD9
IRDY# A_CAD11
CB@43K_4
[15,22] IRDY# 9 OE - CAD11
TRDY# A_CVS1# A_CAD12 10
[15,22] TRDY# A11- CAD12
DEVSEL# A_CVS2# A_CAD14 11
[15,22] DEVSEL# A9 - CAD14
STOP# A_CC/BE1# 12
[15,22] STOP# A8 - CCBE1
PERR# A_CPAR 13
[15,22] PERR# A13- CPAR
SERR# A_CPERR# 14
[15,22] SERR# A14- CPERR
A_CGNT# 15
T85
T83
T82
T84
T100
WE/PGM - CGNT
PCM_SUS#
A_CINT# 16 RDY/BSY,IRQ*INT
AVCC 17 VCC
AVPP 18 VPP1
A_CCLK 19
A_CIRDY# A16- CCLK
20 A15- CIRDY
A_CC/BE2# 21
M10
M11
M13
M12
A12- CCBE2
N11
N10
N13
N12
E10
L11
L10
L12
J13
A_CAD18
M1
M9
G4
H1
N9
C6
D9
22
K3
K1
B1
A1
K9
K8
A2
A4
F4
L3
L2
L1
L8
J4
U6 A_CAD20 A7 - CAD18
23 A6 - CAD20
AD[31..0] A_CAD21 24
[15,22] AD[31..0]
SPKROUT
PCICLK
SERR#
PERR#
STOP#
DEVSEL#
PCIRST#
TRDY#
IRDY#
FRAME#
IDSEL
PCIGNT#
PCIREQ#
G_RST#
SUSPEND#
RI_OUT#/PME#
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
MFUNC1
MFUNC0
VCCD1#
VCCD0#
VPPD1
VPPD0
RSVD/D2
RSVD/D14
RSVD/A18
CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1
CVS2/VS2
A_CAD22 A5 - CAD21
25 A4 - CAD22
AD0 N8 B2 A_CAD31 A_CAD23 26
AD1 AD0 CAD31/D10 A_CAD30 A_CAD24 A3 - CAD23
C
K7 AD1 CAD30/D9 C3 27 A2 - CAD24 C
AD2 L7 B3 A_CAD29 A_CAD25 28
AD3 AD2 CAD29/D1 A_CAD28 A_CAD26 A1 - CAD25
N7 AD3 CAD28/D8 A3 29 A0 - CAD26
AD4 M7 C4 A_CAD27 A_CAD27 30
AD5 AD4 CAD27/D0 A_CAD26 A_CAD29 D0 - CAD27
N6 AD5 CAD26/A0 A6 31 D1 - CAD29
AD6 M6 D7 A_CAD25 A_CRSVD/D2 32
AD7 AD6 CAD25/A1 A_CAD24 A_CCLKRUN# D2 - RFU
K6 AD7 CAD24/A2 C7 33 WP,IOIS16-CKRUN
AD8 M5 A8 A_CAD23 34
AD9 AD8 CAD23/A3 A_CAD22 GND
L5 D8
ENE1410 AJ014100T41 AD10 K5
AD9 CAD22/A4
A9 A_CAD21 35
AD11 AD10 CAD21/A5 A_CAD20 A_CCD1# GND
M4 AD11 CAD20/A6 C9 36 CD1- CCD1
AD12 K4 A10 A_CAD19 A_CAD2 37
AD13 AD12 CAD19/A25 A_CAD18 A_CAD4 D11- CAD2
N3 AD13 CAD18/A7 B10 38 D12- CAD4
AD14 M3 D10 A_CAD17 A_CAD6 39
AD14 CAD17/A24 D13- CAD6
ID Select : AD20 AD15
AD16
N2 AD15 CAD16/A17 E12 A_CAD16
A_CAD15
A_CRSVD/D14
A_CAD8
40 D14- RFU
J2 AD16 CAD15/IOWR# F10 41 D15- CAD8
Interrupt Pin : INTC# AD17
AD18
J1 AD17 CAD14/A9 E13 A_CAD14
A_CAD13
A_CAD10
A_CVS1#
42 CE2- CAD10
H4 AD18 CAD13/IORD# F13 43 RFSH,VS*1-CVS1
Request Indicate : REQ1# AD19
AD20
H3 AD19 CAD12/A11 F11 A_CAD12
A_CAD11
A_CAD13
A_CAD15
44 IORD-CAD13
G3 AD20 CAD11/OE# G10 45 IOWR-CAD15
Grant Indicate : GNT1# AD21
AD22
G2 AD21 CAD10/CE2# G11 A_CAD10
A_CAD9
A_CAD16
A_CRSVD/A18
46 A17- CAD16
F1 AD22 CAD9/A10 G12 47 A18- RFU
AD23 F2 H12 A_CAD8 A_CBLOCK# 48
AD24 AD23 CAD8/D15 A_CAD7 A_CSTOP# A19- CBLOCK
E2 AD24 CAD7/D7 H10 49 A20- CSTOP
AD25 E3 J11 A_CAD6 A_CDEVSEL# 50
AD26 AD25 CAD6/D13 A_CAD5 A21- CDEVSEL
E4 AD26 CAD5/D6 J12 AVCC 51 VCC
AD27 D1 K13 A_CAD4
AD28 AD27 CAD4/D12 A_CAD3
D2 AD28 CAD3/D5 J10 AVPP 52 VPP2
AD29 D4 K10 A_CAD2 A_CTRDY# 53
AD30 AD29 CAD2/D11 A_CAD1 A_CFRAME# A22- CTRDY
C1 AD30 CAD1/D4 K12 54 A23- CFRAME
AD31 C2 L13 A_CAD0 A_CAD17 55
AD31 CAD0/D3 A_CAD19 A24- CAD17
56 A25- CAD19
CSTSCHG/BVD1/STSCHG#
A_CVS2# 57
A_CRST# NC - CVS2
B 58 B
CCLKRUN#/WP/IOIS16#
CBE0# A_CSERR# RESET-CRST
CAUDIO/BVD2/SPKR#
[15,22] CBE0# N5 59
CINT#/READY/IREQ#
CBE1# CBE0# A_CREQ# WAIT-CSERR
[15,22] CBE1# N1 CBE1# 60 INPACK-CREQ
CBE2# J3 H13 A_CC/BE0# A_CC/BE3# 61
CREQ#/INPACK#
[15,22] CBE2# CBE2# CCBE0#/CE1# REG- CCBE3
CSERR#/WAIT#
CDEVSEL#/A21
CBE3# E1 E11 A_CC/BE1# A_CAUDIO 62
CRST#/RESET
CFRAME#/A23
CBLOCK#/A19
[15,22] CBE3# CBE3# CCBE1#/A8 BVD2,SP-CAUDIO
CPERR#/A14
CSTOP#/A20
CTRDY#/A22
PAR M2 A11 A_CC/BE2# A_CSTSCHG 63
CGNT#/WE#
CIRDY#/A15
[15,22] PAR PAR CCBE2#/A12 BVD1,STSCHG-C*
B7 A_CC/BE3# A_CAD28 64
CCLK/A16
CCBE3#/REG# A_CPAR A_CAD30 D8 - CAD28
D13 65
VCCA1
VCCA2
VCC10
CPAR/A13 D9 - CAD30
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
A_CAD31
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
66 D10- CAD31
A_CCD2# 67 CD2- CCD2
68
GND
GND
GND
GND
GND
GND
CB@CB1410 GND
D3
H2
L4
M8
K11
F12
C10
B6
F3
G1
K2
N4
L6
L9
H11
G13
A7
D12
C8
B4
B5
C5
D6
D11
C11
B8
A5
C13
C12
B13
A13
A12
B11
D5
B9
B12
H=1.4mm CB@SANTA-1310671-68P
H=2mm
69
70
71
72
73
74
U8 +3V
VCCD0# 1 16
VCCD1# VCCD0# SHDN# VPPD0
2 VCCD1# VPPD0 15
+3V 3 14 VPPD1
3.3V VPPD1
4 3.3V AVCC 13
+5V 5 12 AVCC +3V AVCC +3V
5V AVCC
6 5V AVCC 11
7 GND AVPP 10 AVPP
8 OC# 12V 9
CB@ENE CP-2211 R_A_CCLK R272 CB@10_4 A_CCLK

A_CRST#
A_CCLKRUN#
A_CFRAME#
A A
A_CIRDY#
A_CTRDY#
+5V +3V AVCC AVPP A_CDEVSEL#
A_CSTOP#
A_CPERR#
A_CSERR#
C286 C283 C287 C270 C265 C273 C269 C267 C268 C271 A_CREQ#
A_CGNT#
[email protected]_6 [email protected]_4 [email protected]_6 [email protected]_4 [email protected]_6 [email protected]_4 [email protected]_4 [email protected]_4 [email protected]_6 [email protected]_4 A_CBLOCK#
A_CINT#
A_CSTSCHG
A_CAUDIO PROJECT : BU1 Santa Rosa
PCMCIA(CB1410) -OPTION 1A

5 4 3 2 1
A B C D E
R5C832 : AJ5C8320H26
+3VSUS +3V
R5C833 : AJ5C8330H05
+3VSUS
5 IN 1 CARD READER CARDREADER POWER
If VCC_3V tied to +3V,
U2B
C207 C169 C129 C126 C116 C158 PME# function is not supported
C213 10 67 +3VSUS
10U_6 .01U_4 .1U_4 .01U_4 10U_6 .01U_4 .01U_4 VCC_PCI1 VCC_3V
20 VCC_PCI2
27 C131 C179
VCC_PCI3
32 VCC_PCI4
41 .01U_4 10U_6 Q6 R207
VCC_PCI5
1
128 VCC_PCI6
2N7002 10K_4
61 Q7
VCC_RIN MC_PWR_CTRL_0#
1 3 2
VCC_ROUT_832 16 VCC_ROUT1 AO3403
34 VCC_ROUT2
C170 C114 64 VCC_ROUT3
2
4 4
C115 C133 114 VCC_ROUT4
3
.01U_4 .01U_4 .47U_4 .47U_4 120 VCC_ROUT5 30mil VCC_XD
VCC_XD
86 MC_PWR_CTRL_0
VCC_MD
R218 C224
4 C125 C120 C117
[15,21] AD[31..0] GND1
13 150K_4 2.2U_6
AD31 GND2 .01U_4 .01U_4 .01U_4
125 AD31 GND3 22
AD30 126 28
AD29 AD30 GND4
127 AD29 GND5 54
AD28 1 62
AD27 AD28 GND6
2 AD27 GND7 63
AD26 3 68 +3VSUS
AD25 AD26 GND8 +3VSUS U4
5 AD25 GND9 118
AD24 6 122 4 3 MC_PWR_CTRL_0
AD23 AD24 GND10 IN EN
9 AD23
AD22 11 AD22 When HWSPND# is GND 2
AD21 12 99
AD20 AD21 AGND1 R181 controlled by system, the C206
14 AD20 AGND2 102 5 IN VO 1 VCC_XD
AD19 15 103 10K_4 pull-up resistor(R4059)
AD18 AD19 AGND3
17 AD18 AGND4 107 dose not need to apply. *1U_4 *G5241T1U C232
REQ0# AD17 AD17 18 111
AD16 AD17 AGND5 *4.7U_6
GNT0# INTA#,B# 19 AD16
AD15 36
AD14 AD15
37 AD14
AD17 R163 150/F_4 R5C833_IDSEL AD13 38
AD12 AD13
39 AD12
AD11 40 D7 *BAS316
AD10 AD11 832_SUS# VCC_XD VCC_XD
PCI / OTHER
42 AD10 HWSPND# 69 1 2 LPC_PD# [16]
AD9 43
AD8 AD9 +3VSUS CN28
44 AD8
AD7 46 21
AD6 AD7 R195 10K_4 XD_D0/MS_D0/SD_D0 SD-VCC
47 AD6 MSEN 58 31 SD-DAT0
PowerOnReset for Vcc AD5 48 XD_D1/MS_D1/SD_D1_C 34
AD4 AD5 R198 10K_4 XD_D2/MS_D2/SD_D2_C SD-DAT1
49 AD4 XDEN 55 9 SD-DAT2 XD-VCC 38
When GRESET# is controlled by system, the pull-up AD3 50 AD3
XD_D3/MS_D3/SD_D3 11 SD-DAT3
3 AD2 51 R197 100K_4 XD_RE#/CLK 25 2 XD_CDZ 3
resistor and capacitor do not need to apply. AD1 52
AD2
57 R196 *100K_4 XD_WE#/MS_BS/SD_CMD 15
SD-CLK XD-CD
3 XD_R/B#/SD_WP#
AD0 AD1 UDIO5 SD_CDZ SD-CMD XD-R/B XD_RE#/CLK
53 AD0 39 SD-C/D XD-RE 4
33 XD_R/B#/SD_WP# 41 5 XD_CE#
[15,21] PAR PAR SD-WP XD-CE
7 65 SCL_CARD 6 XD_CLE
[15,21] CBE3# C/BE3# UDIO3 XD-CLE
21 59 SDA_CARD 19 7 XD_ALE
+3VSUS [15,21] CBE2# C/BE2# UDIO4 SD-VSS1 XD-ALE
35 29 8 XD_WE#/MS_BS/SD_CMD
[15,21] CBE1# C/BE1# SD-VSS2 XD-WE
PCLK_R5C833 45 56 40 13 XD_WPO#
[15,21] CBE0# C/BE0# UDIO2 SD-GND XD-WP
R5C833_IDSEL 8
R177 IDSEL XD_D0/MS_D0/SD_D0
UDIO1 60 12 MS-VCC XD-D0 23
124 XD_D0/MS_D0/SD_D0 22 27 XD_D1/MS_D1/SD_D1
[15] REQ0# REQ# MS-DATA0 XD-D1
22K_4 123 72 XD_D1/MS_D1/SD_D1 24 30 XD_D2/MS_D2/SD_D2
[15] GNT0# GNT# UDIO0/SRIRQ# SERIRQ [16,21,23,26] MS-DATA1 XD-D2
R116 23 XD_D2/MS_D2/SD_D2 20 32 XD_D3/MS_D3/SD_D3
[15,21] FRAME# FRAME# MS-DATA2 XD-D3
GRST#_832 24 XD_D3/MS_D3/SD_D3 16 33 XD_D4
[15,21] IRDY# IRDY# MS-DATA3 XD-D4
*22_4 25 XD_RE#/CLK 14 35 XD_D5
[15,21] TRDY# TRDY# MS-SCLK XD-D5
26 MS_CDZ 18 36 XD_D6
[15,21] DEVSEL# DEVSEL# MS-INS XD-D6
C156 29 115 Default setting: XD_WE#/MS_BS/SD_CMD 26 37 XD_D7
[15,21] STOP# STOP# INTA# INTA# [15] MS-BS XD-D7
C104 30 INTA# is assert to 1394
[15,21] PERR# PERR#
.1U_4 31 116 INTB# is assert to Cardreader 10 1
[15,21] SERR# SERR# INTB# INTB# [15] MS-VSS1 XD-GND1
*22P_4 28 17
GRST#_832 MS-VSS2 XD-GND2
71 GBRST# 42 GND1 GND2 43
[15,21] PCIRST# 119 PCIRST# *CARD_READER_PROCONN-MXP038-A0-4010
[2] PCLK_R5C833 121 PCICLK
[15,21] PCI_PME# 70 PME# TEST 66

+3VSUS
[16,26] CLKRUN# 117 22ohm/1A
CLKRUN#
U2A
R5C833 1394_AVCC L4 BK1608HS220
Reserve MS DUO card issue (For A-test only) 1394
98 C111 C118 C390 C109 R376 TPBIAS0
AVCC_PHY1 0_4
AVCC_PHY2 106
C124 22P_4 1394_XIN 94 110 10U_6 .1U_4 .01U_4 1000P_4 R114 R113 C112 C99
XI AVCC_PHY3 Q28
H=1.2mm AVCC_PHY4 112
2
[email protected]_6 [email protected]_4
24.576MHz Y1 113 TPBIAS0 XD_D1/MS_D1/SD_D1 3 1 XD_D1/MS_D1/SD_D1_C [email protected]/F_4 [email protected]/F_4
2 TPBIAS0 TPB0N XD_D2/MS_D2/SD_D2_C 2
better than 50ppm TPBN0 104
105 TPB0P
TPBP0
1
C123 22P_4 1394_XOUT 95 108 TPA0N *2N7002E

XO TPAN0
2
109 TPA0P R355 *10K_4 1394@*CL-2M2012-121JT
TPAP0
+5V 4 4 3 3
1 1 2 2
87 XD_D7
MDIO17
3
C121 *.01U_4 FIL0_PWR 96 92 XD_D6 L20
FIL0 MDIO16 XD_D5 1394@0_4P2R_S
R5C832 stuff only MDIO15 89
91 XD_D4 Q27 AS CLOSE AS TPA0P 1 2 L1394_TPA0+
MDIO14 XD_D3/MS_D3/SD_D3 SD_CDZ TPA0N L1394_TPA0-
MDIO13 90 2 POSSIBLE TO 3 4
R115 10K/F_4 REXT 101 93 XD_D2/MS_D2/SD_D2 *2N7002E RN1
REXT MDIO12 R5C833
81 XD_D1/MS_D1/SD_D1 TPB0P 3 4 L1394_TPB0+
MDIO11 XD_D0/MS_D0/SD_D0 TPB0N L1394_TPB0-
MDIO10 82 1 2
RN2 1394@0_4P2R_S
2
C113 .01U_4 VREF_PWR 100 75 XD_WPO# +3VSUS
VREF MDIO05 XD_WE#/MS_BS/SD_CMD Q26 R112 R111 1394@*CL-2M2012-121JT
IEEE1394/SD
MDIO08 88
83 XD_ALE XD_D2/MS_D2/SD_D2 3 1 1 1
MDIO19 XD_CLE 2 2
MDIO18 85 4 4 3 3
78 XD_CE# R180 [email protected]/F_4 [email protected]/F_4
MDIO02 XD_R/B#/SD_WP# *2N7002E 1394_COM L21
AS CLOSE AS POSSIBLE TO MDIO03 77 10K_4
R5C833 and GUARD GND
80 SD_CDZ 2 1 XD_CDZ R354 0_4 R389 C392
MDIO00 D5 BAS316
79 MS_CDZ 2 1 1394@270P_4
MDIO01 D6 BAS316 [email protected]/F_4
84 MS_SD_CLK R152 56.2/F_4 XD_RE#/CLK
MDIO09 MC_PWR_CTRL_0
MDIO04 76
74 TP_XD_LED# XD_RE#/CLK should
MDIO06 TP_XD_LED# [25] * NOT Use EEPROM :
97 73 shield GND.
> 1 ms >60 ns
RSV MDIO07
Close to CONN. EEPROM ==>UDIO5 need pull-high.
* Use EEPROM :
L1394_TPB0-
CN32
5
==>UDIO5 need pull-down. 1
R5C833 L1394_TPA0- 3 6
H=1.4mm +3VSUS L1394_TPA0+ 4
L1394_TPB0+ 2 7
VCC
1 8 1
GRST# R193 R194
+3VSUS 1394@1394-C13118-102-4P-V
Close to CONN.
PRST# >100 ns 10K_4 10K_4
XD_WE#/MS_BS/SD_CMD R144 *2.7K_4 SD_CDZ MS_CDZ SDA_CARD
SCL_CARD
XD_D0/MS_D0/SD_D0 R156 *2.7K_4 C137 C139
PCLK(33MHz) XD_D1/MS_D1/SD_D1 R159 *2.7K_4 *270P_4 *270P_4
XD_D2/MS_D2/SD_D2 R142 *2.7K_4 Quanta Computer Inc.

XD_D3/MS_D3/SD_D3 R143 *2.7K_4 Reduced external noise by FAE confirm
SD can't recognize issue in ES1 sample Size Document Number Rev
R5C832/833(5IN1/1394) 3A
Date: Wednesday, March 28, 2007 Sheet 22 of 33

A B C D E
5 4 3 2 1
+3V +1.5V
R481 0_4
[16] CL_RST#1
Mini PCI-E Card +3VSUS
[16] CL_DATA1
[16] CL_CLK1
R467
R466
0_4
0_4
+3V +1.5V +3V_S5
C348 C350 C330 C349 C351

WLAN C331 C329 SERIRQ R308 *0_4
CN20 .1U_4 10U_8 .001U_4 .1U_4 10U_8 +3V
[16,21,22,26] SERIRQ 51 NC +3.3V 52
LDRQ#1 R309 *0_4 49 50
[14] LDRQ#1 C-Link_RST GND
.1U_4 1U_6 PLTRST# R310 *0_4 PLTRST#_PCIE 47 48
[15,16,19,20,24,26] PLTRST# C-Link_DAT +1.5V
PCLK_MINI R311 *0_4 45 46
[2,26] PCLK_DEBUG C-Link_CLK LED_WPAN#
4
2
43 GND LED_WLAN# 44
41 42 RP46
NC NC R462 *0_4
39 NC NC 40
R461 *0_4 37 38 USBP3+_C R331 0_4 4.7KX2
GND USB_D+ USBP3+ [15]
35 36 USBP3-_C R332 0_4 Q20
GND USB_D- USBP3- [15]
2
PCIE_TXP1 33 34 2N7002E
[15] PCIE_TXP1 PETp0 GND
3
1
D D
PCIE_TXN1 31 32 R326 0_4 WL_SMDATA
[15] PCIE_TXN1 PETn0 SMB_DATA
29 30 R327 0_4 WL_SMCLK 3 1 WL_SMDATA
GND SMB_CLK [2,13,16,19,24] SDATA
27 GND +1.5V 28
PCIE_RXP1 25 26
[15] PCIE_RXP1 PERp0 GND
PCIE_RXN1 23 24
[15] PCIE_RXN1 PERn0 +3.3Vaux
21 22 PLTRST#
GND PERST# PLTRST# [15,16,19,20,24,26]
19 20 R325 0_4 +3V
[26] uR_SOUT_CR NC W_DISABLE# RF_EN [26]
[26] uR_SWD 17 NC GND 18
15 16 LFRAME#_PCIE *0_4 R320 LFRAME#

CLK_PCIE_MINI GND NC LAD3_PCIE *0_4 R321 LAD3 LFRAME# [14,26] Q21
[2] CLK_PCIE_MINI 13 REFCLK+ NC 14
2
CLK_PCIE_MINI# 11 12 LAD2_PCIE *0_4 R322 LAD2 LAD3 [14,26] 2N7002E
[2] CLK_PCIE_MINI# REFCLK- NC
9 10 LAD1_PCIE *0_4 R323 LAD1 LAD2 [14,26]
GND NC LAD0_PCIE *0_4 R324 LAD0 LAD1 [14,26] WL_SMCLK
7 CLKREQ# NC 8 [2,13,16,19,24] SCLK 3 1
2N7002E-LF WCS_CLKR 5 6 LAD0 [14,26]
Q23 WCS_DATR BT_CHCLK +1.5V
3 BT_DATA GND 4
[16,20,24] PCIE_WAKE# 3 1 1 WAKE# +3.3V 2 +3V
minipai-c15706-52p-ldv
+3V_S5
2
R291 10K_4
WCS_CLK R314 BT@0_4WCS_CLKR

[24] WCS_CLK
WCS_DAT R315 BT@0_4WCS_DATR
[24] WCS_DAT
To BT
+3G_VDD
+3V 80ohm/4A
Peak: 2.75A
L11 FBJ3216HS800 +3G_VDD +3G_VDD
MINI-Card
1
C307 C306 C292 C289 C297 C298 +3G_VDD
10U/10V_8 10U/10V_8 .1U_4 .1U_4 .47U_6 10P_4 +1.5V
2
C C
CN21
51 Reserved +3.3V 52
49 Reserved GND 50
47 Reserved +1.5V 48
45 Reserved LED_WPAN# 46
43 GND LED_WLAN# 44
41 +3.3Vaux LED_WWAN# 42
39 40 R459 *0_4
R460 0_4 +3.3Vaux GND USBP7+_R R294 0_4
37 GND USB_D+ 38 USBP7+ [15]
35 36 USBP7-_R R293 0_4 USBP7- [15]
PCIE_TXP3 GND USB_D-
[15] PCIE_TXP3 33 PETp0 GND 34
PCIE_TXN3 31 32
[15] PCIE_TXN3 PETn0 SMB_DATA
29 GND SMB_CLK 30
27 GND +1.5V 28
PCIE_RXP3 25 26
[15] PCIE_RXP3 PERp0 GND
PCIE_RXN3 23 24
[15] PCIE_RXN3 PERn0 +3.3Vaux
21 22 PLTRST#
GND PERST# PLTRST# [15,16,19,20,24,26]
19 Reserved W_DISABLE# 20
17 Reserved GND 18
15 GND UIM_VPP 16
[2] CLK_PCIE_MINI2 13 REFCLK+ UIM_RESET 14
[2] CLK_PCIE_MINI2# 11 REFCLK- UIM_CLK 12
9 GND UIM_DATA 10
7 CLKREQ# UIM_PWR 8
5 Reserved +1.5V 6
3 4
GND
GND
Reserved GND
1 WAKE# +3.3V 2
3G@minipai-c15706-52p-ldv
53
54
B
NB SINK CPU SINK MINI CARD SINK EMI B
HOLE8 HOLE9 HOLE3 HOLE5 HOLE4 HOLE6 HOLE13 HOLE14

H-C165D122P2-8 H-C165D122P2-8 H-C165D122P2-8 H-C165D122P2-8 H-C165D122P2-8 H-C165D122P2-8 H-C197D122P2-8 H-C197D122P2-8
7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6
8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4 9 4 9 4 9 4
VIN VIN VIN +1.5V +1.5V +1.5V +5V_S5 +5V +5V
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
C519 C508 C514 C509 C513 C516
MB SINK PCMCIA SINK C512

1500P/X7R-50V_4
C510
1500P/X7R-50V_4
C511
1500P/X7R-50V_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
HOLE17 HOLE18
HOLE7 HOLE1 HOLE20 HOLE21 HOLE12 *H-C177D138P2-8 *H-C177D138P2-8
*H-C236D94P2-8 *H-C236D106P2-8 *H-C236D94P2-8 *H-C236D94P2-8 *H-TC295BC236D94P2-8 7 6 7 6
7 6 7 6 7 6 7 6 7 6 8 5 8 5
8 5 8 5 8 5 8 5 8 5 9 4 9 4
9 4 9 4 9 4 9 4 9 4 +3V +3V +3V +3VSUS +5V_S5 +5V_S5 +3VPCU +3VPCU +3VPCU +3VPCU AVDD18 +1.05V
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
C549 C550 C551 C515 C517 C518 C528 C524 C523 C520 C521 C522
HOLE16 HOLE10 HOLE2 HOLE15

MDC PCMCIA SINK .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
*H-C315D94P2-8 *H-C236D94P2-8 *H-C236D106P2-8 HOLE19 *H-C197D94P2-8 HOLE11 HOLE22

7 6 7 6 7 6 *H-C189D189N 7 6 H-C165D122P2-8 *H-C177D138P2-8
8 5 8 5 8 5 7 6 8 5 7 6 7 6
9 4 9 4 9 4 8 5 9 4 8 5 8 5
9 4 9 4 9 4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
+3V +3V
A A
C547 C548
.1U_4 .1U_4

MINI PCIE/HOLE 3A

5 4 3 2 1
5 4 3 2 1
CN8
+3VPCU CN7
INT KeyBoard 30 Audio Board ACZ_SDOUT_AUDIO +3V
RP43
MX6 MX0 MY4 CN12 ACZ_SYNC_AUDIO R396 16
10 1 [26] MX0 1 [14] ACZ_RST#_AUDIO 1
MX5 9 2 MX4 MX1 MY2 C393
12
[26] MX1 2 1 [14] ACZ_SYNC_AUDIO 2
MX0 8 3 MX7 MX2 MX2 BIT_CLK_AUDIO 0_4
[26] MX2 3 2 [14] ACZ_SDIN0 3
MX1 7 4 MX3 MX3 MX1 +5V_S5 *4.7u_4
[26] MX3 4 3 [14] BIT_CLK_AUDIO 4
MX2 6 5 MX4 MY1 +5V_S5 ACZ_RST#_AUDIO
[26] MX4 5 4 [14] ACZ_SDOUT_AUDIO 5
MX5 MY0 U18 BEEP
[26] MX5 6 [15] USBP0- 5 6
5
10KX8 MX6 MX0 ACZ_SDIN0 SPKR 1
[26] MX6 7 [15] USBP0+ 6 [16] SPKR 7
MX7 MX3 4
[26] MX7 8 [15] USBP1- 7 [26] AMP_MUTE# 8
7 8 MX2 MY5 PCMSPK_DELAY 2
9 [15] USBP1+ 8 [26] DIGVOL_UP 9
5 6 MX1 MY15 MY6 +5V C533 C536 C537 SN74LVC1G86DCKR
[26] MY15 10 9 [26] DIGVOL_DN 10
3
3 4 MX0 MY14 MX5 +3V *15P_4 *15P_4 *15p_4
11
[26] MY14 11 10 [26] LED_LOGO 11
1 2 MX3 MY13 MX6 C534 C535
[26] MY13 12 [26] USB_EN2# 12
MY12 MX4 BT@88266-100XX-XXX-10P-R *15P_4 *15P_4 PAD1
100Px4 [26] MY12 13 13
MY11 MY12
CP1 [26] MY11 14 14
MY10 MY7 EMIPAD134X71
D [26] MY10 15 15 D
7 8 MX5 MY9 MY3 Wire Cable 1.25mm Pitch
[26] MY9 16
5 6 MX6 MY8 MX7 BL121-14R-TAND-14P-L-BU1-BU1
[26] MY8 17
1
3 4 MX4 MY7 MY13
[26] MY7 18
1 2 MX7 MY6 MY9
[26] MY6 19
MY5 MY8 FFC Cable 0.5mm Pitch
100Px4 [26] MY5 20
MY4 MY11
CP2 [26] MY4 21
MY3 MY10
[26] MY3 22
7 8 MY15 MY2 MY14
[26] MY2 23
5 6 MY14 MY1 MY15
3 4 MY13
[26] MY1
MY0 K_LED_P 24 T/P Finger Printer BLUETOOTH MODULE CONNECTOR
[26] MY0 25
1 2 MY12 CAPSLED L10
CAPSLED FN_F10 26 C279 4.7U_8 CN9
[26] CAPSLED 27 1 2 +5V
100Px4 FN_F10 NUMLED BLM18PG181SN1D
12
CP3 [26] FN_F10 28 1
NUMLED C274 .1U_4
[26] NUMLED [15] USBP5+ 2
CN11 CN14
[15] USBP5- 3
WCS_CLK
6
29 +3VSUS 1 [23] WCS_CLK 4
+3V R249 150_4 K_LED_P [15] USBP4- R317 FP@0_6 USBP4-_C
BL121-28R-TAND-28P-L-BU1 +5V_TP 8 R316 FP@0_6 USBP4+_C 2 BT_RESET 5
6 [15] USBP4+ 3 6
TPDATA R276 0_4 TPDATA_1 WCS_DAT
[26] TPDATA 5 4 [23] WCS_DAT 7
TPCLK TPCLK_1
5
R275 0_4 +3V
[26] TPCLK 4 8
FP@88266-040XX-XXX-4P-R USB_DETACH
MY7 3 9
7 8
11
MY6 2 10
5 6 1
3 4 MY5 C276 BT@88266-100XX-XXX-10P-R
MY4 C275 7
1 2
*10P_4 *10P_4 *88058-6 R271 BT@*0_4 BT_RESET
100Px4
CP5 [26] BT_EN
R270 BT@0_4 USB_DETACH
7 8 MY3
5 6 MY2 Wire Cable 1.25mm Pitch Wire Cable 1.25mm Pitch USB_DETACH: Low USB connect
3 4 MY1 High USB disconnect
1 2 MY0 CN10
100Px4 RJ45/USB CN19

CP6 CN37 CN5 +5V_TP 8
+3V_S5
13
TPDATA_1 6 USBPWR1 1
36 36 TPCLK_1 5 U12 USBP2- 2
4 80mil [15] USBP2- 3
C +5VPCU G545B2RD1U [15] USBP2+ USBP2+ C
3 USBPWR1 MDI1+ 4
1 1 2 2 IN1 OUT3 8 [20] MDI1+ 5
3 7 [20] MDI1- MDI1-
2 2 1 IN2 OUT2 MDI0+ 6
CN6 6 [20] MDI0+
3 3 7 R336 0_4 OUT1 MDI0- 7
4 4 30 [26] USB_EN# 4 EN# [20] MDI0- 8
BL123-06R-6P-L C356 1 [20] LAN_ACT#
5 5 .1U_4 GND 9
6 6 9 GND-C OC# 5 R333 *6.34K/F_6 [20] LAN_LINK# 10
MY4_K MY4_K MY4_K
7 7 1 [20,23] AVDD18 11
MY2_K MY2_K MY2_K
14
8 MX2_K 8 MX2_K MX2_K 2 12
9 MX1_K 9 MX1_K MX1_K 3 BL123-12R-12P-L-BU1
10 10 4 FFC Cable 1.0mm Pitch
MY1_K MY1_K MY1_K
11 MY0_K 11 MY0_K MY0_K 5
12 MX0_K 12 MX0_K MX0_K 6
13 13 7 Wire Cable 1.25mm Pitch
MX3_K MX3_K MX3_K
14 MY5_K 14 MY5_K MY5_K 8
15 MY6_K 15 MY6_K MY6_K 9 +3V
16 MX5_K 16 MX5_K MX5_K 10 +3V
[21] PCMSPK
C540
BUTTONS ON KB COVER
17 MX6_K 17 MX6_K MX6_K 11 D32
18 MX4_K 18 MX4_K MX4_K 12 C542 CN13
19 MY12_K 19 MY12_K MY12_K 13 2 0.1U/X7R-50V_6 .1U_4
20 20 14
5
MY7_K MY7_K MY7_K C541 PCM-2 1
21 21 15 3 12
MY3_K MY3_K MY3_K .1U_4 4 PCMSPK_DELAY
22 MX7_K 22 MX7_K MX7_K 16 PCM-1 1
23 23 17 1 2 2
MY13_K MY13_K MY13_K U30 MY16
24 24 18 [26] MY16 3
3
MY9_K MY9_K MY9_K CHN217 TC7SH08FU R492 C543 FR
25 25 19 [26] MX3 4
MY8_K MY8_K MY8_K D33 10K_4 .1U_4 FF
26 26 20 [26] MX2 5
MY11_K MY11_K MY11_K C544 C545 STOP
27 27 21 2 [26] MX1 6
MY10_K MY10_K MY10_K 0.1U/X7R-50V_6 0.1U/X7R-50V_6 PLAY/PAUSE
28 28 22 [26] MX0 7
MY14_K MY14_K MY14_K PCM-3 MEDIDA
29 29 23 3 [26] MEDIDA 8
MY15_K MY15_K MY15_K WWW
30 30 24 [26] WWW 9
K_LED_P_K K_LED_P_K K_LED_P_K NBSWON#
31 31 25 1 [26] NBSWON# 10
CAPSLED_K CAPSLED_K CAPSLED_K
32 FN_F10_K 32 FN_F10_K FN_F10_K 26 CHN217 11
33 NUMLED_K 33 NUMLED_K NUMLED_K 27 SW1 BL123-10R-TAND-10P-L-BU1
34 34 28 PCM-4 R490 200K/F_4 PCM-5
3 1 NBSWON#
R491 4 2 FFC Cable 1.0mm Pitch
B 35 35 29 C546 86.6K/F_4 B
196130-340201-34P-R 88171-3400L-34P-R BL121-28R-TAND-28P-L-BU1 0.1U/X7R-50V_6
Keyboard Side
NEW CARD'S POWER SWITCH

New card (BTO)
+NEW_3V CN16
26 GND1 GND29 29
[15] PCIE_TXP2 25 PETp0 GND30 30
[15] PCIE_TXN2 24 PETn0
4
2
23 GND2
RP44 22
[15] PCIE_RXP2 PERp0
H=1.2mm [15] PCIE_RXN2 21 PERn0
[email protected]_4 U9 20
Q15 NEW@TPS2231PWG4 GND3
[2] CLK_PCIE_NEW 19 REFCLK+
2
4 6 +NEW_3V +3V_S5 18
+3V 3.3VIN 3.3VOUT [2] CLK_PCIE_NEW# REFCLK-
3
1
5 7 CPPE# 17
SDATA NEW_SMDATA 3.3VIN 3.3VOUT CPPE#
[2,13,16,19,23] SDATA 3 1 [2] NEW_CLKREQ# 16 CLKREQ#
2
+3V_S5 18 17 +NEW_3VAUX +NEW_3V 15
NEW@2N7002E AUXIN AUXOUT +3.3V1
14 +3.3V2
+1.5V 16 14 +NEW_1.5V Q13 PERST# 13
1.5VIN 1.5VOUT NEW@*DTC144EU +NEW_3VAUX PERST#
15 1.5VIN 1.5VOUT 13 12 +3.3VAUX
+NEW_3V PCIE_WAKE# 3 1 11
PLTRST# [16,20,23] PCIE_WAKE# +NEW_1.5V WAKE#
[15,16,19,20,23,26] PLTRST# 1 SYSRST# STBY# 3 10 +1.5V1
2 12 CPPE# 9
SHDN# CPPE# CPUSB# NEW_SMDATA +1.5V2
CPUSB# 11 8 SMB_DATA
Q14 19 R288 NEW_SMCLK 7
RCLKEN SMB_CLK
2
9 8 PERST#_R R305 PERST# 6

NC PERST# NEW@0_4 RESERVED1
10 GND OC# 20 5 RESERVED2
SCLK 3 1 NEW_SMCLK [email protected]/F CPUSB# 4
[2,13,16,19,23] SCLK CPUSB#
C319 R286 NEW@0_4 USBP6+_R 3
[15] USBP6+ USB_D+
NEW@2N7002E NEW@3300P_4 R287 NEW@0_4 USBP6-_R 2
[15] USBP6- USB_D-
A CPPE# : ( Internal Pull Up , active low when card support PCIE ) 1 GND4
A
CPUSB# : ( Internal Pull Up , active low when card support USB )

NEW@13160171-1
SHDN# : ( Internal Pull Up )
+3V_S5 +3V +1.5V
+NEW_3VAUX +NEW_3V +NEW_1.5V
C334 C310 C309 C337 C336

C335 C299 C311 C313 C339 C338
[email protected]_4 [email protected]_4 [email protected]_4 [email protected]_4 [email protected]_4 PROJECT : BU1 Santa Rosa
[email protected]_4 [email protected]_8 [email protected]_4 [email protected]_4 [email protected]_8 [email protected]_4 Size Document Number Rev
New Card/Keyboard/WTB 3A

5 4 3 2 1
5 4 3 2 1
+5VPCU
ODD / HDD
LED4 LED_B_LTST-C190TBKT 2 1 TP_XD_LED#_R R328 150_4

2 1 -BATLED0 R301 330_4
+5V TP_XD_LED# [22] CARDREADER +5V
BATLED0# [26] LED7 LED_B_LTST-C190TBKT Blue
2 1 -BATLED1 R303 220_4
BATERRY
BATLED1# [26]
R307
LED5 LED_Y_LTST-C190KFKT Full Charge --> Blue
+3VPCU Charging --> Orange LED9 150_4
1 2 RF_LED_R R242 150_4
LED2 LED_B_LTST-C190TBKT
RF_LED [26] W-LAN&BT
D D
-PWRLED R289 330_4 LED_Y_LTST-C190KFKT
IDE_LED
2 1 Amber
PWRLED# [26]
R297 330_4 2 1
POWER
LED3 Power On --> Blue
2
LED_Y_LTST-C190KFKT S3 --> Orange +5V
3
LED6
LED_B_LTST-C190TBKT
[26] SUSLED_EC 2
R318
DISK LED
1
Q19 10K_4
1
DTC144EU
R255 10K_4
+5VPCU
IDE_LED# 2 1 ODD_LED# [19]
3
ACIN LED D22 BAS316
LED1
1 2 R252 330_4
+5VPCU 2 ACIN
ACIN [26,27]
R319 10K_4 +5V
LED_B_LTST-C190TBKT Q11 MMBT3906
+3VPCU Q12
Q22
1
DTC144EU
D28 2 1 IDELED MMBT3906
DA204U D23 BAS316
1
BATLED1#
+5VPCU 3
2 SATA_LED# [14]
C C
D29
DA204U
1
BATLED0#
3
2
D30
DA204U
1
PWRLED#
+5V 3
2
D31
DA204U
1
TP_XD_LED#
3 +3VPCU
2
R342
10K_4
SW2
B
2 B
[26] KILL_SW 1
W_LAN&BT / 3G DC-IN / Power / Battery /HDD(ODD) / Bridge Media access 3
(Amber) (Blue) (Blue) (Blue) (Blue) (Blue) (Blue) +3VPCU D34 SW-NSS506-212F-AABD1B
*DA204U
(Amber) (Amber) 1
MDC
+1.5V +3V
+3V_S5
+1.5V
+1.5V [4,9,17,23,24,32]
R191 R182
CN31 *0_6 0_6
1 GND RSV 2+1.5V_MDC
3 4 C151
[14] ACZ_SDOUT_MDC AC_SDO RSV
5 6 .1U-10V_4
GND 3.3V
[14] ACZ_SYNC_MDC 7 AC_SYNC GND 8
A
R174 33_4 MDC_SDIN1 9 10
A
[14] ACZ_SDIN1 AC_SDI GND

[14] ACZ_RST#_MDC 11 AC_RST# AC_BCLK 12 BIT_CLK_MDC [14]
ACS_88018-124L
C162 R171
*10P-50V_4 *22_4 Quanta Computer Inc.
C160 PROJECT : BU1 Santa Rosa
*10P-50V_4 Size Document Number Rev
TP/SW/LED 3A

5 4 3 2 1
5 4 3 2 1
DNBSWON#_uR
DIGVOL_UP
SM BUS PU
DIGVOL_DN
+3VPCU
MBCLK R259 4.7K_4

C262 C272 C291 MBDATA R258 4.7K_4
.1U_4 .1U_4 .1U_4 2ND_MBCLK R256 4.7K_4
2ND_MBDATA R257 4.7K_4
WWW R282 4.7K_4
1/13 Comfirm by vendor mail: MEDIDA R283 4.7K_4
+3VPCU 1/13 Vendor mail: +3V
VDD must power up after VCC/AVCC
Dedicate cap for AVCC
L8 BLM18AG601SN1 +A3VPCU L36 BLM18AG601SN1
C264 C284 C288

D D
C260 C266 +3V
.1U_4 .1U_4 10U_8
.1U_4 10U_8 1/13 Comfirm by vendor mail:
CRT_SENSE# R266 4.7K_4
VBAT for keep PLL power let power up can quick.
8769AGND 08/10 FAE: If no VBAT will switch to VCCpower.
115
102
If PLL no power will cause boot time delay.
I/O ADDRESS SETTING
C281 C277 C261 C282 C278 C259 0.1UF
19
46
76
88
80
4
10U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 U7
H=1.6mm
VBAT
VCC1
VCC2
VCC3
VCC4
VCC5
AVCC
VDD
I/O Address
BADDR1-0 Index Data
LFRAME# 3 97
[14,23] LFRAME# LFRAME AD0/GPI90 TEMP_MBAT [27]
LAD0 126 98 R482 0_4 00 XOR TREE TEST MODE
[14,23] LAD0 LAD0 AD1/GPI91 INT_LVDS_BLON [6,18]
LAD1 127 99 WWW
[14,23] LAD1 LAD1 AD2/GPI92 WWW [24]
[14,23] LAD2
LAD2
LAD3
128 LAD2 A/D AD3/GPI93 100 MEDIDA
DIGVOL_UP
MEDIDA [24] 01 CORE DEFINED
[14,23] LAD3 1 LAD3 AD4/GPIO05 108 DIGVOL_UP [24]
PCLK_591 2 96 DIGVOL_DN 10 2Eh 2Fh
[2] PCLK_591 LCLK AD5/GPIO04 DIGVOL_DN [24]
PCLK_591 8 11 164Eh 164Fh
[16,22] CLKRUN# CLKRUN/GPIO11/HGPIO02
DA0/GPI94 101 CC-SET [27]
[14] GATEA20 121 GA20 DA1/GPI95 105 VFAN [3] SHBM=0: Enable shared memory with host BIOS
D/A DA2/GPI96 106
R285 122 107
[14] RCIN# KBRST DA3/GPI97 SUSLED_EC [25]
*22_4 BADDR0 BADDR0 R278 10K_4
[16] SCI#
D18 BAS316 SCI#_uR 29
ECSCI LPC
64 BADDR1 SOUT_CR_DEBUG R273 *10K_4
GPIO01 ACIN [25,27]
6 LDRQ/GPIO24/HGPIO01 GPIO03 95 NBSWON# [24]
93 SHBM RF_EN R265 10K_4
GPIO06/HGPIO06 LID591# [18]
C285 124 94
LPCPD/GPIO10/HGPIO00 GPIO07/HGPIP07 SUSB# [16]
*10P_4 GPIO23 119 EC_FPBACK# [18]
PLTRST# 7 109 1/13 Comfirm by vendor mail :
[15,16,19,20,23,24] PLTRST# LREST GPIO30 LANVCC_EN [20]
GPIO31 120 BATLED0# [25] Disabled ('1') if using FWH device on LPC.
T96 TP_uR_PWUREQ# 123 65
PWUREQ GPIO32 BATLED1# [25] Enabled ('0') if using SPI flash for both system BIOS and EC firmware
GPIO33 66 PWRLED# [25]
SERIRQ 125 15
[16,21,22,23] SERIRQ SERIRQ GPIO36 VRON [29]
GPIO40 16 MAINON [19,30,31,32]
08/10 FAE: SMI DOESN'T NEED DIODE 9 17
ID
C C
[16] KBSMI# SMI GPIO42/TCK RF_LED [25] H=1.75mm
GPIO GPIO43/TMS 20 AMP_MUTE# [24] U13
+3VPCU
GPIO44/TDI 21 ID [27]
MX0 54 22 MBCLK 6 1
[24] MX0 KBSIN0 GPIO45 SUSON [31,32] SCL A0
MX1 55 23 T99 MBDATA 5 2
[24] MX1 KBSIN1 GPIO46/TRST SDA A1
MX2 56 24 T147 3
[24] MX2 KBSIN2 GPO47/JEN0 A2
MX3 57 25
[24] MX3 KBSIN3 GPIO50/TDO D/C# [27]
MX4 58 26 7 8
[24] MX4 KBSIN4 GPIO51 S5_ON [28] WP VCC
MX5 59 27 4
[24] MX5 KBSIN5 GPIO52/RDY BT_EN [24] GND
MX6 60 28 HWPG
[24] MX6 KBSIN6 GPIO53
61 91 DNBSWON#_uR D14 BAS316 24LC08BT-I C257
[24] MX7 KBSIN7 GPIO81 DNBSWON# [16]
GPO82/HGPIO00/TRIS 110 LED_LOGO [24] .1U_4
53 112 BADDR0
[24] MY0 KBSOUT0/JENK GPO84/HGPIO01/BADDR0
[24] MY1 52 KBSOUT1/TCK ADDRESS: A0H
[24] MY2 51 KBSOUT2/TMS
50 31 R456 GS@*0_4
[24] MY3 KBSOUT3/TDI TA1/GPIO56 HDPACT [16,19]
KB
SPI FLASH
49 117 R457 GS@*0_4
[24] MY4 KBSOUT4 TA2/GPIO20 HDPINT [16,19]
[24] MY5 48 KBSOUT5/TDO TB1/GPIO14/HGPIO4 63 FANSIG [3] H=2.16mm
47 +3VPCU
[24] MY6 KBSOUT6/RDY
[24] MY7 43 KBSOUT7 TIMER A_PWM0 32 CONTRAST [18]
42 118 U14
[24] MY8 KBSOUT8 A_PWM1/GPIO21 KILL_SW [25]
41 62 SPI_SDI_uR R463 33_4 SPI_SDI 2 8
[24] MY9 KBSOUT9 B_PWM0/GPIO13 SO VDD
[24] MY10 40 KBSOUT10
39 SPI_SDO_uR R464 33_4 SPI_SDO 5 7
[24] MY11 KBSOUT11 SI HOLD
38 84 CRT_SENSE# C251
[24] MY12 KBSOUT12/GPIO64 SPI_DI/GPIO77 CRT_SENSE# [15,18]
[24] MY13 37 KBSOUT13/GPIO63 SPI SPI_DO/GPO76/SHBM 83 RF_EN RF_EN [23] SPI_SCK_uR R465 33_4 SPI_SCK 6 SCK WP 3 .1U_4
[24] MY14 36 KBSOUT14/GPIO62 SPI_SCK/GPIO75 82 CELL-SET [27]
35 SPI_CS0#_uR 1 4
[24] MY15 KBSOUT15/GPIO61/XOR_OUT CE VSS
MY16 34
[24] MY16 KBSOUT16/GPIO60
FOLLOW INTEL ME-EC INTERFACE SPECIFICATION, MY17 33 75 RSMRST#_uR 0_6 R254 R343 10K_4 +3VPCU W25X80VSSIG
2ND_SMB IS DEDICATED FOR ICH8 CONTROLLER LINK BUS. KBSOUT17/GPIO57/HGPIO03 IRRX1/GPIO72 RSMRST# [16]
IRRX2_IRSL0/GPIO70 73 SUSC# [16]
74 PWROK_EC_uR R262 0_4 1/13 Comfirm by vendor mail :
IRTX/GPIO71 ECPWROK [16]
[3,18,27] MBCLK
MBCLK
MBDATA
70 SCL1 IR SIN_CR/CIRRX/GPIO87 113 CCD_POWERON [18] If the Southbridge enables 'Long Wait Abort' by default, the
[3,18,27] MBDATA 69 14 USB_EN# [24]
SDA1 GPIO34/CIRRX2 flash device should be 50MHz (or faster)
[19] 2ND_MBCLK
2ND_MBCLK 67
SCL2 SMB CIRTX/GPIO16/HGPIO04 114
2ND_MBDATA 68 111 SOUT_CR_DEBUG R274 0_4
[19] 2ND_MBDATA SDA2 SOUT_CR/GPO83/BADDR1 uR_SOUT_CR [23]
EC_ME_ALERT: (Intel 08/28)
B Logic high = “AC present”, Logic low = “AC not present (DC B
72 86 SPI_SDI_uR
[24] TPCLK PSCLK1 F_SDI operation)”.
71 87 SPI_SDO_uR
[24] TPDATA PSDAT1 F_SDO EC must not drive a high value on pin until SUS Well is fully powered to
[24] USB_EN2# 10 PSCLK2/GPIO26 FIU F_CS0 90 SPI_CS0#_uR
SPI_SCK_uR prevent leakage.
[24] CAPSLED 11 PSDAT2/GPIO27 PS/2 F_SCK 92 AC/DC indication should be de-bounced by EC.
[24] FN_F10 12 PSCLK3/GPIO25
13 81 SWD_DEBUG R264 0_4
[24] NUMLED PSDAT3/GPIO12 SWD/GPIO66 uR_SWD [23]
8768_32KX1 77 30 T95
32KX1/32KCLKIN CLKOUT/GPIO55
85 VCC_POR# R267 4.7K_4 +3VPCU +5V
VCC_POR
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R339 20M_6 8768_32KX2 79 104 VREF_uR R263 0_4 +A3VPCU TPCLK R261 10K_4
32KX2 VREF TPDATA R260 10K_4
H=2.5mm 0~AVCC power for DA pin
R341 WPC8763LDG
power reference
5
18
45
78
89
116
103
44
0810 FAE: Y3 33K_6

CHECK X'TAL'S FOOTPRINT
08/14 FAE:
VCORF_uR
4 1 08/10 FAE:
CEECK RESULT: OK 3 2
ADD ONE GAD PAD UNDER X'TAL, Please connect VREF(uRider pin104) to
AND KEEP CLEANCE. +A3VPCU instead of +3VPCU.
C358 32.768KHZ C362
15P_4 15P_4 C280
To Keyboard
+3V L9 1U_6
1/13 Comfirm by vendor mail :
INTERNAL KEYBOARD STRIP SET
HZ0603B601R-00
Connect to AGND
8769AGND R281 +3VPCU
10K_4
MY0 R277 10K_4
8769AGND MY16 R279 10K_4
DEBUG PORTS
MY17 R280 10K_4
D16 BAS316 HWPG 08/10 FAE:
[32] HWPG_2.5V
L83 CAN CHANGE FROM BEAD TO
D21 BAS316 EC Debug Port Reserved for LPC debug card
[28] SYS_HWPG SHORT.
A
[30] HWPG_1.05V
D17 BAS316 BUT, PLEASE PUT AGND & 32K CAP & +3VPCU CN17 A
AVCC CAP AT ONE POINT. +3V 10 10
D19 BAS316 1 LAD0 9
[31] HWPG_1.8V 1 9
SOUT_CR_DEBUG 2 LAD1 8
D20 BAS316 ZS1 STILL USE BEAD FOR SAFE. SWD_DEBUG 3
2 LAD2 7
8
[32] HWPG_1.5V 3 7
4 LAD3 6
4 6
[2,23] PCLK_DEBUG 5 5
CN18 LFRAME# 4
*ACES_88231-0400 PLTRST# 4
3 3
SERIRQ 2 2
1 1 Quanta Computer Inc.
-- DAISY CHAIN TOPOLOGY -- *ACS
EC-PC8763 3A

5 4 3 2 1
5 4 3 2 1
0.02_3720 VIN PQ40

VA PR72 FDS6675BZ
D PCN1 HI0805R800R-00_8 PQ41 D
PF1 PL3 1 SUD45P03-15-LF 1 8
4 1 2 3 1 2 4 3 2 7
2 3 6
3 LITTLE-1206-7A PC49 PC48 5
PF2 PL4 .1U/X7R-25V_8 .1U/X7R-25V_8 PD6 PR73
PC52 PC125
1P
2P
1 2 PDS1040S PR76
33K_6
4
2 0.1U/X7R-25V_8 220K/F_6 0.1U/X7R-25V_8
*LITTLE-1206-7A HI0805R800R-00_8
1 PD5
RB500V
PC50
PC51 .1U/X7R-50V_8 1 6 PR74
87288-044L .1U/X7R-50V_8 10K_6
PR75 2 5 PR77 0_6
220K/F_6 D/C# [26]
PD7 3 4
3
PR70
ACIN_1 2 1 PQ12
[25,26] ACIN
IMD2AT108
10K_6 2
ZD12V CSIN
PR69 PQ11
PR71 CSIP 2N7002E
6.8K/F_6 10K_6
1
PC37 2.2U/X5R-10V_8 VIN
ISL6251_VDD 1 2 PC126 10U/X6S-25V_1206
PR61
18_6 PR58 PL14
4.7_6 PC127 .1U/X7R-50V_8 HI0805R800R-00_8
PC42
0.1U/X7R-50V_6 PC46 4.7U/X5R-10_8
CSIN_1 ISL6251_VDDP 1 2
C C
PD4
19
20
15
1
RB500V
PQ42
CSIP
CSIN
VDD
VDDP
PR55 2.2/F_6 FDS6900AS
CSOP CSOP_1 21 PR65 2.7_6 PC45 .1U/X7R-50V_8
CSOP 6251B_2 6251B_1 G1 VA3
BOOT 16 8 D1 1
2
PC39 7 S1/D2 D1 2 PR139
1U/X7R-25V_8 17 ISL6251_UGATE PL13 .03_3720
UGATE
1
CSON 22 6 G2 3 MPL73-6R8
CSON 6251LR 1 BAT-V
2
18 ISL6251_PHASE 5 S2 4
PHASE
1P
2P
+3VPCU 14 ISL6251_LGATE
PC38 LGATE PC124
23
PR81 PR153 0.1U/X7R-50V_6 ACPRN .01U/X7R-50V_6
*100K_4 10K_4 PGND 13
3216FF20-1206-20A
PC57 PF3 DCIN VREF PR154
24 DCIN GND 12
1 2 PC122 PC123
CN26 HI0805R800R-00_8 2.2_F_6 CSOP 10U/X6S-25V_1206 10U/X6S-25V_1206
PF4 PL12 11 PR66 PR64
MBAT+ 100P_4 BAT-V PR59 6251ACSET 2 VADJ 33K_6 *514K_F_6 CSON
10 1 1 2 ACSET
130K/F_6
2 ID *3216FF20-1206-20A PL11 PC142
11 3 ID [26] ACLIM 10
3 VADJ Float = 2200P_50V_6
4 TEMP_MBAT HI0805R800R-00_8 EN
VCOMP
ICOMP
5 4.2V /
CELLS
CHLIM
PR60 ACLIM
VRFE
6
ICM
7
10K_6 CELL
1
PC56
12 8 PC53 PC54 PR67 PR68
9
6251ICOMP 5
9
0.1U/X7R-50V_6 PU3 33K_6 *514K_F_6
13
2
47P/NPO-50V_4 PR80 10K_6 ISL6251A

+3VPCU
SUYIN BATTERY
PR79 47P/NPO-50V_4 ISL6251_VDD 6251EN
VREF
B B
100_4
6251VCOMP1
PR78 PR57 10K_6 CC-SET [26]
ADDRESS: 16H
100_4 MBDATA [3,18,26]
6251CELLS_1 LIM = 1/R2(((0.05/VREF=2.39)VACLM)+0.050)
MBCLK MBCLK [3,18,26] PC47 CURRNT LIMIT POINT = 3.750A
TEMP_MBAT PR56 *10K_6 100P_4 3.750A=1/0.02((0.05/2.365)Vaclm+0.05)
TEMP_MBAT [26]
1
Vaclm=1.1950V
1
PD9 PD8 PR52 PC40

ZD5.6V PR63
PC55 *10K_6 .01U/X7R-16V_4
ZD5.6V .01U/X7R-50V_6
ICMNT
2
6251CELLS_2 2
6251VCOMP2
2
*100_4
3
PR62
PQ9 3.3K/F_4
*2N7002E
1
[26] CELL-SET 2 PR51

*100K_6 PC43
PQ10 *100P_4 PC41
6251CELLS_1 PR53 *2N7002E .01U/X7R-16V_4
*100K_6
1
PC44
*3300P/X7R-50V_4
2
PR54
0_4
1
CELL-SET = Hi ----> Cells = VDD ---->4S

CELL-SET = Low ----> Cells = GND ---->3S
A A

ISL6251 3A

5 4 3 2 1
5 4 3 2 1
E E
MAIND
MAIND [32]
SUSD
SUSD [32]
[3] SYS_SHDN# 1 2
ISL6236_3V
PR102
PL5 0_4 PL6
VIN VIN
HI0805R800R-00_8 VL HI0805R800R-00_8
VL
2
PC66 PC84 PC79
PR93 4.7U/X7R-10V_8 10U/X6S-25V_1206
1
390K_4
1
3V_DL
PR101 PR97 PR103
39K/F_4 0_4 PC68 0_4
PC72 PC65 PC71 PC63 PC69 1U/10V_6 PC75 PC76
1
0.1U/X7R-50V_6 2200P/X7R-50V_4 10U/X6S-25V_1206 0.1U/X7R-50V_6 0.1U/X7R-50V_6 10U/X6S-25V_1206
2
2
D1
D1
S2
G2
D 10U/X6S-25V_1206 PC70 2200P/X7R-50V_4 D
.01U/X7R-16V_4 PC67
0.1U/X7R-50V_6
1
3V5V_EN PQ28
2 1 FDS6900AS
2
8
7
6
5
S1/D2
2
PR92 PR99 3V_DH OCP : 6.25A
G1
*0_4 PR95
8
7
6
5
4
3
2
1
4 5V_DH 150K/F_4 *0_4 +3VPCU
8
PQ18 3V_DH PL7
LDOREFIN
LDO
VIN
RTC
ONLDO
VCC
TON
REF
OCP: 12A 2.5uH_7.5A
1
FDS8884 +3VPCU
PR106 3V_LX
+5VPCU +5VPCU
9 32 287K/F_4
PL8 BYP REFIN2
10 OUT1 ILIM2 31 1 2
1
2
3
3.3uH 11 PU5 30
+5VPCU 5V_LX FB1 OUT2
1 2 12 ILIM1 SKIP# 29
PR108 267K/F_4 DDPWRGD_R 13 ISL6236 28 DDPWRGD_R PC83 PC77
PGOOD1 PGOOD2
2
8
7
6
5
PR100 3V5V_EN 14 27 3V5V_EN +
*0_4 EN1 EN2
15 DH1 DH2 26
PC81 16 25 0.1U/X7R-50V_6 330U/6.3V_6X5.7
PC86 5V_DL LX1 LX2
4 37 PAD
+ PC95 36
SECFB
PAD
1
PGND
0.1U/X7R-50V_6
BST1
BST2
GND
VDD
PAD
PAD
PAD
DL1
DL2
PC88 PC82
1
10U/X6S-25V_1206 0.1U/X7R-50V_6 0.1U/X7R-50V_6

PR107 PQ19 PR113
35
34
33
17
18
19
20
21
22
23
24
330U/6.3V_6X5.7 0_4 PR116 1_6
1
2
3
FDS6690AS 1_6 1 2
1 2 3V_DL
2
C C
PD12 VL
PC101 PR119 0_6 DDPWRGD_R
2 SYS_HWPG [26]
0.1U/X7R-50V_6
PC90 PR109
3 1U/10V_6 0_6
3
1
OCP:12A CHN217 PC100
PD11 0.1U/X7R-50V_6 OCP:6.25A
L(ripple current) PC97
0.1U/X7R-50V_6 2
=(19-5)*5/(1.5u*0.4M*19) L(ripple current)
2
3 PD10 =(19-3.3)*3.3/(2.5u*0.5M*19)
~6A
BAT54-7-F ~2.18A
1
Iocp=12-(6/2)=9A
CHN217 Iocp=6.25-(2.18/2)=5.16A
Vth=9A*15mOhm=135mV PR124 +3VPCU
R(Ilim)=(135mV*10)/5uA +15V_ALWP 1 2
Vth=5.16A*28mOhm=145mV
15V
1
~270K R(Ilim)=(145mV*10)/5uA
PR122 PR123
22_8 PC102 200K/F_4 39K/F_4 ~294K
0.1U/X7R-50V_6 PC87
1
2
5
6
0.1U/X7R-50V_6
+3VPCU SUSD 3 PQ15

AO6402
+5VPCU +5VPCU
B B
4
PC85 +3VSUS 1.5A
1
2
5
6
PC98 PC99 0.1U/X7R-50V_6
PC62
1
2
5
6
1
2
5
6
0.1U/X7R-50V_6 0.1U/X7R-50V_6 MAIND 3 PQ20 0.1U/X7R-50V_6

AO6402
S5D 3 PQ29 MAIND 3 PQ30
AO6402 AO6402
4
+3V 3.5A
4
+5V_S5 +5V 4.5A PC78

4.5A 0.1U/X7R-50V_6
PC103 PC104
0.1U/X7R-50V_6 0.1U/X7R-50V_6
+3VPCU
VIN +5V_S5 +3V_S5 15V PC80

0.1U/X7R-50V_6
PR128
PR118 PR137 PR135
1
2
5
6
1M_6 22_6 22_6 1M_6
A A
S5_ON_G S5D 3 PQ16
AO6402
3
3
3
2 2 2 2
+3V_S5 1.5A
[26] S5_ON Quanta Computer Inc.
PR129 PQ26 PQ35 PQ31 PC64
PQ33 1M_6 2N7002E 2N7002E 2N7002E 0.1U/X7R-50V_6
1
DTC144EU
1

SYSTEM 5V/3V 1A

5 4 3 2 1
5 4 3 2 1
PL1
HI0805R800R-00_8
VIN_6262
PL2
HI0805R800R-00_8
+1.05V
VIN
1
+
PR38 PR35 PR39 PR36 PR40 PR37 PR41
D *0_6 *0_6 *0_6 *0_6 *0_6 *0_6 *0_6 PR150 D
2
PC148
2.2_F_6 1500P/X7R-50V_4
DELAY_VR_PWRGOOD [3,6,16]
5
PC128
PC3 PC149 PC29 470U/25V Merom: VCC_CORE/ 44A
H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 10U/X6S-25V_1206 PC28 0.1U/X7R-50V_4
0.1U/X7R-50V_6
6262_UG1 4 PC139 10U/X6S-25V_1206
2200P_50V_6
VCC_CORE
1
2
3
PR26 4.99K/F_6 VIN_6262 +3V PQ6
PWR_MON 2 1 PGD_IN AOL1414
PL17
6262_PH1 1 2
1
for ISL6262A PR144 .36uH
1
PC27 10_6 PR29 PR28
4
5
1
0.1U/X7R-50V_6 10_4 + +
2
+5V_S5 1.91K/F_4 PD2
*SSM24PT-LF
2
6262_LG1 4 4
1
[3] PSI# PSI#
2
1
PR145 PC9 PQ5 PQ4 PC135 PC136
1
2
3
1
2
3
10_6 0.1U/X7R-50V_6 PC26 0.1U/X7R-50V_6 *AOL1412 AOL1412 330u_2V_7343 330u_2V_7343
2
PR2 PR1
22
20
48
2
1
PR20 0_8 PU1
PC10 0_6 0_6
VCC
VIN
PGOOD
3V3
1U/X7R-25V_8
1
PR7 3.65K/F_6
ISL6262A VSUM
21 GND UGATE1 35
PR23 2.2/F_6 PR6 10K_6
49 GND_T BOOT1 36 1 2
1
+3VSUS PR4 1_6
PC24
C 0.22U/X5R-25V_8 C
2
34 PR5 *0_6 VIN_6262
PSI# PR27 0_4 PSI#_1 PHASE1 ISEN2
2 PSI#
LGATE1 32
PR22 VR_ON PR24 *0_4 PGD_IN 3 PGD_IN
PGND1 33
10K_4 PR25 147K/F_6 4 RBIAS
1
24 ISEN1
ISEN1
[3] H_PROCHOT# 5 VR_TT#
2
PR140 PR21 6 PC12
470K_4 NTC 4.02K/F_4 NTC
+5V_S5 0.22U/X5R-25V_6 PR151
2
2 1 PC22 7 SOFT
PC23 1 22N/X7R-50V_6 PC21 2.2_F_6 PC25 PC2
2
5
.01U/X7R-16V_4 31 1 2 10U/X6S-25V_1206 PC1 0.1U/X7R-50V_6
H_VID0 PVCC 10U/X6S-25V_1206
Panasonic 37 VID0
[4] H_VID0 4.7U/X6S-25V_8
ERT-J0EV474J H_VID1 38 27 6262_UG2 4 PC140
[4] H_VID1 VID1 UGATE2 PR16 2.2/F_6 2200P_50V_6
H_VID2 39 26 1 2
[4] H_VID2 VID2 BOOT2
1
2
3
PQ3
1
H_VID3 40 AOL1414
[4] H_VID3 VID3 PC17
H_VID4 41 0.22U/X5R-25V_8 PL18
[4] H_VID4 VID4
2
28 6262_PH2 1 2
H_VID5 PHASE2
[4] H_VID5 42 VID5
5
30 6262_LG2 .36uH
LGATE2
4
5
H_VID6 43
[4] H_VID6 VID6
1
PGND2 29
PR33 0_4 VR_ON 44 4 PD1 + +
[26] VRON VR_ON
23 ISEN2 4 *SSM24PT-LF
PR32 499/F_4 DPRSLPVR ISEN2 PQ1
[6,16] PM_DPRSLPVR 45 DPRSLPVR
1
2
3
2
1
AOL1412 PQ2
1
2
3
2
PR31 0_4 46 PC11 *AOL1412
[3,6,14] ICH_DPRSTP# DPRSTP# 0.22U/X5R-25V_6 PC138 PC137
2
PR30 0_4 CLKEN# 47 PR147 PR148 330u_2V_7343 330u_2V_7343
[16] VR_PWRGD_CK410# CLK_EN# PC20
B 25 2 1 0_6 0_6 B
PR14 1K/F_4 NC
1000P/X7R-50V_4
PR12 PC15 8 PR19 13.3K/F_4
OCSET
1 2 13 VDIFF
255/F_4 1000P/X7R-50V_6 19 VSUM
VSUM
PR15 ED8-B -0623-33nf to 68nf
12 PR3
FB2
1
PR8
1K/F_4 PC5 11K/F_4 2.7K_4
11 FB
2
1
68N/X7R-25V_6 PR146 3.65K/F_6

PC19 PC13 VSUM
PR18 97.6K/F_4 2 1
2
0.22U/X7R-10V_6 PR141 PR142 10K/F_6

470P/X7R-50V_4 10 NTC_10K_6 Panasonic
PC16 COMP
2 1
ERT-J1VR103J PR149 1_6
VO 18
220P/X7R-50V_4 PR17 6.81K/F_4
9
DROOP
VW ISEN1
VSEN
ED8-B -0623-390p to330p

RTN
DFB
PC18
1
1 2 PR11 PR143 *0_6

PC4
15
14
16
17
1000P/X7R-50V_6 1K_4 0.22U/X5R-25V_6

2
PR13
PC14 1 2 3.48K/F_4
.01U/X7R-16V_4
PC8
180P/NPO-50V_4
2 1 ISL6262_VO
2
PC7 PC6
A .01U/X7R-16V_4 .01U/X7R-16V_4 A
1
Parallel
PR9 0_4
VCCSENSE [4]
PR10 0_4
VSSSENSE [4]

CPU CAORE (6262A) 2A

5 4 3 2 1
1 2 3 4 5
A A
1500P/X7R-50V_4 VIN-1.5V
PC153 PL15
VIN
+5V_S5 HI0805R800R-00_8
PR43
PC152 PC134 PC132 PC129
2
10_6 .1U/X7R-50V_8 10U/X6S-25V_1206 10U/X6S-25V_1206
PC35 PD3 0.1U/X7R-50V_6
5
PR46 PC36
*.1U/50V_6 SW1010C PQ43
1M_6 4.7U/Y5V-10V_8 AOL1414
2
4
PU2 PC34
1
2
3
SC411MLTRT .1U/X7R-50V_8
PR48 0_6 15 13
[19,26,31,32] MAINON EN/PSV BST
+3V 16 VIN DH 12 DH-1.05V
PL16 16A
1 VOUT LX 11 +1.05V
PR47
*10K_6 2 10 PR50 6.65K_6 1R0UH-9mR
VCCA ILIM
5
PR45
10K_6 3 9
FBK VDDP PR152
1
4 8 DL-1.05V 4 PR42
[26] HWPG_1.05V PGOOD DL 2.2_F_6 + + PC31
6 7 PQ44 11K_6 33P/NPO-50V_6
VSSA PGND
1
2
3
AOL1412
2
5 NC TPAD 17
PC141
14 2200P_50V_6
GND
GND
GND
GND
NC
1
PC30 PC32 PC33 PR44

B 0.1U/X7R-50V_6 PC133 10K_6 B
1000P/X7R-50V_6
.01U/X7R-50V_6 PC131 PC130 10U/Y5U-10V_8
2
18
19
20
21
560U/2.5V_6X5.7 560U/2.5V_6X5.7
VOUT=(1+R2/R3)*0.5
C C
D D

VTT 1.05V (SC11) 2A

1 2 3 4 5
5 4 3 2 1
E E
PL9
VIN
2200P/X7R-50V_6 HI0805R800R-00_8
+1.8VSUS
PC111
5
6
7
8
PR138 PC151
PC120 0.1U/X7R-50V_6
2.2_F_6 PC112 PC150
10U/Y5V-10V_1206 4 PC116 PC113
PU4 PQ39
TPS51116 10U/X6S-25V_1206 10U/X6S-25V_1206
1 19 FDS8884 PC118 1500P/X7R-50V_4
VLDOIN DRVH 2200P_50V_6 10U/X6S-25V_1206
2 20 PC58 0.1U/X7R-50V_6
SMDDR_VTERM VTT VBST PL10
3
2
1
PC119 PC121 4 18 +1.8VSUS
VTTSNS LL
5
6
7
8
5
6
7
8
MAX Current 10A
10U/Y5V-10V_1206 5 17 1R5UH-3.8mR
10U/Y5V-10V_1206 GND DRVL
3 16 PC117 +
VTTGND PGND PR98 PC115
4 4
DIS_MODE 6 11 S3_1.8V PR90 0_6 560U/2.5V_6X5.7 10U/Y5V-10V_8
MODE S3 MAINON [19,26,30,32]
PR84 2.2_F_6
7 12 S5_1.8V PR91 0_6
SMDDR_VREF VTTREF S5 SUSON [26,32]
0_6 5VIN 8 14 5VIN
PC59 COMP V5IN PR87 PC73
3
2
1
3
2
1
D .033U/50V_6 9 13 +3VPCU +3VPCU PQ38 PQ37 2200P_50V_6 D
PR86 VDDSNS PGOOD FDS6690AS FDS6690AS
GND
GND
GND
GND
GND
GND
GND
5VIN 10 15 100K_6
VDDQSET CS
0_6 PR89 *0_6
21
22
23
24
25
26
27
FOR DDR II PC60 PR85 S3_1.8V S5_1.8V
*1000P_50V_6 8.25K/F_6
PR83 *0_6 DIS_MODE PR88

5VIN
+5VPCU HWPG_1.8V [26]
1
0_6 PC61
+1.8VSUS PR82 0_6 4.7U/X5R-6.3V_6
C C
B B
A A

DDR2 1.8V(TP1116) 3A

5 4 3 2 1
5 4 3 2 1
PQ36 FDS8884
+1.8VSUS
8 1
7 2
6 3
+ PC107 PC106 5
PC114
E E
0.1U/Y5V-16V_4 10U/X5R-6.3V_6
4
9338DRV
560U/2.5V_6X5.7
PR134
+1.25V
0_6 3A
+3V
+1.25V [2,9,17]
PR132 100K_4
PC105
[26] HWPG_2.5V 3 PGD DRV 6
.01U/X7R-25V_4 PR121
Rg 15K/F_6
MAINON PR130 0_4 9338EN 4
EN PC109 PC110 + PC108
ADJ 5
GND
1 0.1U/Y5V-16V_4 10U/X5R-6.3V_6
+5VPCU VCC PR125
PC94
Vout1 = (1+Rg/Rh)*0.5 10K_6
2
PU7 Rh
0.1U/Y5V-16V_4 G9338 ADJ
560U/2.5V_6X5.7
D D
+5VPCU
VIN +1.8VSUS +3VSUS 15V
PC89
2 1 PU6
PR114 PR115 PR136 PR120 G966-25-LF
1M_6 22_6 22_6 1M_6 .1U/50V-LF 4 1 HWPG_1.5V [26]
PR127 VPP PGOOD
SUS_ON_G SUSD 1 2 2 6
SUSD [28] [19,26,30,31] MAINON VEN VO +1.5V
0_6
3
3
3 VIN
3
+1.8VSUS 8 GND 1.5A
ADJ
9 GND NC 5
1
2 2 2 2 PC96
[26,31] SUSON PC93 10U/10V-LF_8
7
PR117 PQ24 PQ34 PQ27 *2200P_4 PC92 PR131
2
PQ25 1M_6 2N7002E 2N7002E 2N7002E PC91 .1U/50V-LF_6 1 2
1
DTC144EU 10U/10V-LF_8
1
30K/F_6
PR133
34K/F_6
VO=0.8(R1+R2)/R2
C C
VIN +1.25V +1.05V VCC_CORE +3V +3V +5V +1.5V 15V
PR111 PR126 PR49 PR34 PR96

PR112 PR104 PR94 PR105
1M_6 22_6 22_6 22_6 *22_6 22_6 22_6 22_6 1M_6
RUN_ON_G MAIND
MAIND [28]
B B
3
3
3
2 2 2 2 2 2 2 2 2 PC74
[19,26,30,31] MAINON *2200P_4
PR110 PQ32 PQ8 PQ7 PQ14 PQ23 PQ22 PQ13 PQ17
PQ21 1M_6 2N7002E 2N7002E 2N7002E *2N7002E 2N7002E 2N7002E 2N7002E 2N7002E
1
DTC144EU
1
A A

DISCHARGE/1.5V/VCC1.25 1A

5 4 3 2 1
5 4 3 2 1
Model REV DATE CHANGE LIST NOTE

00 20061218 FIRST RELEASED : 20061218
Page02: Change CLK GEN. low power outs from +1.05V to +1.25V.Because VDD_IO will drop out when high loading Circuit modify
BU1 Page02: REV_01 Remove CLK_MCH_OE#_R had pull up resistor,because had be pull up at NB side Circuit modify
Page03: Del R382,R383,Q60,D39 Circuit modify
Page04: Del R176 for FBS signals batter return path under +1.05V plane Circuit modify
Page08: Change Crestline VCC_AXM to 1.25V, reference to SR ww48 MoW. reserved 0 ohm resister Circuit modify
D D
Page16: Add D43 to avoid leakage from EC to SB,Del R242 Circuit modify
Page18: REV_01 Reserved LCD/LED type panel module and Digital/analogy MIC Circuit modify
01 20061225 Page19: Modify G-Sensor circuit Circuit modify
Page22: Reserved LPC_PD# control signal from SB to R5C833 Circuit modify
Page23: Increase HOLE Circuit modify
Page24: Add 0.1u CAP. C810 from +5VPCU to GND Circuit modify
Page25: Modify IDE LED circuit Circuit modify
Page26: Reserved R756,R766 for EC control G-Sensor Circuit modify
Page27: Add 3 cell Battery always setting circuit Circuit modify
Page28: Add +3V_S5 discharge circuit Circuit modify
Page30: Reserved PD resistor to avoid leakage voltage Circuit modify
Page32: Reserve +3V discharge circuit Circuit modify
1A 20061227 A TEST (PCB REV_1A) RELEASED : 20061227
Page03: Modify thermal protect circuit and FAN control Circuit modify
2A Page14: Modify RTC charge current / SB strip setting / Reserved PU resistor on SATALED# signal / Change XTAL capacitor value BOM/Circuit modify
Page16: Reserver Pull down resistor on HDPINT signal / Reserved C-Link to WLAN / Delete FM function / Add Board ID Circuit modify
Page18: Change panel backlight signal pull up resistor / Change camera power source / Add LED type panel circuit / Add fuse on CRT power BOM/Circuit modify
C
/ Reserved EMI choke on USB signals and add EMI solution / Add RC circuit on LED panel driver IC Circuit modify C
Page19: Modify LDO power source / Add Microprocessor reset IC / Reserved G-sensor SMBUS to SB chipset Circuit modify
Page22: Reserved Cardreader external EEPROM Circuit modify
Page23: Separate RF enable/disable pin from WLAN and 3G card / Add EMI solution and Reserved C-Link circuit / Delete 3G card function Circuit modify
20070201 / Add HOLE for card Bus connector Circuit modify
Page24: Increase CN7 pin for control illumination logo and enable/disable USB port power / Add capacitor on keyboard signals for EMI Circuit modify
/ Change LAN/B cable connector / Delete FM function Circuit modify
Page25: Modify battery LED and RF SW power source / Delete 3G card LED Circuit modify
Page26: Modify EC control circuit / Add EMI solution / Change XTAL capacitor value BOM/Circuit modify
Page27: Change fuse rating and switch MOS Circuit modify
Page29: Add EMI solution Circuit modify
3A Page03: Add CAP to GND for FAN controller IC U12 power pin decoupling Circuit modify
Page13: Change DDR socket height Circuit modify
Page18: Exchange Dioid and Fuse placement Circuit modify
20070326 Page20: Add control LAN power circuit to enable/disable LAN Circuit modify
Page22: Change 1394 connector type and delete card reader connector 2nd source Circuit modify
B Page23: Change mini-card 3V power source from +3VSUS to +3V_S5 for support wake on WLAN from S3/S4 / Change HOLE pad size Circuit modify B
Page24: Reserve EMI capacitor / add solve insert PCMCIA Card speaker has bo sound circuit Circuit modify
Page25: Add ESD protect circuit Circuit modify
Page27: Change MOS footprint Circuit modify
Page14: Modify RTC short pad footprint Circuit modify
Page17: Modify inductance type Circuit modify
20070327
Page23: Add capacitors for EMI Circuit modify
Page24: Modify FFC connector footprint Circuit modify
Page26: Add capacitor for EMI Circuit modify
Page27: Reserve EMI circuit Circuit modify
20070328
Page22: Delete card reader external EEPROM Circuit modify
Page23: Add pull up resistor on PCIE_WAKE# signal Circuit modify
Page18: Delete CMO LED type connector Circuit modify
20070329 Page25: Reserve ESD protect on kill-switch Circuit modify
Page31: Stuff R/C Snubber for EMI BOM modify
A A

Change List 3A

5 4 3 2 1
www.s-manuals.com

Dabu1mb16e0 Rev e - Quanta - Bu1 - R3a - 20070326 - Schematics

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1 2 3 4 5 6 7 8

PCB STACK UP BU1 Block Diagram

LAYER 6 : BOT FSB(667/800MHZ)

ICH8M MINI CARD MINI CARD NEW CARD 100/10 LAN

Page 24 USB PORT 6 PCMCIA 1394

FAN Touch Key FLASH

HP HP AMP AUDIO CODEC

INT SPK SPK AMP BTO BOM OPTION

Quanta Computer Inc.

Date: Monday, March 26, 2007 Sheet 1 of 33

Clock Generator Clock Gen Differential IO power +1.25V_VDD +1.25V

R85 56_4 PCLK_DEBUG_R 1 35 CLK_PCIE_3GPLL#_R RP58 1 2 0X2

Clock Gen I2C

B C406 30P_4 CG_XOUT B

(5)SLG505YC64 CK505 Standar parts follow standar setting +3V

CPU Clock select

+1.05V R408 *1K_4

1 0 1 100Mhz R55 0_4 CLK_BSEL2

Date: Monday, March 26, 2007 Sheet 2 of 33

CPU Thermal monitor

[14] H_FERR# A5 FERR# THERMTRIP# C7 Default PU 56ohm if no use.

F23 D[4]# D[36]# V23

PU/PD (ITP700) Thermal Trip

H_D#9 D[8]# D[40]# H_D#41 +1.05V

M24 D[21]# D[53]# AC26

D[26]# D[58]# SYS_SHDN# [28]

Date: Monday, March 26, 2007 Sheet 3 of 33

Merom Ball-out Rev 1a

Quanta Computer Inc.

Date: Monday, March 26, 2007 Sheet 4 of 33

Quanta Computer Inc.

CFG_8 CRT_GREEN# PEG_TX_3

MCH_CFG_18 L32 AG39

E35 T16 CRESTLINE_1p0

[13] PM_EXTTS#1 J36 PM_EXT_TS#_1 GFX_VR_EN E36

NC_2 CL_RST# CL_RST#0 [16]

TP_MCH_NC11 NC_10 SDVO_CTRL_DATA

A R104 C93 C95 A

3.01K_4 .01U_4 2.2U_6

Date: Monday, March 26, 2007 Sheet 6 of 33

[13] M_A_DQ[63:0] [13] M_B_DQ[63:0]

AT13 SA_DQ_33 SA_MA_1 BD20 BE11 SB_DQ_33 SB_MA_1 BG28

M_A_DQ46 BD7 M_B_DQ46 BJ8

Quanta Computer Inc.

Date: Monday, March 26, 2007 Sheet 7 of 33

VCC AXM NCTF

AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26

AF21 VCC_AXG_24 VCC_SM_LF3 BE39

Date: Thursday, February 01, 2007 Sheet 8 of 33

+1.25V R118 0_6 +1.25VM_VCCA_SM AW18 B23 +1.25V_VCC_AXF .1U_4

.1U_4 22N_4 +1.05V D26 2 1 PDZ5.6B +1.05V_SD

Date: Tuesday, February 06, 2007 Sheet 9 of 33

Date: Thursday, February 01, 2007 Sheet 10 of 33

Pin Name Strap description Configuration

CFG[2:0] FSB Frequency Select 010 = FSB 800MHz

CFG5 DMI X2 Select 0 = DMI X2

CFG7 CPU Strap 0 = Reserved

CFG8 Low power PCI Express 0 = Normal mode

B140 1000P_4 1000P_4