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Class Notes Digital Lec11

EEPROMs have lower density and higher cost compared with UV EPROMs. The memory cell of an EEPROM is a floating-gate MOS structure with a thin oxide layer above the drain of the MOS memory cell. Application of a high-voltage programming pulse between gate and drain induces charge in the floatinggate region which can be erased.

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54 views2 pages

Class Notes Digital Lec11

EEPROMs have lower density and higher cost compared with UV EPROMs. The memory cell of an EEPROM is a floating-gate MOS structure with a thin oxide layer above the drain of the MOS memory cell. Application of a high-voltage programming pulse between gate and drain induces charge in the floatinggate region which can be erased.

Uploaded by

Asif Kishor
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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`~ivjvcbx t Telephone :

wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &


COMMUNICATION ENGINEERING
KwgDwb‡Kkb BwÄwbqvwis wefvM
UNIVERSITY OF DHAKA
XvKv wek¦we`¨vjq DHAKA-1000, BANGLADESH
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
E-MAIL: [email protected]

Ref. No............................ July 13, 2010


Dated, the………………………….

Electrically Erasable PROM:


The memory cell of an EEPROM is a floating-gate MOS structure with a thin oxide layer above the drain of the MOS
memory cell. Application of a high-voltage programming pulse between gate and drain induces charge in the floating-
gate region which can be erased by reversing the polarity of the pulse. Since the charge transport mechanism
requires very low current, erasing and programming operations can be carried out without removing the chip from the
circuit.
It is also possible to erase and rewrite data in the individual bytes in the memory array.
The EEPROMs have lower density and higher cost compared with UV EPROMs.
+5V

A12
I/O7
I/O6
A11
I/O5
Address -
- I/O4 Data
inputs
- A1 I/O3
EEPROM I/O2
A0 8Kx8 I/O1
2864
I/O0
OE Inputs
Mode CE OE WE I/O pins
Control CE READ LOW LOW HIGH DATAOUT
inputs
WRITE LOW HIGH LOW DATAIN
WE
Standby HIGH X X High Z

Fig.: Logic symbol and operating modes for 2864 EEPROM.


Intel 2864 is organized as an 8Kx8 array with 13 address inputs and 8 data I/O pins. Three control inputs determine
the operating mode according to the table.
To write into a memory location, the output buffers are disabled so that the data to be written can be applied as inputs
to the I/O pins.
Write operation –
Prior to t1, the device is in the standby mode. A new address is applied at that time.
At t2, the CE and WE inputs are driven LOW to begin the write operation. OE is HIGH so that the data pins will
remain in the Hi-Z state.
At t3, data are applied to the I/O pins.
At t4, data are written into the address location on the rising edge of WE . CE is returned HIGH, the chip is back in
the standby mode.
At t5, the data are removed.

Lec-11, Pg-01 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
`~ivjvcbx t Telephone :
wc,G,we,G·, 9661920-73/4980 PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &


COMMUNICATION ENGINEERING
KwgDwb‡Kkb BwÄwbqvwis wefvM
UNIVERSITY OF DHAKA
XvKv wek¦we`¨vjq DHAKA-1000, BANGLADESH
XvKv-1000, evsjv‡`k FAX: 880-2-8615583
E-MAIL: [email protected]

Ref. No............................ July 13, 2010


Dated, the………………………….

Standby mode Write mode Standby mode


1
ADDRESS ADDRESS STABLE
0
1
CE
0
1
WE
0
OE 1
1
DATA
DATA I/O Hi-Z state
VALID
0
t1 t2 t3 t4 t5 Erase and store
Typically 200ns operations,; typically 5ms

Fig.: Timing for write operation to 2864 EEPROM.

Semiconductor RAM:
The term RAM stands for random-access memory, meaning that any memory address location is as easily accessible
as any other. RAM is used in computers for the temporary storage of programs and data. RAM is volatile and will lose
all stored information if power is interrupted or turned off. It can be written into and read from RAM rapidly as the
computer executes a program with equal ease.
Depending upon the nature of the memory cell used, there are two types of RAM –
(I) Static RAM (SRAM)
SRAM can be broadly classified as –
(a) Asynchronous SRAM and
(b) Synchronous SRAM.
(II) Dynamic RAM (DRAM).
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

Lec-11, Pg-02 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

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