Solutions: Solutions Manual For Sensors and Actuators Engineering System Instrumentation 2Nd Edition Silva

SOLUTIONS MANUAL FOR SENSORS AND ACTUATORS ENGINEERING SYSTEM
INSTRUMENTATION 2ND EDITION SILVA
SOLUTIONS

Chapter 2 Component Interconnection and Signal Conditioning
Solution 2.1
(a):
Voltage Output
Electrical Impedance =
Current Input
Force Output
Mechanical Impedance =
Velocity Input
(b): Both these impedances are frequency response functions (defined in the frequency
domain). Both define the resistance provided by the load against the driving force. High-
impedance devices need high levels of effort (voltage or force) to drive them (i.e., to pass
current through electrical impedances, or to cause movement of mechanical loads). Note that
voltage is an across-variable whereas force is a through-variable. Hence, there is an
inconsistency in the definitions of “impedance,” with respect to the force-current analogy.
(c): To avoid this inconsistency, we may use the force-voltage analogy, in which voltage and
force are termed “effort” variables and velocity and current are “flow” variables, as in the
“bond graph” nomenclature.
Note, however, that in order to use general relations for interconnecting basic
elements (in forming multicomponent devices or circuits), it is the across-variable and
through-variable nomenclature that is applicable. Specifically, when two elements are
connected in series, the through-variable is common and the across-variables add; when two
elements are connected in parallel, the across-variable is common and the through-variables
add. Hence, it is the through- and across-variable nomenclature that is natural with regard to
component interconnection. In this context we may define a generalized series element or
generalized impedance (to include electrical impedance or mechanical mobility) and a
generalized parallel element (to include electrical admittance or mechanical impedance).
(d): The input impedance has to be comparatively high for a measuring device that is
connected in parallel, to measure an across variable, whereas the input impedance has to be
quite low for a device that connected in series, to measures a through variable. This is
essential to reduce loading errors. The output impedance of a measuring device has to be
low in order to maintain a high sensitivity, and get acceptable signal levels for processing,
actuating or recording.
When cascading two devices, in order to reduce the “loading” of one device by the
other, and to maintain good frequency characteristics, the output impedance of the first
device (which provides the signal) has to be smaller in comparison to the input impedance of
the second device (which receives the signal). Otherwise, the signal will be distorted by the
second device (the load). If power transfer characteristics are important, however, one
impedance should be the complex conjugate of the other. Different matching criteria are
used depending on the applications.
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14 SENSORS AND ACTUATORS
Solution 2.2
1. Maximum power transfer
2. Power transfer at maximum efficiency
3. Reflection prevention in signal transmission
4. Loading reduction
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Solution 2.3
When a measuring device is connected to a system, the conditions in the system itself will
change, as the measured signal flows through the measuring device. For example, in
electrical measurements, a current may pass through the measuring device, thereby altering
the voltages and currents in the original system. This is called “electrical loading,” and will
introduce an error, as the measurand itself is distorted. Similarly, in mechanical
measurements, due to the mass of the measuring device, the mechanical condition (forces,
motions) of the original system will change, thereby affecting the measurand and causing an
error. This is called mechanical loading.
 Zi 
Now consider the system shown in Figure P2.3. We have: vo = K   vi
 Zs + Zi 
 Zi 
For a voltage follower, K = 1 and Zo << Zi . Hence, vo = 
vo
=
( Zi / Zs ) .
 vi , or
 Zs + Zi  vi 1 + ( Zi / Zs )
This relationship is sketched in Figure S2.3.
0.8
0.6
0.4
0.2
00 1 2 3 4 5 6 7 8 9 10
Figure S2.3: Non-dimensional curve of loading performance.
COMPONENT INTERCONNECTION AND SIGNAL CONDITIONING 15
Some representative values of the curve are tabulated below.
Zi / Zs vo / vi
0.1 0.091
0.5 0.55
1 0.5
2 0.667
5 0.855
7 0.875
10 0.909
Note: Performance improves with the impedance ratio Zi / Zs .

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Solution 2.4
Open-circuit voltage at the output port is (in the frequency domain)

 1 
 R2 + jωC 
voc =   = veq (i)
 1 
 R1 + R2 + jωL + jωC 
 
Note: Equivalent source veq is expressed here as a function of frequency. Its corresponding
time function veq (t ) is obtained by using inverse Fourier transform. Alternatively, first
R + 1 
 2 sC 
replace jω by the Laplace variable s: veq ( s) = v( s) . Then obtain the
 R + R + sL + 1 
 1 2
sC 
inverse Laplace transform, for a given v(s), using Laplace transform tables.
Now, in order to determine Zeq, note from Figure P2.4(b) that if the output port is
veq
shorted, the resulting short circuit current iSC is given by: iSC = . Hence,
Zeq
veq voc
Zeq = = (ii)
isc isc
Since we know voc (or veq ) from equation (i) we only have to determine isc . Using the
actual circuit with shorted output, we see that there is no current through the parallel
1
impedance R2 + because the potential difference across it is zero. Thus,
jω C
v
isc = (iii)
( R1 + jωL)
Now substituting Equations (i) and (iii) in (ii) we have:
 1  
  R2 + 
jω C 
[ R1 + jωL] 
Zeq = 
 1 
  R1 + R2 + jωL + 
 jωC  
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Solution 2.5
Rl Rl / Rs
=
(a) Load power efficiency η =
( Rl + Rs ) ( Rl / Rs + 1)
vs 2 Rl vs 2
(b) Load power pl = ; Maximum load power (occurs at Rl = Rs ) pmax =
[ Rl + Rs ]2 4 Rs
4 Rl / Rs
 pl / pmax =
[ Rl / Rs + 1]2
We use the following MATLAB script (.m file) to generate the two curves:
% Efficiency and load power curves

lr=[]; eff=[]; pw=[]; % declare vectors
lr=0; eff=0; pw=0; %initialize variables
for i=1:100
a=0.1*i; %load resistance ratio
lr(end+1)=a; % store load resistance
eff(end+1)=a/(a+1); % efficiency
pw(end+1)=4*a/(a+1)^2; % load power
end
plot(lr,eff,'-',lr,pw,'-',lr,pw,'x')
The two curves are plotted in Figure S2.5.
It is seen that maximum efficiency does not correspond to maximum power. In

particular, the efficiency increases monotonically with the load resistance while the
maximum power occurs when Rl = Rs . Hence, a reasonable trade-off in matching the
resistances would be needed when both considerations are important.
Efficiency and Load Power Curves

1
0.9
0.8
Efficiency (fractional)
0.7
Load power/Max power
0.6
0.5
0.4
0.3
0.2
0.1
0
0 1 2 3 4 5 6 7 8 9 10
Load Resistance/Source Resistance Ratio
Figure S2.5: Variation of efficiency and maximum power with load resistance.
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Solution 2.6
Voltage is an across variable. In order to reduce loading effects, the resistance of a voltmeter
should be much larger than the output impedance of system or load impedance. Then, the
voltmeter will not draw a significant part of the signal current (and will not distort the
signal). Current is a through variable. The resistance of an ammeter should be much smaller
than the output impedance of system or load impedance. Then, the ammeter will not provide
a significant voltage drop (and will not distort the signal).
Voltmeter should be able to operate with a low current (due to its high resistance) and
associated low torque, in conventional electromagnetic deflection type meters. Low torque
means, a torsional spring having low stiffness has to be used to get an adequate meter
reading. This makes the meter slow, less robust, and more nonlinear, even though high
sensitivity is realized.
Ammeter should be able to carry a large current because of its low resistance. Hence
meter torque would be high in conventional designs. This can create thermal problems,
magnetic hysteresis, and other nonlinearities. The device can be made fast, robust, and
mechanically linear, however, while obtaining sufficient sensitivity.
Note: The torque is not a factor in modern digital multi-meters.
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Solution 2.7
(a) The input impedance of the amplifier = 500 MΩ.

10
=
Estimated error ×100%
= 2%
(500 + 10)
(b) Impedance of the speaker = 4 Ω.
0.1
Estimated error= ×100%= 2.4%
(4 + 0.1)
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Solution 2.8
∂F1 ∂F
vo = F1 ( fo , fi ) ⇒ δvo = δfo + 1 δfi (i)
∂fo ∂fi
∂F2 ∂F
vi = F2 ( fo , fi ) ⇒ δ vi = δfo + 2 δfi (ii)
∂fo ∂fi
In terms of incremental variables about an operating point, we can define the input
impedance Zi and the output impedance Z o as
δvi
Zi = with δf o = 0 (iii)
δfi
δvo with δf o = 0
Zo = (iv)
δfo with δvo = 0
Note: δfo = 0 corresponds to incremental open-circuit condition and δvo = 0 corresponds to
incremental short-circuit condition.
∂F
From (ii) with δfo = 0 (i.e., open circuit at output) we get Z i = 2 .
∂fi
Now using the open-circuit by subscript “oc” and the short-circuit by subscript “sc” we have:
From (i):
∂F
δvo = 1 δfi oc (v)
oc ∂fi
From (ii):
∂F
δvi = 2 δfi oc (vi)
oc ∂fi
Note: δv i is an independent increment, which does not depend on whether oc or sc condition
exists at the output. But δf i will change depending on the output condition.
From (v) and (vi):
∂F ∂F2
δvo oc = 1 δvi (vii)
∂fi ∂fi
From (i):
∂F ∂F
0 = 1 δfo sc + 1 δfi sc (viii)
∂fo ∂fi
From (ii):
∂F2 ∂F2
δvi = δfo + δfi (ix)
∂fo sc
∂fi sc
Eliminating δf i sc
from Equations(viii) and (ix) we get,
1
δfo sc = δvi (x)
 ∂F2 ∂F1 ∂F2 ∂F1 
 − ⋅ 
 ∂f o ∂fo ∂f i ∂fi 
Substitute (vii) and (x) in (iv):
 ∂F ∂F2   ∂F2 ∂F1 ∂F2 ∂F1  ∂F1 ∂F2 ∂F1 ∂F1
= Zo  1  − ⋅ =  . −
 ∂fi ∂fi   ∂f o ∂f o ∂f i ∂f i  ∂fi ∂f o ∂f i ∂f o
One way to experimentally determine Zi and Zo (under static conditions) is to first
experimentally determine the two sets of operating curves given by vo = F1 ( fo , fi ) and
vi = F2 ( fo , fi ) under steady-state conditions. For example fo is kept constant and fi is
changed in increments to measure vo and vi once the steady state is reached. This will give
two curves fi versus vo and vi versus vi for a particular value of fo. Next fo is incremented and
another pair of curves is obtained. Once these two sets of curves are obtained for the
required range for fi and fo, the particular derivatives are determined from using the general
∂z ∂z ∆z
method shown in Figure S2.8, for the case z = F(x,y) with: ≅ α and ≅ .
∂x ∂y ∆y
z y+Δy
Δz
Figure S2.8: Computation of local slopes.

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Solution 2.9
(a)
We have: vi = Z c ii , vt = Z l it , vr = − Z c ir , v=
t vi + vr , and it= ii + ir , where “i” denotes current
and the subscript “r” denotes “reflected.”
v v Zl Zl Zl
Substitute: v=
t Z l=it Z l (ii + ir= ) Zl ( i − r = ) (vi − vr=
) (vi − (vt − vi ))
= (2vi − vt )
Zc Zc Zc Zc Zc
Z Z 2Zl
 (1 + l )vt = 2 l vi  vt = vi
Zc Zc (Zl + Z c )
2Zl
(b) We need vt = vi  = 1  Zl = Zc
(Zl + Z c )
(c) Use a transformer with the required impedance ratio = (turns ratio)2
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Solution 2.10
1 × 10 6
For the given system, ω n = rad/s = 100 rad/s and ω ≥ 200 rad/s. Hence, we have
100
the frequency ratio r ≥ 2.0.
1 + 16ζ 2
5
For r = 2.0 and T f = 0.5 we have 0.5 = or, ζ = . Hence,
9 + 16ζ 2
48
5
b 2ζωn m
= = 2 ×100 ×100 N.s/m → =
b 6.455 ×103 N.s/m .
48
With this damping constant, for r ≥ 2, we will have T f ≤ 0.5. Decreasing b will decrease
T f in this frequency range.
To plot the Bode diagram using MATLAB, first note that:

2ζωn = b/m = 64.55 rad/s and ωn 2 = 104 (rad/s) 2
6.455 × 103 /100 =
64.55s + 104
The corresponding transmissibility function is T f = 2 with s = jω
s + 64.55s + 104
The following MATLAB script will plot the required Bode diagram:
% Plotting of transmissibility function

clear;
m=100.0;
k=1.0e6;
b=6.455e3;
sys=tf([b/m k/m],[1 b/m k/m]);
bode(sys);
The resulting Bode diagram is shown in Figure S2.10. A transmissibility magnitude of 0.5
corresponds to 20 log10 0.5 dB = -6.02 dB .
Note from the Bode magnitude curve in Figure S2.10.4 that at the frequency 200 rad/s the
transmissibility magnitude is less than -6 dB and it decreases continuously for higher
frequencies. This confirms that the designed system meets the design specification.
Bode Diagram
10
0
Magnitude (dB)
-10
-20
-30
-40
-50
0
Phase (deg)
-45
-90
-135
1 2 3 4
10 10 10 10
Frequency (rad/sec)
Figure S2.10: Transmissibility magnitude and phase curves of the designed system.
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Solution 2.11
(a) Mechanical Loading

A motion variable that is being measured is modified due to forces (inertia, friction, etc.) of
the measuring device.
(b) Electrical Loading

The output voltage signal of the sensor is modified from the open circuit value due to the
current flowing through external circuitry (load).
Mechanical loading can be reduced by using noncontact sensors, reducing inertia and
friction, etc.
Electrical loading can be reduced by using a low-output-impedance sensor, high-

impedance load, impedance transformer, etc. Some typical values of the listed parameters are
given in the following table:
Parameter Ideal Value Typical Value

Input Impedance Infinity 1MΩ
Output Impedance Zero 50 Ω
Gain Infinity 106
Bandwidth Infinity 10 kHz
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Solution 2.12
The differential signal from the secondary windings is amplified by the ac amplifier and is
supplied to the demodulator. A carrier signal is used by the demodulator to demodulate the
differential ac signal. The modulating signal that is extracted in this manner is proportional
to the machine displacement. This signal is filtered to remove high-frequency noise (and
perhaps the carrier component left by the demodulator), and then amplified and digitized
(using an ADC) to be fed into the machine control computer.
The compensating resistor Rc may be connected between the points A and B or A and
C, as shown in Figure S2.12.
AC
Excitation
Primary
Coil
Secondary
Coils
A
C B
RC
Differential
Output
Figure S2.12: Null compensation for an LVDT.

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Solution 2.13
(a)
Scanning
Logic
Control
Image Sensor
Capacitive- Computer
CCD or and Image
Monitored Light Coupled
CMOS ADC Acquisition
Object Amplifier
Matrix Hardware/
and Filter
Software
Process Drive
DAC
Action Drive Amplifier
Signal
Figure S2.13: Monitoring of an industrial process using image processing.
(b) Data rate = 488 × 380 × 8 × 30 bits/s = 44.5 Megabits/s
(c) Since hardware processors are faster, we prefer them for this level of high data rates
for real-time action. Also, they are cheaper when mass produced. Disadvantages include
limitations on algorithm complexity in image processing and memory size.
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Solution 2.14
Since the open-loop gain K of an op-amp is very high (105 to 109) and the output voltage
cannot exceed the saturation voltage (which is of the order of 10 V) the input voltage
vi = vip − vin is of the order of a few µV, which can be assumed zero (when compared with
the operating voltages) for most practical purposes. Hence, vip = vin . Next since the input
impedance Zi is very high (MΩ), the current through the input leads has to be very small for
this very small vi under unsaturated conditions.
(a) The saturated output of the op-amp must be 14 V in this example. The ac noise (line
noise, ground loops, etc.) in the circuit can easily exceed the saturation input (on the
order of 10 µV) of the op-amp, under open-loop conditions. Hence, vi = vip − vin can
oscillate between + and - values of the saturation input. This provides an output, which
switches between the +ve saturated output +vsat and the -ve saturated output -vsat of the
op-amp.
(b)
Case 1: vip =−1 µV , vin =
+0.5 µV  vi =vip − vin =−1 − 0.5 µV =−1.5 µV
 vo =
−1.5 × 5 ×106 µV =
−1.5 × 5 V =
−7.5 V
This is valid since the output is not saturated.
Case 2: vip = 0 , vin= 5 µV  vi =0 − 5 µV =−5 µV
 vo =−5 × 5 ×106 µV =−25 V

 Op-amp is saturated  The actual output would be vo = −14 V
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Solution 2.15
(a) Offset Current (Typically in nA)

Bias currents are needed to operate the transistor elements in an op-amp IC. These currents
i+ and i- flow through the input leads of an op-amp. The offset current is the difference
i + − i − . Ideally, the offset current is zero.
(b) Offset Voltage (Typically in mV or less)

Due to internal circuitry (IC) in an op-amp, the output voltage might not be zero even when
the two inputs are maintained at the same potential (say, ground). This is known as the offset
voltage at output. Furthermore, due to unbalances in the internal circuitry, the potentials at
the two input leads of an op-amp will not be equal even when the output is zero. This
potential difference at the input leads is known as the input offset voltage. This is usually
modeled as a small voltage source connected to one of the input leads
(c) Unequal Gains (Can range over 105 to 109)

The open-loop gain of an op-amp with respect to the “+” input lead may be different from
that with respect to the “-” input lead. This is known as unequal gains.
(d) Slew Rate (Typically about 0.5 V/µs)

When the input voltage is instantaneously changed, the op-amp output will not change
instantaneously. The maximum rate at which the output voltage can change (usually
expressed in V/µs) is known as the slew rate of an op-amp.
Even though K and Zi are not precisely known and can vary with time and frequency,
their magnitudes are large. Hence, we can make the basic assumptions: equal potential at the
two input leads and zero current through the input leads, under unsaturated conditions. Then,
these parameters do not enter the output equations of an op-amp circuit.
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Solution 2.16
(a)
A voltage follower is an amplifier having a unity voltage gain, a very high input impedance,
and a very low output impedance. A simple model for a voltage follower is obtained by
connecting the “-” lead of an op-amp to the output (feedback path) and using the “+” lead as
the input lead. Under unsaturated conditions we have v o = vi . It is known that the input
impedance of a voltage follower is much larger than that of the original op-amp (which itself
is quite large—megohm range) and the output impedance of a voltage follower is much
smaller than that of the original op-amp (which is also small). Hence, a voltage follower
functions primarily as an impedance transformer that provides the ability to acquire a voltage
from a high-impedance device, where the current is rather low (e.g., a high-impedance
sensor) and transmitting that voltage signal into a low-impedance device, without distorting
the acquired voltage.
(b)
Consider circuit in Figure P2.16. Since v B = 0 , we have v A = 0 .
v v
Hence, current summation at node A gives: i + o = 0
R Rf
Note: The current through an input lead of an op-amp has to be zero.
v Rf R
Hence, o = − and K v = − f  This is an inverting amplifier.
vi R R
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Solution 2.17
Slew rate: s = 2πf b a (i)

where, a = output amplitude, fb = bandwidth (Hz).
k
The rise time Tr is inversely proportional to fb. Hence, f b = where, k = constant.
Tr
2πka
Substitution gives: s= (ii)
Tr
From (i): For constant s, bandwidth decreases as a is increased.
0.5
For a sine signal, substitute the given values in (i): f b = MHz = 318
. kHz
2π × 2.5
∆y
Next, for a step input, use s = where, Δy = step size, = Δt rise time
∆t
2.5 ∆y
Substitute numerical values: ∆t = =
µs = 5 µs .
s 0.5
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Solution 2.18
(a) Common-mode voltage vcm = voltage common to the two input leads of a differential
amplifier = average of the two inputs.
Common-mode output voltage vocm = output voltage of the amplifier due to vcm (i.e.,
in the absence of any voltage differential at the input.)
v
(b) Common-mode gain = ocm
v cm
vcm K
(c) = K=
CMRR
vocm common-mode gain
where, K = amplifier gain (i.e., differential gain or gain at the output for the inferential input).
1
=
Specifically: vo K (vip − vin ) + K cm × (vip + vin )
2
Typically CMRR ≈ 20,000 .
When A is closed and B is open, the flying capacitor C gets charged to the differential
voltage vi1 − vi 2 and hence the common-mode voltage does not enter. When A is open and
B is closed, the capacitor voltage, which does not contain the common-mode signal, is
applied to the differential amplifier.
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Solution 2.19
The textbook definition of stability relates to the dynamic model (linear or nonlinear) of a
system and hence to its natural response. In particular, in a linear system, if at least one pole
(eigenvalue) has a positive real part, the natural response of the system will diverge, and the
system is unstable.
Instrumentation stability is linked to the drift associated with change in parameters of
the instrument or change in the environmental conditions.
Change in output
Temperature drift =
Change in temperature
assuming that the other conditions and the input are maintained constant.
Change in output
Long term drift =
Duration
assuming that the other conditions and input are the same.
Ways to Reduce Drift: Regulate the power supply; Use feedback; Keep the environment
uniform; Use compensating elements and circuitry; Recalibrate the device before
each use.
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Solution 2.20
DC High -
Power Frequency
Supply Oscillator
Low-
Voltage DC
Filter Modulator Demodulator Pass
Follower Amplifier
Filter
Input
Output
Transformer
Coupling
Input Output
Section Section
Figure S2.20: An isolation amplifier.

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Solution 2.21
Possible causes:
1. Faulty cellphone charger and it not having a ground lead and pin
2. Faulty laptop charger and it not having a ground lead and pin
Faulty Cellphone Charger: Due to a short-circuit, the high voltage (110-240 VAC) will
leak into its cable and reach the cellphone. If the cellphone is not properly
grounded/isolated, the voltage will form a path through the user’s body. According to
the burns, this path has to include the chest and the ears (possibly through the
headphone cable).
Faulty laptop Charger: Due to a short, the high voltage (110-240 VAC) will leak from the
charger into the DC cable segment that is connected to the laptop. If the laptop is not
properly grounded/isolated, the voltage will form a path through the user’s body.
According to the burns, this path has to include the chest and the ears (possibly through
the headphone cable).
On the one hand, the newspaper report indicated that there were inexpensive and non-
compliant cellphone chargers in the market. However, since the power consumption of
the cellphone charger is relatively low and since the electricity path through the body
included the ears (Note: The headphones were connected to the laptop, not to the
cellphone) the other possibilities of fault need to be investigated as well. Typically,
however, the laptop chargers (particularly those provided by reputed laptop
manufacturers) are subjected to rigorous standards, inspection, and quality control (so
are cellphone chargers from reputed manufacturers).
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Solution 2.22
Passive filters are circuits made of passive elements, which do not require an external power
supply to operate. These circuits allow through those signal components in a certain
frequency range and block off the remaining frequency components.
Advantages and disadvantages of passive filters: See disadvantages and advantages of active
filters.
The voltage follower is an impedance transformer. It reduces loading problems by providing

a very high input impedance and very low output impedance. Furthermore, it does not
change the voltage gain.
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Solution 2.23
Applications:
(a) Anti-aliasing filters in digital signal processing

(b) To remove dc components in ac signals
(c) As tracking filters
(d) To remove line noise in signals.
ki (τ zi s + 1)
Each single-pole stage will have a transfer function of the form: Gi ( s ) =
(τ pi s + 1)
Hence, the cascaded filter will have the transfer function:
( τ zi s + 1 )
G( s ) Π=
= Gi ( s ) Π ki , where “Π“ denotes the product operation.
( τ pi s + 1 )
1
Note that the poles are at − and these are all real; there are no complex poles. Hence,
τ pi
there cannot be resonant peaks.
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Solution 2.24
It provides the flattest magnitude over the pass band among all filters of the same order
(same pole count).
Also, we prefer a very sharp cutoff (i.e., steep roll-up and roll-down).
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Solution 2.25
(a)
Op-amp properties: 1. Voltages at input leads are equal; 2. Currents through input leads = 0
Op-amp property: v=
B v=
P vo (i)
(vi − v A ) (v A − vB ) (v A − vP )
Current Balance at Node A: = + (ii)
Zc Zc R
(v − v ) v
Current Balance at Node B: A B = B (iii)
Zc R
1
Note: Z c = = impedance of capacitor
Cs
(v − v ) vo (v A − vo ) v A 1
Substitute (i) and (iii) in (ii): i A = + =  vi= (1 + )v A (iv)
Zc R R R τs
(v − v ) v 1
Substitute (i) in (iii): A o = o  v A= (1 + )vo (v)
Zc R τs
Note: τ = RC = time constant
vo (τs) 2
Substitute (iv) in (v): G ( s) = =
vi (τs + 1) 2
This is a 2nd order transfer function  2-pole filter
(b)
−τ 2ω 2
With s = jω in G(s), we have G ( jω ) =
(1 + τ jω )
τ 2ω 2
Filter magnitude G ( jω ) =
(1 + τ 2ω 2 )
The magnitude of the filter transfer function is sketched in Figure S2.25. This represents a
high-pass filter.
(c)
1
When, ω << : G ( jω ) ≅ τ 2 ω 2
τ
1 τ 2ω 2
When, ω >> : G ( jω ) ≅ =1
τ τ 2ω 2
1
Hence, we may use ω c = as the cutoff frequency.
τ
Note: G ( jω ) → 1 as ω → ∞
For small ω: Roll-up slope of G ( jω ) curve is 40 dB/decade.
Magnitude
G ( jω )
(Log)
40 dB/decade
0 dB
Frequency ω
(Log)
Figure S2.25: Filter transfer function magnitude.
_________________________________________________________________________
Solution 2.26
Strain Gauge for force Sensing: Low-frequency noise due to ambient temperature
fluctuations. These may be compensated for (using abridge circuit) and also through
high-pass filtering
Wearable Ambulatory Monitoring (WAM): In human mobility monitoring (e.g., in
telehealth applications) a popular WAM sensor is a combined accelerometer and
gyroscope. Both sensors will be affected by bias, removal of which would need high-
pass filtering). High-frequency artifacts may be generated in the sensed signal due to
muscle tremor and low-frequency artifacts may be formed due to respiration. These
may be removed using band-pass filtering.
Microphone (Robotic Voice Commands): A band-pass filter for the human vocal range
(80Hz to 1100Hz).
AC-powered Tachometer for Speed Sensing: Line noise (60 Hz) may be removed using a
notch filter.
_________________________________________________________________________
Solution 2.27
(a)
The main signal component appears sinusoidal with frequency ~ 1 rad/s (period ~ 6.3 s).
From the figure it is not clear whether there is a superimposed sinusoidal signal of high
frequency and/or high-frequency noise, even though some oscillations are observed in the
noise.
(b)
We use the following MATLAB command to obtain the four-pole Butterworth low-pass
filter with cut-off frequency at 2.0 rad/s:
>> [b,a]=butter(4,2.0,'s')
b =
0 0 0 0 16.0000
a =
1.0000 5.2263 13.6569 20.9050 16.0000
Then, we use the following MATLAB commands to filter the data signal using this filter, and
plot the result shown in Figure S2.27(a):
>>y1=lsim(b,a,u,t);
>> plot(t,y1,'-')
(a) Low-pass Filtered Signal with Cut-off 2.0 rad/s

1
0.8
0.6
0.4
0.2
Signal (V)
-0.2
-0.4
-0.6
-0.8
-1
0 1 2 3 4 5 6 7 8 9 10
Time (s)
-3
x 10 (b) Filtered Signal with Pass-band [9.9,10.1] rad/s
5
1
Signal (V)
-1
-2
-3
-4
-5
0 1 2 3 4 5 6 7 8 9 10
Time (s)
(c) Filtered Signal with Pass-band [9.0,11.0] rad/s

0.25
0.2
0.15
0.1
0.05
Signal (V)
-0.05
-0.1
-0.15
-0.2
-0.25
0 1 2 3 4 5 6 7 8 9 10
Time (s)
(d) Filtered Signal with Pass-band [8.0,12.0] rad/s

0.25
0.2
0.15
0.1
0.05
Signal (V)
-0.05
-0.1
-0.15
-0.2
-0.25
0 1 2 3 4 5 6 7 8 9 10
Time (s)
Figure S2.27: Filtered signals. (a) Low-pass at 2.0 rad/s; (b) Band-pass over [9.9,
10.1]; (c) Band-pass over [9.0, 11.0]; (d) Band-pass over [8.0, 12.0].
It is seen that the filtered signal has a frequency of 1.0 rad/s with the correct amplitude (1.0)
and negligible phase shift. Initially some signal distortion is seen due to the transient nature
of the output. However, the steady-state value is reached in half a period of the signal.
(c)
Band-pass filtering for the three cases are obtained using the following MATLAB
commands:
>> Wn=[9.9,10.1];
>> [b2,a2] = butter(4,Wn,'bandpass','s');
>> y2=lsim(b2,a2,u,t);
>> plot(t,y2,'-')
>> Wn=[9.0,11.0];
>> plot(t,y2,'-')
>> Wn=[8.0,12.0];
>> plot(t,y2,'-')
The results are shown in Figures S2.27 (b)-(d). The very narrow pass-band produced a
filtered result that took a rather long time to reach the steady state of amplitude 0.2 (i.e., the
filter had a larger time constant). When the pass-band was increased, the steady state was
reached quicker (i.e., smaller filter time constant). However, the amplitude distortion of the
filtered signal was noticeable as a result.
_________________________________________________________________________
Solution 2.28
If a characteristic of a signal “B” is changed with respect to time, depending on some

characteristic parameter of another signal “A,” this process is termed modulation. The
modulating signal (or data signal) is the signal A. The carrier signal is the signal B. The
output signal of the modulation process is the modulated signal. The process of recovering
the data signal (A) from the modulated signal is known as demodulation.
(a) Amplitude Modulation (AM)

The carrier is a periodic signal (typically a sine wave). The amplitude of the carrier signal is
varied in proportion to the magnitude of the data signal. Specifically, the carrier signal is
multiplied by the data signal. In one form of AM, the carried signal is added again to the
resulting product signal. The AM technique is used in radio transmission and in sensing (e.g.,
differential transformer). The sign of the data signal is represented by a 180° phase change
in the carrier signal.
(b) Frequency Modulation (FM)

The carrier is typically a sine wave signal. The frequency of the carrier signal is varied in
proportion to the magnitude of the data signal. This process is commonly used in radio
transmission and data storage. Sign of the data signal is represented by changing the carrier
phase angle by 180°.
(c) Phase Modulation (PM)

The carrier signal is typically a sine wave. The phase angle of the carrier signal is varied in
proportion to the magnitude of the data signal. Used in signal transmission. Sign of the data
signal is represented by positive or negative phase change in the carrier.
(d) Pulse-width Modulation (PWM)

The carrier is a pulse signal. The pulse width of the carrier is changed in proportion to the
magnitude of the data signal. Both the spacing between the pulses (pulse period) and the
pulse amplitude are kept constant. Used in dc motor speed control, other control applications,
and digital-to-analog conversion (DAC). Sign of data is accounted for by using both +ve and
-ve pulses.
(e) Pulse-Frequency Modulation (PFM)

The carrier is a pulse signal. The frequency of the pulses is changed in proportion to the
magnitude of the data signal. Pulse width and pulse amplitude are maintained constant (and
the pulse period is varied). Used in dc motor speed control. Sign of data is accounted for by
using both +ve and -ve pulses.
(f) Pulse-Code Modulation (PCM)

Carrier signal is a pulse sequence. The value of the data signal at a given time instant is
represented in the binary form and this value is represented in the carrier (of by equally
spaced pulses) using the fact that the presence of a pulse can be used to represent binary 0.
Then for a given word size, say n bits, a maximum of n pulses have to be transmitted. The
sign of the data word may be represented by an additional bit, known as the sign bit (using,
say 1 to represent “+” and 0 to represent “-”). Separation between one data word and the
next may be detected through “framing” a data word using “start bits” and “end bits.” Used
in digital communication.
_________________________________________________________________________
Solution 2.29
Intentional AM
• Radio broadcast
AM will improve signal communication with reduced distortion by noise and
transmission loss. It will also facilitate making several broadcasts
simultaneously in the same geographic area (due to the frequency-shifting
property of AM)
• Signal conditioning
AM enables us to exploit advantages of ac signal conditioning hardware
(improved stability, reduced drift, etc.). Also, the AM process will improve
the signal level and noise immunity as a result of the use of the original signal
(to be conditioned) to modulate a high-frequency, high-power carrier signal.
Natural AM
• Any device that uses the transformer action (primary winding and secondary
winding with the primary coil being excited by an AC; e.g., linear variable
differential transducer or LVDT, ac tachometer).
• A rotating machine with a fault; e.g., a gearbox with a fault on a tooth, a turbine
rotor with eccentricity or damaged blade.
Yes. In the first device AM provides the advantages of ac signal conditioning, and
improves noise immunity and signal level.
In the second device, the AM principle is useful for fault detection and diagnosis (through
identification of the associated frequencies).
_________________________________________________________________________
Solution 2.30
840 + 960
(a) Ball passing frequency = carrier frequency f c = = 900 Hz
2
Hence, Estimated shaft speed = f b = 900 − 840=
rev/s 60= rev/s 3600 r.p.m.
ball passing frequency 900
Number of balls = = = 15
shaft speed 60
Peak frequencies = 900 ± 60 Hz =

[840 and 960 ]Hz, (see Figure P2.30).
(b) Yes.
_________________________________________________________________________
Solution 2.31
(a) Phase-Sensitive Demodulation

If the sign of the data signal (modulating signal) is preserved at all times during modulation
and is properly recovered in the demodulation process, we have a phase-sensitive
demodulation. Note: A sign change corresponds to a 180° phase change of the modulated
signal; hence, the name.
(b) Half-Wave Demodulation

In half-wave demodulation, an output is generated during every other half-period of the
carrier signal.
(c) Full-Wave Demodulation

Here, an output (demodulated value) is generated continuously for every point of the carrier
signal.
The rotating frequency (rev/s) fo modulates the responses produced by the forcing
functions such as gear meshing, ball or roller hammer, and blade passing in rotating
machinery. Hence, if the forcing frequency is fc, according to the modulation theorem, peaks
occur at f c ± f o instead of at fc.
_________________________________________________________________________
Solution 2.32
Resolution corresponds to 1 LSB  10/ 28 = 10/256 = 0.04 V

Quantization error 9rounding off) corresponds to half this value  0.02 V
_________________________________________________________________________
Solution 2.33
(a)
The decimal value of the input binary word is given by
= D 2n −1 bn −1 + 2n − 2 bn − 2 + …+ 20 b0 . (i)
The least significant bit (LSB) is b 0 and the most significant bit (MSB) is b n−1 . The analog
output voltage v of the DAC has to be proportional to D.
Each bit b i in the digital word w will activate a solid-state microswitch in the switching
circuit, typically by sending a switching voltage pulse. If b i = 1, the circuit lead will be
connected to the− v ref supply, providing an input voltage v i = − v ref to the corresponding
weighting resistor 2n−i−1 R. If, on the other hand, b i = 0, then the circuit lead will be
connected to ground, thereby providing an input voltage v i = 0 to the same resistor. Note that
the MSB is connected to the smallest resistor (R) and the LSB is connected to the largest
resistor (2n−1 R). By writing the summation of currents at node A of the output op-amp, we
v v v v
get n −1 + n − 2 +… n −01 + =0.
R 2R 2 R R/2
In writing this equation, we have used the two principal facts for an op-amp: the voltage is
the same at both input leads and the current through each lead is zero. Note that the positive
lead is grounded and hence node A should have zero voltage. Now, since v i = −b i v ref , where
b i = 0 or 1 depending on the bit value (state of the corresponding switch), we have
 b b  vref
= v bn −1 + n − 2 +…+ n0−1  (ii)
 2 2  2
Clearly, as required, the output voltage v is proportional to the value D of the digital word w.
(b)
The full-scale value (FSV) of the analog output occurs when all b i are equal to 1. Hence,
 1 1 v
FSV= 1 + +…+ n −1  ref
 2 2  2
Using the commonly known formula for the sum of a geometric series
(1 − r n )
1 + r + r 2 +…+ r n −1 = (iii)
(1 − r )
we get
 1 
FSV= 1 − n  vref (iv)
 2 
Note: This value is slightly smaller than the reference voltage v ref .
(c)
A major drawback of the weighted-resistor DAC is that the range of the resistance value in
the weighting circuit is very wide. This presents a practical difficulty, particularly when the
size (number of bits n) of the DAC is large. Use of resistors with widely different magnitudes
in the same circuit can create accuracy problems. For example, since the MSB corresponds to
the smallest weighting resistor, it follows that the resistors must have a very high precision.
_________________________________________________________________________
Solution 2.34
For an ADC,
Resolution: This is the change in analog input that corresponds to one LSB change in the
digital output.
Dynamic Range: This is the ratio of the span (maximum value - minimum value) to the
resolution, expressed in dB.
For an n-bit ADC, DR = 2n-1 as a ratio = 20 log 10 (2 n − 1) dB

Full-scale value: The value of the analog input corresponding to the maximum digital output
(i.e., when all the bits are at 1).
Quantization Error: Error introduced due to digitization of a sampled data value. This is
equal to: (Signal value corresponding to the digital output)-(Actual sampled value just
before conversion).
This error is less than one LSB. With rounding-off, this error is less than 1/2 LSB.
_________________________________________________________________________
Solution 2.35
(a) Dual-Slope ADC

A dual-slope ADC is based on timing (i.e., counting the number of clock pulses during) a
capacitor-charging process. It uses an RC integrating circuit. Hence, it is also known as an
integrating ADC. It is simple and inexpensive. In particular, an internal DAC is not utilized
and hence, DAC errors will not enter the ADC output. Furthermore, the parameters R and C in
the integrating circuit do not enter the ADC output. As a result, the device is self-
compensating in terms of circuit-parameter variations due to temperature, aging, so on. A
shortcoming of this ADC is its slow conversion rate because, for accurate results, the signal
integration has to proceed for a longer time in comparison to the conversion time for a
successive approximation ADC.
The principle of operation can be explained with reference to the integrating circuit
shown in Figure S2.35(a). Here, v i is a constant input voltage to the circuit and v is the output
voltage. Since the positive lead of the op-amp is grounded, the negative lead (and node A)
also will have zero voltage. In addition, the currents through the op-amp leads are negligible.
v dv
Hence, the current balance at node A gives i + C = 0 . Integrating this equation for
R dt
constant v i , we get
vt
v=
(t ) v(0) − i (i)
RC
Equation (i) is used in obtaining a principal result for the dual-slope ADC.
(a) Output
v vi
C Slope = −
RC
vi R - Output v
(Constant) A 0 Time t
+
CC SC
(b) Clock
Switching Control Control Logic Data Valid

Unit Signal
Analog C
Input
vs R
(From S/H) - Zero Output Digital
A Detect Output
+ Ti Register
-vref
Integrating
Circuit
Switching
Element
(c)
v
t1 t2 Time t
0
vc
(d)
SC
CC
Clock
Data Valid Signal

Comparator
Control Logic Output Digital
Unit Counter Register Output
Analog
Input Signal - Counting
(From S/H) Control Signal
DAC
Figure S2.35: (a) RC integrating circuit; (b) Dual-slope ADC; (c) Dual-slope charging–
discharging curve; (d) Counter ADC.
A schematic diagram for a dual-slope ADC is shown in Figure S2.35(b). Initially, the
capacitor C in the integrating circuit is discharged (zero voltage). Then, the analog signal v s
is supplied to the switching element and held constant by the S/H. Simultaneously, a control
signal “conversion start” is sent to the control logic unit. This clears the timer and the output
register (i.e., all bits are set to zero) and sends a pulse to the switching element to connect the
input v s to the integrating circuit. Also, a signal is sent to the timer to initiate timing
(counting). The capacitor C will begin to charge. Equation (i) is now applicable with input v i
= v s and the initial state v(0) = 0. Suppose that the integrator output v becomes −v c at time t =
t 1 . Hence, from Equation (i), we get
vt
vc = s 1 (ii)
RC
The timer will keep track of the capacitor charging time (as a clock pulse count n) and will
inform the control logic unit when the elapsed time is t 1 (i.e., when the count is n 1 ). Note: t 1
and n 1 are fixed (and known) parameters, but voltage v c depends on the value of v s , and is
unknown.
At this point, the control logic unit sends a signal to the switching unit, which will
connect the input lead of the integrator to a reference voltage of opposite polarity (a negative
supply voltage − v ref ). Simultaneously, a signal is sent to the timer to clear its contents and
start timing (counting) again. Now the capacitor begins to discharge. The output of the
integrating circuit is monitored by the zero-detect unit. When this output becomes zero, the
zero-detect unit sends a signal to the timer to stop counting. A comparator (differential
amplifier) with one of the two input leads set at zero potential may serve as the zero-detect
unit.
Now suppose that the elapsed time is t 2 (with a corresponding count of n 2 ). It should be
clear that Equation (i) is valid for the capacitor discharging process as well. Note: v i = −v ref
and v(0) = − v c in this case. Also, v(t) = 0 at t = t 2 . Hence, from Equation (i), we have
vref t2
0= −vc + , or
RC
vref t2
vc = (iii)
RC
t
On dividing Equation (ii) by Equation (iii), we get vs = vref 2 . However, the timer pulse
t1
t n
count is proportional to the elapsed time. Hence, 2 = 2 . Now we have
t1 n1
vref
vs = n2 (iv)
n1
Since v ref and n 1 are fixed quantities, v ref /n 1 can be interpreted as a scaling factor for the
analog input. Then, it follows from Equation (iv) that the second count n 2 is proportional to
the analog signal sample v s . Note: The timer output is available in the digital form.
Accordingly, the count n 2 is used as the digital output of the ADC.
At the end of the capacitor discharge period, the count n 2 in the timer is transferred to
the output register of the ADC, and the “data valid” signal is set. The contents of the output
register are now ready to be read by the interfaced digital system, and the ADC is ready to
convert a new sample.
The charging–discharging curve for the capacitor during the conversion process is
shown in Figure S2.35(c). The slope of the curve during charging is − v s /RC, and the slope
during discharging is +v ref /RC. The reason for the use of the term “dual slope” to denote this
ADC is therefore clear.
As mentioned before, any variations in R and C do not affect the accuracy of the output.
But, it should be clear from the foregoing discussion that the conversion time depends on the
capacitor discharging time t 2 (Note: t 1 is fixed), which in turn depends on v c and hence on
the input signal value v s (see Equation (ii)). It follows that, unlike the successive
approximation ADC, the dual-slope ADC has a conversion time that directly depends on the
magnitude of the input data sample. This may be considered as a disadvantage because in
many applications we prefer to have a constant conversion rate.
The foregoing discussion assumes that the input signal is positive. For a negative signal,
the polarity of the supply voltage v ref has to be changed. Furthermore, the sign has to be
properly represented in the contents of the output register as, for example, in the case of
successive approximation ADC.
(b) Counter ADC

The counter-type ADC has several aspects in common with the successive approximation
ADC. Both are comparison-type (or closed loop) ADCs. Both use a DAC unit internally to
compare the input signal with the converted signal. The main difference is that in a counter
ADC the comparison starts with the LSB and proceeds down. It follows that, in a counter
ADC, the conversion time depends on the signal level, because the counting (comparison)
stops when a match is made, resulting in shorter conversion times for smaller signal values.
A schematic diagram for a counter ADC is shown in Figure S2.35(d). Note that this is
quite similar to Figure 2.38 for the Successive approximation ADC. Initially, all registers are
cleared (i.e., all bits and counts are set to zero). As an analog data signal (from the S/H)
arrives at the comparator, an SC pulse is sent to the control logic unit. When the ADC is
ready for conversion (i.e., when data valid signal is on), the control logic unit initiates the
counter. Now, the counter sets its count to 1, and the LSB of the DAC register is set to 1 as
well. The resulting DAC output is subtracted from the analog input, by means of the
comparator. If the comparator output is positive, the count is incremented by one, and this
causes the binary number in the DAC register to be incremented by one LSB. The new
(increased) output of the DAC is now compared with the input signal. This cycle of count
incrementing and comparison is repeated until the comparator output becomes less than or
equal to zero. At that point, the control logic unit sends out a CC signal and transfers the
contents of the counter to the output register. Finally, the data valid signal is turned on,
indicating that the ADC is ready for a new conversion cycle, and the contents of the output
register (the digital output) is available to be read by the interfaced digital system.
The count of the counter is available in the binary form, which is compatible with the
output register as well as the DAC register. Hence, the count can be transferred directly to
these registers. The count when the analog signal is equal to (or slightly less than) the output
of the DAC, is proportional to the analog signal value. Hence, this count represents the
digital output. In bipolar operation, the sign of the input signal has to be properly accounted
for.
_________________________________________________________________________
Solution 2.36
Dual-slope (integrating) ADC: In this case, the conversion time is the total time needed to
generate the two counts n 1 and n 2 (see Figure S2.35(c). Hence,
tc = (n1 + n2 )∆t (i)
Note that n 1 is a fixed count. However, n 2 is a variable count, which represents the digital
output, and is proportional to the analog input (signal level). Hence, in this type of ADC,
conversion time depends on the analog input level. The largest output for an n bit converter is
2n−1. Hence, the largest conversion time may be given by
tc max = (n1 + 2n − 1)∆T (ii)
Counter ADC: For a counter ADC, the conversion time is proportional to the number of bit
transitions (1 LSB/step) from zero to the digital output n o . Hence, the conversion time is
given by
tc= no ∆t (iii)
where n o is the digital output value (in decimal). Note that for this ADC as well, t c depends
on the magnitude of the input data sample. For an n bit ADC, since the maximum value of n o
is 2n − 1, we have the maximum conversion time
tc max = (2n − 1)∆t (iv)

By comparing these results with that obtained for a successive-approximation ADC, it can be
concluded that the successive-approximation ADC is the fastest of the three types.
_________________________________________________________________________
Solution 2.37
(a) Direct-conversion ADC (Flash ADC): An n-bit digital word can represent 2n – 1
digital values, and each additional bit in the word multiplies this by a factor of 2. This
ADC, uses a bank of 2n – 1 comparators, each having a reference value corresponding
to one of these digital values. The analog signal is sampled into the comparators, in
parallel. A comparator fires its digital value if the sampled signal value matches it (to
less than half-bit accuracy). This is very fast and capable of gigahertz sampling rates
(Note: Comparison is done in parallel). Since the bit size increases the number of
comparators in an exponential manner, typically, this ADC is limited to 8 bits (to
reduce hardware costs and error).
(b) Ramp-compare ADC: This is similar to the dual-slope ADC. The main difference of
the present ADC is the use of a ramping signal instead of an integrator. Specifically,
it uses a saw-tooth signal that ramps and then quickly returns to zero. Clock counts
start as the ramping starts, and stops when the ramp voltage matches (as detected by a
comparator) the input signal (analog) value. The clock count gives a digital value,
which represents the analog data value. Note: The full-scale value (FSV) of the ADC
register corresponds to the reference value of the comparator voltage. can be properly
scaled using , a comparator fires, and the timer's value is recorded. An oscillator can
be used to generate the ramp signal. This ADC is relatively simple with regard to
hardware.
(c) Wilkinson ADC: In this ADC, the input voltage (analog data) is compared with that
produced by a charging capacitor. The capacitor is allowed to charge until its voltage
is equal to the amplitude of the input pulse (a comparator determines when this
condition has been reached), and it is discharged to zero. The charge-discharge times
are counted using a clock, and used to determine the corresponding digital value.
Hence, this approach is basically the same as that of a dual-slope (integrating) ADC.
(d) Delta-encoded ADC: It uses a counter, DAC, and a comparator (compare with other
ADCs that use similar hardware). The count is incremented and the resulting digital
value is fed into the DAC. The DAC output is compared with the incoming analog
data value. The count is stopped when the two values match (up to 1 count
increment). The corresponding digital input to the DAC is the output of the ADC.
Note: Here, “delta” denotes the count “increment,” which is essentially one LSB bit
value of the ADC (or DAC). The method is also called “delta-comparison.”
(e) Pipeline ADC: This uses an internal DAC (as with many other ADC methods) and is
somewhat similar to the successive-approximation ADC, but is faster. It uses two or
more steps of conversion, starting with a “coarse” conversion and ending with a
“fine” conversion. After the coarse conversion in the first step, the difference between
the analog input value and the DAC output value is then converted using a finer
ADC, in the next step. The digital results are combined in a last step.
(f) ADC with Intermediate FM Stage: This uses a voltage-to-frequency converter

(VFC or FM) and a frequency counter. First, the VFC is used to convert the analog
input signal into an oscillating signal with a frequency proportional to the analog
input (i.e., a frequency-modulated or FM signal). Next the frequency counter is used
to convert the frequency of the FM signal into a digital value, which is the output of
the ADC.
_________________________________________________________________________
Solution 2.38
Advantages:
• Small size
• More functions
• Capability to handle complex tasks
• Higher accuracy
• Faster speed
• Less power
• Less loading problems
• Low cost
• Easy interfacing with digital systems.
_________________________________________________________________________
Solution 2.39
Bridge δ vo % Nonlinearity
Equation for
vref
1. Constant voltage bridge δR / R δR
50
(4 + 2δR / R) R
2. Constant current bridge δR / R δR
25
(4 + δR / R ) R
3. Half bridge Rf δR / R δR
⋅ 100
R (1 + δR / R) R
Highest Intermediate Lowest

Nonlinearity and Bridge 3 Bridge 1 Bridge 2
Temperature Effects:
Cost: Bridge 2 Bridge 1 Bridge 1
(Regulated (Simple
Current Source) Circuitry)
Percentage error due to change in supply voltage:

 R f (δ R / R) R f (δ R / R) 
 R(1 + δ R / R) ( vref + δ vref ) −
R (1 + δ R / R)
vref  ×100
δv ref
  = × 100%
 R f (δ R / R)  v ref
 R (1 + δ R / R) vref 
 
For a 1% change in supply voltage, error = 1%.
_________________________________________________________________________
Solution 2.40
=
From equation (2.91) we get δvo
[(R + δR)R − R(R − δR)] v −0
(R + δR + R)(R − δR + R )
ref
δvo 2δR / R
This simplifies to = which is nonlinear.
vref 4 − (δR / R) 2
Similarly, it can be shown from equation (2.91) that the pair of changes: R 2 → R+δR and R 4
→ R-δR will result in a nonlinear relation that is the same as before, except for the change in
δvo −2δR / R
sign: =
vref 4 − (δR / R) 2
_________________________________________________________________________
Solution 2.41
=
From equation (2.98) we get δvo
[(R + δR)R − (R − δR)R ] iref − 0
(R + δR + R − δR + R + R )
δvo δR / R
On simplification we get the linear relation: =
Riref 2
If R 4 and R 3 are the active elements, with R 4 in tension and R 3 in compression, it is clear
from equation (2.98) that we get an identical linear result (not even a sign change).
_________________________________________________________________________
Solution 2.42
R1 R3
Starting with = = p , when R 1 is increased by δR 1 , the resulting change in the bridge
R2 R4
(R + δR1 ) / R2 − (R3 / R4 )
output (from zero) is given by δvo = 1 vref By direct substitution
[(R1 + δR1 ) / R2 +1](R3 / R4 +1)
pδ r
of δr = δR 1 /R 1 and simplification, we get δ vo = vref . For a given δr, the
[ p (1 + δ r ) + 1]( p + 1)
p
maximum value of δv o occurs when is a maximum, where α = 1+δr. The
(α p + 1)( p + 1)
maximum point of this expression is determined by differentiating it with respect to p and
equating to zero. We get, (α p + 1)( p + 1) ×1 − p[α p + 1 + α ( p + 1) =0
1 1
On simplification, we have 1 − α p 2 =
0 , or =p =
α 1+ δ r
Since δr is very small compared to 1, we note that the maximum sensitivity occurs when p is
almost equal to 1.
_________________________________________________________________________
Solution 2.43
1 1
= + jωC1 , Z 2 = R2 , Z 3 = R3 , Z 4 = R4 + jωL4
Z1 R1
Balanced condition: Z1 Z 4 = Z 2 Z 3  Z 4 = Z 2 Z 3 / Z1
R2 R3
Substitute: ( R4 + jωL4 ) = R2 R3 ( R1 + jωC1 ) and R4 + jω L4 = + jω C1 R2 R3
1 R1
R2 R3
Equate real parts and imaginary parts: R4 = and ωL4 = ωC1 R2 R3
R1
This gives: L4 = C1 R2 R3
Suppose that R1 and R2 are fine-adjustable. Balance the bridge by varying R2 and then R1 and
again by R2 and so on, in small steps. Then we will be able to determine C1 according to:
R R
C1 = 2 3
L4
and L4 according to: L4 = C1 R2 R3 .
_________________________________________________________________________
Solution 2.44
When the core is centrally located we have: L1 = L2 and vo will be sinusoidal with a zero
average value. When the core is displaced through x in one direction, the average output (vo)
will increase (+ve) in proportion to x and when displaced in the opposite direction the
average output will decrease (-ve) in proportion to x. Hence, the average output is a measure
of x. In a full bridge we use L1 and L2 in Figure P2.44 as two adjacent arms. Also, use two
identical external impedances for the remaining two arms.
This arrangement is shown in Figure S2.44. Then the output vo of the bridge will
behave as in the half-bridge case.
L1 L2 Bridge
Output
vo
L L
~
vref
Figure S2.44: A full-bridge LVDT circuit.
_________________________________________________________________________
Solution 2.45
δv o r δR
We have the bridge equation = with r =
v ref + αδv o 4 + 2r R
Then, 4δv o + 2rδv o = rv ref + αrδv o  δv o [4 + 2r − αr ] = rv ref

δv o r δR
Now, if α = 2 , we get = =
v ref 4 4R
This is linear.
_________________________________________________________________________
Solution 2.46
(a) Sensitivity
Bridge: Output voltage is zero under balanced conditions. Hence the signal directly gives
the “change” in the active strain gauges. Furthermore, we may use 4 active gauges to obtain
the maximum sensitivity. Cross-sensitivities will also balance out.
Pot: The initial output (i.e., when the strain gauges are not active) is not zero, and the change
in resistance of an active gauge is determined by the “change” in the output voltage. This
increment in the output can be masked by the comparatively high initial output voltage.
Furthermore, only one strain gauge is active. Cross sensitivity directly effects reading.
 Bridge circuit has much better sensitivity.
(b) and (c) Accuracy

Bridge: All four gauges drift by nearly the same amount (due to ambient temperature,
humidity, aging, etc.) and they balance out (assuming similar gauges). One resistor can be
used for fine adjustment. Also higher sensitivity means higher signal-to-noise ratio (SNR)
and better accuracy.
Pot: Measurements are affected by drift in the strain gauge and in the circuit itself, and
variations in the supply voltage vref . Since sensitivity is low, it can be affected more by
noise.  Bridge circuit provides better accuracy.
(d) Complexity and Cost: Bridge circuit has four resistors and the failure of one will cause
malfunction. Pot has only one active gauge and is usually more robust. Reliability of the
bridge is low in this sense. However, current through the bridge strain gauges is lower due to
the following: (i) Current is divided among two branches; (ii) Due to lower sensitivity in a
pot circuit, a higher supply voltage or a higher strain gauge current would be needed.
 Life expectancy of a bridge circuit would be higher.
(e) Linearity: In the operating range δ vo and δ R relation is acceptably linear for both
bridge and pot circuits. In a pot circuit, however, linearity tends to be less effective because
the voltage output under non-active conditions is not zero, and hence the “change” in the
output voltage has to be used for the relationship to be linear.
_________________________________________________________________________
Solution 2.47
vref − v A vA vref − v B v B v −v v
Bridge equations: =i+
(i); = − i (ii); i= A B = o (iii)
R2 R1 R4 R3 RL RL
vref 1 1 vref 1 1
(ii)  = v A ( + ) + i and (ii)  = vB ( + ) − i
R2 R1 R2 R4 R3 R4
Form vA – vB from the above two equations:
1 1 1 1 1 1 1 1 1 1 1 1 1 1
vref [ ( + )− ( + )] = ( + )( + )(v A − v B ) + i ( + + + )
R2 R3 R4 R4 R1 R2 R1 R2 R3 R4 R1 R2 R3 R4
Substitute (iii):
1 1 1 1 1 1 1 1 1 1 v 1 1 1 1
vref [ ( + ) − ( + )] = ( + )( + )vo + o ( + + + )
R2 R3 R4 R4 R1 R2 R1 R2 R3 R4 RL R1 R2 R3 R4
1 1 1 1 1 1
[ ( + )− ( + )]
R2 R3 R4 R4 R1 R2
 vo = v
1 1 1 1 1 1 1 1 1 ref
( + )( + ) + ( + + + )
R1 R2 R3 R4 RL R1 R2 R3 R4
Initially: R1 = R 2 = R 3 = R 4 = R ⇒ vo = 0
Next we have: R1 = R + δR ⇒ v o = δv o
 2 1 1 1 
 − ( + ) 
δv o =  R 2 R R + δR R  vref (iv)
( 1 + 1 ) 2 + 1 ( 1 + 3 )
 R + δR R R RL R + δR R 
Under open-circuit condition RL → ∞.
 2 1 1 1 
 R 2 − R ( R + δR + R ) 
Output δvo′ =   vref (v)
 ( 1 1 2 
+ )
 R + δR R R 
1 1 2
( + ) δv
δv o R + δR R R 1
From (iv) and (v): =  o =
δvo′ ( 1 1 2 1 1 3 ′
δvo (1 + ∆)
+ ) + ( + )
R + δR R R R L R + δR R
1 1 3 1
( + ) (3 + )
Where ∆ = RL R R R = + δ R 1 + δR / R
2 1 1 1
( + ) 2 RL (1 + )
R R + δR R 1 + δR / R
δR δv o R
With = 0.01 , we plot against L , in Figure S2.47.
R δvo′ R
δv o
δvo′
1
0.8
0.6
0.4
0.2
0 RL
0 1 2 3 4 5 6 7 8 9 10
R
Figure S2.47: Normalized output of abridge as a function of load resistance.
_________________________________________________________________________
Solution 2.48
 R1 R3 
From the bridge circuit we=
have: vo  −  vref (neglect load current)
 ( R1 + R2 ) ( R3 + R4 ) 
If R1 is changed to R1 + δ R1 we have
 R1 + δ R1 R3 R1 R3 
δ vo 
= − − +  vref
 ( R1 + δ R1 + R2 ) ( R3 + R4 ) ( R1 + R2 ) ( R3 + R4 ) 
 R1 + δ R1 R1   R +δ R 1
=  −  vref =
 2 R + δ R − 2  vref {R1 =
R2 =
R
 ( R1 + R2 + δ R1 ) ( R1 + R2 )   
δR
Hence, δ vo = vref
2 ( 2R + δ R )
( )
If we neglect 0 δR 2 terms compared to R we have: δ vo′ =
δR
4R
vref
δ R δR 
 − 
 %=
error
( δ v − δ vo
'
o
=
)
× 100  4R 2 ( 2R + δ R ) 
×100
δ vo δR
2 ( 2R + δ R )
 4 R + 2δ R  δR
= − 1 ×100 = ×100
 4R  2R
δR 0.05
For = 0.05 : % error = ×100% =2.5%
R 2
_________________________________________________________________________
Solution 2.49
Bridge sensitivity is determined by the output change for a unit change in one of the
resistances in the four arms of the bridge. Bridge sensitivity may be increased by increasing
the supply voltage ( vref ) and decreasing the arm resistance (say, by connecting two resistors
in parallel for each arm).
Input impedance R of the bridge (assuming load current is zero) is given by
1 1 1
= +
R R1 + R2 R3 + R4
2
vref  1 1  2
Power dissipation p= =
 p  +  vref
R  R1 + R2 R3 + R4 
2
vref
For the rest of the discussion, assume R=
1 R=
2 R=
3 R=
4 R  p= (i)
R
δ vo
Bridge sensitivity S b may be expressed as Sb =
δR
δ vo δR
Change R1 by δ R . Then, from the bridge equation = we have:
vref 4R
vref
Sb = (ii)
4R
1 p
Substitute (i) in (ii): Sb =
4 R
Note that Sb is limited by p, for a given R.
__________________________________________________________________________
Solution 2.50
 1 1  v 1 1
=
Bridge equation: vo  −  vref =⇒ o − ⇒
1 + R2 R1 1 + R4 R3  vref 1 + R2 R1 2
1 2vo + vref R2 2vref vref − 2 vo  v − 2vo 
= ⇒= = −1 ⇒ R1 = R2  ref  (i)
1 + R2 R1 2 vref R1 2vo + vref 2vo + vref  vref − 2vo 
It is clear from this result that: vo =0 ⇔ R1 =R2
For the circuit with long cables: New R1 is R1 + Rc and new R2 is R2 + Rc .

 vref + 2vo   vref + 2vo  vo
Then, from (i): R1 + Rc = ( R2 + Rc ) 
=  ⇒ R1 R2   + 4 Rc
 vref − 2vo   vref − 2vo  vref − 2vo 
vc
4 Rc
vref − 2vo  4 R  v 
=
The fractional error: e = c

o

 vref + 2vo  R2  vref + 2vo 
R2  
 vref − 2vo 
Note that e decreases with increasing R2 and vref.

_________________________________________________________________________
Solution 2.51
See Figure S2.51. Furnace temperature is compared with the threshold by the differential
amp. If the difference is negative, the diode circuit provides a zero current. If this difference
is positive, the diode circuit provides a proportional current. The current-to-voltage converter
converts this current into a voltage. The VFC converts this into a pulse signal whose
frequency is proportional to the input voltage. The counter counts the pulses. This count is
proportional to the frequency × time product and hence the temperature × time product. The
count, after properly scaled, is used by the on/off controller to turn off the furnace when the
specified value of Celsius-Minute reading is reached.
Signal Modification:
1. RTD circuit converts temperature into voltage
2. Differential amplifier obtains the difference of the furnace temperature and the
threshold, and amplifies it
3. The diode circuit converts the output of the difference amplifier into a proportional
current, while removing the negative values
4. The current-to-voltage converter converts this current into a voltage
5. The VFC converts voltage into a frequency signal
6. The counter provides a digital count of pulses.
Differential
Amplifier
Diode Circuit
Current to
Temperature Out
Furnace Voltage VFC Counter
Sensor (RTD) In Converter
−
On/Off Temp.
Control Threshold To
Temperature×Time (Degree-Minute) Value
Figure S2.51: Temperature control system for a furnace.

_________________________________________________________________________
Solution 2.52
(a) See Figure S2.52. The pulse sequence from the encoder is fed into a frequency-to-voltage
converter (FVC). This generates an analog signal proportional to the pulse frequency (i.e.,
plant speed).
Position
Analog Plant
Controller
Speed Signal
Incremental
FVC
Encoder
Figure S2.52: A position feedback control loop.
(b) The PWM signal is generated by the digital controller. The pulse amplitude is compatible
with the required voltage excitation level for the drive circuit of the dc motor. The average
signal is varied simply by varying the pulse width of the controller output.
_________________________________________________________________________
Solution 2.53
(a) Conductive Coupling

This allows through almost all types of noise. Grounding, shielding, and perhaps filtering
would be needed to reduce the noise.
(b) Inductive Coupling

Allows through ac noise and rejects dc noise (offsets, etc.). Electromagnetic interference
noise will pass through. Remove the magnetic flux noise (through a low-reluctance path) and
reduce flux linkage (e.g., by reducing the number of coil turns) in order to reduce inductively
coupled noise. High-frequency noise effects are usually less in this case.
(c) Capacitive Coupling

Allow through ac noise and rejects dc noise. High-frequency noise effects are more serious in
this case. Filter out high-frequency noise in order to reduce noise problems.
(d) Optical Coupling

Removes all types of noise except optical noise. Reduce optical noise or modulate the source
in order to reduce noise problems.
Method of Eliminating the Effect of Ambient Light

Modulate the source (by switching, strobing, or shuttering). Demodulate the signal (and
filter) at the photoreceiver.
_________________________________________________________________________
Solution 2.54
Advantages of Optical Coupling

1. Transmission is one way  No loading of the first circuit by changes in the second
circuit
2. Electromagnetic interference does not appear in the optical path
3. Coupling through bundles of optical fiber can be used safely in hazardous (e.g.,
explosive, chemical) environments
4. Large currents and voltages generated in one circuit (due to short-circuit, open-circuit
conditions, malfunctions, etc.) will not damage the other circuit, which might be more
delicate, critical, and costly. Note: When the signal is large, either the optical source
(LED) will saturate or the detector (photosensor) will saturate.
Advantages of Infrared over Visible Light

1. Large wave length  Less problems due to dust, dirt, moisture, etc.
2. Not affected by ambient light
3. Can be used for applications in the dark (security systems, etc.)
Advantages of Pulse Modulation

1. Frequency spectrum is shifted by high-frequency modulation. Hence it is not distorted
by low-frequency noise, which can be filtered out (including ambient light noise)
2. Power usage and thermal effects are reduced.
Advantages of Laser-based Systems

1. High intensity
2. Coherent (in phase) beams
3. Single wave length (monochromatic) light
4. Not very sensitive to ambient temperature changes
5. Very good coupling efficiency.
Disadvantages
1. Power supplies with high voltages would be needed
2. Short life span and stability
3. Possible eye hazards
4. High dynamic range  other devices (electronics) connected to the laser should have
comparable dynamic range  expensive, complex
5. More costly.
Beam vibration can be measured using the arrangement shown in Figure S2.54. The
measured frequency will determine the Young’s modulus E through the formula:
EI
ω = λ2
ρA
where,
ω = natural frequency of vibration
λ = modal parameter = 1.875104/l for the first mode of a cantilever beam
l = beam length
I = second moment of area of the beam cross-section about the neutral axis of bending
A = area of cross section of the beam
ρ = mass density of the beam material.
Reflective Surface
Light Source
Light Sensor
Clock
Frequency
Photo Sensor Timer
(Time for 10 pulses)

Figure S2.54: Determination of Young’s modulus by measuring beam vibration.
_________________________________________________________________________
Solution 2.55
Application: Water quality monitoring (e.g., in natural water sources from remote locations,
reservoirs, household).
Item Information
What parameters or variables have to be pH, turbidity/color, temperature, electrical conductivity
measured in your application?
Nature of the information (parameters and Signal conditioning of analog sensors using filters and
variables) needed for the particular amplifiers: analog signals. Digital sensors: digital.
application (analog, digital, modulated, Transmission: radio signals, modulated signals.
demodulated, power level, bandwidth, Processing in a digital computer for decision making:
accuracy, etc.) digital data.
Sensing: Hz to kHz; wireless transmission: MHz;
sampling: kHz
An overall accuracy of 1% would be adequate
List of sensors needed for the application pH sensor: , turbidity sensor, thermistor, conductivity
sensor
Signal provided by each sensor (type— pH sensor: Vernier, digital output (USB), 0-14 pH range
analog, digital, modulated, etc.; power with accuracy ±0.2 pH, time constant 1 s; turbidity
level; frequency range, etc.) sensor (optical): Vernier, 0-200 NTU range with
accuracy ±2 NTU, analog or digital; thermistor: Omega,
temperature range 0-100 ºC with accuracy ±0.2 ºC, time
constant 2.5 s; conductivity sensor: Campbell Scientific,
can measure both conductivity and temperature,
conductivity range 0.005 to 7.0 mS/cm, temperature
range -15to +50 ºC, conductivity accuracy ±5%, needs a
resistance bridge, analog output
Errors present in the sensor output (SNR, Sensor noise, environmental effects (temperature, dust,
etc.) humidity, etc.), drift and offset (calibration error), line
noise, information distortion and loss during
transmission, sampling errors, quantization errors
Type of signal conditioning or conversion Filtering, amplification, resistance bridge, modulation,
needed with the sensors (filtering, demodulation, S/H, MUX, ADC
amplification, modulation, demodulation,
ADC, DAC, voltage-frequency
conversion, frequency-voltage conversion,
etc.)
Any other comments SensorDAQ from Vernier, which can be used with NI
LabView software and multiple sensor interfaces (analog
and digital I/O) for data acquisition and processing by a
computer.
_________________________________________________________________________
SOLUTIONS MANUAL Courtesy of CRC Press/Taylor & Francis Group
FOR SENSORS AND ACTUATORS ENGINEERING
SYSTEM INSTRUMENTATION 2ND EDITION SILVA
1 0
R(0) F(0)
Component reliability R(t)
Unreliability F(t)
Design life
0 Td 1
Age t
Figure B.1 A typical reliability (unreliability) curve.
A002x001.eps
A and B
A
Figure B.2 Venn diagram illustrating the inclusion–exclusion formula.
A002x002.eps
β(t)
Failure rate
Rapid wearout
burn-in
Initial
Design life
0 Td t
Age
Figure B.3 A typical failure rate curve.
A002x003.eps
R(t)
Reliability
0 t
Age
Figure B.4 Reliability curve under constant failure rate.
A002x004.eps

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What are impedances in electrical and mechanical systems?

What are impedances in electrical and mechanical systems?

What are the differences between series and parallel connections of components?

What are the differences between series and parallel connections of components?

SOLUTIONS MANUAL FOR SENSORS AND ACTUATORS ENGINEERING SYSTEM

INSTRUMENTATION 2ND EDITION SILVA

SOLUTIONS MANUAL FOR SENSORS AND ACTUATORS ENGINEERING SYSTEM

Chapter 2 Component Interconnection and Signal Conditioning

1. Maximum power transfer

2. Power transfer at maximum efficiency

3. Reflection prevention in signal transmission

Some representative values of the curve are tabulated below.

Note: Performance improves with the impedance ratio Zi / Zs .

Open-circuit voltage at the output port is (in the frequency domain)

% Efficiency and load power curves

The two curves are plotted in Figure S2.5.

It is seen that maximum efficiency does not correspond to maximum power. In

Efficiency and Load Power Curves

(a) The input impedance of the amplifier = 500 MΩ.

Figure S2.8: Computation of local slopes.

To plot the Bode diagram using MATLAB, first note that:

% Plotting of transmissibility function

(a) Mechanical Loading

(b) Electrical Loading

Electrical loading can be reduced by using a low-output-impedance sensor, high-

Parameter Ideal Value Typical Value

Figure S2.12: Null compensation for an LVDT.

Figure S2.13: Monitoring of an industrial process using image processing.

(b) Data rate = 488 × 380 × 8 × 30 bits/s = 44.5 Megabits/s

Case 2: vip = 0 , vin= 5 µV  vi =0 − 5 µV =−5 µV

 vo =−5 × 5 ×106 µV =−25 V

(a) Offset Current (Typically in nA)

(b) Offset Voltage (Typically in mV or less)

(c) Unequal Gains (Can range over 105 to 109)

(d) Slew Rate (Typically about 0.5 V/µs)

Slew rate: s = 2πf b a (i)

Figure S2.20: An isolation amplifier.

The voltage follower is an impedance transformer. It reduces loading problems by providing

(a) Anti-aliasing filters in digital signal processing

(a) Low-pass Filtered Signal with Cut-off 2.0 rad/s

(c) Filtered Signal with Pass-band [9.0,11.0] rad/s

(d) Filtered Signal with Pass-band [8.0,12.0] rad/s

If a characteristic of a signal “B” is changed with respect to time, depending on some

(a) Amplitude Modulation (AM)

(b) Frequency Modulation (FM)

(c) Phase Modulation (PM)

(d) Pulse-width Modulation (PWM)

(e) Pulse-Frequency Modulation (PFM)

(f) Pulse-Code Modulation (PCM)

Peak frequencies = 900 ± 60 Hz =

(a) Phase-Sensitive Demodulation

(b) Half-Wave Demodulation

(c) Full-Wave Demodulation

Resolution corresponds to 1 LSB  10/ 28 = 10/256 = 0.04 V

For an n-bit ADC, DR = 2n-1 as a ratio = 20 log 10 (2 n − 1) dB

(a) Dual-Slope ADC

Switching Control Control Logic Data Valid

Data Valid Signal

(b) Counter ADC