Materials Today: Proceedings xxx (xxxx) xxx

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Materials Today: Proceedings

journal homepage: www.elsevier.com/locate/matpr

A 4x4 modified 8 T SRAM cell array using power gating technique

L. Saranya a,⇑, C. Arvind a, P. Karthigaikumar a, K. Balachander b
a
Department of ECE, Karpagam College of Engineering, Coimbatore, India
b
Department of EEE, Karpagam Academy of Higher Education, Coimbatore, India

a r t i c l e i n f o a b s t r a c t

Article history: Low power chip design is focused due to increase in demand of portable battery devices which is involved
Received 3 August 2020 in day to day life. The memory plays an important role in all silicon on chip devices. SRAM’s are most
Received in revised form 26 August 2020 widely used memory in the VLSI devices due to it’s better performance compared to DRAM. In Recent
Accepted 28 August 2020
years SRAM, plays a dominant part in chip design and becomes the crucial research due to the high
Available online xxxx
demand by the use of battery operated devices. To make the circuit more efficient the design should
be successively operated with low leakage power at sub-threshold regions. A modified 8 T SRAM cell is
Keywords:
designed and simulated using Tanner 13.1 EDA tool.
SRAM
Portable devices
Ó 2020 Elsevier Ltd. All rights reserved.
Low leakage power Selection and peer-review under responsibility of the scientific committee of the International
Battery devices Conference on Advances in Materials Research – 2019.
Performance
Sub threshold

1. Introduction throughput, low battery and Silicon on Chip (SoC) product. SRAM’s
are used in the applications of current embedded systems. SRAM’s
SRAM (static Random Access Memory) retains the data till the Occupies around 90 Percentage in the total memory design in the
supply of power continues in the circuit. But DRAM (Dynamic Ran- Silicon on Chip (SoC) [3]. To make the circuit more reliable many
dom Access memory) will be storing the bits in the cell. SRAM’s popular power reduction techniques has been employed. One of
need not be periodically refreshed unlike DRAM. Due to the the common techniques is that by reducing the power supply volt-
increase in the demand of portable gadgets, a power efficient age in the circuit [4] and SKLCT technique which enhances the
device occupies the majority role. During idle mode, the device speed of the device and consumes less power [5].The other power
should not dissipate large amount of power which will damage reduction techniques includes Dual Threshold voltage, MTCMOS.
the whole device contributing to the leakage power in the circuit. Dynamic Voltage Scaling, Power gating [13] using Sleep transistors
In recent submicron technology, Scaling is one of the major param- [6].
eter leading to the total power dissipation in the semiconductor The SRAM’s in mobile application’s which is streaming High
industry [1]. Definition videos and Pictures; motion videos are mainly depen-
The major component in every memory design is SRAM. When dent on low power with high memory design. Due to these crite-
the power consumption is decreased in the memory design, it con- ria’s the battery life should be extended for better experience
tributes to the overall power reduction in the circuit. A memory with the VLSI technology [7].The device should be made to operate
design should be power and energy efficient, low power consump- in deep sub-threshold region with better stability and power[12].
tion and high stable. Due to integration of SRAM with CMOS tech-
nology results in large area consumer in the Silicon on Chip (SoC)
unlike DRAM. The total energy consumption in the SRAM array 2. 8 T SRAM cell
can be calculated by the adding the number of times the cell has
switched and amount of leakage exists in the device [2]. The dom- Low power consumption in SRAM cell is obtained by using dif-
ination of VLSI devices in the electronic industries results in high ferent optimization techniques, one among the logic is power gat-
ing technique. The design is placed in-between the Power gating
logic [8]. By using the logic, direct connection between VDD and
⇑ Corresponding author. GND is neglected; thereby a virtual VDD and GND path is pro-
E-mail address: [email protected] (L. Saranya). duced. The implementation of 8TSRAM cell [9] is shown in Fig. 1.

https://doi.org/10.1016/j.matpr.2020.08.746
2214-7853/Ó 2020 Elsevier Ltd. All rights reserved.
Selection and peer-review under responsibility of the scientific committee of the International Conference on Advances in Materials Research – 2019.

Please cite this article as: L. Saranya, C. Arvind, P. Karthigaikumar et al., A 4x4 modified 8 T SRAM cell array using power gating technique, Materials Today:
Proceedings, https://doi.org/10.1016/j.matpr.2020.08.746
L. Saranya, C. Arvind, P. Karthigaikumar et al. Materials Today: Proceedings xxx (xxxx) xxx

Fig. 1. 8 T SRAM Cell.

Fig. 2. 2:4 Decoder.

3. Row decoder der will be very efficient because of its layout. In each row, a deco-
der with a dynamic NOR gate is designed. It consists of NN NMOS
The Row decoder is NOR based 2:4 Decoder. The word line is transistors connected in parallel, where NN represents the number
selected based on inputs given to the decoder. The designed deco- of address lines which has to be decoded. The NOR is a NOT-AND

2
L. Saranya, C. Arvind, P. Karthigaikumar et al. Materials Today: Proceedings xxx (xxxx) xxx

Fig. 3. Write Driver Circuit.

Fig. 4. Precharge Circuit.

logic, the gate of NMOS transistor will be either the true or comple- the data will not be written. In the memory cell, only one Write
ment value of one address bit. driver circuit is required for one column in the cell. Therefore by
In decoder, it takes n-bit binary number as an input and gener- increasing the number of transistors, the speed of the circuit
ates 2n output lines. Classic decoder Integrated Circuit’s consist of increases and it is controlled by Write control circuit (Fig. 3).
two 2–4 line circuits, 3–8 line circuit, or a 4–16 line decoder circuit.
The 4–10 line decoders can be excluded, designed to modify a Bin-
ary Coded Decimal (BCD) input to 0–9 range of output. If this is
5. Pre-charge circuit
employed in the circuit as a decoder, there exists the need to insert
data latches at the outputs. The Fig. 2 shows the schematic diagram
With the help of precharge circuit, the RBL line is charged to
of 2:4 Decoder.
VDD. The read operation is carried out and the output obtained will
be given to the sense amplifier. A precharge circuit consists of a
4. Write driver circuit precharge time controller to generate the precharge time control
signal based on a threshold voltage of a transistor; a precharge
Write driver circuits provide the data which is the input to the control signal generator for generating a precharge control signal
bit lines. The circuit is controlled by the Write Enable (WE) signal. activated during a predetermined period; and a pre-charger for
Whenever WE = 1 (High), the data will be written in to the cell else pre-charging a bit line.
3
L. Saranya, C. Arvind, P. Karthigaikumar et al. Materials Today: Proceedings xxx (xxxx) xxx

Fig. 5. Sense Amplifier.

Fig. 6. 4x4 Modified 8 T SRAM Cell.

Since the pass transistors are NMOS, the bit lines are pulled bit lines as low and let them pull up through the NMOS and they
HIGH and allow them to discharge. Therefore, they pass a very can start the bit lines high and pull down through the NMOS
solid ’0’ but they pass a degraded ’1’. So, rather than to start the (Fig. 4).

4
L. Saranya, C. Arvind, P. Karthigaikumar et al. Materials Today: Proceedings xxx (xxxx) xxx

Fig. 7. Waveform for 4X4 modified 8 T SRAM cell.

Fig. 8. 2:4 Decoder.

6. Sense amplifier sands of identical sense amplifiers will be present in a modern

memory chip [11] (Fig. 5).
The key component in the read circuitry is sense amplifier,
which is used to read the data from the memory. It will sense all 7. Results and discussions
the signals from a bit line data to be either high or low, and amplify
the low voltage swing to desirable levels providing faster read The schematic Diagram for 4X4 modified 8 T SRAM cell is
operation[10]. The number of sense amplifiers can be minimized shown in Fig. 6.
with the help of column multiplexing. The sense amplifier can be The Waveform for 4X4 modified 8 T SRAM cell is shown in
controlled by using Sense Enable (SE) and it will be pulled high Fig. 7.
whenever read operation has to be done. One sense amplifier is The Fig. 8 shows the waveform for 2:4 decoder circuit.
provided for each column in memory cells, so hundreds or thou- The Fig. 9 shows the waveform for Write Driver circuit.
5
L. Saranya, C. Arvind, P. Karthigaikumar et al. Materials Today: Proceedings xxx (xxxx) xxx

Fig. 9. Waveform for Write Driver circuit.

Fig.10. Waveform for Precharge Circuit.

Fig. 11. Waveform for Sense amplifier circuit.

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L. Saranya, C. Arvind, P. Karthigaikumar et al. Materials Today: Proceedings xxx (xxxx) xxx

The Fig. 10 shows the waveform for Precharge circuit References

The Fig. 11 shows the waveform for Sense Amplifier circuit
[1] Swati S. Kumar, Gaurav Soni, Power, Energy and SNM Optimization of
6TSRAMCell using Power Gating Technique, IEEE, doi: 10.1109/CSNT.2015.133.
8. Conclusion [2] Akshay Bhaskar, Design and Analysis of Low Power SRAM Cells, International
Conference on Innovations in Power and Advanced Computing Technologies [i-
PACT2017].
The 4X4 8 T SRAM Cell array has been designed with the exiting
[3] Rajani Suthar, Kirti S. Pande, N.S. Murty, Leakage Reduction in DT8T SRAM Cell
8 T SRAM Cell. In addition to the 8 T SRAM cell, the internal circuits using BodyBiasing Technique, in: 2017 IEEE International Symposium on
involving 2:4 Decoder, precharge circuit, write driver circuit, sense Nanoelectronic and Information Systems.
amplifier circuits has been designed and simulated in this paper. [4] Neha Sharma, Rajeevan Chandel, Performance Analysis of SRAM Cell Designed
using Floating Gate MOS, International Conference on Inventive
The simulation is done by using Tanner 13.1 EDA tool. Communication and Computational Technologies (ICICCT 2017).
[5] S. Pousia, R. Manjith, Design of Low Power High Speed SRAM Architecture
using SK-LCT Technique, in: Proceeding of 2018 IEEE International Conference
CRediT authorship contribution statement on Current Trends toward Converging Technologies, Coimbatore, India.
[6] H.P. Rajani, S.Y. Kulkarni, High Performance Multi-Mode SRAM Cells, in:
L. Saranya: . C. Arvind: Methodology. P. Karthigaikumar: . K. Proceedings of International Conference on Circuits, Communication, Control
and Computing (I4C 2014).
Balachander: Validation.
[7] Neha Raghav, Dr. Malti Bansal, Analysis of Power Efficient 6-T SRAM Cell with
Performance Measurements.
Declaration of Competing Interest [8] L. Saranya, C. Dr, Arvind,, A Novel 8t Sram Cellwith Reduction In Power Using
Power Gating Technique, Test Eng. Manag. 82 (2020.).
[9] Hiroyuki Yamauchi, A Discussion on SRAM Circuit Design Trend in Deeper
The authors declare that they have no known competing finan- Nanometer-Scale Technologies, IEEE Trans. VLSI Syst. 18 (5) (2010) 763–774.
cial interests or personal relationships that could have appeared [10] Chua-Chin Wang, Deng-Shain Wang, Chiang-Hsiang Liao, Sih-Yu Chen, A
to influence the work reported in this paper. Leakage Compensation Design for Low Supply Voltage SRAM, IEEE
Transactions On Very Large Scale Integration (VLSI) SYSTEMS, 1063-8210 Ó
2015 IEEE.
Acknowledgements [11] Anh-Tuan Do, Zhi-Hui Kong, Kiat-Seng Yeo, Jeremy Yung Shern Low, Design
and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-
Power SRAM, IEEE Trans. VLSI Syst. 19 (2) (2011) 196–204.
We thank the authors of referees for their useful suggestions [12] A. Wang, B.H. Calhoun, A.P. Chandrakasan, Sub-Threshold Designfor Ultra Low-
which helped us to proceed further in our research. We also thank Power Systems, Springer-Verlag, New York, NY, USA, 2005.
our management, Principal Dr. P. Vijayakumar and Head of the [13] Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Design
Techniques and Architectures for Low-Leakage SRAMs, IEEE Trans. Circuits
Department Dr. P. Krathigaikumar for their support towards the Syst. I 59 (9) (2012) 1992–2007.
research and guidance all the time.