Standard for RealTek DVD Recordable

Date: 2013-02-22

Kylin USB3.0
RealTek specification on DVD Recordable Technology

Specification for Kylin: USB3.0 Specification

Warning

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This document is not a DVD Standard. It is distributed for review and comment. It is subject to
change without notice and may not be referred to as a DVD Standard. Recipients of this

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document are invited to submit, with their comments, notification of any relevant patent rights of
which they are aware and to provide supporting documentation. Distribution does not constitute

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publication.

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DVD R1 Architecture Specification 1

1.1 REGISTER:: WRAP_CTR_reg 0x9801_3200

Module::usb Register::WRAP_CTR Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3200

Name Bits R/W Default Comments
Rvd 31..7 - - -
rxdetect_value 6 R/W „b0
rxdetect_sel 5 R/W „b0
resume_cycle_sel 4 R/W „b0
sram_debug_sel 3 R/W „b0 Select sram
1: host

i
0: device
sram_debug_mode 2 R/W „b0 Enable sram debug mode
dbus_multi_req_disable 1 R/W ‟b0 Disable multiple request for Dbus

P
0: enable multiple request
1: disable multiple request
dev_mode 0 R/W ‟b0 Enable peek on AHB burst length
0: host (2)
1: host/dev

1.2 REGISTER:: GNT_INT_reg

Module::usb Register::GNR_INT Set::1

n a
ATTR::nor Type::SR
0x9801_3204

ADDR::0x9801_3204

a
Name Bits R/W Default Comments
Rvd 31..2 - - -
device_int 1 R „b0 USB3 Device MAC interrupt

n
host_int 0 R „b0 USB3 Host MAC interrupt

1.3 REGISTER:: USB2_PHY_UTMI 0x9801_3208

Rvd
Name

reset_utmi_p0

1.4
B a
Module::usb Register::USB2_PHY_UTMI Set::1
Bits
31..1
0

REGISTER:: USB3_PHY_PIPE
R/W
-
R/W
ATTR::ctrl
Default
-
„b0
Type::SR

-
ADDR::0x9801_3208
Comments

UTMI reset to PHY1 (sync and

automatically return to low)

0x9801_320c

Module::usb Register::USB3_PHY_PIPE Set::1 ATTR::ctrl Type::SR ADDR::0x9801_320c

Name Bits R/W Default Comments
Rvd 31..1 - - -
reset_pipe3_p0 0 R/W „b0 PIPE3 reset to PHY1 (sync and
automatically return to low)

1.5 REGISTER:: MDIO_CTR_reg 0x9801_3210

DVD R1 Architecture Specification 2

Module::usb Register::MDIO_CTR Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3210
Name Bits R/W Default Comments
data 31..16 R/W „h0 Write data or read data.
phy_addr 15..13 R/W „d0 MDIO PHY addressing value.
phy_reg_addr 12..8 R/W „d0 MDIO Register addressing value
mdio_busy 7 R/W „d0 -
mdio_st 6..5 R/W „d0 MDIO host controller state Monitor
mdio_rdy 4 R/W „d0 MDIO Pre-amble signal Monitor
mclk_rate 3..2 R/W „d0 MDIO clock rate selection:
2‟b00: clk_sys/32
2‟b01: clk_sys/16
2‟b10: clk_sys/8
2‟b11: clk_sys/4

i
mdio_srst 1 R/W „d0 Assert 1‟b1 to do soft reset
mdio_rdwr 0 R/W „d0 1‟b0: read , 1‟b1: write

1.6 REGISTER:: VSTATUS_port0_reg

P 0x9801_3214

a
Module::usb Register::VSTATUS0_OUT Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3214
Name Bits R/W Default Comments

n
Rvd 31..8 - - -
p0_vstatus_out 7..0 R/W ‟h00 Vstatus output for port1 (It‟s used to
configure PHY‟s control register)

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The process of configuring PHY control register:
1. write VSTATUS_reg (0x9801_3214), (data output to PHY)
2. write GUSB2PHYAccn (0x1802_8280)

a
[25]: vload
[23]: vBusy
[11:8]: vcontrol

B
[7:0]: vstatus_in (data input from PHY)

DVD R1 Architecture Specification 3

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3. polling [23]: vBusy, if [23]=0, then vstatus_in is valid
Example for RealTek PHY:
Vcontrol[3]: low/high address, 0: low, 1: high
Vcontrol[2:0]: address
The control address in RealTek PHY is 6 bits, so it needs to send 2 vcontrol address. For
example, vcontrol=1110 (high address) and 0000 (low address) means 110000=0x30.

1.7 REGISTER:: SLP_BACK_EN_port0_reg 0x9801_3218

Module::usb Register::SLP_BACK0_EN Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3218

Name Bits R/W Default Comments

DVD R1 Architecture Specification 4

Rvd 31..4 - - -
simulation_mode_p0 3 R/W „b0 Reduce counter for entering HS
force_hs_mode_p0 2 R/W „b0 Force HOST IP enter high speed
mode
0: disable
1: enable
test_rst_p0 1 R/W „b0 Self loop back reset
test_en_p0 0 R/W „b0 Self loop back enable

1.8 REGISTER:: SLP_BACK_CTR_port0_reg 0x9801_321c

Module::usb Register::SLP_BACK0_CTR Set::1

Rvd
Name

test_speed_p0
Bits
31..12
11..10
R/W
-
R/W
ATTR::ctrl
Default
-
„h0
Type::SR

P i
ADDR::0x9801_321c
Comments

When Self_loop_back, force PHY

enter High Speed or Full Speed
mode

a
(HS: utmi_xver_select=0,
utmi_term_select[1:0]=00)
(FS: utmi_xver_select=1,

n
utmi_term_select[1:0]=01,
FsLsSerialMode=0)
2‟b01: force PHY in HS

a
2‟b10: force PHY in FS/LS
2‟b00/2‟b11: normal mode
„h0

n
test_seed_p0 9..2 R/W Self_loop_back
Random generator seed
test_psl_p0 1..0 R/W „h0 Select self_loop_back pattern

a
00: all zeros
01: load from seed
10: pseudo random pattern

B
11: incremental counter

1.9 REGISTER::SLP_BACK_ST_port0_reg 0x9801_3220

Module::usb Register::SLP_BACK0_ST Set::1 ATTR::nor Type::SR ADDR::0x9801_3220

Name Bits R/W Default Comments
Rvd 31..2 - - -
test_fail_p0 1 R „b0 Self loop back fail
test_done_p0 0 R „b0 Self loop back done

Slef_loop_back procedure:
(1) Configure PHY as self_loop_back mode (by vloadM interface)
R/W 38 F0 DBNC_E DISCON_E EN_ERR_UN LATE_DL INTG SOP_KK SLB_INNER SLB_EN

DVD R1 Architecture Specification 5

 N NABLE DERRUN LEN
1 1 1 1 1 1 0: digital & 1
analog
1: digital only

(2) set test_psl, test_seed and test_speed

(3) set test_rst=1 & test_en=0 (reset)
(4) set test_rst=0 & test_en=0 (reset)
(5) set test_rst=0 & test_en=1 (enable)
(6) polling test_done
(7) check test_fail

Force MAC to enter High-Speed procedure:

(1) In simulation mode: force_hs_mode=1 & simulation_mode=1
(2) In non-simulation mode (don‟t reduce counter): force_hs_mode=1 &
simulation_mode=0
(3) In normal mode: force_hs_mode=0 & simulation_mode=0
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1.10 REGISTER:: PHY2_SLB0_EN_reg

n a 0x9801_3224

a
Module::usb Register::PHY2_SLB_EN Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3224
Name Bits R/W Default Comments
Rvd 31..2 - - -

n
p0_usb2phy_slb_hs 1 R/W „b0 Usbphy port0 self loop back hs
mode
p0_usb2phy_force_slb 0 R/W „b0 Usbphy port0 self loop back start

Module::usb

Rvd
Name

p0_usb2phy_slb_fail
p0_usb2phy_slb_done
B a
1.11 REGISTER:: PHY2_SLB0_ST_reg

Register::PHY2_SLB_ST
Bits
31..2
1
0
R/W
-
R
R
Set::1 ATTR::nor
Default
-
„b0
„b0
Type::SR

-
0x9801_3228

ADDR::0x9801_3228
Comments

Usbphy port0 self loop back done

Usbphy port0 self loop back fail

1.12 REGISTER:: USB2_SPD_CTR 0x9801_322C

Module::usb Register::USB2_SPD_CTR Set::1 ATTR::ctrl Type::SR ADDR::0x9801_322c

Name Bits R/W Default Comments
Rvd 31..1 - - -
p0_suspend_r 0 R/W ‟b0 -

DVD R1 Architecture Specification 6

1.13 REGISTER:: USB3_ SLB_EN_reg 0x9801_3230

Module::usb Register:: PHY3_SLB_EN Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3230

Name Bits R/W Default Comments
Rvd 31..3 - - -
p0_pipe_bist_sel 2..1 R/W „b0 Self loop back select:
00:counter
01:tseq
10:ts1
11:ts2
p0_pipe_bist_en 0 R/W „b0 Self loop back enable

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1.14 REGISTER:: PHY3_ SLB_CT_reg 0x9801_3234

P
Module::usb Register::PHY3_SLB_CT Set::1 ATTR::nor_up Type::SR ADDR::0x9801_3234
Name Bits R/W Default Comments
Rvd 31..1 - - -
p0_usb3phy_slb_go 0 R/W „b0 Usb3phy port0 self loop back start
transfer

1.15 REGISTER:: PHY3_ SLB_ST_reg

Module::usb Register::PHY3_SLB_ST Set::1

n a
ATTR::nor_up Type::SR
0x9801_3238

ADDR::0x9801_3238

a
Name Bits R/W Default Comments
Rvd 31..2 - - -
„b0

n
p0_usb3phy_slb_fail 1 R Usb3phy port0 self loop back done
p0_usb3phy_slb_done 0 R „b0 Usb3phy port0 self loop back
enable

Rvd
Name B a
1.16 REGISTER:: USB_DBG_reg

Module::usb Register::USB_DBG
Bits
31..13
Set::1
R/W
-
ATTR::ctrl
Default
-
Type::SR

-
0x9801_3240

ADDR::0x9801_3240
Comments

dbg_sel1 12..7 R/W „b0 Select debug signal sets to be

probed via usb_dbg_out1
dbg_sel0 6..1 R/W „b0 Select debug signal sets to be
probed via usb_dbg_out0
dbg_en 0 R/W „b0 Debug enable
When set, selected signals can be
probed via debug ports. When clear,
both usb_dbg_out0 and
usb_dbg_out1 are static 16‟h0.

DVD R1 Architecture Specification 7

1.17 REGISTER:: USB_STCH_reg 0x9801_3244

Module::usb Register::USB_SCTCH Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3244

Name Bits R/W Default Comments
reg1 31..16 R/W „hffff Dummy register with value 1
reg0 15..0 R/W „d0 Dummy register with value 0

1.18 REGISTER:: USB_TMP_SP_reg _0 0x9801_3248

Module::usb Register::USB_TMP_SP Set::1 ATTR::nor Type::SR ADDR::0x9801_3248

Name Bits R/W Default Comments

i
test_sp_reg_0 31..12 R/W „d0 Dummy test register
int_inact_status 11 R/W „d0 ltssm change to ss inactive state
int_ss_dis_status 10 R/W „d0 ltssm change to ss disabled state

P
int_hreset_status 9 R/W „d0 ltssm change to hot reset state
int_recov_status 8 R/W „d0 ltssm change to recovery state
int_rx_det_status 7 R/W „d0 ltssm change to rx detect state
int_poll_status 6 R/W „d0 ltssm change to polling state
int_u3_status 5 R/W „d0 ltssm change to u3 state

a
int_u2_status 4 R/W „d0 ltssm change to u2 state
int_u1_status 3 R/W „d0 ltssm change to u1 state
int_u0_status 2 R/W „d0 ltssm change to u0 state

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int_loopbk_status 1 R/W „d0 ltssm change to loopback state
int_comp_status 0 R/W „d0 ltssm change to compliance state

a
1.19 REGISTER:: USB_TMP_SP_reg_1 0x9801_324C

n
Module::usb Register::USB_TMP_SP Set::1 ATTR::nor Type::SR ADDR::0x9801_3248
Name Bits R/W Default Comments

a
test_sp_reg_1 31..0 R/W „d0 Dummy test register

B
1.20 REGISTER:: USB_TMP_reg 0x9801_3250

Module::usb Register::USB_TMP Set::3 ATTR::ctrl Type::SR ADDR::0x9801_3250

Name Bits R/W Default Comments
test_reg 31..0 R/W „d0 Dummy test register

DVD R1 Architecture Specification 8

1.21 REGISTER:: USB_TMP_reg_3 0x9801_325C

Module::usb Register::USB_TMP Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3250

Name Bits R/W Default Comments
test_reg_3 31..13 R/W „d0 Dummy test register
int_inact_en 12 R/W „d0 ltssm change to ss inactive state
interrupt enable
int_ss_dis_en 11 R/W „d0 ltssm change to ss disable state
interrupt enable
int_hreset_en 10 R/W „d0 ltssm change to hot reset state
interrupt enable
int_recov_en 9 R/W „d0 ltssm change to recovery state
interrupt enable

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int_rx_det_en 8 R/W „d0 ltssm change to rx detect state
interrupt enable
„d0

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int_poll_en 7 R/W ltssm change to polling state
interrupt enable
int_u3_en 6 R/W „d0 ltssm change to u3 state interrupt
enable
int_u2_en 5 R/W „d0 ltssm change to u2 state interrupt
enable

a
int_u1_en 4 R/W „d0 ltssm change to u1 state interrupt
enable
int_u0_en 3 R/W „d0 ltssm change to u0 state interrupt

n
enable
int_loopbk_en 2 R/W „d0 ltssm change to loopback state

a
interrupt enable
int_comp_en 1 R/W „d0 ltssm change to compliance state
interrupt enable

n
Rvd 0 - - -

a
1.22 REGISTER:: USB_HMAC_CTR0_reg 0x9801_3260

B
Module::usb Register::HMAC_CTR0 Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3260
Name Bits R/W Default Comments
Rvd 31 - - -
host_ utmiotg_vbusvalid 30 R/W „b1 -
host_fladj_30mhz 29..24 R/W „d32 -
host_ppc_present 23 R/W „b0 -
host_msi_enable 22 R/W „b0
host_pm_pw_state_req 21..20 R/W „b0
hub_port_over_current 19..16 R/W „b0
Rvd 15..14 - - -
hub_port_perm_attach 13..12 R/W „b0
Rvd 11..10 - -
host_u2_port_disable 9 R/W „b0
host_u3_port_disable 8 R/W „b0
host_num_u2_port 7..4 R/W „d1
host_num_u3_port 3..0 R/W „d1

DVD R1 Architecture Specification 9

1.23 REGISTER:: MAC3_HST_ST_reg 0x9801_3264

Module::usb Register::MAC3_HST_ST Set::1 ATTR::nor Type::SR ADDR::0x9801_3264

Name Bits R/W Default Comments
Rvd 31..4 - - -
host_current_power_state 3..2 R „b0 Current xHC power state
host_hub_vbus_ctrl 1..0 R „b0 Vbus active indication

1.24 REGISTER::DMAC_CTR0_reg 0x9801_3268

Module::usb Register::DMAC_CTR0 Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3268

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Name Bits R/W Default Comments
Rvd 31..27 - - -
xhc_bme 26 R/W „b1

P
dev_vbus_value 25 R/W „b0
dev_utmiotg_vbusvalid 24 R/W „b0
dev_pm_pw_state_req 23..22 R/W „b0
dev_fladj_30mhz 21..16 R/W „d32
dev_usb_outep_pkt_buff 15..0 R/W „hffff

1.25 REGISTER:: MAC3_DEV_ST_reg

Module::usb Register::MAC3_DEV_ST Set::1

n a
ATTR::nor Type::SR
0x9801_326C

ADDR::0x9801_326c

a
Name Bits R/W Default Comments
Rvd 31..2 - - -

n
dev_current_power_state 1..0 R „b0 Current xHC power state

Module::usb

Rvd
Name

p0_by_pass_on_0
p0_DmPulldown
p0_DpPulldown
B a
1.26 REGISTER:: USB2_PHY_reg

Register::USB2_PHY
Bits
31..12
11
10
9
R/W
-
R/W
R/W
R/W
Set::1 ATTR::ctrl Type::SR
Default
-
„b0
„b0
„b0
-
isolation AD
Device = 1‟b0
Device = 1‟b0
Comments
0x9801_3270

ADDR::0x9801_3270

p0_IDPULLUP 8 R/W „b0 Device = 1‟b0

Rvd 7..3 - - -
p0_DmPulldown_sel 2 R/W „b0 p0_dmpulldown =~dev_mode ? 1‟b1:
p0_DmPulldown_sel ?
p0_DmPulldown : 1‟b0
p0_DpPulldown_sel 1 R/W „b0 p0_dppulldown =~dev_mode ? 1‟b1:
p0_DpPulldown_sel ?
p0_DpPulldown : 1‟b0
p0_IDPULLUP_sel 0 R/W „b0 p0_dmpulldown =~dev_mode ? 1‟b1:
p0_IDPULLUP_sel ?
p0_IDPULLUP : 1‟b0

DVD R1 Architecture Specification 10

1.27 REGISTER:: USB_RAM_CTR_reg 0x9801_3274

Module::usb Register::RAM_CTR Set::1 ATTR::nor_up Type::SR ADDR::0x9801_3274

Name Bits R/W Default Comments
Rvd 31..17 - - -
done_st 16 R/W „b0 Write 1 to clear
Rvd 15..1 - - -
go_ct 0 R/W „b0 Start DMA transfer, clear after done

1.28 REGISTER:: USB_RAM_ADDR_reg 0x9801_3278

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Module::usb Register::RAM_ADDR Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3278
Name Bits R/W Default Comments
sram_addr 31..0 R/W „d0 SRAM address, 4-byte align.

P
Bit[0]= use for write/read bit
0: read
1: write

a
1.29 REGISTER:: USB_RAM_WDATA_reg 0x9801_327C

n
Module::usb Register::RAM_WDATA Set::1 ATTR::ctrl Type::SR ADDR::0x9801_327C
Name Bits R/W Default Comments
ram_wdata 31..0 R/W „d0 RAM write data to be write

1.30 REGISTER:: USB3_RAM_RDATA_reg

n a 0x9801_3280

a
Module::usb Register::RAM_RDATA Set::1 ATTR::nor_up Type::SR ADDR::0x9801_3280
Name Bits R/W Default Comments
ram_rdata 31..0 R/W „d0 USB read data to be read back

Module::usb

Rvd
Name

p0_count_num
B
1.31 REGISTER:: USB3_PHY0_ST_reg

Register::PHY0_ST
Bits
31..19
18..0
R/W
-
R
Set::1 ATTR::nor
Default
-
„b0
Type::SR

-
0x9801_3284

ADDR::0x9801_3284
Comments

USB3 PHY count number value

1.32 REGISTER:: USB3_OVR_CT_reg 0x9801_3288

Module::usb Register::USB3_OVR_CT Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3288

Name Bits R/W Default Comments
Rvd 31..2 R/W - -
phy3_lperiod 9..7 R/W „d1 Connect to PHY3
phy3_hperiod 6..4 R/W „d3 Connect to PHY3

DVD R1 Architecture Specification 11

phy3_last 3..2 R/W „d2 Connect to PHY3
host_ovr_current_value 1 R/W „b0
host_ovr_current_sel 0 R/W „b0

Host MAC register

1.33 REGISTER:: SOFT_Reset 0x9801_3300

Module::usb Register::SOFT_RESET Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3300

Name Bits R/W Default Comments
Rvd 31..3 - - -

i
rstn_usb2_phy1 2 R/W „b0 USB2 PHY1 reset for USB2 IP
rstn_usb2_phy0 1 R/W „b0 USB2 PHY0 reset for USB2 IP
rstn_usb2 0 R/W „b0 USB2 IP system reset

1.34 REGISTER:: GBL_USB_CT

P 0x9801_3304

a
Module::usb Register::GBL_USB_CT Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3304
Name Bits R/W Default Comments
usb_mac_ctrl 31..0 R/W „d0 Register use for usb_mac_ctrl

1.35 REGISTER:: GBL_USB_ARB

a n 0x9801_3308

n
Module::usb Register::GBL_USB_ARB Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3308
Name Bits R/W Default Comments

a
Rvd 31..4 -
dbus_robin_enable 3 R/W „b0
cmd_full_number 2..1 R/W „d3

B
dbus_arb_priority 0 R/W „b0

1.36 REGISTER:: UNUSED 0x9801_330C

1.37 REGISTER:: USB3_OTG_STS 0x9801_3310

Module::usb Register::USB3_OTG_STS Set::1 ATTR::nor Type::SR ADDR::0x9801_3310

e
Name Bits R/W Default Comments
Rvd 31..1 - - -
otg_interrupt 0 R „b0 OTG interrupt from USB3 MAC

DVD R1 Architecture Specification 12

1.38 REGISTER:: USB_BC_STS 0x9801_3314

Module::usb Register::USB_BC_STS Set::1 ATTR::nor Type::SR ADDR::0x9801_3314

Name Bits R/W Defau Comments
lt
Rvd 31..2 - - -
chirp_on 1 R „b0 battery charging chirp signal from USB3 MAC
bc_interrupt 0 R „b0 battery charging interrupt from USB3 MAC

1.39 REGISTER:: USB3_BIST1_CTRL 0x9801_3318

i
Module::usb Register::USB3_BIST1_CT Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3318
RL

P
Name Bits R/W Default Comments
Rvd 31..28 - - -
usb3_bist1_ls[2:0] 27..25 R/W 3‟h0 IP SRAM 0~2 LS value
usb3_bist1_rm_3 24..21 R/W 4‟h0 SRAM3 RM value
usb3_bist1_rme_3 20 R/W „b0 SRAM3 RM enable

a
usb3_bist1_rm_2 19..16 R/W 4‟h0 SRAM2 RM value
usb3_bist1_rme_2 15 R/W „b0 SRAM2 RM enable
usb3_bist1_rm_1 14..11 R/W 4‟h0 SRAM1 RM value

n
usb3_bist1_rme_1 10 R/W „b0 SRAM1 RM enable
usb3_bist1_rm_0 9..6 R/W 4‟h0 SRAM0 RM value
usb3_bist1_rme_0 5 R/W „b0 SRAM0 RM enable

a
usb3_drf_1_test_resume 4 W/R „b0 USB3 DRF BIST1 trigger resume signal
usb3_drf_bist1_en 3 W/R „b0 USB3 DRF BIST1 enable
„b0

n
usb3_bist1_en 2 W/R USB3 BIST1 enable
Rvd 1 - - -
usb3_bist1_test_mode 0 W/R „b0 USB3 BIST1 test mode enable

Name
Rvd
B
usb3_bist2_ls[1:0]
a
1.40 REGISTER:: USB3_BIST2_CTRL

Module::usb Register::USB3_BIST2_CTR Set::1 ATTR::ctrl Type::SR

L
Bits
31..17
16..15
R/W
-
R/W
Default Comments
-
2‟h0
-
Pp SRAM LS value
0x9801_331c

ADDR::0x9801_331c

usb3_bist2_rm_1 14..11 R/W 4‟h0 SRAM5 RM value

usb3_bist2_rme_1 10 R/W „b0 SRAM5 RM enable
usb3_bist2_rm_0 9..6 R/W 4‟h0 SRAM4 RM value
usb3_bist2_rme_0 5 R/W „b0 SRAM4 RM enable
usb3_drf_2_test_resume 4 W/R „b0 USB3 DRF BIST2 trigger resume signal
usb3_drf_bist2_en 3 W/R „b0 USB3 DRF BIST2 enable
usb3_bist2_en 2 W/R „b0 USB3 BIST2 enable
Rvd 1 - - -
usb3_bist2_test_mode 0 W/R „b0 USB3 BIST2 test mode enable

DVD R1 Architecture Specification 13

1.41 REGISTER:: USB3_BIST1_STS 0x9801_3320

Module::usb Register::USB3_BIST1_STS Set::1 ATTR::nor Type::SR ADDR::0x9801_3320

Name Bits R/W Default Comments
Rvd 31..11 - - -
usb3_drf_bist1_fail_3 10 R „b0 USB3 DRF1 SRAM3 fail signal
usb3_bist1_fail_3 9 R „b0 USB3 BIST1 SRAM3 fail signal
usb3_drf_bist1_fail_2 8 R „b0 USB3 DRF1 SRAM2 fail signal
usb3_bist1_fail_2 7 R „b0 USB3 BIST1 SRAM2 fail signal
usb3_drf_bist1_fail_1 6 R „b0 USB3 DRF1 SRAM1 fail signal
usb3_bist1_fail_1 5 R „b0 USB3 BIST1 SRAM1 fail signal
usb3_drf_bist1_fail_0 4 R „b0 USB3 DRF1 SRAM0 fail signal

i
usb3_bist1_fail_0 3 R „b0 USB3 BIST1 SRAM0 fail signal
usb3_drf_1_start_pause 2 R „b0 USB3 DRF1 start pause signal
usb3_drf_bist1_done 1 R „b0 USB3 DRF1 done

P
usb3_bist1_done 0 R „b0 USB3 BIST1 done

1.42 REGISTER:: USB3_BIST2_STS 0x9801_3324

a
Module::usb Register::USB3_BIST2_S Set::1 ATTR::nor Type::SR ADDR::0x9801_3324
TS

n
Name Bits R/W Default Comments
Rvd 31..7 - - -
usb3_drf_bist2_fail_1 6 R „b0 USB3 DRF2 SRAM5 fail signal

a
usb3_bist2_fail_1 5 R „b0 USB3 BIST2 SRAM5 fail signal
usb3_drf_bist2_fail_0 4 R „b0 USB3 DRF2 SRAM4 fail signal
„b0

n
usb3_bist2_fail_0 3 R USB3 BIST2 SRAM4 fail signal
usb3_drf_2_start_pause 2 R „b0 USB3 DRF2 start pause signal
usb3_drf_bist2_done 1 R „b0 USB3 DRF2 done

a
usb3_bist2_done 0 R „b0 USB3 BIST2 done

1.43 REGISTER:: USB3_APHY_REG 0x9801_3328

B
Module::usb Register::USB3_APHY_RE Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3328
G
Name Bits R/W Default Comments
Rvd 31..5 - - -
usb3_clk_mode_sel 4..3 R/W „b00 “11” : Diff. 100MHz in, else
CKIN_XTAL in.
IN RL6227 .CKREF comes from
CKIN_XTAL, tie “00”.
usb3_ckbuf_en 2 R/W „b0 CKREF Buffer Enable tie 0
usb3_mbias_en 1 R/W „b1 Bias Circuit Enable.
1: Bias Circuit enable
0: Bias Circuit disable
usb3_bg_en 0 R/W „b0 Bandgap Enable. IN RL6227,no
BG inside the USB3.0 block, tie 0

1.44 REGISTER:: USB3_BC_STS2_REG 0x9801_332C

Module::usb Register::USB3_BC_STS2_ Set::1 ATTR::nor Type::SR ADDR::0x9801_332c
REG

DVD R1 Architecture Specification 14

 Name Bits R/W Default Comments
Rvd 31..8 - - -
hst_prtbl_det_0_usb3 7 R „b0
hst_comp_out_0_usb3 6 R „b0 Debug signal
hst_sh_out_0_usb3 5 R „b0 Debug signal
hst_v0p07_out_0_usb3 4 R „b0 DP>0.35V, output=low,
DP<0.35V, output=high
hst_v0p41_out_0_usb3 3 R „b0 DM>THD, output=low,
DM<THD, output=high
hst_v0p46_out_0_usb3 2 R „b1 don't care. Output=high.
dev_chg_det_0_usb3 1 R „b0 Detector result
dev_dcp_det_0_usb3 0 R „b0 Detector result

i
1.45 REGISTER:: USB3_BC_CTL_REG 0x9801_3330
Module::usb Register::USB3_BC_CTL_ Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3330
REG

P
Name Bits R/W Default Comments
Rvd 31..15 - - -
LF_PD_R_en 14 R/W „b1
hst_pow_charge_0_usb3 13 R/W „b0 Enable charge, high enable
hst_vdm_src_en_0_usb3 12 R/W „b0 Enable VDM_SRC output, high

a
enable
hst_idp_sink_en_0_usb3 11 R/W „b0 Enable DP current sink, high
enable

n
hst_app_div_en_0_usb3 10 R/W „b0 Enable Apple mode, high enable
hst_app_div_sel_0_usb3 9 R/W „b0 Select Apple charge current

a
2.1A/1A
0: DP=2.0V, DM=2.7V
1: DP=2.7V, DM=2.0V

n
hst_dcp_app_comp_en_0_u 8 R/W „b0 Enable comparator for detect
sb3 Apple/DCP mode, high enable
hst_note_div_en_0_usb3 7 R/W „b0 Enable NOTE mode, high enable,

a
DP=1.25V
hst_dcp_en_0_usb3 6 R/W „b0 Enable DCP mode, high enable,
short DP and DM.

B
dev_pow_charge_0_usb3 5 R/W „b0 Enable charger, high enable
dev_dcp_chg_mode_0_usb 4 R/W „b0 0: select CHG_DET detect
3 1: select DCP_DET detect
dev_vdp_src_en_0_usb3 3 R/W „b0 Enable DP output voltage, high
enable
dev_vdm_src_en_0_usb3 2 R/W „b0 Enable DM output voltage, high
enable
dev_idp_sink_en_0_usb3 1 R/W „b0 Enable DP current sink, high
enable
dev_idm_sink_en_0_usb3 0 R/W „b0 Enable DM current sink, high
enable

1.46 REGISTER:: USB3_DUMMY_0_REG 0x9801_3334

Module::usb Register::USB3_DUMMY_ Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3334
0_REG
Name Bits R/W Default Comments
dummy_0 31..0 R/W 32‟h0 Dummy register,default:0

DVD R1 Architecture Specification 15

1.47 REGISTER:: USB3_DUMMY_1_REG 0x9801_3338
Module::usb Register::USB3_DUMMY_ Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3338
1_REG
Name Bits R/W Default Comments
dummy_1 31..0 R/W 32‟hFFFF_FFF Dummy register,default:1
F

1.48 REGISTER:: USB3_LTSSM_STS 0x9801_333C

Module::usb Register::USB3_LTSSM_S Set::1 ATTR::nor Type::SR ADDR::0x9801_333c
TS
Name Bits R/W Default Comments

i
Rvd 31..4 - - -
Ltdb_sub_state 3..0 R „b0 Ltssm sub-state from USB3 IP

P
1.49 REGISTER:: USB_PHY_CTRL 0x9801_3340
Module::usb Register::USB_PHY_CTRL Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3340
Name Bits R/W Default Comments
Rvd 31..6 - - -

a
usb_ldo_en 5..2 R/W „b0 U2phy0~U2phy3 ldo enable
usb3_isolate_mac2phy 1..0 R/W „b0 isolate UPHY AD

1.50 REGISTER:: USB_PWR_CTRL

Module::usb Register::USB_PWR_CTR
L

a
Set::1

n
ATTR::ctrl Type::SR
0x9801_3344
ADDR::0x9801_3344

n
Name Bits R/W Default Comments
u3_det_time_val 31..16 R/W „hfa u3_det_time_val
u2_det_time_val 15..9 R/W „h3 u2_det_time_val

a
u3_ip_clk_en 8..7 R/W „h3 u3_ip_clk_en
u3_ip_rstn 6..5 R/W „h3 u3_ip_rstn
mac_phy_pll_en 4..3 R/W „h3 mac_phy_pll_en

B
u2_det_debounce_en 2 R/W „b0 u2_det_debounce_en
recv_det_start_hst 1 R/W „b0 recv_det_start_hst
recv_det_start_drd 0 R/W „b0 recv_det_start_drd

1.51 REGISTER:: USB_PWR_STS 0x9801_3348

Module::usb Register::USB_PWR_STS Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3348
Name Bits R/W Default Comments
usb_pwr_ctrl_en 31 R/W „h0 usb_pwr_ctrl_en
sw_reset_pwr_fsm 30..29 R/W „h0 sw_reset_pwr_fsm
rxterm_dly_en 28 R/W „b1 rxterm_dly_en
Rvd 27..10 - - -
recv_det_int_en_hst 9 R/W „b0 recv_det_int_en_hst
recv_det_int_en_drd 8 R/W „b0 recv_det_int_en_drd
Rvd 7..2 - - -
recv_det_int_sts_hst 1 R/W „b0 recv_det_int_sts_hst
recv_det_int_sts_drd 0 R/W „b0 recv_det_int_sts_drd

DVD R1 Architecture Specification 16

1.52 REGISTER:: USB_TYPEC_CTRL_CC1_0
0x9801_334C
Module::usb Register::USB_TYPEC_CT Set::1 ATTR::ctrl Type::SR ADDR::0x9801_334C
RL_CC1_0
Name Bits R/W Default Comments
Rvd 31..30 - - -
EN_SWITCH 29 R/W „h0 En switch
Txout_sel 28 R/W „h0 Txout_sel
Rxin_sel 27 R/W „h0 Rxin_sel
Reg_cc1_rp4pk_code 26..22 R/W „h0 Reg_cc1_rp4pk_code
Reg_cc1_rp36k_code 21..17 R/W „h0 Reg_cc1_rp36k_code
Reg_cc1_rp12k_code 16..12 R/W „h0 Reg_cc1_rp12k_code
Reg_cc1_rd_code 11..7 R/W „h0 Reg_cc1_rd_code

i
Reg_cc1_mode 6..5 R/W „h0 Reg_cc1_mode
En_cc1_rp4p7k 4 R/W „h0 En_cc1_rp4p7k
„h0

P
En_cc1_rp36k 3 R/W En_cc1_rp36k
En_cc1_rp12k 2 R/W „h0 En_cc1_rp12k
En_cc1_rd 1 R/W „h0 En_cc1_rd
En_cc1_det 0 R/W „h0 En_cc1_det

a
1.53 REGISTER:: USB_TYPEC_CTRL_CC1_1
0x9801_3350

n
Module::usb Register::USB_TYPEC_CT Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3350
RL_CC1_1

a
Name Bits R/W Default Comments
Rvd 31..29 - - -
Reg_cc1_ vref_2p6v 28..26 R/W „h0 Reg_cc1_ vref_2p6v

n
Reg_cc1_ vref_1p23v 25.22 R/W „h0 Reg_cc1_ vref_1p23v
Reg_cc1_ vref_0p8v 21..18 R/W „h0 Reg_cc1_ vref_0p8v
Reg_cc1_ vref_0p66v 17..14 R/W „h0 Reg_cc1_ vref_0p66v

a
Reg_cc1_ vref_0p4v 13.11 R/W „h0 Reg_cc1_ vref_0p4v
Reg_cc1_vref_0p2v 10..8 R/W „h0 Reg_cc1_vref_0p2v
„h0

B
Reg_cc1_ vref1_1p6v 7..4 R/W Reg_cc1_ vref1_1p6v
Reg_cc1_vref0_1p6v 3..0 R/W „h0 Reg_cc1_vref0_1p6v

1.54 REGISTER:: USB_TYPEC_CTRL_CC2_0

0x9801_3354
Module::usb Register::USB_TYPEC_CT Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3354
RL_CC2_0
Name Bits R/W Default Comments
Rvd 31..27 - - -
Reg_CC2_rp4pk_code 26..22 R/W „h0 Reg_CC2_rp4pk_code
Reg_CC2_rp36k_code 21..17 R/W „h0 Reg_CC2_rp36k_code
Reg_CC2_rp12k_code 16..12 R/W „h0 Reg_CC2_rp12k_code
Reg_CC2_rd_code 11..7 R/W „h0 Reg_CC2_rd_code
Reg_CC2_mode 6..5 R/W „h0 Reg_CC2_mode
En_CC2_rp4p7k 4 R/W „h0 En_CC2_rp4p7k
En_CC2_rp36k 3 R/W „h0 En_CC2_rp36k
En_CC2_rp12k 2 R/W „h0 En_CC2_rp12k
En_CC2_rd 1 R/W „h0 En_CC2_rd

DVD R1 Architecture Specification 17

En_CC2_det 0 R/W „h0 En_CC2_det

1.55 REGISTER:: USB_TYPEC_CTRL_CC2_1

0x9801_3358
Module::usb Register::USB_TYPEC_CT Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3358
RL_CC2_1
Name Bits R/W Default Comments
Rvd 31..29 - - -
Reg_CC2_ vref_2p6v 28..26 R/W „h0 Reg_CC2_ vref_2p6v
Reg_CC2_ vref_1p23v 25.22 R/W „h0 Reg_CC2_ vref_1p23v
Reg_CC2_ vref_0p8v 21..18 R/W „h0 Reg_CC2_ vref_0p8v
„h0

i
Reg_CC2_ vref_0p66v 17..14 R/W Reg_CC2_ vref_0p66v
Reg_CC2_ vref_0p4v 13.11 R/W „h0 Reg_CC2_ vref_0p4v
Reg_CC2_vref_0p2v 10..8 R/W „h0 Reg_CC2_vref_0p2v

P
Reg_CC2_ vref1_1p6v 7..4 R/W „h0 Reg_CC2_ vref1_1p6v
Reg_CC2_vref0_1p6v 3..0 R/W „h0 Reg_CC2_vref0_1p6v

1.56 REGISTER:: USB_TYPEC_STS 0x9801_335C

a
Module::usb Register::USB_TYPEC_ST Set::1 ATTR::nor Type::SR ADDR::0x9801_335C
S
Name Bits R/W Default Comments

n
Rvd 31..6 - - -
cc2_det 5..3 RO „h7 CC2_det

a
cc1_det 2..0 RO „h7 CC1_det

n
1.57 REGISTER:: USB_TYPEC_CTRL 0x9801_3360
Module::usb Register::USB_TYPEC_CT Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3360

a
RL
Name Bits R/W Default Comments
Rvd 31..12 - - -

B
cc2_det_int_en 11 R/W „h0 cc2 det interrupt en
cc1_det_int_en 10 R/W „h0 cc1 det interrupt en
cc2_det_int 9 R/W „h0 cc2 det interrupt sts
cc1_det_int 8 R/W „h0 cc1 det interrupt sts
cc_detect_time_value 7..1 R/W „h3 debounce time scale
cc_det_debounce_en 0 R/W „h1 cc detect debounce en

1.58 REGISTER:: USB_DBUS_PWR_CTRL

0x9801_3364
Module::usb Register::USB_DBUS_PW Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3364
R_CTRL
Name Bits R/W Default Comments
Rvd 31..12 - - -
clk_en_gap 11..10 R/W „h0 00:50ns
01:300ns
10:500ns
11:1us

DVD R1 Architecture Specification 18

sram_ls_gap 9..8 R/W „h0 00:200ns
01:300ns
10:100ns
11:500ns
Rvd 7..2 - - -
dbus_pwr_ctrl_sw_rst 1 R/W „h0 dbus power ctrl software reset to
idle
dbus_pwr_ctrl_en 0 R/W „h0 dbus power ctrl enable

1.59 REGISTER:: USB3_HOST_WRAP_CTR_reg

0x9801_3C00

i
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C00
USB3_HOST_WRAP_CT

P
R
Name Bits R/W Default Comments
Rvd 31..7 - - -
rxdetect_value 6 R/W „b0
rxdetect_sel 5 R/W „b0
„b0

a
resume_cycle_sel 4 R/W
sram_debug_sel 3 R/W „b0 Select sram
1: host

n
0: device
sram_debug_mode 2 R/W „b0 Enable sram debug mode
dbus_multi_req_disable 1 R/W ‟b0 Disable multiple request for Dbus

a
0: enable multiple request
1: disable multiple request
dev_mode 0 R/W ‟b0 Enable peek on AHB burst length

n
0: host (2)
1: host/dev

Rvd
0x9801_3C04

Module::usb

device_int
Name
R_INT
a
1.60 REGISTER:: USB3_HOST_GNT_INT_reg

B
Register::USB3_HOST_GN Set::1

Bits
31..2
1
R/W
-
R
ATTR::nor

Default
-
„b0
Type::SR

-
ADDR::0x9801_3C04

Comments

USB3 Device MAC interrupt

host_int 0 R „b0 USB3 Host MAC interrupt

1.61 REGISTER:: USB3_HOST_USB2_PHY_UTMI

0x9801_3C08

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C08

USB3_HOST_USB2_PHY_
UTMI
Name Bits R/W Default Comments
Rvd 31..1 - - -

DVD R1 Architecture Specification 19

reset_utmi_p0 0 R/W „b0 UTMI reset to PHY0 (sync and
automatically return to low)

1.62 REGISTER:: USB3_HOST_VSTATUS_port0_reg

0x9801_3C14

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C14

USB3_HOST_VSTATUS0
_OUT
Name Bits R/W Default Comments

i
Rvd 31..8 - - -
p0_vstatus_out 7..0 R/W ‟h00 Vstatus output for port0 (It‟s used to
configure PHY‟s control register)

The process of configuring PHY control register:

3. write VSTATUS_reg (0x9801_3C14), (data output to PHY)
4. write GUSB2PHYAccn (p0:0x9803_1280)
P
a
[25]: vload
[23]: vBusy
[11:8]: vcontrol

n
[7:0]: vstatus_in (data input from PHY)

n a
B a

DVD R1 Architecture Specification 20

 P i
n a
n a
B a
3. polling [23]: vBusy, if [23]=0, then vstatus_in is valid
Example for RealTek PHY:
Vcontrol[3]: low/high address, 0: low, 1: high
Vcontrol[2:0]: address
The control address in RealTek PHY is 6 bits, so it needs to send 2 vcontrol address. For
example, vcontrol=1110 (high address) and 0000 (low address) means 110000=0x30.

1.63 REGISTER:: USB3_HOST_SLP_BACK_EN_port0_reg

0x9801_3C18

Module::usb Register::USB3_HOST_SL Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C18

DVD R1 Architecture Specification 21

 P_BACK0_EN
Name Bits R/W Default Comments
Rvd 31..4 - - -
simulation_mode_p0 3 R/W „b0 Port0 Reduce counter for entering
HS
force_hs_mode_p0 2 R/W „b0 Port0 Force HOST IP enter high
speed mode
0: disable
1: enable
test_rst_p0 1 R/W „b0 Port0 Self loop back reset
test_en_p0 0 R/W „b0 Port0 Self loop back enable

i
1.64 REGISTER:: USB3_HOST_SLP_BACK_CTR_port0_reg

P
0x9801_3C1c

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C1c

USB3_HOST_SLP_BACK0_

a
CTR
Name Bits R/W Default Comments
Rvd 31..12 - - -

n
test_speed_p0 11..10 R/W „h0 When Self_loop_back, force PHY
enter High Speed or Full Speed
mode

a
(HS: utmi_xver_select=0,
utmi_term_select[1:0]=00)

n
(FS: utmi_xver_select=1,
utmi_term_select[1:0]=01,
FsLsSerialMode=0)

a
2‟b01: force PHY in HS
2‟b10: force PHY in FS/LS
2‟b00/2‟b11: normal mode

B
test_seed_p0 9..2 R/W „h0 Self_loop_back
Random generator seed
test_psl_p0 1..0 R/W „h0 Select self_loop_back pattern
00: all zeros
01: load from seed
10: pseudo random pattern
11: incremental counter

1.65 REGISTER:: USB3_HOST_SLP_BACK_ST_port0_reg

0x9801_3C20

Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3C20

USB3_HOST_SLP_BACK
0_ST
Name Bits R/W Default Comments
Rvd 31..2 - - -

DVD R1 Architecture Specification 22

test_fail_p0 1 R „b0 Port0 Self loop back fail
test_done_p0 0 R „b0 Port0 Self loop back done

Slef_loop_back procedure:
(8) Configure PHY as self_loop_back mode (by vloadM interface)
R/W 38 F0 DBNC_E DISCON_E EN_ERR_UN LATE_DL INTG SOP_KK SLB_INNER SLB_EN
N NABLE DERRUN LEN
1 1 1 1 1 1 0: digital & 1
analog

i
1: digital only

P
(9) set test_psl, test_seed and test_speed
(10) set test_rst=1 & test_en=0 (reset)
(11) set test_rst=0 & test_en=0 (reset)
(12) set test_rst=0 & test_en=1 (enable)
(13) polling test_done

a
(14) check test_fail

n
Force MAC to enter High-Speed procedure:

a
(4) In simulation mode: force_hs_mode=1 & simulation_mode=1
(5) In non-simulation mode (don‟t reduce counter): force_hs_mode=1 &
simulation_mode=0

n
(6) In normal mode: force_hs_mode=0 & simulation_mode=0

a
1.66 REGISTER:: USB3_HOST_PHY2_SLB0_EN_reg
0x9801_3C24

Module::usb

Rvd
Name

p0_usb2phy_slb_hs

p0_usb2phy_force_slb
B
Register::
USB3_HOST_PHY2_SLB_
EN
Bits
31..2
1

0
R/W
-
R/W
Set::1

R/W
ATTR::ctrl

Default
-
„b0

„b0
Type::SR

-
ADDR::0x9801_3C24

Comments

Usbphy port0 self loop back hs

mode
Usbphy port0 self loop back start

1.67 REGISTER:: USB3_HOST_PHY2_SLB0_ST_reg

0x9801_3C28

Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3C28

USB3_HOST_PHY2_SLB_
ST

DVD R1 Architecture Specification 23

 Name Bits R/W Default Comments
Rvd 31..2 - - -
p0_usb2phy_slb_fail 1 R „b0 Usbphy port0 self loop back done
p0_usb2phy_slb_done 0 R „b0 Usbphy port0 self loop back fail

1.68 REGISTER:: USB3_HOST_USB2_SPD_CTR

0x9801_3C2C

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C2c

USB3_HOST_USB2_SPD
_CTR

i
Name Bits R/W Default Comments
Rvd 31..2 - - -
p0_suspend_r 0 R/W ‟b0 -

1.69 REGISTER:: USB3_HOST_USB_DBG_reg

0x9801_3C40

P
Module::usb

Rvd
Name
Register::
USB3_HOST_USB_DBG
Bits
31..13
Set::1

R/W
-
a
ATTR::ctrl

n
Default
-
Type::SR

-
ADDR::0x9801_3C40

Comments

a
dbg_sel1 12..7 R/W „b0 Select debug signal sets to be
probed via usb_dbg_out1
„b0

n
dbg_sel0 6..1 R/W Select debug signal sets to be
probed via usb_dbg_out0
dbg_en 0 R/W „b0 Debug enable

a
When set, selected signals can be
probed via debug ports. When clear,
both usb_dbg_out0 and

B
usb_dbg_out1 are static 16‟h0.

1.70 REGISTER:: USB3_HOST_USB_STCH_reg

0x9801_3C44

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C44

USB3_HOST_USB_SCT
CH
Name Bits R/W Default Comments
reg1 31..16 R/W „hffff Dummy register with value 1
reg0 15..0 R/W „d0 Dummy register with value 0

DVD R1 Architecture Specification 24

1.71 REGISTER:: USB3_HOST_USB_TMP_SP_reg _0
0x9801_3C48

Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3C48

USB3_HOST_USB_TM
P_SP
Name Bits R/W Default Comments
test_sp_reg_0 31..0 R/W „d0 Dummy test register

1.72 REGISTER:: USB3_HOST_USB_TMP_SP_reg_1

0x9801_3C4C

i
Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3C48
USB3_HOST_USB_TM
P_SP

P
Name Bits R/W Default Comments
test_sp_reg_1 31..0 R/W „d0 Dummy test register

1.73 REGISTER:: USB3_HOST_USB_TMP_reg _2

a
0x9801_3C50

n
Module::usb Register:: Set::3 ATTR::ctrl Type::SR ADDR::0x9801_3850
USB3_HOST_USB_TMP

a
Name Bits R/W Default Comments
test_reg_2 31..0 R/W „d0 Dummy test register

n
1.74 REGISTER:: USB3_HOST_USB_TMP_reg_3

a
0x9801_3C5C

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C5C

B
USB3_HOST_USB_TMP
Name Bits R/W Default Comments
test_reg_3 31..0 R/W „d0 Dummy test register

1.75 REGISTER:: USB3_HOST_USB_HMAC_CTR0_reg

0x9801_3C60

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C60

USB3_HOST_HMAC_CT
R0
Name Bits R/W Default Comments
Rvd 31..30 - - -
host_fladj_30mhz 29..24 R/W „d32 -
host_ppc_present 23 R/W „b0 -
host_msi_enable 22 R/W „b0
host_pm_pw_state_req 21..20 R/W „b0
hub_port_over_current 19..16 R/W „b0

DVD R1 Architecture Specification 25

hub_port_perm_attach 15..12 R/W „b0
host_u2_port_disable 11..9 R/W „b0
host_u3_port_disable 8 R/W „b0
host_num_u2_port 7..4 R/W „d1
host_num_u3_port 3..0 R/W „d0

1.76 REGISTER:: USB3_HOST_MAC3_HST_ST_reg

0x9801_3C64

Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3C64

USB3_HOST_MAC3_HS

i
T_ST
Name Bits R/W Default Comments
Rvd 31..6 - - -

P
host_current_power_state 5..4 R „b0 Current xHC power state
host_hub_vbus_ctrl 3..0 R „b0 Vbus active indication

1.77 REGISTER:: USB3_HOST_DMAC_CTR0_reg

a
0x9801_3C68

n
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C68
USB3_HOST_DMAC_CT
R0

a
Name Bits R/W Default Comments
Rvd 31..27 - - -
host_xhc_bme 26 R/W „b1

n
Rvd 25..3 - - -
host_utmiotg_vbusvalid 2..0 R/W „h7

Rvd
0x9801_3C6C

Module::usb

Name B
V_ST
a
1.78 REGISTER:: USB3_HOST_MAC3_DEV_ST_reg

Register::
USB3_HOST_MAC3_DE

Bits
31..2
Set::1

R/W
-
ATTR::nor

Default
-
Type::SR

-
ADDR::0x9801_3C6c

Comments

dev_current_power_state 1..0 R „b0 Current xHC power state

1.79 REGISTER:: USB3_HOST_USB2_PHY_reg

0x9801_3C70

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C70

USB3_HOST_USB2_PHY
Name Bits R/W Default Comments

DVD R1 Architecture Specification 26

Rvd 31..13 - - -
phy_pll_en 12 R/W „b1 1:phy pll always on(for CR 480MHz)
p0_by_pass_on_1 11 R/W „b0 Isolation AD
p0_DmPulldown 10 R/W „b0 Device = 1‟b0
p0_DpPulldown 9 R/W „b0 Device = 1‟b0
p0_IDPULLUP 8 R/W „b0 Device = 1‟b0
Rvd 7..3 - - -
p0_DmPulldown_sel 2 R/W „b0 p0_DmPulldown_sel ?
p0_DmPulldown : 1‟b0
p0_DpPulldown_sel 1 R/W „b0 p0_DpPulldown_sel ?
p0_DpPulldown : 1‟b0
p0_IDPULLUP_sel 0 R/W „b0 p0_IDPULLUP_sel ?
p0_IDPULLUP : 1‟b0

1.80 REGISTER:: USB3_HOST_USB_RAM_CTR_reg

0x9801_3C74

Module::usb Register::
USB3_HOST_RAM_
Set::1 ATTR::nor_up Type::SR

P i
ADDR::0x9801_3C74

a
CTR
Name Bits R/W Default Comments
Rvd 31..17 - - -

n
done_st 16 R/W „b0 Write 1 to clear
Rvd 15..1 - - -
go_ct 0 R/W „b0 Start DMA transfer, clear after done

n a
1.81 REGISTER:: USB3_HOST_USB_RAM_ADDR_reg
0x9801_3C78

a
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C78
USB3_HOST_RAM_ADD

B
R
Name Bits R/W Default Comments
sram_addr 31..0 R/W „d0 SRAM address, 4-byte align.
Bit[0]= use for write/read bit
0: read
1: write

1.82 REGISTER:: USB3_HOST_USB_RAM_WDATA_reg

0x9801_3C87C

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3C87

USB3_HOST_RAM_WDA C
TA
Name Bits R/W Default Comments
ram_wdata 31..0 R/W „d0 RAM write data to be write

DVD R1 Architecture Specification 27

1.83 REGISTER:: USB3_HOST_RAM_RDATA_reg
0x9801_3C80

Module::usb Register:: Set::1 ATTR::nor_up Type::SR ADDR::0x9801_3C80

USB3_HOST_RAM_RD
ATA
Name Bits R/W Default Comments
ram_rdata 31..0 R/W „d0 USB read data to be read back

1.84 REGISTER:: USB3_HOST_PHY0_ST_reg

0x9801_3C84

i
Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3C84

P
USB3_HOST_PHY0_ST
Name Bits R/W Default Comments
Rvd 31..19 - - -
p0_count_num 18..0 R „b0 USB3 PHY count number value

a
1.85 REGISTER:: USB3_HOST_OVR_CT_reg
0x9801_3C88

Module::usb

Rvd
Name
R_CT
Bits
31..2

a
R/W
R/W
n
Register::USB3_HOST_OV Set::1 ATTR::ctrl

Default
-
Type::SR

-
ADDR::0x9801_3C88

Comments

n
phy3_lperiod 9..7 R/W „d1 Connect to PHY3
phy3_hperiod 6..4 R/W „d3 Connect to PHY3
phy3_last 3..2 R/W „d2 Connect to PHY3

a
host_ovr_current_value 1 R/W „b0
host_ovr_current_sel 0 R/W „b0

B
1.86 REGISTER:: USB3_HOST_SOFT_Reset
0x9801_3D00

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3D00

USB3_HOST_SOFT_RES
ET
Name Bits R/W Default Comments
Rvd 31..3 - - -
rstn_usb2_phy1 2 R/W „b0 USB2 PHY1 reset for USB2 IP
rstn_usb2_phy0 1 R/W „b0 USB2 PHY0 reset for USB2 IP
rstn_usb2 0 R/W „b0 USB2 IP system reset

1.87 REGISTER:: USB3_HOST_GBL_USB_CT

0x9801_3D04

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3D04

DVD R1 Architecture Specification 28

 USB3_HOST_GBL_USB_
CT
Name Bits R/W Default Comments
usb_mac_ctrl 31..0 R/W „d0 Register use for usb_mac_ctrl

1.88 REGISTER:: USB3_HOST_GBL_USB_ARB

0x9801_3D08

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3D08

USB3_HOST_GBL_USB_

i
ARB
Name Bits R/W Default Comments
Rvd 31..4 -

P
dbus_robin_enable 3 R/W „b0
cmd_full_number 2..1 R/W „d3
dbus_arb_priority 0 R/W „b0

a
1.89 REGISTER:: UNUSED 0x9801_3D0C

1.90 REGISTER:: USB3_HOST_OTG_STS

0x9801_3D10

a n
n
Module::usb Register::USB3_HOST_OTG Set::1 ATTR::nor Type::SR ADDR::0x9801_3D10
_STS e

a
Name Bits R/W Default Comments
Rvd 31..1 - - -
otg_interrupt 0 R „b0 OTG interrupt from USB3 MAC

Name
0x9801_3D14

Module::usb B
1.91 REGISTER:: USB3_HOST_USB_BC_STS

Register::
USB3_HOST_USB_BC_
STS
Bits R/W
Set::1

Defau
ATTR::nor

Comments
Type::SR ADDR::0x9801_3D14

lt
Rvd 31..2 - - -
chirp_on 1 R „b0 battery charging chirp signal from USB3 MAC
bc_interrupt 0 R „b0 battery charging interrupt from USB3 MAC

DVD R1 Architecture Specification 29

1.92 REGISTER:: USB3_HOST_BIST1_CTRL
0x9801_3D18 (IP sram)

Module::usb Register::USB3_HOST_BIS Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3D18

T1_CTRL
Name Bits R/W Default Comments
Rvd 31..28 - - -
usb3_bist1_ls[2:0] 27..25 R/W 3‟h0 SRAM0~2 LS value
usb3_bist1_rm_3 24..21 R/W 4‟h0 SRAM3 RM value
usb3_bist1_rme_3 20 R/W „b0 SRAM3 RM enable
usb3_bist1_rm_2 19..16 R/W 4‟h0 SRAM2 RM value
usb3_bist1_rme_2 15 R/W „b0 SRAM2 RM enable

i
usb3_bist1_rm_1 14..11 R/W 4‟h0 SRAM1 RM value
usb3_bist1_rme_1 10 R/W „b0 SRAM1 RM enable
usb3_bist1_rm_0 9..6 R/W 4‟h0 SRAM0 RM value

P
usb3_bist1_rme_0 5 R/W „b0 SRAM0 RM enable
usb3_drf_1_test_resume 4 W/R „b0 USB3 DRF BIST1 trigger resume signal
usb3_drf_bist1_en 3 W/R „b0 USB3 DRF BIST1 enable
usb3_bist1_en 2 W/R „b0 USB3 BIST1 enable
Rvd 1 - - -

a
usb3_bist1_test_mode 0 W/R „b0 USB3 BIST1 test mode enable

n
1.93 REGISTER:: USB3_HOST_BIST2_CTRL
0x9801_3D1c (PPsram)

a
Module::usb Register::USB3_HOST_BIS Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3D1c

n
T2_CTRL
Name Bits R/W Default Comments
Rvd 31..17 - - -

a
usb3_bist2_ls[1:0] 16..15 R/W 2‟h0 SRAM4~5 LS value
usb3_bist2_rm_1 14..11 R/W 4‟h0 SRAM5 RM value
usb3_bist2_rme_1 10 R/W „b0 SRAM5 RM enable

B
usb3_bist2_rm_0 9..6 R/W 4‟h0 SRAM4 RM value
usb3_bist2_rme_0 5 R/W „b0 SRAM4 RM enable
usb3_drf_2_test_resume 4 W/R „b0 USB3 DRF BIST2 trigger resume signal
usb3_drf_bist2_en 3 W/R „b0 USB3 DRF BIST2 enable
usb3_bist2_en 2 W/R „b0 USB3 BIST2 enable
Rvd 1 - - -
usb3_bist2_test_mode 0 W/R „b0 USB3 BIST2 test mode enable

1.94 REGISTER:: USB3_HOST_BIST1_STS 0x9801_3D20

Module::usb Register::USB3_HOST_BIST1 Set::1 ATTR::nor Type::SR ADDR::0x9801_3D20

_STS
Name Bits R/W Default Comments
Rvd 31..11 - - -
usb3_drf_bist1_fail_3 10 R „b0 USB3 DRF1 SRAM3 fail signal
usb3_bist1_fail_3 9 R „b0 USB3 BIST1 SRAM3 fail signal

DVD R1 Architecture Specification 30

usb3_drf_bist1_fail_2 8 R „b0 USB3 DRF1 SRAM2 fail signal
usb3_bist1_fail_2 7 R „b0 USB3 BIST1 SRAM2 fail signal
usb3_drf_bist1_fail_1 6 R „b0 USB3 DRF1 SRAM1 fail signal
usb3_bist1_fail_1 5 R „b0 USB3 BIST1 SRAM1 fail signal
usb3_drf_bist1_fail_0 4 R „b0 USB3 DRF1 SRAM0 fail signal
usb3_bist1_fail_0 3 R „b0 USB3 BIST1 SRAM0 fail signal
usb3_drf_1_start_pause 2 R „b0 USB3 DRF1 start pause signal
usb3_drf_bist1_done 1 R „b0 USB3 DRF1 done
usb3_bist1_done 0 R „b0 USB3 BIST1 done

1.95 REGISTER:: USB3_HOST_BIST2_STS

0x9801_3D24

Module::usb

Name
Rvd
Register::USB3_HOST_B
IST2_STS

usb3_drf_bist2_fail_1
usb3_bist2_fail_1
Bits R/W
31..7 -
6
5
R
R
Set::1

Default
-
„b0
„b0
ATTR::nor

Comments
-
Type::SR

USB3 DRF2 SRAM5 fail signal

USB3 BIST2 SRAM5 fail signal
P i
ADDR::0x9801_3D24

a
usb3_drf_bist2_fail_0 4 R „b0 USB3 DRF2 SRAM4 fail signal
usb3_bist2_fail_0 3 R „b0 USB3 BIST2 SRAM4 fail signal
usb3_drf_2_start_pause 2 R „b0 USB3 DRF2 start pause signal

n
usb3_drf_bist2_done 1 R „b0 USB3 DRF2 done
usb3_bist2_done 0 R „b0 USB3 BIST2 done

a
1.96 USB3_HOST_BC_STS2_REG 0x9801_3D2C
Module::usb Register::USB3_HOST_BC Set::1 ATTR::nor Type::SR ADDR::0x9801_3D2

n
_STS2_REG C
Name Bits R/W Default Comments

a
Rvd 31..8 - - -
hst_prtbl_det_0_usb3 7 R „b0
hst_comp_out_0_usb3 6 R „b0 Debug signal

B
hst_sh_out_0_usb3 5 R „b0 Debug signal
hst_v0p07_out_0_usb3 4 R „b0 DP>0.35V, output=low,
DP<0.35V, output=high
hst_v0p41_out_0_usb3 3 R „b0 DM>THD, output=low,
DM<THD, output=high
hst_v0p46_out_0_usb3 2 R „b1 don't care. Output=high.
dev_chg_det_0_usb3 1 R „b0 Detector result
dev_dcp_det_0_usb3 0 R „b0 Detector result

1.97 REGISTER:: USB3_HOST_BC_CTL_REG

0x9801_3D30
Module::usb Register::USB3_HOST_BC Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3D30
_CTL_REG
Name Bits R/W Default Comments
Rvd 31..15 - - -
lf_pd_r_en_0_usb3 14 R/W „b1
hst_pow_charge_0_usb3 13 R/W „b0 Enable charge, high enable
hst_vdm_src_en_0_usb3 12 R/W „b0 Enable VDM_SRC output, high

DVD R1 Architecture Specification 31

 enable
hst_idp_sink_en_0_usb3 11 R/W „b0 Enable DP current sink, high
enable
hst_app_div_en_0_usb3 10 R/W „b0 Enable Apple mode, high enable
hst_app_div_sel_0_usb3 9 R/W „b0 Select Apple charge current
2.1A/1A
0: DP=2.0V, DM=2.7V
1: DP=2.7V, DM=2.0V
hst_dcp_app_comp_en_0_u 8 R/W „b0 Enable comparator for detect
sb3 Apple/DCP mode, high enable
hst_note_div_en_0_usb3 7 R/W „b0 Enable NOTE mode, high enable,
DP=1.25V
hst_dcp_en_0_usb3 6 R/W „b0 Enable DCP mode, high enable,

i
short DP and DM.
dev_pow_charge_0_usb3 5 R/W „b0 Enable charger, high enable
dev_dcp_chg_mode_0_usb 4 R/W „b0 0: select CHG_DET detect

P
3 1: select DCP_DET detect
dev_vdp_src_en_0_usb3 3 R/W „b0 Enable DP output voltage, high
enable
dev_vdm_src_en_0_usb3 2 R/W „b0 Enable DM output voltage, high
enable
dev_idp_sink_en_0_usb3 1 R/W „b0 Enable DP current sink, high

a
enable
dev_idm_sink_en_0_usb3 0 R/W „b0 Enable DM current sink, high

n
enable

1.98 REGISTER:: USB3_HOST_DUMMY_0_REG

a
0x9801_3D34
Module::usb Register::USB3_HOST_DU Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3D34

n
MMY_0_REG
Name Bits R/W Default Comments
dummy_0 31..0 R/W 32‟h0 Dummy register,default:0

a
1.99 REGISTER:: USB3_HOST_DUMMY_1_REG

B
0x9801_3D38
Module::usb Register::USB3_HOST_DU Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3D38
MMY_1_REG
Name Bits R/W Default Comments
dummy_1 31..0 R/W 32‟hFFFF_FFF Dummy register,default:1
F

1.100 REGISTER:: USB3_HOST_USB_DBUS_PWR_CTRL

0x9801_3D60
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3D60
USB3_HOST_USB_DBUS
_PWR_CTRL
Name Bits R/W Default Comments
Rvd 31..12 - - -
clk_en_gap 11..10 R/W „h0 00:50ns
01:300ns

DVD R1 Architecture Specification 32

 10:500ns
11:1us
sram_ls_gap 9..8 R/W „h0 00:200ns
01:300ns
10:100ns
11:500ns
Rvd 7..2 - - -
dbus_pwr_ctrl_sw_rst 1 R/W „h0 dbus power ctrl software reset to
idle
dbus_pwr_ctrl_en 0 R/W „h0 dbus power ctrl enable

1.101 REGISTER:: USB3_U3_HOST_WRAP_CTR_reg

i
0x9801_3E00

P
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E00
USB3_U3_HOST_WRAP_
CTR
Name Bits R/W Default Comments
Rvd 31..7 - - -
„b0

a
rxdetect_value 6 R/W
rxdetect_sel 5 R/W „b0
resume_cycle_sel 4 R/W „b0

n
sram_debug_sel 3 R/W „b0 Select sram
1: host
0: device

a
sram_debug_mode 2 R/W „b0 Enable sram debug mode
dbus_multi_req_disable 1 R/W ‟b0 Disable multiple request for Dbus
0: enable multiple request

n
1: disable multiple request
dev_mode 0 R/W ‟b0 Enable peek on AHB burst length

a
0: host (2)
1: host/dev

B
1.102 REGISTER:: USB3_U3_HOST_GNT_INT_reg
0x9801_3E04

Module::usb Register::USB3_U3_HOST Set::1 ATTR::nor Type::SR ADDR::0x9801_3E04

_GNR_INT
Name Bits R/W Default Comments
Rvd 31..2 - - -
device_int 1 R „b0 USB3 Device MAC interrupt
host_int 0 R „b0 USB3 Host MAC interrupt

1.103 REGISTER:: USB3_U3_HOST_USB2_PHY_UTMI

0x9801_3E08

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E08

USB3_U3_HOST_USB2_PH
Y_UTMI

DVD R1 Architecture Specification 33

 Name Bits R/W Default Comments
Rvd 31..1 - - -
reset_utmi_p0 0 R/W „b0 UTMI reset to PHY0 (sync and
automatically return to low)

1.104 REGISTER:: USB3_U3_HOST_PHY_PIPE

0x9801_3E0c

Module::usb Register::USB3_U3_HOST Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E0c

_PHY_PIPE
Name Bits R/W Default Comments

i
Rvd 31..1 - - -
reset_pipe3_p0 0 R/W „b0 PIPE3 reset to PHY1 (sync and
automatically return to low)

1.105 REGISTER:: USB3_U3_HOST_MDIO_CTR_reg

0x9801_3E10
P
a
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E10
USB3_U3_HOST_MDIO_C

n
TR
Name Bits R/W Default Comments
data 31..16 R/W „h0 Write data or read data.

a
phy_addr 15..13 R/W „d0 MDIO PHY addressing value.
phy_reg_addr 12..8 R/W „d0 MDIO Register addressing value

n
mdio_busy 7 R/W „d0 -
mdio_st 6..5 R/W „d0 MDIO host controller state Monitor
mdio_rdy 4 R/W „d0 MDIO Pre-amble signal Monitor

a
mclk_rate 3..2 R/W „d0 MDIO clock rate selection:
2‟b00: clk_sys/32
2‟b01: clk_sys/16

B
2‟b10: clk_sys/8
2‟b11: clk_sys/4
mdio_srst 1 R/W „d0 Assert 1‟b1 to do soft reset
mdio_rdwr 0 R/W „d0 1‟b0: read , 1‟b1: write

1.106 REGISTER:: USB3_U3_HOST_VSTATUS_port0_reg

0x9801_3E14

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E14

USB3_U3_HOST_VSTAT
US0_OUT
Name Bits R/W Default Comments
Rvd 31..8 - - -
p0_vstatus_out 7..0 R/W ‟h00 Vstatus output for port0 (It‟s used to
configure PHY‟s control register)

DVD R1 Architecture Specification 34

The process of configuring PHY control register:
5. write VSTATUS_reg (0x9801_3E14), (data output to PHY)
6. write GUSB2PHYAccn (p0:0x981F_8280)
[25]: vload
[23]: vBusy
[11:8]: vcontrol
[7:0]: vstatus_in (data input from PHY)

P i
n a
n a
B a
3. polling [23]: vBusy, if [23]=0, then vstatus_in is valid
Example for RealTek PHY:
Vcontrol[3]: low/high address, 0: low, 1: high
Vcontrol[2:0]: address

DVD R1 Architecture Specification 35

The control address in RealTek PHY is 6 bits, so it needs to send 2 vcontrol address. For
example, vcontrol=1110 (high address) and 0000 (low address) means 110000=0x30.

1.107 REGISTER:: USB3_U3_HOST_SLP_BACK_EN_port0_reg

0x9801_3E18

Module::usb Register::USB3_U3_HOST Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E18

_SLP_BACK0_EN
Name Bits R/W Default Comments

i
Rvd 31..4 - - -
simulation_mode_p0 3 R/W „b0 Port0 Reduce counter for entering

P
HS
force_hs_mode_p0 2 R/W „b0 Port0 Force HOST IP enter high
speed mode
0: disable
1: enable
test_rst_p0 1 R/W „b0 Port0 Self loop back reset

a
test_en_p0 0 R/W „b0 Port0 Self loop back enable

0x9801_3E1c

a n
1.108 REGISTER:: USB3_U3_HOST_SLP_BACK_CTR_port0_reg

n
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E1c

a
USB3_U3_HOST_SLP_BAC
K0_CTR
Name Bits R/W Default Comments

B
Rvd 31..12 - - -
test_speed_p0 11..10 R/W „h0 When Self_loop_back, force PHY
enter High Speed or Full Speed
mode
(HS: utmi_xver_select=0,
utmi_term_select[1:0]=00)
(FS: utmi_xver_select=1,
utmi_term_select[1:0]=01,
FsLsSerialMode=0)
2‟b01: force PHY in HS
2‟b10: force PHY in FS/LS
2‟b00/2‟b11: normal mode
test_seed_p0 9..2 R/W „h0 Self_loop_back
Random generator seed
test_psl_p0 1..0 R/W „h0 Select self_loop_back pattern
00: all zeros
01: load from seed
10: pseudo random pattern
11: incremental counter

DVD R1 Architecture Specification 36

1.109 REGISTER:: USB3_U3_HOST_SLP_BACK_ST_port0_reg
0x9801_3E20

Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3E20

USB3_U3_HOST_SLP_BA
CK0_ST
Name Bits R/W Default Comments
Rvd 31..2 - - -
test_fail_p0 1 R „b0 Port0 Self loop back fail
test_done_p0 0 R „b0 Port0 Self loop back done

Slef_loop_back procedure:

R/W
(15) Configure PHY as self_loop_back mode (by vloadM interface)
38 F0 DBNC_E DISCON_E EN_ERR_UN LATE_DL INTG SOP_KK SLB_INNER
N
1
NABLE
1
DERRUN
1
LEN
1 1 1
P i0: digital &
SLB_EN

a
analog
1: digital only

(16)
(17)
(18)
set test_rst=1 & test_en=0 (reset)
set test_rst=0 & test_en=0 (reset)
n
set test_psl, test_seed and test_speed

a
n
(19) set test_rst=0 & test_en=1 (enable)
(20) polling test_done
(21) check test_fail

B a
Force MAC to enter High-Speed procedure:
(7) In simulation mode: force_hs_mode=1 & simulation_mode=1
(8) In non-simulation mode (don‟t reduce counter): force_hs_mode=1 &
simulation_mode=0
(9) In normal mode: force_hs_mode=0 & simulation_mode=0

1.110 REGISTER:: USB3_U3_HOST_PHY2_SLB0_EN_reg

0x9801_3E24

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E24

USB3_U3_HOST_PHY2_S
LB_EN
Name Bits R/W Default Comments
Rvd 31..2 - - -
p0_usb2phy_slb_hs 1 R/W „b0 Usbphy port0 self loop back hs
mode

DVD R1 Architecture Specification 37

p0_usb2phy_force_slb 0 R/W „b0 Usbphy port0 self loop back start

1.111 REGISTER:: USB3_U3_HOST_PHY2_SLB0_ST_reg

0x9801_3E28

Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3E28

USB3_U3_HOST_PHY2_S
LB_ST
Name Bits R/W Default Comments
Rvd 31..2 - - -
p0_usb2phy_slb_fail 1 R „b0 Usbphy port0 self loop back done
„b0

i
p0_usb2phy_slb_done 0 R Usbphy port0 self loop back fail

P
1.112 REGISTER:: USB3_U3_HOST_USB2_SPD_CTR
0x9801_3E2C

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E2c

USB3_U3_HOST_USB2_

a
SPD_CTR
Name Bits R/W Default Comments

n
Rvd 31..2 - - -
p0_suspend_r 0 R/W ‟b0 -

0x9801_3E30

n a
1.113 REGISTER:: USB3_U3_HOST_ SLB_EN_reg

a
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E30
USB3_U3_HOST_PHY3_S
LB_EN

B
Name Bits R/W Default Comments
Rvd 31..3 - - -
p0_pipe_bist_sel 2..1 R/W „b0 Self loop back select:
00:counter
01:tseq
10:ts1
11:ts2
p0_pipe_bist_en 0 R/W „b0 Self loop back enable

1.114 REGISTER:: USB3_U3_HOST_PHY3_ SLB_CT_reg

0x9801_3E34

Module::usb Register:: Set::1 ATTR::nor_up Type::SR ADDR::0x9801_3E34

USB3_U3_HOST_PHY3
_SLB_CT
Name Bits R/W Default Comments
Rvd 31..1 - - -

DVD R1 Architecture Specification 38

p0_usb3phy_slb_go 0 R/W „b0 Usb3phy port0 self loop back start
transfer

1.115 REGISTER:: USB3_U3_HOST_PHY3_ SLB_ST_reg

0x9801_3E38

Module::usb Register:: Set::1 ATTR::nor_up Type::SR ADDR::0x9801_3E38

USB3_U3_HOST_PHY3
_SLB_ST
Name Bits R/W Default Comments
Rvd 31..2 - - -
„b0

i
p0_usb3phy_slb_fail 1 R Usb3phy port0 self loop back done
p0_usb3phy_slb_done 0 R „b0 Usb3phy port0 self loop back
mode

1.116 REGISTER:: USB3_U3_HOST_USB_DBG_reg

0x9801_3E40
P
Module::usb Register::
USB3_U3_HOST_USB_
DBG
Set::1

n a
ATTR::ctrl Type::SR ADDR::0x9801_3E40

a
Name Bits R/W Default Comments
Rvd 31..13 - - -
„b0

n
dbg_sel1 12..7 R/W Select debug signal sets to be
probed via usb_dbg_out1
dbg_sel0 6..1 R/W „b0 Select debug signal sets to be

a
probed via usb_dbg_out0
dbg_en 0 R/W „b0 Debug enable
When set, selected signals can be

B
probed via debug ports. When clear,
both usb_dbg_out0 and
usb_dbg_out1 are static 16‟h0.

1.117 REGISTER:: USB3_U3_HOST_USB_STCH_reg

0x9801_3E44

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E44

USB3_U3_HOST_USB_
SCTCH
Name Bits R/W Default Comments
reg1 31..16 R/W „hffff Dummy register with value 1
reg0 15..0 R/W „d0 Dummy register with value 0

DVD R1 Architecture Specification 39

1.118 REGISTER:: USB3_U3_HOST_USB_TMP_SP_reg _0
0x9801_3E48

Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3E48

USB3_U3_HOST_USB_
TMP_SP
Name Bits R/W Default Comments
test_sp_reg_0 31..12 R/W „d0 Dummy test register
int_inact_status 11 R/W „d0 ltssm change to ss inactive state
int_ss_dis_status 10 R/W „d0 ltssm change to ss disabled state
int_hreset_status 9 R/W „d0 ltssm change to hot reset state
int_recov_status 8 R/W „d0 ltssm change to recovery state
int_rx_det_status 7 R/W „d0 ltssm change to rx detect state

i
int_poll_status 6 R/W „d0 ltssm change to polling state
int_u3_status 5 R/W „d0 ltssm change to u3 state

P
int_u2_status 4 R/W „d0 ltssm change to u2 state
int_u1_status 3 R/W „d0 ltssm change to u1 state
int_u0_status 2 R/W „d0 ltssm change to u0 state
int_loopbk_status 1 R/W „d0 ltssm change to loopback state
int_comp_status 0 R/W „d0 ltssm change to compliance state

a
1.119 REGISTER:: USB3_U3_HOST_USB_TMP_SP_reg_1
0x9801_3E4C

Module::usb Register::
USB3_U3_HOST_USB_
TMP_SP
Name Bits
Set::1

a
R/W
n
ATTR::nor

Default
Type::SR ADDR::0x9801_3E48

Comments

n
test_sp_reg_1 31..0 R/W „d0 Dummy test register

a
1.120 REGISTER:: USB3_U3_HOST_USB_TMP_reg _2
0x9801_3E50

Module::usb

test_reg_2
Name
B
Register::
USB3_U3_HOST_USB_T
MP
Bits
31..0
Set::3

R/W
R/W

1.121 REGISTER:: USB3_U3_HOST_USB_TMP_reg_3

ATTR::ctrl

Default
„d0
Type::SR ADDR::0x9801_3850

Comments
Dummy test register

0x9801_3E5C

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E5C

USB3_U3_HOST_USB_T
MP
Name Bits R/W Default Comments
test_reg_3 31..13 R/W „d0 Dummy test register
int_inact_en 12 R/W „d0 ltssm change to ss inactive state
interrupt enable

DVD R1 Architecture Specification 40

int_ss_dis_en 11 R/W „d0 ltssm change to ss disable state
interrupt enable
int_hreset_en 10 R/W „d0 ltssm change to hot reset state
interrupt enable
int_recov_en 9 R/W „d0 ltssm change to recovery state
interrupt enable
int_rx_det_en 8 R/W „d0 ltssm change to rx detect state
interrupt enable
int_poll_en 7 R/W „d0 ltssm change to polling state
interrupt enable
int_u3_en 6 R/W „d0 ltssm change to u3 state interrupt
enable
int_u2_en 5 R/W „d0 ltssm change to u2 state interrupt

i
enable
int_u1_en 4 R/W „d0 ltssm change to u1 state interrupt
enable

P
int_u0_en 3 R/W „d0 ltssm change to u0 state interrupt
enable
int_loopbk_en 2 R/W „d0 ltssm change to loopback state
interrupt enable
int_comp_en 1 R/W „d0 ltssm change to compliance state
interrupt enable

a
Rvd 0 - - -

n
1.122 REGISTER:: USB3_U3_HOST_USB_HMAC_CTR0_reg
0x9801_3E60

Module::usb

Name
Register::
USB3_U3_HOST_HMAC
_CTR0
Bits

n
R/W
a
Set::1 ATTR::ctrl

Default
Type::SR ADDR::0x9801_3E60

Comments

a
Rvd 31..30 - - -
host_fladj_30mhz 29..24 R/W „d32 -

B
host_ppc_present 23 R/W „b0 -
host_msi_enable 22 R/W „b0
host_pm_pw_state_req 21..20 R/W „b0
hub_port_over_current 19..16 R/W „b0
hub_port_perm_attach 15..12 R/W „b0
host_u2_port_disable 11..9 R/W „b0
host_u3_port_disable 8 R/W „b0
host_num_u2_port 7..4 R/W „d1
host_num_u3_port 3..0 R/W „d1

1.123 REGISTER:: USB3_U3_HOST_MAC3_HST_ST_reg

0x9801_3E64

Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3E64

USB3_U3_HOST_MAC3
_HST_ST
Name Bits R/W Default Comments

DVD R1 Architecture Specification 41

Rvd 31..6 - - -
host_current_power_state 5..4 R „b0 Current xHC power state
host_hub_vbus_ctrl 3..0 R „b0 Vbus active indication

1.124 REGISTER:: USB3_U3_HOST_DMAC_CTR0_reg

0x9801_3E68

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E68

USB3_U3_HOST_DMAC
_CTR0
Name Bits R/W Default Comments

i
Rvd 31..27 - - -
host_xhc_bme 26 R/W „b1
Rvd 25..3 - - -

P
host_utmiotg_vbusvalid 2..0 R/W „h7

1.125 REGISTER:: USB3_U3_HOST_MAC3_DEV_ST_reg

0x9801_3E6C

Module::usb

Name
Register::
USB3_U3_HOST_MAC3_
DEV_ST
Bits
Set::1

R/W

n a
ATTR::nor

Default
Type::SR ADDR::0x9801_3E6c

Comments

a
Rvd 31..2 - - -
dev_current_power_state 1..0 R „b0 Current xHC power state

a n
1.126 REGISTER:: USB3_U3_HOST_USB2_PHY_reg
0x9801_3E70

B
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E70
USB3_U3_HOST_USB2_
PHY
Name Bits R/W Default Comments
Rvd 31..13 - - -
phy_pll_en 12 R/W „b1 1:phy pll always on(for CR 480MHz)
p0_by_pass_on_1 11 R/W „b0 Isolation AD
p0_DmPulldown 10 R/W „b0 Device = 1‟b0
p0_DpPulldown 9 R/W „b0 Device = 1‟b0
p0_IDPULLUP 8 R/W „b0 Device = 1‟b0
Rvd 7..3 - - -
p0_DmPulldown_sel 2 R/W „b0 p0_DmPulldown_sel ?
p0_DmPulldown : 1‟b0
p0_DpPulldown_sel 1 R/W „b0 p0_DpPulldown_sel ?
p0_DpPulldown : 1‟b0
p0_IDPULLUP_sel 0 R/W „b0 p0_IDPULLUP_sel ?
p0_IDPULLUP : 1‟b0

DVD R1 Architecture Specification 42

1.127 REGISTER:: USB3_U3_HOST_USB_RAM_CTR_reg
0x9801_3E74

Module::usb Register:: Set::1 ATTR::nor_up Type::SR ADDR::0x9801_3E874

USB3_U3_HOST_R
AM_CTR
Name Bits R/W Default Comments
Rvd 31..17 - - -
done_st 16 R/W „b0 Write 1 to clear
Rvd 15..1 - - -
go_ct 0 R/W „b0 Start DMA transfer, clear after done

i
1.128 REGISTER:: USB3_U3_HOST_USB_RAM_ADDR_reg
0x9801_3E78

Module::usb

Name
Register::
USB3_U3_HOST_RAM_
ADDR
Bits R/W
Set::1 ATTR::ctrl

Default
Type::SR

P
ADDR::0x9801_3E78

Comments

a
sram_addr 31..0 R/W „d0 SRAM address, 4-byte align.
Bit[0]= use for write/read bit
0: read

n
1: write

a
1.129 REGISTER:: USB3_U3_HOST_USB_RAM_WDATA_reg
0x9801_3E87C

Module::usb Register::

DATA

a
USB3_U3_HOST_RAM_W

n
Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E87
C

B
Name Bits R/W Default Comments
ram_wdata 31..0 R/W „d0 RAM write data to be write

1.130 REGISTER:: USB3_U3_HOST_RAM_RDATA_reg

0x9801_3E80

Module::usb Register:: Set::1 ATTR::nor_up Type::SR ADDR::0x9801_3E80

USB3_U3_HOST_RAM
_RDATA
Name Bits R/W Default Comments
ram_rdata 31..0 R/W „d0 USB read data to be read back

1.131 REGISTER:: USB3_U3_HOST_PHY0_ST_reg

0x9801_3E84

Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3E84

DVD R1 Architecture Specification 43

 USB3_U3_HOST_PHY0_S
T
Name Bits R/W Default Comments
Rvd 31..19 - - -
p0_count_num 18..0 R „b0 USB3 PHY count number value

1.132 REGISTER:: USB3_U3_HOST_OVR_CT_reg

0x9801_3E88

Module::usb Register::USB3_U3_HOST Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3E88

_OVR_CT

i
Name Bits R/W Default Comments
Rvd 31..2 R/W - -
phy3_lperiod 9..7 R/W „d1 Connect to PHY3

P
phy3_hperiod 6..4 R/W „d3 Connect to PHY3
phy3_last 3..2 R/W „d2 Connect to PHY3
host_ovr_current_value 1 R/W „b0
host_ovr_current_sel 0 R/W „b0

a
1.133 REGISTER:: USB3_U3_HOST_SOFT_Reset
0x9801_3F00

n
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3F00
USB3_U3_HOST_SOFT_

a
RESET
Name Bits R/W Default Comments
Rvd 31..3 - - -

n
rstn_usb2_phy1 2 R/W „b0 USB2 PHY1 reset for USB2 IP
rstn_usb2_phy0 1 R/W „b0 USB2 PHY0 reset for USB2 IP
„b0

a
rstn_usb2 0 R/W USB2 IP system reset

B
1.134 REGISTER:: USB3_U3_HOST_GBL_USB_CT
0x9801_3F04

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3F04

USB3_U3_HOST_GBL_U
SB_CT
Name Bits R/W Default Comments
usb_mac_ctrl 31..0 R/W „d0 Register use for usb_mac_ctrl

1.135 REGISTER:: USB3_U3_HOST_GBL_USB_ARB

0x9801_3F08

Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3F08

USB3_U3_HOST_GBL_U
SB_ARB

DVD R1 Architecture Specification 44

 Name Bits R/W Default Comments
Rvd 31..4 -
dbus_robin_enable 3 R/W „b0
cmd_full_number 2..1 R/W „d3
dbus_arb_priority 0 R/W „b0

1.136 REGISTER:: UNUSED 0x9801_3F0C

1.137 REGISTER:: USB3_U3_HOST_OTG_STS

i
0x9801_3F10

P
Module::usb Register::USB3_U3_HOST_ Set::1 ATTR::nor Type::SR ADDR::0x9801_3F10
OTG_STS e
Name Bits R/W Default Comments
Rvd 31..1 - - -
otg_interrupt 0 R „b0 OTG interrupt from USB3 MAC

1.138 REGISTER:: USB3_U3_HOST_USB_BC_STS

0x9801_3F14

n a
a
Module::usb Register:: Set::1 ATTR::nor Type::SR ADDR::0x9801_3F14
USB3_U3_HOST_USB_
BC_STS

n
Name Bits R/W Defau Comments
lt

a
Rvd 31..2 - - -
chirp_on 1 R „b0 battery charging chirp signal from USB3 MAC
bc_interrupt 0 R „b0 battery charging interrupt from USB3 MAC

Name
Rvd
B
1.139 REGISTER:: USB3_U3_HOST_BIST1_CTRL
0x9801_3F18 (IP sram)

Module::usb Register::USB3_U3_HOST_
BIST1_CTRL
Bits
31..28
R/W
-
Set::1

Default
-
ATTR::ctrl

Comments
-
Type::SR ADDR::0x9801_3F18

usb3_bist1_ls[2:0] 27..25 R/W 3‟h0 SRAM0~2 LS value

usb3_bist1_rm_3 24..21 R/W 4‟h0 SRAM3 RM value
usb3_bist1_rme_3 20 R/W „b0 SRAM3 RM enable
usb3_bist1_rm_2 19..16 R/W 4‟h0 SRAM2 RM value
usb3_bist1_rme_2 15 R/W „b0 SRAM2 RM enable
usb3_bist1_rm_1 14..11 R/W 4‟h0 SRAM1 RM value
usb3_bist1_rme_1 10 R/W „b0 SRAM1 RM enable
usb3_bist1_rm_0 9..6 R/W 4‟h0 SRAM0 RM value
usb3_bist1_rme_0 5 R/W „b0 SRAM0 RM enable

DVD R1 Architecture Specification 45

usb3_drf_1_test_resume 4 W/R „b0 USB3 DRF BIST1 trigger resume signal
usb3_drf_bist1_en 3 W/R „b0 USB3 DRF BIST1 enable
usb3_bist1_en 2 W/R „b0 USB3 BIST1 enable
Rvd 1 - - -
usb3_bist1_test_mode 0 W/R „b0 USB3 BIST1 test mode enable

1.140 REGISTER:: USB3_U3_HOST_BIST2_CTRL

0x9801_3F1c (PPsram)

Module::usb Register::USB3_U3_HOST_ Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3F1c

BIST2_CTRL

i
Name Bits R/W Default Comments
Rvd 31..17 - - -
usb3_bist2_ls[1:0] 16..15 R/W 2‟h0 SRAM4~5 LS value

P
usb3_bist2_rm_1 14..11 R/W 4‟h0 SRAM5 RM value
usb3_bist2_rme_1 10 R/W „b0 SRAM5 RM enable
usb3_bist2_rm_0 9..6 R/W 4‟h0 SRAM4 RM value
usb3_bist2_rme_0 5 R/W „b0 SRAM4 RM enable
usb3_drf_2_test_resume 4 W/R „b0 USB3 DRF BIST2 trigger resume signal

a
usb3_drf_bist2_en 3 W/R „b0 USB3 DRF BIST2 enable
usb3_bist2_en 2 W/R „b0 USB3 BIST2 enable
Rvd 1 - - -

n
usb3_bist2_test_mode 0 W/R „b0 USB3 BIST2 test mode enable

a
1.141 REGISTER:: USB3_U3_HOST_BIST1_STS
0x9801_3F20

Module::usb

Name

a
ST1_STS
Bits
n
Register::USB3_U3_HOST_BI

R/W
Set::1

Default
ATTR::nor

Comments
Type::SR ADDR::0x9801_3F20

B
Rvd 31..11 - - -
usb3_drf_bist1_fail_3 10 R „b0 USB3 DRF1 SRAM3 fail signal
usb3_bist1_fail_3 9 R „b0 USB3 BIST1 SRAM3 fail signal
usb3_drf_bist1_fail_2 8 R „b0 USB3 DRF1 SRAM2 fail signal
usb3_bist1_fail_2 7 R „b0 USB3 BIST1 SRAM2 fail signal
usb3_drf_bist1_fail_1 6 R „b0 USB3 DRF1 SRAM1 fail signal
usb3_bist1_fail_1 5 R „b0 USB3 BIST1 SRAM1 fail signal
usb3_drf_bist1_fail_0 4 R „b0 USB3 DRF1 SRAM0 fail signal
usb3_bist1_fail_0 3 R „b0 USB3 BIST1 SRAM0 fail signal
usb3_drf_1_start_pause 2 R „b0 USB3 DRF1 start pause signal
usb3_drf_bist1_done 1 R „b0 USB3 DRF1 done
usb3_bist1_done 0 R „b0 USB3 BIST1 done

1.142 REGISTER:: USB3_U3_HOST_BIST2_STS

0x9801_3F24

Module::usb Register::USB3_U3_HOS Set::1 ATTR::nor Type::SR ADDR::0x9801_3F24

DVD R1 Architecture Specification 46

 T_BIST2_STS
Name Bits R/W Default Comments
Rvd 31..7 - - -
usb3_drf_bist2_fail_1 6 R „b0 USB3 DRF2 SRAM5 fail signal
usb3_bist2_fail_1 5 R „b0 USB3 BIST2 SRAM5 fail signal
usb3_drf_bist2_fail_0 4 R „b0 USB3 DRF2 SRAM4 fail signal
usb3_bist2_fail_0 3 R „b0 USB3 BIST2 SRAM4 fail signal
usb3_drf_2_start_pause 2 R „b0 USB3 DRF2 start pause signal
usb3_drf_bist2_done 1 R „b0 USB3 DRF2 done
usb3_bist2_done 0 R „b0 USB3 BIST2 done

1.143 REGISTER:: USB3_U3_HOST_APHY_REG

i
0x9801_3F28
Module::usb Register::USB3_U3_HOST Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3F28
_APHY_REG

P
Name Bits R/W Default Comments
Rvd 31..5 - - -
usb3_clk_mode_sel 4..3 R/W „b00 “11” : Diff. 100MHz in, else
CKIN_XTAL in.
IN RL6227 .CKREF comes from

a
CKIN_XTAL, tie “00”.
usb3_ckbuf_en 2 R/W „b0 CKREF Buffer Enable tie 0
usb3_mbias_en 1 R/W „b1 Bias Circuit Enable.

n
1: Bias Circuit enable
0: Bias Circuit disable
usb3_bg_en 0 R/W „b0 Bandgap Enable. IN RL6227,no

a
BG inside the USB3.0 block, tie 0

n
1.144 REGISTER:: USB3_U3_HOST_BC_STS2_REG
0x9801_3F2C
Module::usb Register::USB3_U3_HOST Set::1 ATTR::nor Type::SR ADDR::0x9801_3F2C

a
_BC_STS2_REG
Name Bits R/W Default Comments

B
Rvd 31..8 - - -
hst_prtbl_det_0_usb3 7 R „b0
hst_comp_out_0_usb3 6 R „b0 Debug signal
hst_sh_out_0_usb3 5 R „b0 Debug signal
hst_v0p07_out_0_usb3 4 R „b0 DP>0.35V, output=low,
DP<0.35V, output=high
hst_v0p41_out_0_usb3 3 R „b0 DM>THD, output=low,
DM<THD, output=high
hst_v0p46_out_0_usb3 2 R „b1 don't care. Output=high.
dev_chg_det_0_usb3 1 R „b0 Detector result
dev_dcp_det_0_usb3 0 R „b0 Detector result

1.145 REGISTER:: USB3_U3_HOST_BC_CTL_REG

0x9801_3F30
Module::usb Register::USB3_U3_HOST Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3F30
_BC_CTL_REG
Name Bits R/W Default Comments
Rvd 31..15 - - -
lf_pd_r_en_0_usb3 14 R/W „b1

DVD R1 Architecture Specification 47

hst_pow_charge_0_usb3 13 R/W „b0 Enable charge, high enable
hst_vdm_src_en_0_usb3 12 R/W „b0 Enable VDM_SRC output, high
enable
hst_idp_sink_en_0_usb3 11 R/W „b0 Enable DP current sink, high
enable
hst_app_div_en_0_usb3 10 R/W „b0 Enable Apple mode, high enable
hst_app_div_sel_0_usb3 9 R/W „b0 Select Apple charge current
2.1A/1A
0: DP=2.0V, DM=2.7V
1: DP=2.7V, DM=2.0V
hst_dcp_app_comp_en_0_u 8 R/W „b0 Enable comparator for detect
sb3 Apple/DCP mode, high enable
hst_note_div_en_0_usb3 7 R/W „b0 Enable NOTE mode, high enable,

i
DP=1.25V
hst_dcp_en_0_usb3 6 R/W „b0 Enable DCP mode, high enable,
short DP and DM.

P
dev_pow_charge_0_usb3 5 R/W „b0 Enable charger, high enable
dev_dcp_chg_mode_0_usb 4 R/W „b0 0: select CHG_DET detect
3 1: select DCP_DET detect
dev_vdp_src_en_0_usb3 3 R/W „b0 Enable DP output voltage, high
enable
dev_vdm_src_en_0_usb3 2 R/W „b0 Enable DM output voltage, high

a
enable
dev_idp_sink_en_0_usb3 1 R/W „b0 Enable DP current sink, high

n
enable
dev_idm_sink_en_0_usb3 0 R/W „b0 Enable DM current sink, high
enable

a
1.146 REGISTER:: USB3_U3_HOST_DUMMY_0_REG
0x9801_3F34

n
Module::usb Register::USB3_U3_HOST Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3F34
_DUMMY_0_REG

a
Name Bits R/W Default Comments
dummy_0 31..0 R/W 32‟h0 Dummy register,default:0

B
1.147 REGISTER:: USB3_U3_HOST_DUMMY_1_REG
0x9801_3F38
Module::usb Register::USB3_U3_HOST Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3F38
_DUMMY_1_REG
Name Bits R/W Default Comments
dummy_1 31..0 R/W 32‟hFFFF_FFF Dummy register,default:1
F

1.148 REGISTER:: USB3_U3_HOST_LTSSM_STS

0x9801_3F3C
Module::usb Register::USB3_U3_HOST Set::1 ATTR::nor Type::SR ADDR::0x9801_3F3C
_LTSSM_STS
Name Bits R/W Default Comments
Rvd 31..4 - - -
Ltdb_sub_state 3..0 R „b0 Ltssm sub-state from USB3 IP

DVD R1 Architecture Specification 48

1.149 REGISTER:: USB3_U3_HOST_USB_DBUS_PWR_CTRL
0x9801_3F60
Module::usb Register:: Set::1 ATTR::ctrl Type::SR ADDR::0x9801_3F60
USB3_U3_HOST_USB_D
BUS_PWR_CTRL
Name Bits R/W Default Comments
Rvd 31..12 - - -
clk_en_gap 11..10 R/W „h0 00:50ns
01:300ns

i
10:500ns
11:1us
sram_ls_gap 9..8 R/W „h0 00:200ns

P
01:300ns
10:100ns
11:500ns
Rvd 7..2 - - -
dbus_pwr_ctrl_sw_rst 1 R/W „h0 dbus power ctrl software reset to
idle

a
dbus_pwr_ctrl_en 0 R/W „h0 dbus power ctrl enable

a n
a n
B
DVD R1 Architecture Specification 49