A NOVEL LOW POWER ENERGY RECOVERY

FULL ADDER CELL

R. Shalem’, E. John* and L. K. John’

’ Electrical and Computer Engineering 2 Electrical Engineering

The University of Texas at Austin The University of Texas - Pan American
Austin, TX 78712 Edinburg, TX 78539

Abstract
A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this
paper. The power consumption and general characteristics of the SERF adder are then compared against
three low powerful1 adders; the transmission function adder (TFA), the dual value logic (DVL) adder and
the fourteen transistor (14T)full adder. The proposed SERF adder design was proven to be superior to the
other three designs in power dissipation and area, and second in propagation delay only to the DVL adder.
The combination of low power and low transistor count makes the new SERF cell a viable option for low
power design.

1. Introduction load capacitance during logic level high is drained

to ground during logic level low. An energy
The explosive growth in laptop and portable recovering logic reuses charge, which charges the
systems and in cellular networks has intensified the load capacitance during logic high to drive the
research efforts in low power microelectronics. gates rather than draining charge to ground.
Today there is an ever-increasing number of Tzartzanis et al [2] recently proposed an energy
portable applications requiring low power and high recovering adder which was shown to be power
throughput than ever before. For example, efficient however it required complex dynamic
notebook and laptop computers, representing the logic for its operation.
fastest growing segment of the computer industry,
are demanding the same computation capabilities as In this paper we present a new low power full adder
found in desktop machines. Equally demanding are design, namely the Static Energy-Recovery Full
developments in personal communication services Adder (SERF). The proposed low power energy-
(PCS’s), such as the current generation of digital recovering logic consumes less energy and has a
cellular telephony networks which employ complex lower transistor count than previously proposed full
speech compression algorithms and sophisticated adder cells. In order to demonstrate the efficiency
radio modems in a pocket sized device. Even more of the new design, in this paper, we compare the
dramatic are the proposed future PCS applications, power consumption and other general
with universal portable multimedia access characteristics of the SERF design against three
supporting full motion digital video and control via other low power full adder cells proposed in past
speech recognition [I]. Thus, designing low-power literature [6] [7] [8].
digital systems especially the processor is
becoming equally important to designing a high 2. Background and Prior Research
performance one.
The three major components that contribute to the
An adder is one of the most critical components of power consumption in CMOS circuits are the static
a processor which determines its throughput, as it is dissipation due to leakage current, the dissipation
used in the ALU, the floating-point unit, and for due to switching transient current and the
address generation in case of cache or memory dissipation due to charging and discharging of load
access. Recently there have been several attempts capacitance. The total power in a CMOS circuit is
to design energy recovering logic in the pursuit of given by the following equation [4]
energy efficient circuitry [2,3]. Energy recovering
logic reuses charge and therefore consumes less
power than non-energy recovering logic. In non-
energy recovering logic the charge applied to the

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 where VDD is the power supply voltage, v,wlnR is the
voltage swing of the output which is ideally equal
to VDD, Cloti is the output load capacitance at node
i, f is the system clock frequency, P, is the
switching activity at node i, I,,< is the short circuit
current at node i, and 1, is the leakage current. The
summation is over all the nodes of the circuit. It is
important to note that, in simulation studies, the
number of simulation cycles that are needed for
accurate estimation of the switched capacitance is
critical. It is recommended to have between 50 and
100 simulation cycles for an accurate estimation of
the capacitance 151. A reduction in any of the
appropriate components in the above equation will Figure 2. The dual value logic (DVL) adder [7]
obviously reduce power consumption.
A B-
Several designs of low power adder cells can be
found in the literature [6] [7] [8]. The transmission
function full adder [6], which uses 16 transistors for
the realization of the circuit, is shown in Figure 1.
For this circuit there are two possible short circuit
paths to ground. This design uses both pull-up and
pull-down logic as well as complementary pass
logic to drive the load. The DVL full adder [7]
illustrated in Figure 2, uses 23 transistors for the
realization of the adder function. DVL was
developed to improve the characteristics of double
pass transistor logic which was designed to have
the logic level high signal passed to the load
through a p-transistor and the logic level low
Figure 3. The fourteen transistor (14T) adder [8]
drained from the load through an n-transistor. The
fourteen transistor full-adder [8], as the name
3. Static Energy-Recovery Full Adder
implies, uses 14 transistors to realize the adder
function (See Figure 3). To date this is the most
As an initial step toward designing low power
area efficient design. The 14T full adder cell, like
arithmetic circuit modules, we designed a Static
the transmission function full adder cell,
Energy Recovery Full adder (SERF) cell module
implements the complementary pass logic to drive
illustrated in Figure 4. The cell uses only 10
the load. The performance of these three adder
transistors and it does not need inverted inputs. The
circuits is compared with the new SERF adder
design was inspired by the XNOR gate full adder
design and the results are given in the following
design. In non-energy recovery design the charge
section.
applied to the load capacitance during logic level
high is drained to ground during the logic level low.
It should be noted that the new SERF adder has no
direct path to the ground. The elimination of a path
to the ground reduces power consumption,
removing the Psc variable (product of Isc and
voltage) from the total power equation. The charge
stored at the load capacitance is reapplied to the
control gates. The combination of not having a
B
direct path to ground and the re-application of the
load charge to the control gate makes the energy-
recovering full adder an energy efficient design. To
Figure 1. The transmission function adder (TFA) the best of our knowledge this new design has the
lowest transistor count for the complete realization
[61 of a full adder.

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 that the SERF cell is far superior in transistor count
with only 10 transistors. While transistor count is
an inaccurate method for area analysis, transistor
count does provide a guideline as to possible die
area consumption for the differing design
structures. Table 2 illustrates the results for the 8-
bit ripple carry adders. A graphical comparison of
delay and power are presented in Figures 5 and 6.

Table 1 Delay and Area Comparison Results for 2-

bit RCA Analysis

Figure 4. The New Static Energy-Recovery Full

(SERF) Adder COUT COUT
TYPE DELAY DELAY TRANSISTOR
The performance of the SERF full adder cell is ( ) ( ) COUNT
compared for power consumption, delay and silicon S E R F 2.;:32 I;;33 10
area against the transmission function adder (TFA) TFA 2.0000 1.0938 16
[6], dual value logic (DVL) adder [7], and the DVL 1.0625 0.6667 23
fourteen transistor (14T) adder [8]. 14T 1.5789 0.8615 14

4. Simulation Methodology and Results

Two bit and eight bit ripple carry adders using the
previously discussed full adder cells as basic blocks
were constructed and modeled in PSPICE using Table 2 Energy Consumption and Delay
1.2~ and 0.6~ transistors. The SERF and the three Comparison Results for the g-bit RCA Analysis
full adders chosen from the literature (and shown in
Figures 1, 2 and 3), were modeled. The simulations
were conducted at SOMHz to 2OOMHz for 300ns
while skipping initial transient solution. Buffers
were placed between the full adder stages of the
ripple carry adders to allow for strong signal
propagation. All input and output signals were TFA 0 3 7 ’ 0.75 1.40 0.10’0.20’0393’ 6.13 4.63

buffered. DVL 035 0.65 1.66 0.92 0.21 0 422 5.44 3.26

14T 0.45 0.79 1.25 0.16 0.20 0.356 7.33 4.19

The power consumed by the adders was determined

by the following equation [ 11.
A careful examination of the results shows that the
T proposed SERF adder design takes approximately
P total = VDD ‘bmtanmus
26% to 55% less energy than the other three
10 designs chosen from the literature for error free
operation. The DVL adder was the fastest, however
Where V,, is the supply voltage, IinS,~n~~~~~ is the it used 23 transistors and 50% more energy than the
instantaneous supply current and T is the simulation SERF did. Compared to the 14T adder design,
cycle time. This method of power estimation takes which is the fastest among the remaining adder
into account static, dynamic and short circuit power designs selected for comparison, the SERF design
dissipation to give a complete and accurate power is shown to be 19% faster. Since the new SERF
dissipation analysis for Ptoto,. design needs only 10 transistors for the adder
circuit realization obviously it is the most area
The results of the simulations for the 2-bit full efficient design.
adders are presented in Table 1. The results show

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 Power Comparison
Circuits, Vol. 27, No.4, pp. 473-483, April
1992.

P N. Tzartzanis and W. C. Athas, “Design and

Analysis Design”, IEEE Journal of Solid State
of a Low-Power Energy-Recovery Adder”,
Proceedings of the IEEE Great Lakes
Symposium on VLSI, 1995, pp. 66-69.

13 K. P. Parhi, “Fast Low-Energy VLSI Binary

Addition”, Proceedings of the International
Conference on Computer Design, 1997, pp.
676-684.
Figure 5. Comparison of Power Consumption of 8-
bit SERF Adder to Other Full Adders [41 Gerard M Blair, “Designing low power
CMOS”, IEEE Electronics and
Communication Engineering Journal, vol. 6,
No. 5, pp. 229-236, October 1994.
Propagation delay
[51 A. P. Chandrakasan, and R. W. Broderson,
“Low Power Digital CMOS Design”, Kluwer
0 SERF Academic Publishers, Boston, MA, 1995.
n TFA
0 DVL
q 14T [61 Nan Zhuang and Haomin Wu, “A new design
of the CMOS full adder” IEEE Journal of
3.3V - 0.6~ 5v - la
Solid State Circuits, Vol. 27, No.5, pp. 840-
844, May 1992.

Figure 6. Comparison of Propagation Delay of [71 V. G. Oklobdzija, M Soderstrand and B.

Various g-bit Full Adders Duchene “Development and Synthesis
Method for Pass-Transistor Logic Family for
High-Speed a n d L o w P o w e r C M O S ”
5. Conclusion Proceedings of the 1995 IEEE 38th Midwest
Symposium on Circuits and Systems, Rio de
In this paper we presented a novel low power and Janeiro, 1995.
low transistor count static energy-recovering full
adder and compared its performance against three PI Ahmed M. Shams and Magdy A. Bayoumi,
other full adder cells for power consumption, area “A New Full Adder Cell for low-power
and delay. The three full adder cells for Applications”, Proceedings of the IEEE Great
comparison against SERF adder were selected Lakes Symposium on VLSI, 1998, pp. 45-49.
recent literature on the topic of low power design.
Analysis and simulation studies were performed on [91 E. Abu-Shama, A. Elchouemi, S. Sayed and
2-bit and 8-bit ripple carry adders. The proposed M. Bayoumi, “An Efficient Low Power Basic
SERF adder design was proven to be superior to the Cell for Adders” Proceedings of the 1995
other three designs in power dissipation and area, IEEE 38th Midwest Symposium on Circuits
and second in propagation delay only to the DVL and Systems, Rio de Janeiro, 1995:
adder. The combination of low power and low
transistor count makes the new SERF adder cell a * E. John’s research is supported by the National
viable option for low power design. Science Foundation under grant number ECS-9714993.
L. John’s research is supported by the National Science
Foundation under grant numbers CCR-9796098, EIA-
9807112, the State of Texas Advanced Technology
References Program and the University of Texas.

[II A. P. Chandrakasan, S. Sheng, and R. W.

Broderson, “Low Power CMOS Digital

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