EE 658

Diagnosis and Design of Reliable

Digital Systems

Lecture 11:
Delay faults, tests and testing

University of Southern California

Viterbi School of Engineering
Ming Hsieh Dept. of Electrical Engineering
Moe Tabar
Fall 2019

References: Dr. Brueur’s lecture slides, books listed in the syllabus, and online resources
Outline
⚫ Why circuits have delay?
⚫ What is a delay fault?
⚫ What is a test for a delay fault?
⚫ How do we generate tests for delay faults?
⚫ How are these tests applied to the CUT?

Dr. Moe Tabar - EE 658 2

Introduction
⚫ Goal of Delay Testing
◦ Primary: Verify circuit timing (e.g. clock
frequency) over supply voltage and
temperature range
◦ Secondary: Identify marginal circuits that
meet specifications

Dr. Moe Tabar - EE 658 3

 Animation

Transistor delay (NAND gate)

0→ 1 Let V1=(A, B)=(0, 1) and V2=(1,
1
A B 1), so C goes from 1 to 0. It
takes time for A to change and
C for the nFET driven by A to
Q turn ON; this can be modeled
Cp by an input delay. It takes time
to discharge the output load
capacitance; this can be
modeled by an output delay.

Dr. Moe Tabar - EE 658 4

Manufacturing defects

Dr. Moe Tabar - EE 658 5

Circuit delays
⚫ Delay is a function of
many factors
A B D including line
C
Cload
resistance,
CP capacitance to
substrate (CP) and
other wires, load
t1 t2 t3 t4 capacitance (Cload),
transistor threshold
A voltage, transistor
gain, etc.
B ⚫ Signal/transition/
C propagation delay
occurs in wires and
D gates.
⚫ It takes time to
t2-t1= gate B delay charge/discharge a
t3-t2= interconnect delay
capacitor.
t4-t3= gate D delay

Dr. Moe Tabar - EE 658 6

 Circuit delays
⚫ Here gate B has
A B C D more delay than
Cload intended.
CP
⚫ Sometimes delay is
measured from 50%
t1 t2 t3 t4 of input swing to
50% of output swing.
A
⚫ What is really
B
important is when
C does a signal cross
D the respective
threshold voltage for
a device.

Dr. Moe Tabar - EE 658 7

Why does delay vary and how
does this hurt?
⚫ Process variation
⚫ Defects
⚫ Crosstalk
⚫ Ground bounce
⚫ Etc.

⚫ So it is important in modern high-speed circuits to

test for delay faults, i.e., effects that slow up signal
propagation an unacceptable amount.
⚫ Such effects change the set-up and hold-times on
signals in synchronous circuits, and can lead to
steady state errors.

Dr. Moe Tabar - EE 658 8

 Delays associated with signal transitions
▪ Assume a single lumped inertial delay model for each gate
▪ Assume PI transitions occur with zero time skew

Path P1

13
0 1

246
P2 1

Capture
2 Time
0 33
P3

0 2 5

▪ We expect output to be stable after 6 unit of delay

Dr. Moe Tabar - EE 658 9

 Delays associated with signal transitions
▪ Assume a single lumped inertial delay model for each gate
▪ Assume PI transitions occur with zero time skew

Path P1

13
0 1

24 9
P2 4-fault

Capture
2 Time
0 33 (error)
P3

0 2 5

▪ Last OR gate has delay fault!!

Dr. Moe Tabar - EE 658 10

 Digital circuit timing
Input Output Transient
signals signals region Stable
change captured region

Inputs
Comb.
logic

Outputs
Synchronized
with clock

time
Clock period

Dr. Moe Tabar - EE 658 11

Huffman Sequential Circuit Model
⚫ Primary Inputs (PI) x1, x2,…
⚫ Primary Outputs (PO) z1, z2,…
⚫ Pseudo Primary Inputs (PPI)
y1, y2,…
⚫ Pseudo Primary Outputs (PPO)
Y1, Y2,…

Dr. Moe Tabar - EE 658 12

Delay Testing Approaches (1)
⚫ Random
◦ Apply random patterns at rated clock speed
◦ Advantages
● Can generate patterns on-chip (BIST)
● Applied as in normal operation
● Fortuitous detection of unmodeled faults
◦ Disadvantages
● Poor coverage of long paths
● Higher than normal circuit activity (power, noise)

Dr. Moe Tabar - EE 658 13

Delay Testing Approaches (2)
⚫ Functional
◦ Apply functional patterns at rated clock speed
◦ Advantages
● Most accurate test
● Chip operating in normal mode
● Fortuitous detection of unmodeled faults
◦ Disadvantages
● Poor coverage, coverage difficult to compute
● High test pattern development cost
● High test application cost without large on-chip
cache/memory

Dr. Moe Tabar - EE 658 14

Delay Testing Approaches (3)
⚫ Structural
◦ Use delay fault models and circuit structure to
generate tests
◦ Advantages
● Automatic test pattern generation
● High fault coverage
● Easier diagnosis
◦ Disadvantages
● Simplifying assumptions in delay fault model
● Design for testability (DFT) required for high coverage
● Test application very different than normal operation

Dr. Moe Tabar - EE 658 15

 Circuit Delay Models (1)
⚫ Some delay fault models need circuit
delays
⚫ Gate delay
◦ Delay from gate input to output
◦ Can have different delays for rising or falling
transitions, different inputs to outputs
◦ Interconnect delay lumped with gate
⚫ Gate transport delay
◦ Gate delay without interconnect delay
⚫ Interconnect propagation delay
◦ Separate delay to each net fanout (gate
input)

Dr. Moe Tabar - EE 658 16

Circuit Delay Models (2)
⚫ Inertial delay
◦ Minimum pulse width that propagates
through a gate
◦ Used to analyze glitch generation and
propagation
⚫ Min-max delay
◦ Abstraction of process variation
◦ Gate and interconnect delay correlations
usually not available

Dr. Moe Tabar - EE 658 17

Delay Test Application (1)
⚫ Launch transitions into circuit from PIs
and PPIs (referred to collectively as PIs)
⚫ Capture circuit response at POs and
PPOs (collectively POs) at specified time
⚫ Compare results with correct response
⚫ Two-pattern test required to launch
transitions:
◦ First (initialization) vector initializes circuit
◦ Second (test) vector launches transitions

Dr. Moe Tabar - EE 658 18

 Delay Test Application (2)
⚫ We need a two vector test to detect a delay fault. But
how to hold two test vectors in scan chains?
⚫ There are three well known architectures to do delay
testing.
◦ Enhanced scan – holding-latch on output of flip-flop
● Scan first vector in, transfer to holding latches, scan second
vector in, enable holding latches launches transitions
● Expensive in area and delay, so seldom used
◦ Launch-on-shift (LOS) – also known as skewed load,
launch-off-shift. Uses a shifted version of the first vector as
the second vector.
◦ Launch-on-capture (LOC) – also known as broadside
test, or double-capture, launch-off-capture) uses the
functional response of the first vector as the second vector.
⚫ Details later

Dr. Moe Tabar - EE 658 19

 Transition Fault Model (a.k.a. gate
delay model)
⚫ Assumes a large/gross delay is present at a circuit
node (gate or interconnect)
◦ Slow-to-rise (STR), slow-to-fall (STF)
⚫ Irrespective of which path the effect is propagated, the
gross delay defect effect will be late arriving at an
observable point
⚫ Most commonly used in industry
◦ Simple and number of faults linear to circuit size
◦ Also needs 2 vectors to test
⚫ Node x slow-to-rise (x-STR) can be modeled simply as
two stuck-at faults
◦ First time-frame: x Sa1 needs to be excited (put 0 on it)
◦ Second time-frame: x Sa0 needs to be excited and propagated
(put 1 on it)
◦ This produces a 0 to 1 transition at x.

Dr. Moe Tabar - EE 658 20

 Enhanced scan 1/5
Scan flip-flop register R1

Scan flip-flop register R2

C

Latch register L1

R1 is the input scan register; R2 is the output scan register; and L1 is a latch
based register used to hold the test vector V1.

Dr. Moe Tabar - EE 658 21

 Enhanced scan 2/5
1
Scan flip-flop register R1 0

Scan flip-flop register R2

0
1
C

Latch register L1

First V1 is scanned into R1.

Dr. Moe Tabar - EE 658 22

 Enhanced scan 3/5
1 1
Scan flip-flop register R1 0 0

Scan flip-flop register R2

0 0
1 1
C

0 0

Latch register L1

Secondly, V1 is parallel loaded from R1 into L1

Dr. Moe Tabar - EE 658 23

 Enhanced scan 4/5
1 1
0 0
Scan flip-flop register R1

Scan flip-flop register R2

1 0
1 1
C

1 0

Latch register L1

Next R1 is loaded with V2.

Dr. Moe Tabar - EE 658 24

 Enhanced scan 5/5
1 1
0 0
Scan flip-flop register R1

Scan flip-flop register R2

1 0⇾1
1 1
C

1 0⇾1

Latch register L1

Finally V2 is loaded into L1 creating transitions at the input to C that are

intended to propagate through C and be captured in R2.

Dr. Moe Tabar - EE 658 25

 Transition fault testing with stuck-at
vectors for enhanced scan

⚫ First perform Stuck-at ATPG for stuck-at faults

⚫ Then build a dictionary for the vectors generated,
i.e., which vectors detect which faults
⚫ Use the dictionary to identify vector-pairs for each
transition fault
⚫ This works if the test hardware uses enhanced
scan

Dr. Moe Tabar - EE 658 26

 Launch-on-shift approach
Last scan-in
Launch cycle Capture cycle
shift cycle

Scan 1 Scan-in
enable 0
A
Combinational
Circuit
1
B

Scan-out
Dr. Moe Tabar - EE 658 27
Launch-on-shift approach
Last scan-in
Launch cycle Capture cycle
shift cycle

Scan 1
enable 0
A
Combinational
Circuit
1
B

Dr. Moe Tabar - EE 658 28

Launch-on-shift approach
Last scan-in
Launch cycle Capture cycle
shift cycle

Scan Scan-in
enable 1
A
Combinational
Circuit
0
B

Scan-out
Dr. Moe Tabar - EE 658 29
Launch-on-shift approach
Last scan-in
Launch cycle Capture cycle
shift cycle

Scan Scan-in
enable 1
A
Combinational
Circuit
0
B

Scan-out
Dr. Moe Tabar - EE 658 30
 Launch-on-shift approach Steps
●

●
Launch-on-shift implication
Scan-in

1X
A Combinational
Circuit

X0
C

Scan-out
Dr. Moe Tabar - EE 658 32
Launch-on-shift implication (cont.)
● Scan-in

Dr. Moe Tabar - EE 658 33

Untestable transition fault
⚫ STF on signal d is untestable under
Launch on Shift
◦ Second vector needs to be abc=000
◦ First vector must then be abc=00X

Dr. Moe Tabar - EE 658 34

 Launch-on-shift test generation
1
C(t) 0 C(t+1)
X
1
0 X 1 X

Sout

Make an iterative array of depth two. In second time frame develop a test for a
SAF at fault line (for example ith primary input in this case). This results in the
state of the scan register at time t+1. Next reflect these values back to the
register at time t, remembering that this is one shift backwards. Also set the i th
scan flip flop to the opposing value compared to the state at t+1 so as to impose
a transition. Then imply this state forward. Then solve the justification problem
for time frame t. If no solution, backtrack.

Dr. Moe Tabar - EE 658 35

Launch-on-shift summary
⚫ Pro
◦ If scan design is used then very little overhead
⚫ Con
◦ Constraints placed on the vectors
◦ Larger test volume because you need many
tests
◦ The scan-enable signals must be able to
operate at full speed.

Dr. Moe Tabar - EE 658 36

Launch-on-capture approach
Last scan-in Launch Capture
Dummy cycle
shift cycle

Scan Scan-in
enable 0
A
Combinational
Circuit
1
B

Scan-out
Dr. Moe Tabar - EE 658 37
Launch-on-Capture Approach
Last scan-in
Dummy cycle Launch Capture
shift cycle

Scan Scan-in
enable 0 0
A
Combinational
Circuit
1 0
B

Scan-out
Dr. Moe Tabar - EE 658 38
Launch-on-Capture Approach
Last scan-in
Dummy cycle Launch Capture
shift cycle

Scan Scan-in
enable 0 0
A
Combinational
Circuit
0 1
B

Scan-out
Dr. Moe Tabar - EE 658 39
Launch-on-Capture Approach
Last scan-in Launch Capture
Dummy cycle
shift cycle

Scan Scan-in
enable 0
A
Combinational
Circuit
0
B

Scan-out
Dr. Moe Tabar - EE 658 40
 Launch-on-Capture Approach Steps
●
●

●
Launch-on-Capture Implication
Scan-in

A Combinational
Circuit
1X
B

X0
C

Scan-out
Dr. Moe Tabar - EE 658 42
Launch-on-capture test generation
R(t) R(t+1) R(t+2)
1 1
1 C(t) 0 C(t+1)
1 Justify X
0
0 X 1 X
X 1

Sout

For the target node X in time frames t and t+1 we place opposite logic
values to ensure that a transition is established. We then generate a test for
a SAF at X in time frame t+1, thus sensitizing a path from X to a PO. We
then justify the values in R(t+1) and the value on X (opposite value of
C(t+1)) in C(t) to determine the state of R(t).
To apply the test we scan in R(t), wait for a slow clock and capture the data
in R(t+1) which launches a transition that is captured with a real time clock
in R(t+2).

Dr. Moe Tabar - EE 658 43

Pros and cons of launch-on-capture
⚫ Pro
◦ Second vector is functional
◦ Less constraints than launch-on-shift
◦ Scan en does not have to work with at speed
clock
⚫ Con
◦ More tests than enhanced scan

Dr. Moe Tabar - EE 658 44

 One taxonomy of delay faults
⚫ Delay fault (DF) - a fault that affects the temporal (timing)
behavior of an element, such as a gate or wire.
◦ Gate delay fault (GDF) - an input or output of a gate has a
lumped DF manifested as a slow to rise (0→1) or slow to fall
(1→0) transition.
● Gross gate delay fault (G-GDF) - a very large delay, and
hence any transition from a PI to a PO through this gate will be
seriously delayed; sometimes referred to as a transition fault
(TF). The delay is at least longer than a clock period.
● Small gate delay fault (S-GDF) - a GDF that is not a
G-GDF
◦ Path delay fault (PDF) - a path from a PI line to a PO line that
is slow to propagate a rising or falling transition starting at the PI
and terminating at the PO.
● Depending on the direction of the transition at the input, there
are rising and falling PDFs

◦ The GDF is a weaker model than the PDF, i.e., a circuit can pass
a test for GDFs yet fail a test for PDFs.

Dr. Moe Tabar - EE 658 45

 READ only

Types of delay faults

Physical defects in integrated digital circuits cause a variety of failures, leading to
malfunctions either in the steady state or dynamic behavior of a circuit. To
overcome the complexity of the physical level, defects are modeled on a higher
level of abstraction, usually the gate level, for test generation purpose. Defects
degrading the dynamic behavior of a circuit are modeled as delay faults. The
amount of time a signal is delayed in presence of a defect is called delay fault size.
If a size greater an operational clock cycle is assumed, the model is called
transition fault model as well.
In order to solve the problem of dynamic testing, two delay fault models have
been proposed, the path delay fault model and the gate delay fault model.
A circuit is declared free of path delay faults, if it propagates a rising and a falling
transitions on every path of the circuit within the operational system clock
interval. In the gate delay fault model a lumped delay fault at a gates input or
output is assumed, that delays a transition through a faulty gate. The path delay
fault model is more exact. All distributed small delays causing malfunctions are
detected, if a test for each path can be found. In the gate delay fault model
distributed small delay faults are not addressed explicit and may stay undetected.

Dr. Moe Tabar - EE 658 46

Another delay fault taxonomy
• All Delay fault models in use today are logic models
• Transition Faults: Assumes large delay defect
concentrated at one logical node, such that any
signal transition passing through this node will be
delayed past the clock period. Same as a gate delay
fault (GDF).
• Path Faults: Assumes a distributed delay along a
combinational path from latch to latch. This model is
suitable to detect small delay defects.
• Segment Delay Fault Model: Assumes
distributed delay along a small segment of a long
path

Dr. Moe Tabar - EE 658 47

Other terms to be defined later
⚫ Robust test (RT)
⚫ Non-robust test (N-RT)
⚫ Hazard-free robust test (HF-RT)
⚫ Non-hazard-free robust test
⚫ Validatable non-robust test

Dr. Moe Tabar - EE 658 48

 Delay tests and testing for
combinational logic
We see that to test for a delay
xx E fault requires a test that
A S0 consists of at least two (2)
S0 vectors or patterns. In this
B F example, V1=<x010>, and
S0
V2=<x011>. The transition
S1 I starting at D is propagated
C G H
over a sensitized path to the
D output. S0 represents static 0
(no hazard)

Dr. Moe Tabar - EE 658 49

 Simplified view of test application
i o
n u
p R R t If the change in the output
u 1 C 2 p due to V2 does not get to
t u
s t the output register in time,
s the “old” value of the output
Φ1 Φ2 will be captured in R2, rather
than the “new” value, and an
Long enough for error will be detected.
inputs to R2 to This is the critical
be at steady state transition time This is often referred to as
being verified “slow-slow-fast” clocking.
Φ1
Φ2
t0 t1 t2
V1 applied to V2 applied to Outputs
C via R1 C via R1 sampled at
R2

Dr. Moe Tabar - EE 658 50

 Animation

Better late than never!

Dr. Moe Tabar - EE 658 51

Miscellaneous notes
⚫ Let DPmax be the maximum path delay allowed in a
circuit-determined by the designer
⚫ Then TC= t2-t1 ≥ DPmax
⚫ Thus running tests for stuck-at faults at a slow rate is
not an effective way to detect delay faults
⚫ V1 applied at t0 is referred to as the initialization
input vector
⚫ V2 applied at t1 is referred to as the test vector
⚫ An exhaustive delay test consists of applying all pairs
of vectors of the form < V1, V2>, where V1 ≠ V2.
⚫ For an n-input circuit, there are 2n(2n-1) such tests.

Dr. Moe Tabar - EE 658 52

 Pin-to-pin delay model
A DA In the “pin-to-pin” delay model
DC C that is commonly used, DA and DB
B DB are independent. In some more
advanced delay models, such as
delayless the simultaneous delay model,
they are not independent. That is,
A DA+ DC if transitions occur on both A and
C
DB+ DC B at nearly the same time, then the
B
delay through the gate is different
Simplified delay model than if only one transition occurs
and the other input is S1.
DX can be fairly complex; i.e.,
it can represent either
transport and/or inertial
delay, and the rise and fall
delays can be different.

Dr. Moe Tabar - EE 658 53

 Gate delay faults (GDFs)
⚫ Notation:
◦ Let x be a rising or falling transition
◦ Let md(r, x) be the largest modeled (design)
acceptable propagation delay for transition x through
circuit element r
◦ Let ad(r, x) be the actual propagation delay for
transition x through circuit element r in a CUT
◦ TC is the clock period of the CUT
◦ M(r, x) is the longest modeled delay of the longest
acceptable modeled delay of a path in the CUT that
includes r when there is a transition x on signal line r
⚫ Definition: Element r is said to have a transition x
fault in the CUT if ad(r, x) > md(r, x), and (ad(r, x)-md(r,
x)) is the size of the fault.
⚫ Definition: The x-slack (slack for transition x) of an
element or signal line r in a CUT is TC - M(r, x).

Dr. Moe Tabar - EE 658 54

 Transition x-fault and x slack

md(r, x)
ad(r, x)
M ( r , x)
slack
TC

The modeled slack is reduced by (ad(r, x)-md(r, x)).

Dr. Moe Tabar - EE 658 55

 Generating tests for gate delay faults

Some items to be considered

⚫ Single vs. multiple gate delay faults
⚫ Allowing for hazards
⚫ Employing more than one test for a single gate
delay to cover a range of delay values--not
discussed here

Dr. Moe Tabar - EE 658 56

 Example 1: A single gate delay fault

An interconnect or
gate delay fault
XX
00 X1 D
X1 C
11
X0 W
X1

∆ B
A’
11 A

01
X1
a path

Dr. Moe Tabar - EE 658 57

 Example 1 cont’d.
⚫ Find V1 such that A=0. (Can use D-Alg. or PODEM)
⚫ Find V2 such that it is a test for A s-a-0, i.e., V2 places a “D” at
line A and sensitizes a path from line A to a PO. (Can use
D-Alg. or PODEM)
⚫ Theorem: <V1, V2> is a test for the gate delay fault on line A.
⚫ When V2 is applied, the output W goes from 0 to 1. If ∆ exists,
this transition will hopefully be late. If it is very late, then it
might arrive after the clock edge and an error will be created in
a flip-flop.
⚫ What if a rising transition on the side input to gates B, C
and/or W come early with respect to the transition on the
sensitized path? Then the transition still propagates as
expected. What if one of these transition arrives late?

Dr. Moe Tabar - EE 658 58

The Proof - Case1
⚫ Consider an arbitrary gate Z along the sensitized path
from the site of the fault to the output.
⚫ Assume all the side fan-in (off-path) line values are
hazard free and static for the transition V1 to V2.
Then if the fault exists, the output transition will be
late because the transition must pass through A in
going to the sensitized output being observed.

off-path input Y is late ⇒ Z is late

X (Z = 1 is correct answer)
11
X Z static 1
Y
Y Actual time
Y and Z change
Z
assume zero delay Expected time for
Y and Z to change

Dr. Moe Tabar - EE 658

Case 2
⚫ Assume that X has a transition

X X As long as X transitions
before Y does, Y being late
Y Y still implies that the last
transition at Z will be late.
Z Z

⚫ But what if X transitions after Y does

But now if Y is late, the
X X transition on Z is not
affected, and in fact does not
Y Y occur. So if X is also late, it
will mask the fault in Y.
Z Z

▪ So here a second fault that affects X masks the erroneous operation.

So we need to consider only single delay faults!

Dr. Moe Tabar - EE 658 60

Path delay faults
⚫ For each physical path P from a PI to a
PO there are two corresponding
transition paths, the rising path (Pr) and
the falling path (Pf).
⚫ These correspond to a rising vs. falling
transition at the PI of the path. Px
represents Pr or Pf.
⚫ Definition: Px is said to have a path
delay fault if the propagation delay is
larger than (t2 – t1).

Dr. Moe Tabar - EE 658 61

Off-path sensitizing input
⚫ Definition: Let G be a gate on a path P
and r be an input to G; r is called an
off-path sensitizing input if r is not on
path P.
off-path sensitizing inputs

Dr. Moe Tabar - EE 658 62

 Robust tests
⚫ Definition: <V1, V2> is a robust delay test
for path delay fault Px iff when Px is faulty and
<V1, V2> is applied, the transition at the input
line to Px is x, and the circuit output is in error
at sampling time t2, irrespective of other path
delays
⚫ That is, when testing path Px, we do not want
variations in delay along other paths of the
circuit to either mask an error or create an
error not created by Px.

Dr. Moe Tabar - EE 658 63

 Some properties related to robust
testing of delay faults
⚫ The presence of other path delay faults has no
effect on the ability to test for a targeted path delay
fault when using a robust test.
⚫ Thus there can be numerous delay issues due to
various problems, such as process variations,
defects, and crosstalk.
⚫ Theorem: If a robust test exists for a path delay
fault in a circuit, then a robust test with only a
single input transition also exists for that path.
Thus only one input, say yi, needs transition from 0
to 1 (or 1 to 0) when V1 to V2 transition happens.

Dr. Moe Tabar - EE 658 64

More properties
⚫ Any stuck-at fault lying on a path that is tested
robustly is tested (detected) if the value of the
stuck fault is opposite to the final value
propagated to that point, i.e., by V2, because the
output of the path never changes value in such a
case.
⚫ Note: Even though a robust test may have only
one primary input making a transition, because of
fan-out there can be many paths having
transitions. Also, because of reconvergent
fan-out, there can be many paths from the input
transition line to the output transition line.

Dr. Moe Tabar - EE 658 65

Example 2
Consider the circuit shown below. Transition delays are shown, e.g.,
gate j has a 2 unit (ns.) fall inertial delay on each input line. The longest
path delay appears to be 8. Let the clock period be 8.5 ns.

0 3
3
a 3 4
f h
1
1 7
b g j 8
1 i
1 2
c 2
3 1
d
TC = 8.5
e

Dr. Moe Tabar - EE 658 66

 More on Example 2
Consider the test T = <0 1 0 1 0, 1 0 1 1 0> shown below, which is a
non-robust test for the path a – f – h – i – j for “a” rising. The delay fault
consists of 3 becoming a 4 at gate f, and 2 becoming a 3
at gate j.

0-> 1 4
f 3 6
3 23 5
a
fault 4
1
1-> 0
g 1
b 3
1 h 6
0-> 1 1
c 2 3
12 3 1
i
d Filtered out by j
1-> 1 gate i fault
TC = 8.5
e 0-> 0
Dr. Moe Tabar - EE 658 67
 Still more on Example 2
⚫ The final value of all the off path sensitizing values
due to V2 are correct, such as a 1 on line g.
⚫ At all gates along the path a – f – h – i – j , the
off-path sensitizing signals at the gate inputs
stabilize to their final values before the on-path
signal arrives at the gate inputs.
⚫ But this circuit passes the test even though the
longest path delay now appears to be 9. But an
error (spike) may occur!
⚫ T is not a robust test because the off-path
sensitizing input g to the on-path AND gate h is
not guaranteed to be at a steady (glitchless) value
of 1, as specified by the robust test requirements.

Dr. Moe Tabar - EE 658 68

 Animation

Modifying the delay in Example 2

Changing the rise delay at g we get the following.

0>1 4
f
3 5
a
fault 4
1
1>0
g 1
b 6
1 h 9
0>1 1
c 1 1-> 1 3
3 1
i
d j
1-> 1
fault
TC = 8.5
e 0-> 0

Dr. Moe Tabar - EE 658 69

 A new test for Example 2
So maybe this fault is detectable! Consider the robust test TR = <0 x 0
1 0, 1 x 0 1 0> for the same path.

0 f
3 4
a 4 h
1 5
g S1
1 6
b x->x 1 i j 9
0->0 S1 1 3
c 2
3 1
1->1 S1
d
0->0 S0 Tc = 8.5
e

Dr. Moe Tabar - EE 658 70

 Another case in Example 2
⚫ Now at Tc = 8.5ns we sample a 1 and hence
detect an error.
⚫ So what went wrong before? Did a hazard
block the propagation of a fault effect to an
output?
⚫ Note – we assume that all input transitions are
hazard free.

Dr. Moe Tabar - EE 658 71

Example 3 (why inputs need to be hazard free)
⚫ Consider the “manufactured” circuit shown below that has the delays
as shown, where the designed circuit had all unit delay values. Yes, I
have a hazard at a PI (c). Clearly, this circuit has delay faults.
⚫ Let Tc = 3ns. Consider the path a – d – e and the test T = <1 1 1, 0 1
1>, but where a static 1-hazard occurs on line c.
⚫ Since the correct expected value of e is 0, and a 0 is sampled at Tc = 3,
the circuit passes the test.
⚫ This occurred because a dynamic hazard occurred at line e, thus
invalidating the test T.

1->0
d 8
a 8
1
b 8 e 2 4 10
02
2
c 2
Dr. Moe Tabar - EE 658
T =3 72
 Hazards on inputs!
Note – if no hazards occur at the inputs we still could
have gotten this result as shown below.

0 02
x 2
y 0
0

Dr. Moe Tabar - EE 658 73

Sufficient conditions for a robust test
Condition #1 The output may not change
before Y changes, but is allowed
X to change later due to changes at
x1 line X.
Z
Y
Final Value must be a 1. But
can have a static or dynamic
hazard.

If the transition at a gate’s input on the path being tested is

from a controlling value c to a non-controlling value, then
the side fan-ins (off-path) signal values can be of the form
<x,cbar>, where c is the controlling value and cbar = c’.

Dr. Moe Tabar - EE 658 74

Sufficient conditions (con’t)
Condition #2 The output will not change
until Y changes if line X is
held constant at 1.
11 X
Z
Y
Static hazard free

If the transition at a gate’s input on the path being tested is

to the controlling value c from the non-controlling value,
then the side fan-ins signal value should be a constant and
hazard free at the non-controlling value cbar.

Dr. Moe Tabar - EE 658 75

 Notation in Jha and Gupta
5 valued logic: the symbols are: {S0, S1, U0, U1, XX}
S0 = Hazard free static 0
S1 = Hazard free static 1
U0 = Final value is a 0
U1 = Final value is a 1
But if U0 is assigned to a PI, then U0 is interpreted as 1 to 0
hazard free transition.
XX NAND in 5 valued logic
A
U0 U1 S0 U0 S1 U1 XX
S0 S1 S1 S1 S1 S1

S0 S1 U0 S1 U1 U1 U1 U1
Lattice of containment B S1 S1 U1 S0 U0 XX
U1 S1 U1 U0 U0 XX
XX S1 U1 XX XX XX
C

Dr. Moe Tabar - EE 658 76

Side input values
Gate type AND/ NAND OR/NOR
On-input
transition
U1 U1 S0
U0 S1 U0
Robust test

U1 U1 U0
U0 U1 U0
Non-robust test

U1 U1 XX
U0 XX U0
Functional sensitization

Gate has two inputs: 1) Side Input 2) on-input transition

Dr. Moe Tabar - EE 658 77

 Example 8.7: Testing for a G-GDF
Consider the circuit below. Suppose there is a slow-to-rise gross
gate delay fault (G-GDF) at line c3. First we need an initialization
vector P1that makes c3=0. Such a vector is (x, x, 0, x, x). Then we
need a vector P2 that makes c3=1 (thus a rising transition) and
sensitizes any path from c3 to z. (0, x, 1, 1, 1) is such a vector.
Thus one possible two-pattern test is {(0, 0, 0, 1 ,1), (0, 0, 1, 1, 1)
which leads to a single input bit transition.

S0 x1 c5
S0 x2 c1 U0
U1
S1 c3 z
U1 x3
U0 U1
c2 c4
S1 x4 S0
S1 x5 c6

Dr. Moe Tabar - EE 658 78

Example 8.8: Testing for a S-GDF
Consider the circuit shown below. Consider the slow-to-fall
small gate delay fault (S-GDF) at c3. A possible longest
structural path through the fault site is shown in red. This is a
functional path and can be sensitized via the vectors shown.
This corresponds to the two-pattern test
{(1, 0, 1, 1, 0), (1, 0, 0, 1, 0)}. Here robust propagation rules
have been used.

S1 x c5
1
S0 x c1 S0
2

S1 c3 z
U0 x U0
3 U1
U1
c2 c4
S1 x U0
4 U1
S0 x5 c6

Dr. Moe Tabar - EE 658 79

Developing a test for a PDF
⚫ Consider the circuit in Figure 8.18(a). This
circuit has 11 physical paths, and hence, 22
logical paths. Suppose the PDF to be tested is
x5c4z2↑, as shown in bold in the figure. The
objective now is to derive a list of other
paths in the circuit, the compatibility set C,
that may be simultaneously tested with this
PDF. The compatible fault set contains only
this PDF at this point. First, we concern
ourselves with only robust testing. We
perform the following steps.

Dr. Moe Tabar - EE 658 80

Figure 8.18: Testing PDF’s
x1 c1 S1
x4 c3
x2
c2 z1 z2
x3 U1 c5 U1

x5 c4 U0
U1 (a)
x1 c1
x4 c3
x2
c2 z1 z2
x3 c5 U1
U0
x5 c4 U0
U1 U1
U0
(b)

Dr. Moe Tabar - EE 658 81

Figure 8.18 con’t.
x1 c1
x4 c3
x2
c2 z1 z2
x3 c5 U1
x2c2c3z1↑
x5 c4 U0
U1 (c)
x1 c1
x4 c3
x2
c2 z1 z2
x3 c5 U1

x5c4z1↑ x5 c4 U0
U1
(d)

Dr. Moe Tabar - EE 658 82

Figure 8.18 con’t.
x1 c1
x4 c3
x2
U0
c2 z1 z2
x3 c5
U1
x2c2c4z2↑
x5 c4 U0
U1
(e)

Dr. Moe Tabar - EE 658 83

 Explanation of Figure 8.18
⚫ Figure 8.18(a): Here we see the circuit and the path
to be tested (in boldface) x5c4z2↑, and some of the
line assignments. The assignments in red are the side
inputs.
⚫ Figure 8.18 (b): Here we see that x5c4z2↓ cannot be
tested concurrently with x5c4z2↑because of a conflict
in line assignments.
⚫ Figure 8.18 (c): Here we see that the path x2c2c3z1↑
cannot be tested concurrently with x5c4z2↑ because
c5=U0 blocks the sensitization path.
⚫ Figure 8.18 (d): Here we see that the path x5c5z1↑ can
be tested concurrently with x5c4z2↑.
⚫ Figure 8.18 (e): Here we see that the path x2c2c4z2↑
can be tested concurrently with x5c4z2↑, but requires
the additional constraint of x2=U0.

Dr. Moe Tabar - EE 658 84

Path activation and incompatible paths
⚫ Path activation: This step involves placing
appropriate signal values on the path being
tested. We will use the five-valued logic system.
This gives the following signal values: x5 = U1, c4
= U0, and z2 = U1.
⚫ Next, in order to determine which PDFs can be
tested simultaneously with the above PDF, we
first determine which PDFs cannot be tested
based on the above necessary assignments. It is
observed that any PDF requiring x5 = U0 or c4 =
U1 or z2 = U0 cannot be tested. Thus, this rules
out PDFs x5c4z1↓, x5c4z2↓, x3c2c4z2↓, x2c2c4z2↓,
x2c2c4z1↓, and x3c2c4z1↓.

Dr. Moe Tabar - EE 658 85

 Derivation of sensitizing values for
side-inputs
⚫ For the PDF being tested, the side inputs are c1and c2.
Based on the propagation rules for robust testing, one
can observe that the required assignments for these
side-inputs are: c1= S1 and c2 = U1. Since line c1
assumes a steady value, no PDF can be tested through
it. This rules out x1c1z2↑, x1c1z2↓, x2c1z2↑, and x2c1z2↓.
Since c2 = U1, any PDF that requires c2 to be U0
cannot be tested. This rules out the following PDFs,
which have not already been ruled out: x2c2c3z1↓and
x3c2c3z1↓·
⚫ Constraint propagation: We observe that line c5
assumes value U0 due to fanout. Thus, no PDF
through line c3 can be tested because its robust
propagation to output z1 is prevented by c5 = U0. The
newly ruled out PDFs are therefore x2c2c3z1↑,
x3c2c3z1↑, x4c3z1↑, and x4c3z1↓.

Dr. Moe Tabar - EE 658 86

 Testing more paths
⚫ Based on the above reasoning, out of the 21 remaining
PDFs, we have identified 16 as being incompatible with
x5c4z2↑. Hence, the search is now restricted to only five
PDFs: x5c4z1↑, x2c2c4z1↑, x2c2c4z2↑, x3c2c4z1↑, and x3c2c4z2↑.
If we now pick x5c4z1↑ to be in the compatible set C, then
C = {x5c4z2↑, x5c4z1↑}. We now superimpose the
necessary conditions for testing x5c4z1↑ over the
conditions for testing x5c4z2↑, and repeat this process until
no more paths can be considered.
⚫ Finally, C = {x5c4z2↑, x5c4z1↑, x2c2c4z2↑, x2c2c4z1↑}. This is
the maximal potentially compatible fault set. Test
generation can now be performed to satisfy necessary
conditions imposed by all these paths. In this case, such a
test does exist, and is given by (x1, x2, x3, x4, x5) = (S0, U0,
S1, S0, U1).

Dr. Moe Tabar - EE 658 87

What needs to be done next
⚫ We can now start with the next
undetected PDF and repeat the process
until all PDFs have been considered for
robust testing. Among the PDFs that
remain, similar test generation should be
done except that now rules for
non-robust propagation can be used.
Finally, for the PDFs that still remain,
rules for functional sensitization can be
used.

Dr. Moe Tabar - EE 658 88

 Advanced

Stabilization of V1 – the need for

slow-fast clocks
Fault free circuit should
stabilize no later than here
t1 t2 t3

Normal clock Circuit Faulty circuit stabilizes

period is stable
somewhere out here.
t2 - slow clock
t3 - fast clock
But wouldn't it be better to test at-speed?
Yes, if we only knew how to determine delay fault coverage. Let’s see
how stabilization can effect a test.

Dr. Moe Tabar - EE 658 89

 Advanced

Example 4: At speed testing

0 14 Testing for path
e T = V1, V2, V3, … , Vm
a 14 * Vi is both an initialization for test
delay fault Pr
b 11 14 f 16
Ti, and the test vector for Ti-1,
0 2 except for V1 which is not a test
vector, and Vm which is not an
c 2 g 18
2 initialization vector.
00
d 2
Tc = 7
Assume in the circuit shown above all delays are 2ns. So the gate with inputs a and
b has two gross delay faults. Let TC=7ns, where the longest path delay in the fault
free circuit (a-e-f-g or b-e-f-g) is 6ns, and for the fault Pr has a delay of 18ns, where
Pr = a-e-f-g. This path delay fault is detected by the robust test TR = < Vi, Vi+1 > =
<0100,1110> provided that the 0→1 transitions at a and c begin after a, b, c, d, e
and g have stabilized to their final values (due to Vi) of <0,1,0,0,0,0,0>.
*Pr represents a rising transition at the beginning of path P.

Dr. Moe Tabar - EE 658 90

 Advanced

Example 4: At speed testing cont’d.

0 Testing for path
e 14
a 14 delay fault Qf
b 11 14 f 2
0 2
c 2 g 2
0 2
d 2
Tc = 7

Now consider the path Q: d-g, and the robust test T’R=<1111,0100> for Qf.
(Required side input at g is U0.) So T’R “passes” because there is no fault along
the path Q. Also <1111,0100> and <1110, 0110> are robust tests for Qf and Pf.

Dr. Moe Tabar - EE 658 91

 Advanced

Example 4: At speed testing cont’d.

Now applying a test sequence at the clock-rate

(at-speed), and let t0= -7. Let V1=1111, V2=0100,
V3=1110 and V4=0110.
Assume that prior to applying V1 we set all inputs to 1,
i.e., to V1, so the circuit is stable when V1 is applied and
remains stable.
Note that:
▪ (V1, V2) is robust test for Qf.
▪ (V2, V3) is robust test for Pr.
▪ (V3, V4) is robust test for Pf.

Dr. Moe Tabar - EE 658 92

 Advanced
Example 4: At speed testing cont’d.
V1 V2 V3 appliedV4 applied
▪ Waveform for faulty circuit applied applied
for test sequence V1, V2,
V 3, V 4.
a
▪ The robust test (V2, V3) for
Pr is invalidated since the b
correct expected value of 1
(under V3) is sampled at c
output g at t=14. Thus the
path fault Pr goes
d
undetected.
▪ The robust test (V3, V4) for e
Pf is also invalidated.
f 2 9 16

g 4 11 18
t=-7 t=0 t=7 t=14 t=21

Dr. Moe Tabar - EE 658 93

 Advanced

Example 4: At speed testing cont’d

⚫ This invalidation is due to long delays, i.e.,
signals are still propagating through the circuit
as one applies new values at a fixed rate at the
primary inputs. The circuit has not reached
steady-state when the input changes!
⚫ Assume that in 99.9% of all cases of faulty
circuits that the size of the delay fault is at
most 4 times the design delay Td. Thus setting
T*= 5Td should be sufficient to compensate
for the effects just illustrated. Thus T* is the
period of the slow test clock.

Dr. Moe Tabar - EE 658 94

 Advanced

Validatable non-robust tests

⚫ Unfortunately, for most circuits, the majority (over
70%) of the paths do not have robust tests. So
then what should be done?
⚫ Definition: A set S of two-pattern tests is a
validatable non-robust test for a path delay
fault PX iff no element of S is a robust test for PX,
and if the circuit passes all tests in S, it can be
concluded that the desired transition propagates
along path P in the time allowed.

Dr. Moe Tabar - EE 658 95

 Advanced

Example 5
Let S = {T1,T2}, where T1 =<111,011>, T2 =<110,010>.
T1 is not a robust test for Pf : A-a-b-g-d.

P
Not S1 for robustness
A e v
B
S1 d

T1
a b
g
S1
C

Dr. Moe Tabar - EE 658 96

 Advanced

Example 5 cont’d.
⚫ T2 is a robust test for Qf: e-v-d.
Thus if T2 passes, then the path
Qf is verified to be good.
Q
⚫ So when T1 is applied the
A e v transition along Qf will not be
B late enough to invalidate T1, i.e.,
S1 d an erroneous conclusion.
T2 ⚫ So if the circuit passes both T1
a b and T2 , then Pf is adequately
g S1
tested. For T2, the transition at v
S0
C will appear and if there is a delay
fault, the transition at g will
appear later and a static 1-hazard
will appear at d.

Dr. Moe Tabar - EE 658 97

 Advanced

Some theory
⚫ For every path and desired input transition in a single output
irredundant two level logic circuit, there exists either a robust test
or a validatable non-robust test set to detect each path delay fault.
⚫ But, for general multi-level circuits, validatable non-robust tests
may not occur for many situations due to the existence of hazards.

Dr. Moe Tabar - EE 658 98

Some miscellaneous topics
⚫ Some paths are false paths, i.e., they exist in
hardware but are not functionally sensitizable.
⚫ Many algorithms exists for generating tests for various
types of faults, such as gate and path.
⚫ Many algorithms exists for generating various types of
tests, such as robust, non-robust and functional.
⚫ Can extend the quality of delay tests by considering
triplets <V1, V2, V3>, so that complex gates and
stored charge on transistor gates can be taken into
consideration.
⚫ There are additional delay fault models, such as
segment delay faults.

Dr. Moe Tabar - EE 658 99

 More misc. and advanced topics
⚫ What should be done regarding the fact that
most paths do not have a robust test?
◦ Generate lesser quality tests!
◦ Focus only on critical paths!
⚫ What should be done about the fact that for
many circuits, the number of paths is
astronomically large?
⚫ We would like to test a circuit at-speed. How
can this be done?
⚫ How would you determine the delay fault
coverage of such a test?

Dr. Moe Tabar - EE 658 100

State of the art
⚫ Delay faults are of major concern to the
industry
⚫ Few systems exists for generating high quality
delay tests
⚫ Applying such tests usually requires skew load
or functional V2.
⚫ Delay testing is a very active field of research
and development
⚫ Transition fault tests are primarily used
⚫ Fault coverage is hard to estimate
⚫ Very few paths have robust tests

Dr. Moe Tabar - EE 658 101

THE END

102