Design & Analysis of Matrix Arbiter For NoC
Design & Analysis of Matrix Arbiter For NoC
Abstract: Network-on-Chip (NoC) is a general purpose on- Dr. M.A.Gaikwad, Dean (R&D) Department of Electronics,
BDCOE,SevagramWardha,(M.H)India(e-mail:
chip communication concept that offers high throughput, [email protected])
which is the basic requirement to deal with complexity of .
modern systems. Arbiter is used in NoC Router when
number of input port are request for same output port. In
II. NoC ROUTER
this paper we are design Matrix Arbiter for NoC
architecture. When all input port are request for same
output port in this situation matrix arbiter first form a
matrix 5*5 After that matrix arbiter assign the Priority to
all input request and generate the grant signal. In this
input port a output port a
paper we are analyze the Area, power.
input port b output port b
Keywords- Network on–Chip, Matrix Arbiter
input port c output port c
FIFO Buffers Crossbar
I.INTRODUCTION input port d output port d
As the area and speed on a single chip now faces
input port e output port e
the big challenge on a single chip, more and more
processing elements now are placed on System on chip. Write
Network-on-chip (NoC) is on a chip becomes a primary So S1 S2 S3 S4
factor which limits the performance and power
consumption. As the switch speed of crossbar switch
increases rapidly, on big problem we should a new Read
method for on chip communication to solve the problem
that challenges the system on chip. The physical
Arbiter
interconnection resolve is to implement a fast and fairness
arbiter to maximize the switch throughput and timing
performance for Network-on-chips.
NoC has advantages on architecture, Fig 1: Block diagram of NOC Router
performance, reusability and scalability than traditional
bus-based system-on-chip. Among these basic modules, The design of router mainly consists of three parts:
the data flow control of virtual channel play an important
role to alleviate the package congestion. The architecture 1. FIFO
and dataflow control will affect the design of arbiter of 2. Arbiter
NOC significantly. The arbitration should guaranteed the 3. Crossbar
fairness in scheduling, avoid starvation, and provide high
throughput [ 1]. FiFo is used in NoC Router for storage of packet of input
The NoC's switches should provide high speed port. Arbiter is used to trap the source and destination
and cost-effective contention resolution scheme when address of input and output port. Arbiter generate the
multiple packets from different input ports compete for control signal according to priority so that crossbar
the same output port. A fast arbiter is one of the most switch transmit data from source to destination.
dominant factors for high performance NoC switches [4].
For the above reasons, the analysis of the performance of In this paper we are design Arbiter block and work on
the arbiters are significantly meaningfulness in the design Priority based Matrix Arbiter.
of Network-on-chips.
III ARBITER output port. In that matrix arbiter set the corresponding
bit which is requested for same output port. Now matrix
The arbiter trap the source and destination address from
arbiter check the priority if input a has highest priority
the output 0f buffer and generate the control signal so that
input data from source side sending to the output port. and input e has lowest priority then matrix arbiter gives
priority to input a and input e will get lowest
priority.Matrix Arbiter generate a control signal so
particular select line is selected and source packet is
transmitted to destination
IV MATRIX ARBITERATION
Fig No. 4 without contention Table
In matrix arbitration when all input packet have
From above table all the input port are requested
the same priority request for same output port then matrix for different output port so matrix generator first generate
arbiter generate the matrix depending upon input and matrix of dimension 5*5 and set corresponding bit one. In
101
All Rights Reserved © 2012 IJARCSEE
ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
B) With contention
Fig 9.Changes of priority matrix after receiving
request
S I/p SA DA Grant Select line O/p port
r. Here we have given matrix generator for four
N port [4:0] inputs similarly it will generate matrix for fifth input.
o
In above table there is contention for output port so that In this paper after synthesize we found the area
the Matrix generated shown in figure gate count is 32,352 and power consumption is 7mW.
102
All Rights Reserved © 2012 IJARCSEE
ISSN: 2277 – 9043
International Journal of Advanced Research in Computer Science and Electronics Engineering
Volume 1, Issue 5, July 2012
CONCLUSION
In this paper we are design matrix arbiter. this
arbiter uses same arbitration algorithm as Round Robin
Arbiter. this arbiter fairly treated with each input request
so that every input transmit packet to the output.
REFRENCES
[1]Yun-Lung Lee, Jer Min Jou and Yen-Yu Chen,a High Speed and
decentralized arbiter Design for NoC[J],350-353
103
All Rights Reserved © 2012 IJARCSEE