Basics of DAC-based Wireline Transmitters

Friedel Gerfers
Technische Universität Berlin

[email protected]
www.msc.tu-berlin.de

Friedel Gerfers Basics of DAC-based Wireline Transmitters 1

Self Introduction
Dipl.-Ing. & Dr.-Ing. in Microelectronics, University Duisburg-Essen &
1997 / 2003
Albert-Ludwigs Universität Freiburg
2003 – 2006 Senior Design Engineer, Philips Semiconductors, Munich
2006 – 2007 Senior Researcher, Research Fellowship, Intel, Santa Clara, USA
2007 – 2012 Technical Director, Aquantia, Milpitas, USA
2012 – 2013 Technical Director, Alvand Technologies, Santa Clara, USA
2013 – 2014 Director, IDT, San Jose, USA
2014 Design Manager, Apple Inc., Cupertino, USA
2012 – 2014 Member Advisory Board, Berkeley Design Automation, USA
Since 2014 Member Advisory Board, Mentor Siemens, Fremont, USA
Since 2020 Member of the Board of Trustees, Leibniz Institute IHP, Germany
Since 2015 Full Professor, Head of Chair Mixed Signal Circuit Design, TU Berlin
Since 2019 Einstein Professor, Einstein Foundation, TU Berlin
Since 2009 Founder NiederRhein Technologies, Mountain View, USA
Since 2018 Founder IC4X GmbH, Berlin, Germany

Friedel Gerfers Basics of DAC-based Wireline Transmitters 2

Basics of DAC-based Wireline Transmitters
This tutorial presents a practical overview of current-mode (CM) and voltage-
mode (VM) DAC drivers, focusing on the fundamentals, accuracy challenges and
design solutions.
First, the tutorial explains transmitter specifications for swing, jitter, equalization
and linearity, introduces DAC performance metrics and discusses their overall
impact on wireline systems.
Next, the current-mode and voltage-mode DAC architectures are introduced
while highlighting the Pros / Cons of each. High-speed design challenges,
bandwidth and non-linearity trade-offs are reviewed. PVT & mismatch effects,
swing enhancements and calibration techniques are introduced.
The tutorial concludes with several DAC design examples utilizing deep
submicron CMOS technologies reaching up to 56Gbaud/s.

Friedel Gerfers Basics of DAC-based Wireline Transmitters 3

Relevant Past ISSCC Tutorials
 ISSCC 2015: High-Speed Current-Steering DACs, Jan Mulder
 Performance Metrics, DAC Design & Optimizations, Layout Effects

 ISSCC 2017: Signal Integrity Analysis for GB/s Links

Tony Chan Carusone
 Channel & Crosstalk Modeling, Statistical Eye Analysis

 ISSCC 2018: ADC-Based Serial Links: Design and Analysis

Sam Palermo
 Performance Metrics, ADC based Links, ADC Design and Optimization

All ISSCC tutorials are available for free to SSCS members at:
https://resourcecenter.sscs.ieee.org
Friedel Gerfers Basics of DAC-based Wireline Transmitters 4
Tutorial Overview
 High-speed transceiver overview
 Key TX metrics and design objectives
 Transmitter termination
 High-speed design solutions
 Current-mode DAC drivers
 Segmentation
 Voltage-mode DAC drivers
 Signal swing enhancements
 High-speed data serialization
 Data multiplexing

Friedel Gerfers Basics of DAC-based Wireline Transmitters 5

Consumer High-Speed Serial Links

HDMI

Courtesy: Internet

 Examples are e. g. HDMI™ and Thunderbolt™ infrastructure

 Both are point-to-point links
Basics of DAC-based Wireline Transmitters 6
Industry High-Speed Serial Links

Courtesy: Internet

 Backplane and chip-to-chip (e.g. processor, memory, …)

 Data center networks (e.g. Ethernet, fiber optical networks, … )
Basics of DAC-based Wireline Transmitters 7
Trend of Ever-Increasing Data Rate
•28nm: NRZ
•28nm: PAM4

 PAM4 based transceivers drive the data rate beyond 100GBit/s

 7nm CMOS technology enables power-efficiency <10pJ/conv.
 Details of the wireline transceiver survey: [1], [2]
Friedel Gerfers Basics of DAC-based Wireline Transmitters 8
Basic Wireline Link - SerDes
TX RX
RT ZL RT

DEMUX
MUX
Eq. Driver Eq.

CDR
PLL PLL

 Transmitter (TX): Converts the digital (time-discrete) data into a

(time-continuous) analog electrical signal  D-to-A conversion
 Channel: Transmission media for the analog signal
 Receiver (RX): Digitizes the analog signal back to bits (quantize
in voltage and time)  A-to-D conversion
 Serialize (TX) – Deserialize (RX)  “SerDes”
Friedel Gerfers Basics of DAC-based Wireline Transmitters 9
NRZ and PAM4 Eye Diagram
NRZ eye PAM4 eye
diagram diagram
Vout,TX
NRZ eye Full Scale (FS)
D1 D0
diagram
1 1 1
1 2/3
Vout,TX 1 0
1/3 0 1
0 0 0 0

1Tbit =1UI 1Tbit =1UI

(UI ≡ unit interval)

 Eye diagram construction by overlaying waveform segments

 Non-return-to-zero (NRZ)  1bit/symbol, PAM4  2 bits/symbol
Friedel Gerfers Basics of DAC-based Wireline Transmitters 10
 NRZ Eye Diagram Analysis
Probability distribution of noise
Vtop
opening / height

(µtop)
Vertical eye

𝝈top
amplitude
Eye
Vbot
(µbot)

𝝈bot
Horizontal eye opening / width 𝝈cross1 𝝈cross2
tcross1 tcross2

 Eye height= (Vtop – 3𝝈top) – (Vbot + 3𝝈bot)

 Eye width = (tcross2 – 3𝝈cross2) – (tcross1 + 3𝝈 cross1)
Friedel Gerfers Basics of DAC-based Wireline Transmitters 11
Bit Error Rate (BER)
tS tj,pp
 If the received bit is different
from the transmitted  bit error

VDTH
No. of bit errors
 BER
No. of transmitted bits

 BER characterization: BER-tester

or loop back

 Mathematical model with a normalized threshold of VDTH=0.5

 This area is the probability that 0 is decoded as 1
 This area is the probability that 1 is decoded as 0
Friedel Gerfers Basics of DAC-based Wireline Transmitters 12
Bit Error Rate (BER) II
𝑥−𝜇
Φ ≡ 𝐶𝐷𝐹
𝜎
 Noise is assumed to be normal distributed [3] VDTH
 Mean free 𝜇 0 and variance 𝜎 x/1V
0 0.5
1 .
𝑝 𝑥 0.5 𝑒 𝑑𝑥
 “BER” means the probability that noise . 2𝜋𝜎
becomes larger than the threshold VDTH 𝑝 𝑥 0.5 1−Φ
0.5 − 0
Φ −
0.5
𝜎 𝜎

 Probability of an error p(bit error)  BER

𝑝 bit error 𝑝 TX 0 ·𝑝 𝑥 0.5 𝑝 TX 1 ·𝑝 𝑥 0.5 VDTH
. . x/1V
𝑝 bit error 0.5 · Φ − 0.5 · Φ −
0.5 1
. .
𝑝 bit error Φ − 1 .
𝑝 𝑥 0.5 𝑒 𝑑𝑥
2𝜋𝜎
 For low BER: maximize signal amplitude, 0.5 − 1 0.5
𝑝 𝑥 0.5 Φ Φ −
minimize noise & jitter 𝜎 𝜎
Friedel Gerfers Basics of DAC-based Wireline Transmitters 13
Bit Error Rate (BER) III
 Vertical and horizontal BER
 BER depends on decision threshold VDTH and sample instant tS

BER Horizontal BER Vertical

(1)
0.5 eye margin 0.5 eye margin (2)
Better

10-12 10-12

tS VDTH
0 Bit period Tbit Vbot Eye
Bitamplitude
period Vtop
("0") ("1")

 (1) Faster link speed  shorter bit period (Tbit)  higher BER
 (2) Higher TX eye amplitude  improved SNR  lower BER
Friedel Gerfers Basics of DAC-based Wireline Transmitters 14
PAM4 Eye Linearity
V3 𝑆 min 𝑉 − 𝑉 , 𝑉 − 𝑉 , 𝑉 − 𝑉
3 ⋅𝑆
V2 𝑅𝐿𝑀
𝑉 −𝑉
V1
max 𝑉 − 𝑉 , 𝑉 − 𝑉 , 𝑉 − 𝑉
V0 Eye linearity
min 𝑉 − 𝑉 , 𝑉 − 𝑉 , 𝑉 − 𝑉

 PAM4 eye linearity critical for low BER

 Eye compression:
 Minimum signal level 𝑆  swing between adjacent symbol levels
 Resulting relative level mismatch (𝑅𝐿𝑀)
 Eye linearity: Compares maximum to minimum eye voltage level
Friedel Gerfers Basics of DAC-based Wireline Transmitters 15
Basic Wireline Link - TX
TX RX
RT ZL RT

DEMUX
MUX
Eq. Driver Eq.

Vout,TX CDR
PLL PLL

 TX serializes parallel data

 TX drives channel with large (enough) voltage swing
 TX amplitude critical for link SNR and BER
 TX linearity critical for PAM4-based link SNR and BER

Friedel Gerfers Basics of DAC-based Wireline Transmitters 16

Single-Ended Serial Link
TX RX
RT ZL
MUX Vin,RX + vnoise,gnd

DEMUX
Eq. Driver
Vout,TX Cin
Vref

 Transmit signal needs a return path

 Gnd signals (TX & RX) are not exactly same voltage  SNR, BER
 Finite transmitter supply impedance  switching noise (SSO)
 Demands large amount of local decoupling capacitance at TX and RX (Vref)
 Pro: Single-ended links exhibit compact footprint, 1 pin, 1 wire, …
 Con: Sensitive to power supply noise, xtalk (even with local Vref)
Friedel Gerfers Basics of DAC-based Wireline Transmitters 17
Differential Serial Link
TX RX
RT RT
ZL

DEMUX
MUX

Eq. Driver Eq.

CDR
PLL PLL

 Pro: Voltage/current difference transmitted  better noise immunity

 Pro: Signal is self-referenced, can achieve twice the signal swing,
rejects common-mode noise, return current is ideally only DC
 Con: Differential links have twice the complexity, # of pins, wires,…
Friedel Gerfers Basics of DAC-based Wireline Transmitters 18
Channel – Physical Media
TX RX
RT ZL RT

DEMUX
MUX
Eq. Driver Eq.

L
CDR
PLL PLL

 Typically, copper interconnect

 E. g. shielded twisted pair (STP), PCB trace, vias, connectors, … Allowed IL

 Channel length L varies (L ≥ 𝜆clk, Tbit)

 Channel cause frequency-dependent loss  insertion loss (IL)
 Crosstalk (NEXT, FEXT,..)
 Discontinuities due to connectors & IO interfaces
Friedel Gerfers Basics of DAC-based Wireline Transmitters 19
Insertion Loss – Attenuation & ISI
TX RX
RT ZL RT

DEMUX
MUX
Eq. Driver Eq.

CDR
PLL PLL

 Channel has a low-pass behavior

|Insertion loss| (dB)

Allowed IL
 Skin effect 𝐻 𝑓 ∝ and dielectric losses 𝐻 𝑓 ∝

 Attenuates transmit signal (IL)

 Introduces Intersymbol Interference (ISI) Example IL

 Both affect link SNR and BER Frequency (GHz)

Friedel Gerfers Basics of DAC-based Wireline Transmitters 20

Return Loss – Reflection Coefficient
TX RX
Vr
RT ZL RT

DEMUX
MUX
Eq. Driver Eq.
Vi
CDR
PLL ZIn PLL

 Transmit signal 𝑉 might get reflected at RX 𝑅𝐿 dB 20 · log10 𝛤

Reflection coefficient 𝛤 and return loss RL

|Return loss| (dB)



𝑉 𝑍 −𝑍 Allowed RL
𝛤
𝑉 𝑍 𝑍

 For “matched load“ i. e. 𝑍 𝑍 𝛤 0

Friedel Gerfers Basics of DAC-based Wireline Transmitters 21
Tutorial Overview
 High-speed transceiver overview
 Key TX metrics and design objectives
 Transmitter termination
 High-speed design solutions
 Current-mode DAC drivers
 Segmentation
 Voltage-mode DAC drivers
 Signal swing enhancements
 High-speed data serialization
 Data multiplexing

Friedel Gerfers Basics of DAC-based Wireline Transmitters 22

Transmitter Termination
 Off-chip vs. on-chip termination
 Series vs parallel termination
 AC vs DC coupled termination
 Termination calibration
 Finite TX output bandwidth
 TX with shunt peaking
 TX with bridged T-coil

Friedel Gerfers Basics of DAC-based Wireline Transmitters 23

Termination
TX RX
RT ZL RT

DEMUX
MUX
Eq. Driver Eq.

CDR
PLL PLL

 Termination RT is typ. part of the transmitter / DAC driver design

 Mismatch RT ≠ZL introduces amplitude variations, RL, …
 Termination RT is commonly an on-chip passive component
 RT often built from a digitally tunable resistor to match ZL

Friedel Gerfers Basics of DAC-based Wireline Transmitters 24

Off-Chip vs On-Chip Termination
RT RX
TX
ZL

DEMUX
MUX
Eq. Driver Eq.
Lp

RX
TX RT
ZL

DEMUX
MUX

Eq. Driver Eq.

Lp

 Off-chip: package parasitics act as unterminated stub  reflections

 On-chip: package inductance Lp part of transmission line
Friedel Gerfers Basics of DAC-based Wireline Transmitters 25
 Series vs Parallel Termination
Series Termination Parallel Termination
RT ZL ZL

VTX ITX RT

Double Termination (TX & RX)

RT ZL ZL

VTX RT ITX RT RT

 Low impedance voltage-mode drivers employ series termination

 High impedance current-mode drivers employ parallel termination
Friedel Gerfers Basics of DAC-based Wireline Transmitters 26
 Series vs Parallel Termination
Series Termination Parallel Termination
RT ZL ZL

VTX ITX RT

Double Termination (TX & RX)

RT ZL ZL

VTX RT ITX RT RT

 Double termination yields best signal quality

 Improved signal integrity forms a trade-off with signal amplitude
Friedel Gerfers Basics of DAC-based Wireline Transmitters 27
AC vs DC Coupled Termination
 DC coupling allows for ITX VCM,RX = ITXRT/2
uncoded data ZL
D D VCM,RX
(non-DC-balanced)
2RT
 RX common-mode set by
transmitter current level RT=ZL RT=ZL ZL VCM,RX

 AC coupling enables flexible ITX

VCM,RX = VTT

RX common-mode level VTT

D D ZL CAC
 Channel has low frequency RCM

high pass corner  data 2RT

must be coded / scrambled ZL CAC RCM
RT=ZL RT=ZL
VTT
Friedel Gerfers Basics of DAC-based Wireline Transmitters
On-Chip Termination Calibration
TX
R R0 R1 R2
RT ZL RT

DEMUX
MUX
Eq. Driver D0 Eq. D1 D2

Di ∈ {0,1}
CDR
PLL Rsw =PLL
0Ω
RT

 Trimmable poly resistor RT  digital code D<2:0> alters actual RT

 Goal ZL = RT with RT = 1/(1/R + D2 /R2 + D1 /R1 + D0 /R0 )
 Note: Switch impedance Rsw usually not negligible
 Note: Temperature dependency
 How to obtain the optimum D<2:0>?
Friedel Gerfers Basics of DAC-based Wireline Transmitters 29
On-Chip Termination Calibration II
VDD,ext
Rext
On-chip Calibration
VDD,int
Replica Terminator RT*
R R0 R1 R2
Cal Code <D2,D1,D0>
D0 D1 D2
Up
Down Count
MUX
I I

Clock

 Calibration loop uses an accurate Rext to match to the replica RT*

 Tuning range & resolution (LSB) considers process variations & RL
 Up ±20% process variations  3 bit lead to ~5% LSB step
Friedel Gerfers Basics of DAC-based Wireline Transmitters 30
Termination, ESD, IO Pads
TX
RT
MUX Ctot = Cp,TX + Cpad + CESD
Eq. Driver
CESD Cp,TX+Cpad
𝑓 𝑝 2𝜋𝑅 𝐶

PLL

 Driver output impedance is frequency dependent  output pole 𝑓

 Contributors:
 TX output and routing capacitance Cp,TX
 IO pad capacitance Cpad
 ESD capacitance CESD, package, bondwire, …

Friedel Gerfers Basics of DAC-based Wireline Transmitters 31

TX Output Bandwidth Limitation
TX 𝜏 𝑅 𝐶
MUX RT ITX Io Vout,TX Io
Eq. Driver
Ctot 0 ITX Io RTRT CC tot
tot 0
0 0 t
Tb Tb
PLL
Tb Tb

 TX output signal 𝑉 , and final settling error 𝑒 at t=Tb=(Rb)-1

 Tb denotes TX bit period and Rb denotes TX data rate
 Low-frequency pole  TX high and low levels experience ISI
𝑡 𝐼 𝑅 −𝑉 , 𝑇 𝑇 2𝜋𝑓
𝑉 , 𝑡 𝐼 𝑅 1 − exp − 𝑒 exp − exp −
𝜏 𝐼 𝑅 𝜏 𝑅
Friedel Gerfers Basics of DAC-based Wireline Transmitters 32
TX Output Bandwidth Limitation
TX
RT eTX (%) 2𝜋𝑓
MUX 𝑒 exp −
Eq. Driver 𝑅
10
Ctot
1

0.1 f-3dB
PLL
0.25 0.5 0.75 1.0 Rb

 Error grows exponentially as bit (data) rate increases

 Typical bandwidth chosen  𝑓 =0.7·Rb  𝑒 ~2.4% (0.2dB)
 Trade off between noise (bandwidth) and ISI
 Example: Rb=56Gbaud/s, 𝑓 = 0.7Rb, RT = 50Ω  Ctot ≤ 80fF

Friedel Gerfers Basics of DAC-based Wireline Transmitters 33

TX with Shunt Peaking
TX
𝑅 1 𝑠
ZT 𝑍 𝑠
1 𝑠𝑅 𝐶 𝑠2𝐿 𝐶
MUX
Eq. Driver
LT
Ctot
ITX Ctot Im(s)
RT p2 z1
PLL Re(s)
p1

 Connect inductor LT in series with termination resistor RT

 Additional zero z1 = –RT /LT and pole p2 = –(1/(RTCtot)+RT /LT)
 Idea: More current used for longer time to charge load capacitance
 Resonance is avoided if damping factor ζ = LT/(RT2Ctot)<1  (p1 < z1)
Friedel Gerfers Basics of DAC-based Wireline Transmitters 35
TX with Shunt Peaking II
TX f-3dB,wo = 39GHz
MUX ZT f-3dB,flat = 67GHz
Eq. Driver f-3dB,max = 72GHz
Ctot

PLL

 Shunt series-peaking increases small-signal bandwidth

 Maximum bandwidth extension of 1.84 for LT/(RT2Ctot)=√2/2=0.707
 Note: 1.5dB peaking
 Maximum flat extension of 1.72 for LT/(RT2Ctot)=1/(1+√2)=1/2.828
Friedel Gerfers Basics of DAC-based Wireline Transmitters 36
TX with Bridged T-Coil
[B. Razavi, JSSC Magazine, 2015]
TX
RT R T=50 , Ctot =80fF
f-3dB,wo = 39GHz
0 f-3dB,flat = 67GHz
L2 f-3dB,Tcoil = 110GHz

|H| (dB)
M Cb
L1 -5
ITX Ctot wo shunt peaking, wo T-coil
w shunt peaking, max. flat
w bridged T-coil
CL -10
0 1 2 3
10 10 10 10
Frequency (GHz)

 T-coil configuration for high output impedance drivers

 Effective output impedance is RT
 Maximum bandwidth extension of 2.83 for ζ=√2/2
 Assumes L1=L2, 4Cb(1+k)=(1-k)CL with k=M/√(L1L2)
Friedel Gerfers Basics of DAC-based Wireline Transmitters 37
TX with Bridged T-Coil II
[J. Paramesh, TCAS I, 2007]
TX
RT
A
L2
C M Cb
ITX Ctot L1

B
CL

 L1=L2=L leads to simple spiral inductor

 Trace (metal) spacing defines mutual coupling
 Outer dimensions and Nr. of turns define the inductance L
 Be aware of self-resonance
Friedel Gerfers Basics of DAC-based Wireline Transmitters 38
TX with Bridged T-Coil III
[B. Razavi, JSSC Magazine, 2015]
TX
RT RT

L2 L2
M Cb Series peaking Cb M
ITX Ctot L1 LS L1 CL

CL ITX CTX

 Input impedance of 2nd-order T-coil is constant

 T-coil input/output can be combined with series peaking LS
 Enables cancellation of large TX parasitic capacitance CTX
Friedel Gerfers Basics of DAC-based Wireline Transmitters 39
Tutorial Overview
 High-speed transceiver overview
 Key TX metrics and design objectives
 Transmitter termination
 High-speed design solutions
 Current-mode DAC driver
 Segmentation
 Voltage-mode DAC driver
 Signal swing enhancements
 High-speed data serialization
 Data multiplexing

Friedel Gerfers Basics of DAC-based Wireline Transmitters 39

Current-Mode DAC Driver
 High-impedance current-mode driver
 Current-mode logic (CML) driver
 N-Bit current-mode DAC
 DAC segmentation
 Non-linear effects and gradient errors

Friedel Gerfers Basics of DAC-based Wireline Transmitters 40

Current-Mode TX (DAC) Driver
TX RX
RT ZL RT

DEMUX
MUX
Eq. Driver Eq.

ZOut CDR
PLL PLL

 Signal integrity demands Zout ≈ RT = ZL = 50Ω output impedance

 Output impedance of driver ≫ RT
 Current-mode drivers use (Norton-equivalent) parallel termination
 Easier to tune output impedance RT
 Review first single-ended design
Friedel Gerfers Basics of DAC-based Wireline Transmitters 41
 High-Impedance Current-Mode Driver
VTT
Vin,H
Vin
τd RT Vin,L = 0V
VTX VRX VTT
rOut,TX = rDS VTX
ITX ZL VTT – ITX ZL
ZL = RT
Vin M1 rDS ≫ RT VRX τd
t
 Keep current source (CS) M1 in saturation region!
 VTT – ITXZL = VTT – ITXRT = VRX > VDSsat,M1
 Make sure rDS ≫ RT across desired bandwidth  cascoded CS
 Keep driver current constant
 Use feedback to set ITX (Vin,H)
 IR drop can shift the bias point: Use current reference

Friedel Gerfers Basics of DAC-based Wireline Transmitters 42

Current-Mode Logic (CML) Driver
VDD VDD

RT=ZL RT=ZL RT=ZL I/2 RT=ZL

I/2 ZL
Vout,TX I/2 Vin,RX

D I ZL
Vin,RX,0 = - (I/2) × RT
D
Vin,RX,1 = + (I/2) × RT
VBias I Vin,RX,ppd = I × RT
I = Vin,RX,ppd / RT

 Differential RX signal swing is ±IRT/2 with double termination

 High output common-mode keeps current source saturated
 Power consumption is Pdiss=VDD×I
Friedel Gerfers Basics of DAC-based Wireline Transmitters 43
Current-Mode Logic (CML) Driver II
VDD

RT=ZL RT=ZL
¾I ZL
Vout,TX ¼I Vin,RX
2RT=2ZL

D I ZL
Vin,RX,0 = - (I/4) × 2RT
D
Vin,RX,1 = + (I/4) × 2RT
VBias I Vin,RX,ppd = I × RT
I = Vin,RX,ppd / RT
 Differential termination with 2RT
 RX signal swing is still ±IRT/2 with double termination
 Power consumption is Pdiss=VDD×I
Friedel Gerfers Basics of DAC-based Wireline Transmitters 44
2-Bit Current-Mode DAC
[B. Razavi, JSSC Magazine, 2018]
VDD
RT=ZL RT=ZL
DAC transfer func.
ZL
+½(3I)RT
Vout,TX 2RT

Vin,RX [V]
Vin,RX
+½(1I)RT
D<1> D<0> ZL -½(1I)RT

D<1> D<0> -½(3I)RT

VBias 2I VBias I 00 01 10 11
MSB LSB D<1:0>
 Binary DAC (I is LSB current)  current sources scale by 2x
 Two bits (D<1> & D<0> ∈ {0,1})  4 levels with 2IRT spacing
 Note: Constant current of 3I independent of D<1:0>
Friedel Gerfers Basics of DAC-based Wireline Transmitters 45
N-Bit Current-Mode DAC Model
VDD
RT=ZL RT=ZL

2RT Vout,TX (x) = ½ · (2x–n) · I · RT

Vout,TX
Vout,TX (N=2, x=3)= ½ · 3 · I · RT

Vout,TX (N=2, x=0)= ½ · (–3) · I · RT

x·I (n-x)·I

 n=2N-1 LSB unit current cells

 x is DAC input code with x ∈ {0,….,n}
Friedel Gerfers Basics of DAC-based Wireline Transmitters 46
4-Bit Binary Weighted Current-Mode DAC
[C.-H. Lin, JSSC, 1998]
VDD
[J. Mulder, ISSCC Tutorial, 2015]
RT=ZL RT=ZL
Vout,TX
possible
glitch
Vout,TX Vin,RX 2RT

Tb Tb

8I 4I 2I I t

(1 0 0 1 )2 = (9)10 = Dpre<3:0>

(0 1 1 0 )2 = (6)10 = Dnew<3:0>
 Data change from (9)10  (6)10  Dnew=Dpre – 8 – 1 + 4 + 2
 Switching of many binary current cells  can cause glitches
Friedel Gerfers Basics of DAC-based Wireline Transmitters 47
4-Bit Thermometer Decoded DAC
VDD
RT=ZL RT=ZL Vout,TX
avoids glitch

Vout,TX Vin,RX 2RT

Tb Tb

I I I t

(0 …………………… 0 1 1 1 1 1 1 1 1 1)2 = (9)10 = Dpre<3:0>

 Unary DAC  15 equal current source with current value I

 Data change from (9)10  (6)10  Dnew=Dpre – 3
 Binary-to-thermometer decoder required
Friedel Gerfers Basics of DAC-based Wireline Transmitters 48
4-Bit Segmented DAC
[C.-H. Lin, JSSC, 1998]
VDD
RT=ZL RT=ZL

Vout,TX Vin,RX 2RT

4I 4I 4I 2I I

Thermometer Binary
(0 1 1 0 1)2 = (9)10
 To balance DAC complexity  segmentation
 MSBs are thermometer encoded, LSBs are binary encoded
Friedel Gerfers Basics of DAC-based Wireline Transmitters 49
Current Source Matching
[M. J.M. Pelgrom, JSSC, 1989]
VDD
[K. R. Lakshmikumar, JSSC, 1989]
RT=ZL RT=ZL
 Current sources designed for matching
Vout,TX 𝜎 Δ𝐼 𝜎 Δ𝛽 𝑔
= + 𝜎 Δ𝑉 (1)
𝐼 𝛽 𝐼

𝜎 Δ𝛽 (𝐴 )2 (𝐴 )2
I+ΔI = (2) 𝜎 Δ𝑉 = (3)
𝛽 𝑊⋅𝐿 𝑊⋅𝐿

 Good matching requires:

𝑔 2  Low Aβ and AVth (CMOS technology parameter)
=  Large transistor area (W·L)  parasitic Cpar
𝐼 𝑉
 Low gm (high overdrive Vgt)  voltage headroom

Friedel Gerfers Basics of DAC-based Wireline Transmitters 50

Output Impedance Variation
VDD
RT RT
 Current sources have finite conductance gds
 Current I is switched
 Conductance gds is switched as well
Vout,TX

 Effective output impedance RT,eff is a function

II ggdsds of DAC input code
I gds
I I g
gdsds

 Introduces DAC non-linearity

Friedel Gerfers Basics of DAC-based Wireline Transmitters 51

 N-Bit Rout DAC Model
[C.-H. Lin, JSSC, 2009]
VDD
x·gds RT RT (n-x)·gds
GT,P = GT + x · gds

Vout,TX GT,N GT,N = GT + (n-x) · gds

GT,P
𝑅
x·I (n-x)·I 𝐻𝐷 ≈
4𝑟

 n=2N-1 LSB unit current cells

 x is DAC input code with x ∈ {0,….,n}
 GT = 1 / RT and rDAC = 1/ (n · gds)
Friedel Gerfers Basics of DAC-based Wireline Transmitters 52
N-Bit Cascoded DAC
VDD
RT RT
 Trade-offs for good linearity:
Vout,TX
(gmrds)3rds
 Decrease RT  power consumption, signal
Mcas2 Mcas2 (gmrds)2rds swing (usually fixed by line impedance)
 Increase rDAC
Msw Msw
 Decrease I  signal swing
(gmrds)rds
 Increase Vgt  voltage headroom
Mcas rds  Use cascodes  voltage headroom
MCS

𝑅
𝐻𝐷 ≈
4𝑟
Friedel Gerfers Basics of DAC-based Wireline Transmitters 53
Output Impedance Distortion
25 47.75
R
T,p
R
24.5 T,n
R
T,eff

24 47.7
RT,p, RT,n

𝑅 𝑅 ·𝑛

T,eff
23.5
𝐻𝐷 ≈ ≈
4𝑟 4·𝑟 ,

R
23 47.65

22.5
𝑛 = 2 − 1 = 2 −1 = 255
22 47.6
0 50 100 150 200 250
DAC input code x

 Example: N=8bit DAC, RT=25Ω

 rds,cell = 63.75kΩ (255·250Ω)  rDAC=1/gDAC= rds,cell/n=250Ω
  |HD3|= 64dB
Friedel Gerfers Basics of DAC-based Wireline Transmitters 54
 N-Bit Cascoded DAC II
[C.-H. Lin, JSSC, 2009]
VDD
RT RT
 Capacitance at source node S
 Switched impedance
Vout,TX  Code-dependent Cout
Mcas2 Mcas2
Cgs Cgs

Msw
 Dynamic non-linearity
IBias Msw IBias
S

Mcas
 Non-linear Cgs of Mcas2 devices
MCS

 Small current IBias linearizes Cgs

 Few % of switched current
 Significant linearity improvement
 Small power increase only
Friedel Gerfers Basics of DAC-based Wireline Transmitters 55
DAC Cell Switches Msw
 Switches operate in:
 Saturation region
 Triode region

 Re-timing of data required

 Latch
 Switch driver
MMswp Mswn
M
swp M swn QQ DD
M
Mswp Mswn
swp swn Q
Q D
D di
QQQ
Q clk
latch

Friedel Gerfers Basics of DAC-based Wireline Transmitters 56

Switches Signals
 Distortion due to glitches at node S
 Coupling to bias node Mswp Mswn
 Glitch mismatch between DAC cells S
MCS
 Optimize crossing point of switch signal
 Non-overlap: Current source turns off shortly
 Overlap: Current division between switches
 Optimum: Small glitch

 Switch signal swing

 Low-swing (CML) driver: Smaller glitch
 CMOS-swing driver: Shorter glitch
Friedel Gerfers Basics of DAC-based Wireline Transmitters 57
Clock & Output Summing Tree Structure
Ioutp Ioutn

Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
D D D D D D D D
clk clk clk clk clk clk clk clk

Vclk
 Equal delay to/from DAC unit cells
 Tree structures recommended for: supply & bias routing
 Separate analog and digital supply rails (data-dependent currents)
Friedel Gerfers Basics of DAC-based Wireline Transmitters 58
Tutorial Overview
 High-speed transceiver overview
 Key TX metrics and design objectives
 Transmitter termination
 High-speed design solutions
 Current-mode DAC drivers
 Segmentation
 Voltage-mode DAC drivers
 Signal swing enhancements
 High-speed data serialization
 Data multiplexing

Friedel Gerfers Basics of DAC-based Wireline Transmitters 59

Voltage-Mode DAC Drivers
 Basic voltage-mode transmitter
 Low-swing and high-swing voltage-mode driver
 N-Bit voltage-mode DAC
 Static current compensation
 Impedance calibration
 Signal swing enhancement

Friedel Gerfers Basics of DAC-based Wireline Transmitters 60

Voltage-Mode TX
TX RX
RT ZL RT

DEMUX
MUX
Eq. Driver Eq.

ZOut CDR
PLL PLL

 Signal integrity demands ZOut+RT=ZL output impedance

 Voltage-mode drivers use (Thévenin-equivalent) series termination
 Potential ½ to ¼ the current for given output swing
 Review first single-ended design
Friedel Gerfers Basics of DAC-based Wireline Transmitters 61
Low-Impedance Voltage-Mode Driver
VO τd VRX Vin,H = VS
RT VTX D
D Vin,L = 0V
ZL
ZOut VSZOut/(2ZL) VS
VS VO 0V
τd VRX VS/2 VS
VO RT VTX VTX
D τd τd
ZL VS
VRX
t0 t0+τd t0+2τd
t
 Inverter switches VO between VS / gnd
 Driver on-resistance ZOut contributes to termination ZL = ZOut + RT
 Duplicating drivers for differential signaling
 Pseudo-differential architecture
Friedel Gerfers Basics of DAC-based Wireline Transmitters 62
Differential Voltage-Mode Driver

D D RT=ZL ZL
VS Vin,RX,0 = - VS / 2
Vin,RX Vin,RX,1 = + VS / 2
VS Vin,RX,ppd = VS
D D RT=ZL ZL I = VS / (2RT)
RT=ZL RT=ZL

D D RT=ZL ZL
VS Vin,RX,0 = - VS / 2
2RT Vin,RX Vin,RX,1 = + VS / 2
VS Vin,RX,ppd = VS
D D RT=ZL ZL I = VS / (4RT)

 Differential RX signal swing is ±VS/2

Friedel Gerfers Basics of DAC-based Wireline Transmitters 63
Simple Low-Swing Voltage-Mode Driver
[K.-L. J. Wong, JSSC, 2004]
VS < 4/3(VDD-VTH-VDSsat) [J. Poulton, JSSC, 2007]
VS VZcont VS
VTX,P (D=0)= ¼·VS
VS VTX,P (D=1)= ¾·VS
D WNtop D WNtop
VTX,P VTX,P
Vin,RX,ppd=VS
ZL ZL

VTX,N VTX,N
ZL ZL
D WNbot D WNbot
VTX,N (D=0)= ¾·VS
VTX,N (D=1)= ¼·VS

 All-NMOS TX driver  transistor width (WN) designed to RNMOS=RT

 Note: Effective VGS different for top and bottom NMOS
 Pre-driver power supply used to control TX impedance
Friedel Gerfers Basics of DAC-based Wireline Transmitters 64
High-Swing Voltage-Mode Driver
[M. Kossel, JSSC, 2008]
VS > VTH+VDSsat [C. Menolfi, ISSCC, 2018]
VS VS

VO,P RT VTX,P VO,P RT VTX,P

D D
VS ZL VS ZL

Zd,P Zd,P

VO,N RT VO,N RT
D D
VTX,N ZL VTX,N ZL

Zd,N Zd,N

 CMOS TX driver  source impedance defined by Zd,i+RT=ZL

 To meet termination resistance of 50Ω  large transistor width
 Trade-off: Pre-driver strength, jitter, timing vs. power consumption
Friedel Gerfers Basics of DAC-based Wireline Transmitters 65
2-Bit Voltage-Mode DAC
VS VS
Zd Zd
 Binary DAC  RU scales by 2x
RU RU
D<1> D<1>
RU RU
 LSB resistance is 2RU
Zd Zd
VTX,N 2RT
 Example: D<1:0>=11 VS VS
VTX,P
Zd Zd
 Rtot = RU || 2 RU = RT = 50Ω
2RU 2RU
D<0> D<0>
 RU = 75Ω 2RU 2RU
Zd Zd
Zd=0Ω

Friedel Gerfers Basics of DAC-based Wireline Transmitters 66

N-Bit Voltage-Mode DAC Model

 n = 2N-1 LSB unit resistors

VS VS
RU RU
 x is DAC input code with x ∈ {0,….,n} x
2RT n–x

 RU = n·RT = n·ZL RU Vout,TX RU

n–x x
 Example: N = 4  n = 15

 RU = 750Ω
RU / 0  ∞

Friedel Gerfers Basics of DAC-based Wireline Transmitters 67

High-Swing Voltage-Mode DAC Driver
VS VS
Cp Cp

VO,P ZL RU ZL
D<n:0> VTX,P D<n:0> VTX,P
RU RT
VS VS
Cp Cp

VO,N RU
D<n:0> D<n:0>
RU VTX,N ZL RU
VTX,N
ZL

Cp

 N-Bit voltage-mode DAC driver  n=2N-1 parallel unit cells

 RU is defined by DAC resolution  RU=n·50Ω
 Note: Data-dependent current consumption  max. at mid-code
Friedel Gerfers Basics of DAC-based Wireline Transmitters 68
4-Bit Voltage-Mode IVDD
VS VS VS VS
RU RU
8
RU IVDD RU
7 15 0
2RT 2RT
10mA
RU Vout,TX RU RU Vout,TX RU
7 8 0 15

5mA
(15𝑅 + 112𝑅 ) 𝑉
𝐼 (𝑥 = 8) = 𝑉 𝐼 (𝑥 = 0) =
𝑅 (2𝑅 + 15𝑅 ) 𝑅
x 2+ 2𝑅
0 3 78 12 15 15
𝐼 (𝑥 = 8) = 9.978𝑚𝐴 𝑉
𝐼 (𝑥 = 0) = = 5mA
4𝑅

 Example: n = 2N-1=15, RU = 750Ω and VS =1V

 VM DAC has ~2x (data dependent) supply current variation
Friedel Gerfers Basics of DAC-based Wireline Transmitters 69
Efficient VM Static Current Compensation
[W. Dettloff, ISSCC, 2010]
[R. Sredojevic, JSSC, 2011]

IVDD
VS
VS VS
10mA
R a*
Ra Rb VTX,N ZL
2RT Di
RT
VS
Vout,TX Xi 2RT
Rb Ra 5mA
R b*
Rc/2 Rc/2 Di
VTX,P
Cac R a* ZL

x
0 3 78 12 15

 Reduce static current variations IVDD

 Employ shunting devices between diff. outputs
 Per code x, new set of Ra, Rb, Rc selected to maintain Rdiff and RCM
 Trade-off: Hardware complexity vs. power consumption
Friedel Gerfers Basics of DAC-based Wireline Transmitters 70
Fast Switching
[H. Ghafarian, SSC Letters, 2020]
VS
𝑉 1 3𝑉 1
Zd 𝑉 = 𝑉 =
4 1+𝑟 4 1+𝑟
RU ZL
D<n:0> VTX,P

RT
VS
Zd 𝑉 𝑟 = 4 = 50 … 150𝑚𝑉
RU
D<n:0>
VTX,N
RU ZL 𝑉 𝑟 = 2 = 83 … 250𝑚𝑉
Zd

 Make transistors become significant part of impedance RT

 Smaller ratio rR=RU/Zd  increase Zd  decrease W  smaller Cp
 Trade-off: Switch non-linearity vs. timing performance
Friedel Gerfers Basics of DAC-based Wireline Transmitters 71
VM Driver: Digital Impedance Calibration
[A. DeHon, ISSCC, 1993]
VS

VS P1 1x P2 2x P5 16x 8x }Z Cal,P

Zd,P RT+Zd,P ≠ ZL
Zd,P
RT RT
D VTX,P D
RT VTX,P
RT
RT+Zd,N ≠ ZL
Zd,N Zd,N
N1 1x N2 2x N5 16x 8x }Z Cal,N

 Process variations of RT & Zd,N / Zd,P result in impedance mismatch

 Choose digital Ni, Pi such that RT+Zd,N+ZCal,N ≜ RT+Zd,P+ZCal,P ≜ ZL
 Note: always-on device defines maximum ZCal,N & ZCal,P value
Friedel Gerfers Basics of DAC-based Wireline Transmitters 72
Signal-Swing Enhanced VM Transmitter
NRZ VDDH PAM4 2IS/3 IS/3
MSB MSB LSB LSB
IS
VS
3/2RT
D MSB
D VTX,P

VTX,P 3RT
VO,P RT LSB
ZL
D
VS ZL 3/2RT
MSB

3RT VTX,N ZL
VO,N RT LSB
D
VTX,N ZL
MSB MSB LSB LSB
2IS/3 IS/3
[A. Joy, ISSCC, 2011] [M. Bassi, ISSCC, 2016]

 VM driver + CML stage

 Enhanced output swing from VS to (VS +2ISRT)
 Slightly affects the TX return loss & needs calibration
Friedel Gerfers Basics of DAC-based Wireline Transmitters 73
Current-Mode vs. Voltage-Mode Comparison
Driver / Termination Signal Current Normalized Current
Current-Mode / Single-Ended Vin,RX,pp/ZL 1x
Current-Mode / Differential Vin,RX,pp/ZL 1x
Voltage-Mode / Single-Ended Vin,RX,pp/(2ZL) 0.5x
Voltage-Mode / Differential Vin,RX,pp/(4ZL) 0.25x

 Pro: Ideal voltage-mode driver with differential RX termination

 potential of 4x reduction in power consumption
 Actual driver power consumption depends on:
 Output impedance control, pre-driver power consumption, equalization
implementation
 Con: Voltage-mode driver has limited power supply rejection
Friedel Gerfers Basics of DAC-based Wireline Transmitters 74
Tutorial Overview
 High-speed transceiver overview
 Key TX metrics and design objectives
 Transmitter termination
 High-speed design solutions
 Current-mode DAC drivers
 Segmentation
 Voltage-mode DAC drivers
 Signal swing enhancements
 High-speed data serialization
 Data multiplexing

Friedel Gerfers Basics of DAC-based Wireline Transmitters 75

High-Speed Data Serialization
 Full-rate TX architecture
 Half-rate TX architecture
 Clock duty-cycle mismatch
 Quarter-rate TX architecture
 Output-multiplexed TX architecture

Friedel Gerfers Basics of DAC-based Wireline Transmitters 76

 Full-Rate TX Architecture
TX d0 FF
1 1 UI critical path
d2 clk
FF L 0 d02 FF
1 RT clk/2
FF dout
Driver
d13 FF L 0 clk/4
d1 FF
1
d2d02 d0 d2 d0 d2 d0
d3 FF L 0
d3d13 d1 d3 d1 d3 d1
clk/4 clk/2
1/2 1/2 clk dout
d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2

 Final flip-flop (FF) uses a full-rate clock clk of Tclk = Tbit

 Critical path defines maximum data rate
 FF clk-Q delay tFF,CQ + mux delay tMUX + FF setup time tFF,set < 1 UI
 Full-rate TX architecture with cascade of 2:1 mux stages
Friedel Gerfers Basics of DAC-based Wireline Transmitters 77
 Full-Rate TX Architecture II
TX d0 FF
1 1 UI critical path
d2 clk
FF L 0 d02 FF
1 RT clk/2
FF dout
Driver
d13 FF L 0 clk/4
d1 FF
1
d2d02 d0 d2 d0 d2 d0
d3 FF L 0
d3d13 d1 d3 d1 d3 d1
clk/4 clk/2
1/2 1/2 clk dout
d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2

 Pro: Full-rate architecture relaxes clock duty-cycle sensitivity

 Con: Limited data rate (tFF,CQ + tMUX + tFF,set < 1 UI)
 Generate and distribute high-speed clock
 Demands high-speed flip-flops (FF) and latches (L)
Friedel Gerfers Basics of DAC-based Wireline Transmitters 78
 Half-Rate TX Architecture
TX d0 FF
1 1 UI critical path
d2 FF L 0 d02 FF
0 RT clk/2
dout
Driver
d13 FF L 1 clk/4
d1 FF
1
d2d02 d0 d2 d0 d2 d0
d3 FF L 0
d3d13 d1 d3 d1 d3 d1
clk/4
1/2 clk/2 dout
d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2

 Half-rate TX architecture uses both clock phases of clk/2

 Half-rate architecture relies on accurate (50%) clk/2 duty-cycle
 Final MUX control swapped to prevent glitches

Friedel Gerfers Basics of DAC-based Wireline Transmitters 79

 Half-Rate TX Architecture II
TX d0 FF
1 1 UI critical path
d2 FF L 0 d02 FF
0 RT clk/2
dout
Driver
d13 FF L 1 clk/4
d1 FF
1
d2d02 d0 d2 d0 d2 d0
d3 FF L 0
d3d13 d1 d3 d1 d3 d1
clk/4
1/2 clk/2 dout
d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2

 Pro: Critical path without flip-flop  data rate maximized

 Pro: Half-rate architecture  lower power
 No high-speed (full-rate) clock distribution
 Con: Data eye sensitive to clock duty-cycle mismatch
Friedel Gerfers Basics of DAC-based Wireline Transmitters 80
Half-Rate TX – Duty-Cycle Mismatch
TX 50% duty-cycle Non-50% duty-cycle

dodd RT dodd
dout
Driver deven
deven
clk/2
clk/2 dout

dout eye

 Problem: Clock duty-cycle mismatch of clk/2

 Duty-cycle mismatch affects transmitter output eye
 Long – short dout pattern
 Half-rate transmitters demand a duty-cycle correction circuit
Friedel Gerfers Basics of DAC-based Wireline Transmitters 81
Quarter-Rate TX
TX TX
dodd RT d0 RT
d1 4:1
Driver Driver
d2 MUX
deven d3

clk90
clk0

clk180
clk270
clk/2
clk/2

 CMOS 2:1 MUX able to propagate minimum pulse

 Half-rate clk/2 distribution still limited by clock distribution
 Quarter-rate architecture  enables 56Gbaud/s in 22nm FDX
Friedel Gerfers Basics of DAC-based Wireline Transmitters 82
Current-Mode Output-Multiplexed TX
[C.-K. K. Yang, 1998]
TX VDD [C. Menolfi, ISSCC, 2011]
RT RT

Vout,TX
clk/2 Mclk Mclk clk/2 clk/2 Mclk Mclk clk/2

deven Msw Msw deven dodd Msw Msw dodd

 2:1 current-mode MUX function at TX output pads

 Makes sense if output time constant 𝝉 is smaller than on-chip
 𝝉 =25Ω·COut
 Very sensitive to clock phase spacing
Friedel Gerfers Basics of DAC-based Wireline Transmitters 83
Relevant TX Papers to See This Year
Suggested TX papers based on ISSCC 2021 Advance Program

 8.1: „A 224Gb/s DAC-based PAM-4 Transmitter with 8-Tap FFE in

10nm CMOS“
 8.2: „An Output Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter
with 5-Tap FFE in 28nm CMOS“
 8.3: „An 8b DAC-based SST TX using metal gate resistors with
1.4pJ/b efficiency at 112Gb/s PAM4 and 8-taps FFE in 7nm CMOS“
 8.4: „A 116Gb/s DSP based Wireline Transceiver in 7nm CMOS
achieving 6pJ/bit at 45dB Loss in PAM4/Duo-PAM4 and 52dB in PAM2“
 11.2: „A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit
efficiency in 7nm CMOS “

Friedel Gerfers Basics of DAC-based Wireline Transmitters 84

References I
[1] TU Berlin Wireline Transceiver Survey: https://www.msc.tu-berlin.de/menue/research/wireline_survey/
[2] Oregon State Wireline Transceiver Survey: https://web.engr.oregonstate.edu/~anandt/linksurvey/
[3] MIT, Digital Communication Systems: http://web.mit.edu/6.02/www/s2011/handouts/L07_slides.pdf

T-Coil
 J. Paramesh, D. Allstot, “Analysis of the Bridged T-Coil Circuit Using the Extra-Element Theorem“,
IEEE Tran. Circuits and Systems II, 2007
 B. Razavi, “The bridged T-Coil”, IEEE Solid-State Circuits Magazine, 2015

MOS Matching, Tuning

 M. J.M. Pelgrom, et al., “Matching properties of MOS transistors”, JSSC, 1989
 K. R. Lakshmikumar, et al., “Characterization and modeling of mismatch in MOS transistors for
precision analog design”, JSSC, 1989
 A. DeHon, et al. “Automatic Impedance Control“, ISSCC, 1993
 E. Wittenhagen, et al., “Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in
CMOS”, TCAS I, 2020

Friedel Gerfers Basics of DAC-based Wireline Transmitters 85

References II
Current-Steering DAC
 B. Razavi, “The Current-Steering DAC [A Circuit for All Seasons]”, JSSC Magazine, 2018
 J. Mulder, “High-Speed Current-Steering DACs”, ISSCC Tutorial, 2015
 C.-H. Lin, et al., “A 12b 2.9GS/s DAC with IM3 <-60dBc Beyond 1GHz in 65nm CMOS”, JSSC, 2009
 K. O. Andersson, et al., “A Method of Segmenting Digital-to-Analog Converters”, Symp. MSD, 2003
 C.-H. Lin, et al., “A 10-b 500MSample/s CMOS DAC in 0.6mm2”, JSSC, 1998
 Chih-Kong Ken Yang, “Design of high-speed serial Links in CMOS”, PhD Stanford, 1998
 T. Toifl, et al., "A 0.3pJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14nm CMOS”,
Symp. VLSI Circuits, pp. 53-54, Jun. 2018
 J. Kim et al., “A 112-Gb/s PAM-4 56 Gb/s NRZ reconfigurable transmitter with thee-tap FFE in 10-
nm FinFET”, JSSC, 2019.
 Z. Toprak-Deniz et al. "A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm
CMOS," ISSCC, 2019
 E. Groen et al., “A 10-to-112Gb/s DSP-DAC-based transmitter with 1.2Vppd output swing in 7nm FinFET,”
ISSCC, pp. 120-122, Feb. 2020

Friedel Gerfers Basics of DAC-based Wireline Transmitters 86

References III
Voltage-Mode DACs
 W.D. Dettloff, et al., “A 32mW 7.4Gb/s Protocol-Agile Source-Series Terminated Transmitter in 45nm CMOS
SOI”, ISSCC, 2010
 R. Sredojevic, “Fully Digital Transmit Equalizer With Dynamic Impedance Modulation”, JSSC, 2011
 K.-L. J. Wong et al., “A 27-mW 3.6Gb/s I/O Transceiver”, JSSC, 2004
 J. Poulton, et al.,”A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS”, JSSC, 2007
 M. Kossel, et al., “A T-Coil-Enhanced 8.5Gb/s High-Swing SST Transmitter in 65nm Bulk CMOS With <-16dB
Return Loss Over 10GHz Bandwidth”, JSSC, 2008
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