• Gate-level minimization

Karnaugh map, K-map or Veitch diagram

• A K-map is a diagram made up of squares, with each square
representing one minterm of the function.
Note: Any Boolean function can be expressed as the sum of minterms.
 n 2n

Note:
Karnaugh map steps
1. Two variable k-map
n = 2 means 22 => 4 squares or cells (4 minterms)

3
AB A+B
2. Three variable K-map
3 variables means 23 => 8 squares
or cells (minterms)
Note: The minterms are arranged,
not according to the binary
sequence, rather they are arranged
so that the change between two
consecutive rows or columns is only
one single variable; changes its logic
value from 0 to 1 or from 1 to 0. Note: The map can be constructed with
different order, like B as row and A&C as
columns, but with the same mis.
Map method

Simplify f = a’bc +a’bc’ + ab’c’ +ab’c using k-map.

b’c’ b’c bc bc’

a’
1 1
a
1 1

f = a’b + ab’
Map method

Simplify f = a’bc +ab’c’ + abc +abc’ using k-map.

b’c’ b’c bc bc’

a’
1
a
1 1 1

f = ac’ + bc
Map method

Simplify f = a’b’c +a’bc + a’bc’ +ab’c + abc using k-map.

b’c’ b’c bc bc’

Ex: simplify the expression
a’ 1 1 f(a,b,c) = Σ(0,1, 2,4,6)
1
a
1 1

f = c + a’b
 3. 4 variable k-map
4 variables, 24 => 16 squares or minterms
 When two adjacent squares are combined, it is called a
pair and represents a term with three literals.
 Four adjacent squares, when combined, are called a
quad and its number of literals is two.
 If eight adjacent squares are combined, it is called an
octet and represents a term with one literal.
 If all sixteen squares can be combined, the function will
be reduced to 1.
Eg: f(a,b,c,d) = Σ (1,3,5,6,7,12,13,14,15)
 0
f’ f
 1

X
 Note:

A B C D Y CD
0 0 0 0 0 00 01 11 10
0 0 0 1 0 AB
0

0
0

0
1

1
0

1
0

0
00
0 1 0 0 0 01 1
0 1 0 1 0

0 1 1 0 0 11 x x x x
0

1
1

0
1

0
1

0
1

1
10 1 1 x x
1 0 0 1 1
Without “don’t care”
1 0 1 0 X
Y  AB C  A BCD
1 0 1 1 X

1 1 0 0 X
With “don’t care”
1 1 0 1 X Y  A  BCD
1 1 1 0 X

1 1 1 1 X
 NAND & NOR Implementation
• Digital circuits are mainly made from NAND and NOR components
due to the ease of their electrical circuit manufacturing.
• they are prominent in digital IC manufacturing and there are rules
and procedures are already setup for converting Boolean functions
given in AND, OR and NOT into the equivalent NAND or NOR logic
diagrams.
 ► NAND

Any digital circuit can be constructed with NAND logic gates and it is
called universal gate.

NOT

AND

OR
AND-Invert
Equivalent
multivariable NAND
representations
Invert -OR
Steps:
1.
2.

3.
 Eg 1 f = a’b’c +a’bc + a’bc’ +ab’c + abc
and implement it with NAND gates only.

b’c’ b’c bc bc’

a’ 1 1 1
a
1 1

f = c + a’b
 Eg 2 f = Σ(1,2,3,4,5,7)
and implement it with NAND gates only.

b’c’ b’c bc bc’

a’ 1 1 1
a
1 1 1

f = ab’ + a’b + c
 ► NOR

• It is the dual of NAND operation.

• NOR gate can be used to implement all Boolean functions.

NOT

OR

AND
 Level 1 Level 2 Level 3 Level 4
C
F = A (B + C D) + B C' D
Original F
B
AND-OR
A
network
B
C’

C
D
introduction and F
B
conservation of
A
bubbles
B
C’

C
redrawn in terms D
F
of conventional B’
NAND gates A
B
C’
 Level 1 Level 2 Level 3 Level 4
F = A (B + C D) + B C' C
D
Original F
AND-OR B
network A
B
C’
C

introduction and D
F
conservation of B
bubbles A
B
C’

C’
D’ F
redrawn in terms
B
of conventional
NOR gates A’
B’
C
NOT-AND-OR implementation

NAND implementation
Reading assignment