Digital electronics

1-Sequential circuit counters

Such a group of flip- flops is a counter. The number of flip-flops used and the way in which
they are connected determine the number of states and also the specific sequence of states
that the counter goes through during each complete cycle.
Counters are classified according to the way they are clocked: asynchronous and
synchronous. Within each of these two categories, counters are classified primarily by the
type of sequence, the number of states, or the number of flip-flops in the counter.

1-Asynchronous Counter Operation

Asynchronous counters called ripple counters, the first flip-flop is clocked by the external
clock pulse and then each successive flip-flop is clocked by the output of the preceding flip-
flop. The term asynchronous refers to events that do not have a fixed time relationship with
each other . An asynchronous counter is one in which the flip-flops within the counter do not
change states at exactly the same time because they do not have a common clock pulse.

A 2-Bit Asynchronous Binary Counter

Fig1-1 shows a 2-bit counter connected for asynchronous operation. Notice that the clock
(CLK) is applied to the clock input (C) of only the first flop-flop, FF0, which is always the
least significant bit (LSB). The second flip-flop, FF1, is triggered by the ‾Q0 out-put of FF0.
FF0 changes state at the positive-going edge of each clock pulse. But FF1 changes only when
triggered by a positive-going transition of the ‾Q0 output of FF0. Because of the inherent
propagation delay tie through a flip-flop, a transition of the input clock pulse (CLK) and a
transition of the ‾Q0 output of FF0 can never occur at exactly the same time. Therefore, the
two flip-flops are never simultaneously triggered, so the counter operation is asynchronous.

Fig1-1 2-bit asynchronous counter

The Timing Diagram

Applying 4clock pulses to FF0, Both flip-flops are connected for toggle operation (J=1, K=1)
and initially RESET (Q LOW). The positive-going edge of CLK1 (clock pulse1) causes the Q0
output of FF0 to go HIGH. At the same time the ‾Q0 output goes LOW, but it has no effect on
FF1 because a positive-going transition must occur to trigger the flip-flop. After the leading
edge of CLK1, Q0=1 & Q1=0. The positive-going edge of CLK2 causes Q0 to go LOW.
‾Q0 goes HIGH and triggers FF1, causing Q1 to go HIGH. After the leading edge of CLK2,
Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again. Output ‾Q0
goes LOW and has no effect on FF1. Thus, after the leading edge of CLK3, ‾Q0=1 & Q1=1.
The positive-going edge of CLK4 causes Q0 to go LOW, while ‾Q0 goes HIGH and triggers
1
FF1, causing Q1 to go LOW. After the leading edge of CLK4, Q0 =0 & Q1=0. The 2-bit
counter exhibits four different states, as you would expect with two flip-flops (22 = 4).

Fig 1-2 Timing diagram for the counter of Fig1-1 Table 1-1Binary state sequence

The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it refers to
the transition of the counter from its final state back to its original state.

A 3-Bit Asynchronous Binary Counter

Table1-2 State sequence for a 3-bit binary counter

Fig 1-3 Three-bit asynchronous binary counter and its timing diagram for one cycle.
2
 Fig 1-4Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

Example 1-1: A 4-bit asynchronous binary counter is shown in Fig1-5(a). Each flip-flop is
negative edge-triggered and has a propagation delay for 10 ns. Develop a timing diagram
showing the Q output of each flip-flop, and determine the total propagation delay time from
the triggering edge of a clock pulse until a corresponding change can occur in the state of
Q3, Also determine the maximum clock frequency at which the counter can be operated.
Solution: The timing diagram with delays omitted is as shown in Fig1-5(b). For the total
delay time, the effect of CLK8 or CLK 16 must propagate through four flip-flops before Q3
changes, so tP(tot) = 4 x 10 ns = 40 us
The maximum clock frequency is fmax =1/ tP(tot) = 1/40 ns = 25 MHz

Fig 1-5 4-bit asynchronous binary counter and its timing diagram.
3
Related Problem: Show the timing diagram if all of the flip-flops in Fig1-5(a) are positive
edge- triggered.
Asynchronous Decade Counters
The modulus is the number of unique states through which the counter will sequence. The
maximum possible number of states of a counter is 2n where n is the number of flip-flops.
Counters can be designed to have a number of states in their sequence that is less than the
maximum of 2n. This type of sequence is called a truncated sequence. One common modulus
for counters with truncated sequences is 10 (Modules10). A decade counter with a count
sequence of zero (0000) through 9 (1001) is a BCD decade counter because its 10-state
sequence produces the BCD code. To obtain a truncated sequence, it is necessary to force the
counter to recycle before going through all of its possible states. A decade counter requires 4
flip-flops. One way to make the counter recycle after the count of 9 (1001) is to decode count
10 (1010) with a NAND gate and connect the output of the NAND gate to the clear (CLR)
inputs of the flip-flops, as shown in Fig1-6(a).
Partial Decoding: in Fig1-6(a) only Q1 & Q3 are connected to the NAND gate inputs. This
arrangement is an example of partial decoding, in which the two unique states (Q1=1 &
Q3=1) are sufficient to decode the count of 10 because none of the other states (0 through 9)
have both Q1 & Q3 HIGH at the same time.

Fig 1-6 an asynchronously clocked decade counter with asynchronous recycling.

4
Example1-2: Show how an asynchronous counter can be implemented having a modulus of
12 with a straight binary sequence from 0000 through 1011
Solution: 4 flip-flops are required to produce any modulus greater than 8 but less than or
equal to 16. When the counter gets to its last state.1011, it must recycle back to 0000 rather
than going to its normal next state of 1100, as illustrated in the following sequence chart:

Observe that Q0 & Q1 both go to 0 anyway, but Q2 & Q3 must be forced to 0 on the 12 clock
pulse. Fig1-7a shows the modulus-12 counter. The NAND gate partially decodes count 12
(1100) and resets flip-flop2 & flip-flop 3. Thus, on the 12 clock pulse, the counter is forced to
recycle from count 11 to count 0, as shown in the timing diagram of fig1-7b.

Fig1-7 asynchronously clocked modulus-12 counter with asynchronous recycling

Related Problem How can the counter in fig1-7a be modified to make it a modulus-13
counter?
5
2- Synchronous counter operation
In synchronous counters, the clock input is connected to all of the flip-flops so that they are
clocked simultaneously. The term synchronous refers to events that have a fixed time
relationship with each other.
A 2-Bit Synchronous Binary Counter

Fig 1-8 A 2-bit synchronous binary counter

First, when the positive edge of the first clock pulse is applied, FF0 will toggle and Q0 will
therefore go HIGH. When FF1at the positive-going edge of CLK1 inputs J1 & K1 are both
LOW because Q0 has not yet gone HIGH. So, J1=0 & K1=0 . This is a no-change condition,
and therefore FF1 does not change state (fig1-9a).
When the leading edge of CLK2 occurs, FF0 will toggle and Q0 will go LOW and Q1 goes
HIGH. Thus, after CLK2, Q0=0 & Q1=1 (Fig1-9b).
When the leading edge of CLK3 occurs, FF0 again toggles to the SET state (Q0= 1), and FF1
remains SET (Q1=1 . After this triggering edge, Q0 =1 & Q1 =1 (Fig1-9c).
at the leading edge of CLK4, Q0 & Q1 go LOW (Fig1-9d).

Fig 1-9 timing details for the1-bit synchronous counter operation

Fig 1-10 complete timing diagram for the counter

6
A 3-Bit Synchronous Binary Counter

Fig1-11 3-bit synchronous counter

Fig1-12 the timing diagram Table1-3 Binary state sequence

A 4-Bit Synchronous Binary Counter

Fig1-13 a 4-bit synchronous binary counter and timing diagram. Points where the AND
gate outputs are HIGH are indicated by the shaded areas.
7
A 4-Bit Synchronous Decade Counter

Fig1-14 a synchronous BCD decade counters

Fig1-15 Timing diagram for the BCD Counter table 1-4 States of a BCD decade

3-Up-Down counter
An up/down (bidirectional) counter is one that is capable of progressing in either direction
through a certain sequence.

An examination of Q0 for both the up and down sequences shows that FF0 toggles on each
clock pulse. Thus, the J0 & K0 inputs of FF0 are J0=K0=1. For the up sequence, Q1 changes
state on the next clock pulse when Q0 =1. For the down sequence, Q1 changes on the next
clock pulse when Q0= 0. Thus, the J1 & K1 inputs of FF1 must equal 1 under the conditions
expressed by the following equation:
J1 = K1 = (Q0 .UP) + (‾Q0 .DOWN)
For the up sequence, Q2 changes state on the next clock pulse when Q0=Q1=1. For the down
sequence, Q2 changes on the next clock pulse when Q0=Q1= 0. Thus, the J2 & K2 inputs of
FF2 must equal 1 under the conditions expressed by the following equation:

J2 = K2 = (Q0 .Q1.UP) + (‾Q0 .‾Q1 .DOWN)

Notice that the UP/ ‾‾DOWN control input is HIGH for UP and LOW for DOWN.
8
Fig1-16 a basic 3-bit up/down synchronous counter table1-5 Up/Down sequence

Example1-4: Show the timing diagram and determine the sequence of a 4-bit synchronous
binary up/down counter if the clock and UP/‾‾DOWN control inputs have waveforms as
shown in fig1-7a. The counter starts in the all 0s state and is positive edge-triggered.
Solution: From the waveforms of fig2-17b, the counter sequence is as shown in Table 1-6.

Fig 1-17 Table 1-6

Related Problem Show the timing diagram if the UP/ ‾‾DAWN control waveform in fig1-17a
is inverted.

Design of synchronous counters

General Model of a Sequential Circuit
a general sequential circuit consists of a combinational logic section and a memory section
(flip-flops), as shown in Fig 1-18.

9
 Figure 1-18 General clocked sequential circuit
The information stored in the memory section, as well as the inputs to the combinational
logic (I0, I1, . . ., Im), is required for proper operation of the circuit. At any given time the
memory is in a state called the present state and will advance to a next state on a clock pulse
a determined by conditions on the excitation lines (Y0, Y1 , . . . , Yp) the present state of the
memory is represented by the state variables (Q0 , Q1, . . . , Qt). These state variables, along
with the inputs (I0, I1,,. . . . , Im) determine the system outputs (O0 , O1, . . . , On).
a general design procedure for sequential circuits is applied to synchronous counters in a
series of steps:
Step 1: State Diagram
The first step in the design of a counter is to create a state diagram. A state diagram shows
the progression of states through which the counter advances when it is clocked. As an
example, Fig1-19 is a state diagram for a basic 3-bit Gray code counter. This particular
circuit has no inputs other than the clock and no outputs other than the outputs taken off each
flip-flop in the counter.

Fig 1-19 State diagram for a 3-bit Gray code counter

Step 2: Next-State Table
Once the sequential circuit is defined by a state diagram, the second step is to derive a next-
state table, which lists each state of the counter (present state) along with the corresponding
next state. The next state is the state that the counters guess to from its present state upon
application of a clock pulse the next-state table is derived from the state diagram and is
shown in Table 1-7 for the 3-bit Gray code counter. Q0 is the least significant bit.

10
 Table1-7 Next-state table for 3-bit Gray code counter.
Step 3: Flip-Flop Transition Table
Table 1-8 is a transition table for the J-K flip-flop. All possible output transitions are listed
by showing the Q output of the flip-flop going from present states to next states. QN is the
present state of the flip-flop (before a clock pulse) and QN + 1 is the next state (after a clock
pulse). For each output transition the J & K inputs that will cause the transition to occur are
listed. An X indicates a "don't care" (the input can be either a 1 or 0).

Table1-8 Transition table for a J-K flip-flop

To design the counter, the transition table is applied to each of the flip-flops in the counter,
based on the next-state table (Table 1-7). For example, for the present state 000, Q0 goes
from a present state of 0 to a next state of 1. To make this happen J0 must be a 1 and you
don't care what K0 is (J0= 1, K0 = X), as you can see in the transition table (Table 1-8). Next,
Q1 is 0 in the present state and remains 0 in the next state. For this transition, J1 = 0 & K1 =
X. Q2 is 0 in the present state and remains 0 in the next state. Therefore, J2= 0 & K2 = X.
Step 4: Karnaugh Maps
Karnaugh maps can be used to determine the logic required for the J & K inputs of each flip-
flop in the counter. There is a Karnaugh map for the J input & a Kamaugh map for the K
input of each flip-flop. Each cell in a Karnaugh Maps represents one of the present states in
the counter sequence listed in Table 1-7. From the J & K states in the transition table (Table
1-8) a 1,0, or X is entered into each present state cell on the maps depending on the
transition of the Q output for a particular flip- flop. To illustrate this procedure, two sample
entries are shown for the J0 & K0 inputs to the least significant flip-flop (Q0) in Fig 1-20.

11
Fig1-20Examples of the mapping procedure for the counter sequence

Fig1-21 Q( ) Karnaugh maps for present-state J & K inputs.

12
The completed Karnaugh Maps for all three flip-flops in the counter are shown in fig1-21.
The cells are grouped as indicated and the corresponding Boolean expressions for each
group are derived.
Step 5: logic Expressions for Flip-Flop Inputs
From the Karnaugh maps of fig1-21 you obtain the following expressions for the J & K
inputs of each flip-flop:

Step 6: Counter Implementation

The final step is to implement the combinational logic from the expressions for the J & K
inputs and connect the flip-flops to form the complete 3-bit Gray code counter as in fig 1-22.

Fig1-22 3-bit Gray code counters

A summary of steps used in the design of this counter follows. In general, these steps can be
applied to any sequential circuit:
1. Specify the counter sequence and draw a state diagram.
2. Derive a next-state table from the state diagram.
3. Develop a transition table showing the flip-flop inputs required for each transition, The
transition table is always the same for a given type of flip-flop.
4. Transfer the J & K states from the transition table to Karnaugh maps. There is a
Karnaugh map for each input of each flip-flop.
5. Group the Karnaugh map cells to generate and derive the logic expression for each flip-
flop input.
6. implement the expressions with combinational logic, and combine with the flip-flops to
create the counter.
Example1-5:Design a counter with the binary count sequence shown in the state diagram of
Fig 1-23. Use J-K flip-flops.

13
 Fig1-23 state diagram for Ex5
Solution:
Step 1: Although there are only 4 states, a 3-bit counter is required to implement this
sequence because the maximum binary count is 7. Since the required sequence dues not
include all the possible binary, states, the invalid states (0, 3, 4, & 6) can be treated as "don't
cares" in the design. However, if the counter should erroneollsly get into an invalid state, you
must make sure that it goes back to a valid state.
Step 2: The next-state table is developed from the state diagram and is given in Table 1-9.

Table 1-9Next state table

Step 3:
The transition table for the J-K flip-flop is repeated in Table 1-10.

Table 1-10 transition table for J-K flip-flop

Step 4:
The J & K inputs are plotted on the present-state Karnaugh maps in fig1-24. Also "don't
cares" can be placed in the cells corresponding to the invalid states of 000, 011, 100, and
110, as indicated by the Xs.

14
 Fig1-24
Step 5:
Group the 1s, taking advantage of as many of the "don't care" states as possible for maximum
simplification(fig1-24). Notice that when all cells in a map are grouped, the expression is
simply equal to1. The expression for each J & K input taken from the maps is as follows:
Step 6:
The implementation of the counter is shown in Fig1-25.

Fig1-25
Analysis shows that if the counter, by accident, gets into one of the invalid states (0, 3, 4, 6 ),
it will always return to a valid state according to the following sequences: 0→3→ 4 →7. &
6→ 1
Cascaded counter
Counters can be connected in cascade to achieve higher-modulus operation. In essence,
cascading means that the last age output of one counter drives the input of the next counter.
An example of two counters connected in cascade is shown in fig1-26 for a 2-bit & a 3-bit
ripple counter.

Fig1-26 Two cascaded counters (all J & K inputs are HIGH).

15
 Fig1-27 Timing diagram for the cascaded counter configuration of Fig1-26

The timing diagram is shown in fig1-27. Notice that the final output of the modulus-8
counter, Q4 , occurs once for every 32 input clock pulses. The overall modulus of the
cascaded counters is 32; that is, they act as a divide-by-32 counter.
When operating synchronous counters in a cascaded configuration, it is necessary to e the
count enable and the terminal count functions to achieve higher-modulus operation. On some
devices the count enable is CTEN (or G), and terminal count (TC) is analogous to ripple
clock output (RCO) on some IC counters.
Fig1-28 shows two decade counters connected in cascade. The terminal count (TC) output of
counter 1 is connected to the count enable (CTEN) input of counter 2.
Counter 2 is inhibited by the LOW on its CTEN input until counter 1 reaches its last, or
terminal, state and its terminal count output goes HIGH. This HIGH now enables counter 2,
so that when the first clock pulse after counter 1 reaches its terminal count (CLK10), counter
2 goes from its initial state to its second state. Upon completion of the entire second cycle of
counter 1 (when counter 1 reaches terminal count the second time), counter 2 is again
enabled and advances to its next state. This sequence continues. Since these are decade
counters. Counter1 must go through ten complete cycles be fore counter 2 completes its first
cycle. In other words, for every ten cycles of counter 1, counter 2 goes through one cycle.
Thus, counter 2 will complete one cycle after one hundred clock pulses. The overall modulus
of these two cascaded counters is 10 x 10 = 100.

Fig1-28 A modulus-100 counter using two cascaded decade counters.

16
When viewed as a frequency divider, the circuit of fig1-28 divides the input clock frequency
by 100. Cascaded counters are often used to divide a high-frequency clock signal to obtain
highly accurate pulse frequencies. Cascaded counter configurations used for such purposes
are sometimes called countdown chains. For example, suppose that you have a basic clock
frequency of 1 MHz and you wish to obtain 100 kHz, 10 kHz, and 1 kHz: a series of cascaded
decade counters can be used. If the 1 MHz signal is divided by 10, the output is 100 kHz.
Then if the 100 kHz signal is divided by 10, the output is 10 kHz. Another division by 10
produces the 1 kHz frequency. The general implementation of this countdown in fig1-29

Fig1-29 Three cascaded decade counters forming a divide-by-1000 frequency divider with
intermediate divide-by-10 and divide-by-100 outputs.

Example1-7 :Determine the overall modulus of the two cascaded counter configurations in
fig1-30.

fig 1-30
Solution: In fig1-30(a), the overall modulus for the 3-counter configuration is:
8 x 12 x 16 = 1536
In fig1-3(b), the overall modulus for the 4-counter configuration is:
10 x 4 x 7 x 5 = 1400

Related Problem: How many cascaded decade counters are required to divide a clock
frequency by 100,000?

Counter decoding
In many applications, it is necessary that some or all of the counter states be decoded. The
decoding of a counter involves using decoders or logic gates to determine when the counter is
in a certain binary state in its sequence.
Suppose that you wish to decode binary state 6(110) of a 3-bit binary counter. When Q2= 1,
Q1 = 1. & Q0 = 0. a HIGH appears on the output of the decoding gate, indicating that the

17
counter is at state 6(fig1-31). This is called active-HIGH decoding. Replacing the AND gate
with a NAND gate provides active-LOW decoding.

Fig 1-31 Decoding of state 6

Example:1-9:Implement the decoding of binary state 2 and binary state 7 of a 3-bit
synchronous counter. Show the entire counter timing diagram and the output waveforms of
the decoding gates. Binary 2 = ‾Q2‾Q1‾Q0 and binary 7 = Q2Q1Q0.

Fig1-32 A 3-bit counter with active HIGH decoding of count 2 and count 7.
18
Related Problem Show the logic for decoding state 5 in the 3-bit counter.

1-3 Counter application

A Digital Clock :fig1-33 is a simplified logic diagram of a digital clock that displays seconds,
minutes, and hours. First, a 60 Hz sinusoidal ac voltage is converted to a 60 Hz pulse
waveform and divided own to a 1Hz pulse waveform by a divide-by-60 counter formed by a
divide-by-10 counter allowed by a divide-by-6 counter. Both the seconds and minutes counts
are also produced by divide-by-60 counters. These counters count from 0 to 59 and then
recycle to 0 . Notice that the divide-by-6 is formed with a decade counter with a truncated
sequence achieved by using the decoder count 6 to asynchronously clear the counter. The
terminal count, 59, is also decoded to enable the next counter in the chain.

Fig 1-33 Simplified logic diagram for a 12-hour digital clock

The hours counter is implemented with a decade counter and a flip-flop as shown in fig1-34.
Consider that initially both the decade counter and the flip-flop are RESET, and the decode-
12 gate and decode-9 gate outputs are HIGH. The decade counter advances through all of its
states from zero to nine, and on the clock pulse that recycles it from nine back to zero, the
flip-flop goes to the SET state (J=1, K=0). This illuminates a 1 on the tens-of-hours display.
The total count is now ten (the decade counter is in the zero state and the flip-flop is SET).
Next, the total count advances to eleven and then to twelve. In state 12 the Q2 output of the
decade counter is HIGH, the flip-flop is still SET, and thus the decode-12 gate output is
LOW. This activates the ‾‾PE input of the decade counter. On the next clock pulse, the decade
Counter is preset to state I by the data inputs, and the flip-flop is RESET (J=0, K=1).
As you can see, this logic always causes the counter to recycle from twelve back to one rather
than back to zero.
19
Fig 1-34 Logic diagram of typical divide-by-60 counter using synchronous decade counters.
Note that the outputs are in binary order (the right-most bit is the LSB).

Fig1-35 Logic diagram for hours counter and decoders. Note that on the counter inputs and
outputs, the right-most bit is the LSB.

20