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Assignment 7: Due November 12, 1996

This document describes an assignment to design a DRAM controller circuit to interface between a CPU and bank of 1Mbit DRAM chips. The controller must handle read and refresh cycles over a 4 clock cycle bus. It is provided the CPU clock, address, address valid and hold acknowledge signals. It must output the hold request, row access strobe, column access strobe and 10-bit multiplexed DRAM address signals according to the timing diagram. The assignment is to write synthesizable VHDL code for the controller, test it with a test bench, synthesize it and submit the files.

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Dr-Raghad Al-Faham
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59 views1 page

Assignment 7: Due November 12, 1996

This document describes an assignment to design a DRAM controller circuit to interface between a CPU and bank of 1Mbit DRAM chips. The controller must handle read and refresh cycles over a 4 clock cycle bus. It is provided the CPU clock, address, address valid and hold acknowledge signals. It must output the hold request, row access strobe, column access strobe and 10-bit multiplexed DRAM address signals according to the timing diagram. The assignment is to write synthesizable VHDL code for the controller, test it with a test bench, synthesize it and submit the files.

Uploaded by

Dr-Raghad Al-Faham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ELEC 464 : M ICROCOMPUTER S YSTEM D ESIGN

1996/97 W INTER S ESSION T ERM 1

Assignment 7
Due November 12, 1996

Design a DRAM controller to interface a bank of 1 CAS and RAS: CAS* and RAS* strobes. Their
Mbit DRAMs to a simple CPU. Your controller need behaviour must agree with the timing diagram
only deal with read and refresh cycles. shown below. Note that these signals are active-
The controller’s inputs are: low and that the refresh cycle uses CAS*-
before-RAS* refresh.
CLK: A clock input. The clock has a 50% duty
cycle and each bus cycle starts on the falling The timing diagram below shows the desired be-
edge of the clock. There are 4 clock cycles per haviour of the DRAM controller signals for RAM
bus cycle. Each read or refresh cycle should read and refresh cycles.
take 4 clock cycles. Read Cycle

clk
A: A 20-bit address bus from the CPU. This ad-
avalid
dress is valid only during the first clock cycle of
a bus cycle so your circuit must latch it. a

rama row col


AVALID: An ‘address valid’ signal from the
CPU. This signal is only asserted during the first ras
clock cycle of a bus cycle. cas
HOLDA: A hold acknowledge signal from the
CPU. This signal is asserted when the CPU has Refresh Cycle

relinquished control of the bus and will not at- clk

tempt to access the DRAM. This signal is as- rfrsh


serted at the start of a bus cycle and stays active
hold
until the start of the bus cycle after HOLD is
holda
released.
ras
RFRSH: A refresh request input from a exter-
cas
nal timer circuit. This signal is synchronized so
rama
that it will go active at the start of the last clock
cycle of a bus cycle if a memory refresh cycle
Write a synthesizeable VHDL description of a cir-
is required. It will stay active for two clock pe-
cuit that implements this DRAM controller. Test
riods. your design with the supplied test bench. Synthe-
The controller’s outputs are: size your code using the ’class’ target library. Sub-
mit your VHDL code, the testbench output and the
HOLD: A hold request to the CPU. It must be
schematic electronically using the keys 7vhd, 7ps
asserted at least half a clock period before the
and 7log respectively.
end of a bus cycle for the CPU to release the
Use the following VHDL entity:
bus during the next clock cycle.
RAMA: The multiplexed 10-bit address sup- entity dramc is
plied to the DRAMs. The DRAMs have zero port ( clk, rfrsh, avalid, holda : in bit ;
a : in bit_vector (19 downto 0) ;
ns setup times and a hold times of less than hold, ras, cas : out bit ;
one clock period for both row and column ad- rama : out bit_vector (9 downto 0) ) ;
end ;
dresses.

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