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com

d) The collector current is always zero and

the base current is always non zero
EC8351
Answer: b
ELECTRONIC Explanation: Both collector and emitter
current are zero in cut-off region.

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CIRCUITS I 3. Which of the following is true for a typical
active region of an npn transistor?

ECE - 3rd Semester -

a) The potential difference between the
emitter and the collector is less than 0.5 V
b) The potential difference between the
Reg. 2017 emitter and the collector is less than 0.4 V

.c
c) The potential difference between the
emitter and the collector is less than 0.3 V
d) The potential difference between the

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emitter and the collector is less than 0.2 V
UNIT I BIASING OF Answer: c
DISCRETE BJT, JFET pa Explanation: Most commonly used
transistors have Vce less than 0.4 V for the
AND MOSFET active region.

TOPIC 1.1 BIPLOLAR 4. Which of the following is true for the

active region of an npn transistor?
JUNCTION TRANSISTOR (BJT)
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a) The collector current is directly
proportional to the base current
1. Which of the following condition is true b) The potential difference between the
for cut-off mode? emitter and the collector is less than 0.4 V
a) The collector current Is zero c) All of the mentioned
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b) The collector current is proportional to the d) None of the mentioned

base current
c) The base current is non zero Answer: c
d) All of the mentioned Explanation: The base current and the
collector current are directly proportional to
Answer: a each other and the potential difference
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Explanation: The base current as well as the between the collector and the base is always
collector current are zero in cut-off mode. less than 0.4 V.

2. Which of the following is true for the cut-

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5. Which of the following is true for the

off region in an npn transistor? saturation region of BJT transistor?
a) Potential difference between the emitter a) The collector current is inversely
and the base is smaller than 0.5V proportional to the base current
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b) Potential difference between the emitter b) The collector current is proportional to the
and the base is smaller than 0.4V square root of the collector current
c) The collector current increases with the c) The natural logarithm of the collector
increase in the base current current is directly proportional to the base

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current than 0.3V, for an npn transistor it is greater

d) None of the mentioned than 0.3V.

Answer: b 9. Which of the following is true for a pnp

Explanation: The collector current is directly transistor in active region?
proportional to the base current in the a) CB junction is reversed bias and the EB

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saturation region of the BJT. junction is forward bias
b) CB junction is forward bias and the EB
6. Which of the following is true for a npn junction is forward bias
transistor in the saturation region? c) CB junction is forward bias and the EB
a) The potential difference between the junction is reverse bias
collector and the base is approximately 0.2V d) CB junction is reversed bias and the EB
b) The potential difference between the junction is reverse bias

.c
collector and the base is approximately 0.3V
c) The potential difference between the Answer: a
collector and the base is approximately 0.4V Explanation: Whether the transistor in npn or
d) The potential difference between the pnp, for it be in active region the EB junction

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collector and the base is approximately 0.5V must be reversed bias the CB junction must
be forward bias.
Answer: d
Explanation: The commonly used npn 10. Which of the following is true for a pnp
pa
transistors have a potential difference of
around 0.5V between he collector and the
transistor in saturation region?
a) CB junction is reversed bias and the EB
base. junction is forward bias
b) CB junction is forward bias and the EB
7. The potential difference between the base junction is forward bias
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and the collector Vcb in a pnp transistor in c) CB junction is forward bias and the EB
saturation region is ________ junction is reverse bias
a) -0.2 V d) CB junction is reversed bias and the EB
b) -0.5V junction is reverse bias
c) 0.2 V
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d) 0.5 V Answer: b
Explanation: Whether the transistor in npn or
Answer: b pnp, for it be in saturation region the EB
Explanation: The value of Vcb is -0.5V for a junction must be forward bias the CB
pnp transistor and 0.5V for an npn transistor. junction must be forward bias.
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8. For a pnp transistor in the active region the

value of Vce (potential difference between TOPIC 1.2 NEED FOR BIASING -
the collector and the base) is DC LOAD LINE AND BIAS
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a) Less than 0.3V POINT

b) Less than 3V
c) Greater than 0.3V
1. Which of the following depicts the DC
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d) Greater than 3V
load line?
Answer: a
Explanation: For a pnp transistor Vce is less

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2. For the circuit shown, find the quiescent

point.

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a)

.c
a) (10V, 4mA)
b) (4V, 10mA)
c) (10V, 3mA)

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d) (3mA, 10V)

Answer: c
b) pa Explanation: We know,
IE=VEE/RE=30/10kΩ=3mA
IC=α IE =IE =3mA
VCB=VCC-ICRL=25-15=10V. So, quiescent
point is (10V, 3mA).
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3. Which of the following depicts the load
line for the circuit shown below?
c)
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d)
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Answer: a
Explanation: In transistor circuit analysis,
sometimes it is required to know the collector
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currents for various collector emitter voltages.

The one way is to draw its load line. We
require the cut off and saturation points.

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VCB=VCC-ICRL=20-15=5V. So, quiescent

point is (5V, 3mA).

4. For the circuit shown, find the quiescent

point.

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a)

.c
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a) (6V, 1mA)
b) (4V, 10mA)
b)
pa c) (10V, 3mA)
d) (3mA, 10V)

Answer: c
Explanation: We know, VCE=12V
jin
(IC)SAT =VCC/RL=12/6K=2mA.
IB=10V/0.5M=20µA. IC= βIB=1mA. I
VCE=VCC-ICRL=12-1*6=6V. So, quiescent
point is (6V, 1mA).
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c)
5. Which of the following depicts the load
line for the given circuit?
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d)

Answer: d
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Explanation: We know,
IE=VEE/RE=15/5kΩ=3mA
IC=α IE =IE =3mA

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VCE=VCC-ICRL=10-1*2=8V. So, quiescent

point is (8V, 1mA).

6. The DC equivalent circuit for an NPN

common base circuit is.

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a)

.c
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b)
pa
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c)
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d)
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Answer: d
Explanation: We know, VCE=6V
(IC)SAT =VCC/RL=10/2K=5mA.
IB=10V/0.5M=20µA. IC= βIB=1mA. I

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7. The DC equivalent circuit for an NPN

common emitter circuit is.

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.c
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pa
jin
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Answer: a
Explanation: In the common base circuit, the
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emitter diode acts like a forward biased ideal

diode, while collector diode acts as a current
source due to transistor action. Thus an ideal
transistor may be regarded as a rectifier diode
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in the emitter and a current source at

collector.

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emitter configuration?

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.c
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pa
jin
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Answer: b
Explanation: In the common emitter circuit,
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the ideal transistor may be regarded as a

rectifier diode in the base circuit and a current
source in the collector circuit. In the current
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source, the direction of arrow points in

direction of conventional current.

8. What is the other representation of the Answer: d

given PNP transistor connected in common Explanation: The emitter junction is forward

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biased with the help of battery VEE by which, VCB=VCC-ICRL=20-10=10V. So, quiescent
negative of the battery is connected to the point is (10V, 2mA).
emitter while positive is connected to base.
RE is the emitter resistance. The collector
TOPIC 1.3 DC ANALYSIS OF
junction is reversed biased.
TRANSISTOR CIRCUITS

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9. What is the DC characteristic used to prove
that the transistor is indeed biased in 1. The feature of an approximate model of a
saturation mode? transistor is
a) IC = βIB a) it helps in quicker analysis
b) IC > βIB b) it provides individual analysis for different
configurations
c) IC >> βIB

.c
c) it helps in dc analysis
d) IC < βIB d) ac analysis is not possible

Answer: d Answer: a

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Explanation: When in a transistor is driven Explanation: The small signal model helps in
into saturation, we use VCE(SAT) as another quicker ac analysis of a transistor. The
linear parameter. In, addition when a approximate model is applicable for all the
transistor is biased in saturation mode, we
pa configurations. The dc analysis is not
have IC < βIB. This characteristic used to obtained by using a small signal model of
prove that the transistor is indeed biased in transistor.
saturation mode.
2 A transistor has hfe=100, hie=2kΩ,
10. For the circuit shown, find the quiescent hoe=0.005mmhos, hre=0. Find the output
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point. impedance if the lad resistance is 5kΩ.
a) 5kΩ
b) 4kΩ
c) 20kΩ
d) 15kΩ
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Answer: b
Explanation: RO=I/hoe=1/0.005m
=20kΩ.ROI= RO || RLI=20||5
=4kΩ.
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3. A CE amplifier when bypassed with a

a) (10V, 4mA) capacitor at the emitter resistance has
b) (4V, 10mA)
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a) increased input resistance and increased

c) (10V, 3mA) voltage gain
d) (3mA, 10V) b) increased input resistance and decreased
voltage gain
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Answer: c c) decreased input resistance and increased

Explanation: We know, voltage gain
IE=VEE/RE=10/5kΩ=2mA d) decreased input resistance and decreased
IC=α IE =IE =2mA voltage gain

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Answer: c
Explanation: When a transistor is bypassed
with a capacitor, it short circuits in the small
signal analysis of transistor and the resistor
too shorts. The input resistance becomes
RI=hie. The value of the input resistance is

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decreased and the gain now will be
increasing.

4. A transistor has hie =2kΩ, hoe=25µmhos a) 100kΩ

b) 50kΩ
and hfe=60 with an unbypassed emitter c) 40kΩ
resistor Re=1kΩ. What will be the input d) 60kΩ

.c
resistance and output resistance?
a) 90kΩ and 50kΩ respectively Answer: b
b) 33kΩ and 45kΩ respectively Explanation: RAB=RO||100Ω
c) 6kΩ and 40kΩ respectively
= (RSI+hie/1+hfe)||100

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d) 63kΩ and 40kΩ respectively
=9+1/100||100=100||100=50Ω.
Answer: d
Explanation: As the emitter is unbypassed,
pa 7. Which of the following acts as a buffer?
the input resistance Ri=hie+(1+hfe)Re a) CC amplifier
b) CE amplifier
=2+61=63kΩ. The output resistance
c) CB amplifier
RO=1/hoe=1/25MΩ=40kΩ.
d) cascaded amplifier
5. A transistor has hie =1KΩ and hfe=60 with Answer: a
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an bypassed emitter resistor Re=1kΩ. What Explanation: The voltage gain of a common
will be the input resistance and output collector amplifier is unity. It is then used as a
resistance? buffer. The CC amplifier is also called as an
a) 90kΩ and 50kΩ respectively emitter follower. Though there is no
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b) 33kΩ and 45kΩ respectively amplification done, the output will be

c) 6kΩ and 40kΩ respectively stabilised.
d) 63kΩ and 40kΩ respectively
8. Which of the following is true?
Answer: d a) CC amplifier has a large current gain
Explanation: As the emitter is bypassed, the b) CE amplifier has a large current gain
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input resistance Ri=hie c) CB amplifier has low voltage gain

=1kΩ. The output resistance RO=1/hoe but d) CC amplifier has low current gain
the value is not given. Answer: b
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So, hoe=0 and RO=1/0=∞. Explanation: The CE amplifier has high

current and voltage gains. The CC amplifier
6. In the given circuit, find the equivalent has unity voltage gain which cannot be
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resistance between A and B nodes. regarded as high. The common base amplifier
has a unity current gain and high voltage
gain.

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9. In an NPN silicon transistor, α=0.995, IC = βIB and IE = IC + IB

IE=10mA and leakage current ICBO=0.5µA. Hence, IE = (β + 1) IB.
Determine ICEO.
a) 10µA 2. For best operation of a BJT, which region
b) 100µA must the operating point be set at?
c) 90µA a) Active region

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d) 500µA b) Cutoff region
c) Saturation region
Answer: b d) Reverse active region
Explanation: IC=α IE +ICBO
=0.995*10mA+0.5µA=9.9505mA. Answer: a
IB=IE-IC=10-9.9505=0.0495mA. β=α/(1- Explanation: Operating point for a BJT must
always be set in the active region to ensure

.c
α)=0.995/(1-0.995)=199
proper functioning. Setting up of Q-point in
ICEO=9.9505-199*0.0495=0.1mA==100µA.
any other region may lead to reduced
functionality.
10. In CB configuration, the value of

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α=0.98A. A voltage drop of 4.9V is obtained 3. From the given circuit, using a silicon
across the resistor of 5KΩ when connected in transistor, what is the value of IBQ?
collector circuit. Find the base current.
pa
a) 0.01mA
b) 0.07mA
c) 0.02mA
d) 0.05mA

Answer: c
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Explanation: Here, IC=4.9/5K=0.98mA
α = IC/IE .So,
IE=IC/α=0.98/0.98=1mA.
IB=IE-IC=1-0.98=0.02mA.
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a) 47.08 mA
b) 47.08 uA
TOPIC 1.4 VARIOUS BIASING c) 50 uA
METHODS OF BJT d) 0 mA

Answer: b
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1. Which of the following is the correct Explanation: Consider the BJT to be in

relationship between base and emitter current saturation. Then IC=12-0.2/2.2k=5.36 mA
of a BJT? And IB=12-0.8/240k=0.047 mA
a) IB = β IE
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IBMIN=ICSAT/β=5.09/50=0.1072mA which is
b) IB = IE
greater than above IB.
c) IB = (β + 1) IE
Hence transistor is in the active region.
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d) IE = (β + 1) IB Thus IC=βIB.
VBE=0.7V
Answer: d
Explanation: For a BJT, the collector current IB=12-0.7/240=47.08μA

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4. From the given circuit, using a silicon BJT, b) -6.13 V

what is the value of VCEQ? c) 7 V
d) -7 V

Answer: b
Explanation: Consider the BJT to be in

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saturation. Then IC=12-0.2/2.2k=5.36 mA
And IB=12-0.8/240k=0.047 mA
IBMIN=ICSAT/β=5.09/50=0.1072mA which is
greater than above IB.
Hence transistor is in the active region.
Thus IC=βIB.

.c
a) 7 V VBE=0.7V
b) 0.7 V IB=12-0.7/240=47.08μA
c) 6.83 V
IC=50×47.08=2.354 mA
d) 7.17 V

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VCE=VCC-ICRC=12-2.354*2.2=12-
Answer: c 5.178=6.83V
Explanation: Consider the BJT to be in
pa Hence VBC = 0.7-6.83 = -6.13V.
saturation. Then IC=12-0.2/2.2k=5.36 mA
And IB=12-0.8/240k=0.047 mA 6. From the given circuit, using silicon BJT,
IBMIN=ICSAT/β=5.09/50=0.1072mA which is what is the value of the saturation collector
greater than above IB. current?
Hence transistor is in the active region.
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Thus IC=βIB.
VBE=0.7V
IB=12-0.7/240=47.08μA
IC=50×47.08=2.354 mA
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VCE=VCC-ICRC=12-2.354*2.2=12-
5.178=6.83V.

5. From the given circuit, using a silicon BJT,

what is the value of VBC? a) 5 mA
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b) 5.36 mA
c) 5.45 mA
d) 10.9 mA
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Answer: b
Explanation: To obtain an approximate
answer, under saturation the BJT is ON and
w

hence acts like a short circuit. However,

ideally a drop exists for the transistor which is
a fixed value. For an exact answer, if the BJT
is a Silicon transistor, then drop VCE = 0.2V
a) 6.13 V and current is 12-0.2/2.2=5.36 mA.

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7. In the given circuit, what is the value of IC

if the BJT is made of Silicon?

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.c
a) 20 V
b) 15.52 V

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a) 2.01 mA c) 14.98 V
b) 2.01 uA d) 13.97 V
c) 10.05 mA
Answer: b
d) 10.05 uA

Answer: a
pa Explanation: Consider the BJT to be in
saturation. Then IC=20-0.2/2k=9.9 mA
Explanation: Consider the BJT to be in And IB=20-0.8/430k=0.044 mA
saturation. Then IC=20-0.2/2k=9.9 mA IBMIN=ICSAT/β=5.09/50=0.198mA which is
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And IB=20-0.8/430k=0.044 mA greater than above IB.
IBMIN=ICSAT/β=5.09/50=0.198mA which is Hence transistor is in the active region.
greater than above IB. Thus IC=βIB.
Hence transistor is in the active region. VBE=0.7V
Thus IC=βIB.
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IB=20-0.7/430=44.88μA
VBE=0.7V IC=50×44.88=2.24 mA
IB=20-0.7/430=44.88μA VCE=20-2.24*2=15.52V.
IC=50×44.88=2.24 mA.
9. In the given circuit, what is the value of VE
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8. In the given circuit, using a silicon BJT, when using a silicon BJT?
what is the value of VCE?
w
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.c
a) 2.01 V a) 10 mA
b) 0.28 V b) 8.77 mA

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c) 0 V c) 6.67 mA
d) 2.28 V d) 5 mA

Answer: d Answer: c

saturation. Then IC=20-0.2/2k=9.9 mA

pa
Explanation: Consider the BJT to be in Explanation: To obtain an approximate
answer, under saturation the BJT is ON and
And IB=20-0.8/430k=0.044 mA hence acts like a short circuit. However,
ideally a drop exists for the transistor which is
IBMIN=ICSAT/β=5.09/50=0.198mA which is
a fixed value. For an exact answer, if the BJT
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greater than above IB. is a Silicon transistor, then drop VCE = 0.2V
Hence transistor is in the active region. and current is 20-0.2/2.2=9.9 mA.
Thus IC=βIB.
VBE=0.7V
TOPIC 1.5 BIAS CIRCUIT
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IB=20-0.7/430=44.88μA
DESIGN - THERMAL
IC=50×44.88=2.24 mA
STABILITY - STABILITY
VCE=20-2.24*2=15.52V
FACTORS
VE=IERE=(1+β)IBRE=51*44.88*1=2.28V.
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10. In the given circuit using a silicon BJT, 1. What is Stability factor?
what is the value of saturation collector a) Ratio of change in collector current to
current? change in a current amplification factor
b) Ratio of change in collector current to
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change in base current

c) Current amplification factor
d) Ratio of base current to collector current
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Answer: a
Explanation: Stability factor is defined as the
rate at which collector current changes when
Base to emitter voltage changes, keeping base

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current constant. It can also be defined as the change in beta does not affect much on the
ratio of change in collector current to change collector current. When S is high, even if IB
in base current when temperature changes changes by a small value, the IC current will
occur. drastically vary. Hence stability factor must
possess lesser value for the proper working of
2. The base current for a BJT remains
a transistor.

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constant at 5mA, the collector current
changes from 0.2mA to 0.3 mA and beta was 5. What is the value of Stability factor for an
changed from 100 to 110, then calculate the ideal transistor?
value of S.
a) 100
a) 0.01m
b) 1000
b) 1m
c) infinite
c) 100m

.c
d) 0
d) 25m
Answer: 0
Answer: a
Explanation: For a transistor, the ideal value
Explanation: Since the current in the above

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of S is 0 which interprets that for a change in
case, remains constant, therefore stability
beta, there should not be changing. In Ideal
factor is 0.01 as it is defined as the ratio of
transistor, the collector current will vary only
change in collector current to change in beta.
pa if either base or emitter current varies or
S=change in collector current/change in
hence for an ideal transistor the value of S is
beta=0.1mA/10=0.01m.
zero.
3. For a n-p-n transistor, the collector current
6. For a fixed bias circuit having Ic = 0.3mA
changed from 0.2mA to 0.22mA resulting a
change of base emitter voltage from 0.8v to and In=0.0003mA, S is______________
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0.8005V. What is the value of Stability a) 100
factor? b) 0
a) 0 c) 11
b) 0.25 d) 111
c) 0.04
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Answer: c
d) 0.333
Explanation: For fixed bias S=1+beta
Answer: c Beta=IC/IB=10
Explanation: Change in Vbe = 0.0005V S=1+10=11.
Change in collector current = 0.02mA
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S = 0.02m/0.0005 = 0.04. 7. For a fixed bias circuit having RC=2Kohm

and VCC=60V, IB=0.25mA and S=101, find
4. There are two transistors A and B having Vce.
‘S’ as 25 and 250 respectively, on comparing
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a) 12V
the value of S, we can say B is more stable b) 10V
than A. c) 5V
a) True d) 2.5V
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b) False
Answer: b
Answer: b Explanation: S = 1 + beta,
Explanation: More the value of S, lesser the => 100 = IC/IB => Ic = 25mA
stability, since A has lesser S value the

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Vce = VCC – Ic RC 1. The compensation techniques are used

Vce = 10V. to_________
a) increase stability
8. For an ideal transistor having a fixed bias b) increase the voltage gain
configuration, what will be the value of Beta? c) improve negative feedback
a) 0 d) decrease voltage gain

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b) 2
c) -1 Answer: b
d) 1 Explanation: Usually, the negative feedback
is used to produce a stable operating point.
Answer: c But it reduces the voltage gain of the circuit.
Explanation: S = 1 + Beta This sometimes is intolerable and should be
S=0 avoided in some applications. So, the biasing

.c
Beta = -1. techniques are used.

9. The temperature changes do not affect the 2. Compensation techniques refer to the use
of_________

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Stability.
a) True a) diodes
b) False b) capacitors
pa c) resistors
Answer: b d) transformers
Explanation: The temperature changes the
value of beta which in turn changes the Answer: a
stability of the transition. The temperature Explanation: Compensation techniques refer
changes affect the mobility of the charge to the use of temperature sensitive devices
such as thermistors, diodes, transistors,
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carries which results in a change of the
current parameters affecting stability. sensistors etc to compensate variation in
currents. Sometimes for excellent bias and
10. Comparing fixed and collector to base thermal stabilization, both stabilization and
bias which of the following statement is true? compensation techniques are used.
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a) Fixed bias is more stable

b) Collector to base bias is more stable 3. In a silicon transistor, which of the
c) Both are the same in terms of stability following change significantly to the change
d) Depends on the design in IC?
a) VCE
Answer: b b) IB
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Explanation: For fixed bias circuit, S =

c) VBE
1+beta, more the beta, lesser the stability
For collector to base bias S = b) IE
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(1+beta)/(1+beta(RC/RC+RB))
Hence collector to base bias is more stable. Answer: c
Explanation: For germanium transistor,
changes in ICO with temperature contribute
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TOPIC 1.6 BIAS more serious problem than for silicon

COMPENSATION TECHNIQUES transistor. On the other hand, in a silicon
USING DIODE, THERMISTOR transistor, the changes of VBE with
AND SENSISTOR

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temperature possesses significantly to the means, its resistance decreases exponentially

changes in IC. with increasing T. The thermistor RT is used
to minimize the increase in collector current.
4. What is the compensation element used for
variation in VBE and ICO? 7. Which of the following has a negative
a) diodes temperature coefficient of resistance?

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b) capacitors a) capacitor
c) resistors b) diode
d) transformers c) thermistor
d) sensistor
Answer: a
Answer: d
Explanation: A diode is used as the
Explanation: The sensistor has a positive
compensation element used variation in VBE

.c
temperature coefficient of resistance. It is a
and ICO. The diode used is of the same temperature sensitive resistor. It is a heavily
material and type as that of transistor. Hence, doped semiconductor. When voltage is
the voltage across the diode has same decreased, the net forward emitter voltage

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temperature coefficient as VBE of the decreases. As a result the collector current
transistor. decreases.

8. Increase in collector emitter voltage from

pa
5. The expression for IC in the compensation
for instability due to ICO variation_________ 5V to 8V causes increase in collector current
from 5mA to 5.3mA. Determine the dynamic
a) βI+βIO+βICO
output resistance.
b) βI+βIO a) 20kΩ
c) βIO+βICO b) 10kΩ
jin
d) βI+βICO c) 50kΩ
d) 60kΩ
Answer: a
Answer: b
Explanation: In this method, diode is used
Explanation: ro=∆VCE/∆IC
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for the compensation in variation of ICO. The

=3/0.3m=10kΩ.
diode used is of the same material and type as
that of transistor. Hence, the reverse
9. The output resistance of CB transistor is
saturation current IO of the diode will
given by _________
increase with temperature at the same rate as a) ∆VCB/∆IC
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the transistor collector saturation current ICO.

b) ∆VBE/∆IB
6. Which of the following has a negative c) ∆VBE/∆IC
temperature coefficient of resistance? d) ∆VEB/∆IE
w

a) sensistor
b) diode Answer: a
c) thermistor Explanation: The ratio of change in collector
w

d) capacitor base voltage (∆VCB) to resulting change in

collector current (∆IC) at constant emitter
Answer: c
current (IE) is defined as output resistance.
Explanation: The thermistor has a negative
temperature coefficient of resistance. It This is denoted by ro.

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10. The negative sign in the formula of to VGS, and small changes in VGS cause
amplification factor indicates_________ proportionate changes in IDS, and the device
a) that IE flows into transistor while IC flows can act as an amplifier.
out it
b) that IC flows into transistor while IE flows 2. In the given situation for n-channel JFET,
out it we get drain-to-source current is 5mA. What

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c) that IB flows into transistor while IC flows is the current when VGS = – 6V?
out it
d) that IC flows into transistor while IB flows
out it

Answer: a

.c
Explanation: When no signal is applied, the
ratio of collector current to emitter current is
called dc alpha, αdc of a transistor. αdc=-

ul
IC/IE. It is the measure of the quality of a
transistor. Higher is the value of α, better is
the transistor in the sense that collector
current approaches the emitter current.
pa a) 5 mA
b) 0.5A
c) 0.125 A
TOPIC 1.7 BIASING BJT d) 0.5A
SWITCHING CIRCUITSJFET -
DC LOAD LINE AND BIAS Answer: c
Explanation: IDS = IDSS(1-VGS/VP)2
jin
POINT, VARIOUS BIASING
METHODS OF JFET - JFET When VGS = 0, IDSS = IDS = 5mA
BIAS CIRCUIT DESIGN When VGS = -6V, IDS = 5mA(1 + 4)2
IDS = 5 x 25 = 125 mA.
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1. Which of the following statements are

true? 3. Consider the following circuit. Given that
P: JFET is biased to operate it in active region VDD = 15V, VP = 2V, and IDS = 3mA, to bias
Q: MOSFET is biased to operate it in the circuit properly, select the proper
saturation region statement.
a) Both P and Q are correct
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b) P is correct and Q is incorrect

c) P is incorrect and Q is correct
d) Both P and Q are incorrect
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Answer: c
Explanation: While transistors are biased to
work in the active region, to act as amplifiers,
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FET devices are instead biased in the

saturation region to work as an amplifier,
whether it be a JFET or a MOSFET. In
saturation, current IDS changes with respect

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om
.c
a) RD < 6kΩ

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b) RD > 6kΩ a) -30V
c) RD > 4kΩ b) 30V
c) 33V
d) RD < 4kΩ

Answer: a
pa d) Any value of voltage less than 12 V

Answer: c
Explanation: In given circuit, VGS = -5V Explanation: VDS = VDD – IDS(10k + 5k)
VDS = VDD – IDSRD 3 = VDD – 2(15)
jin
To bias properly VDS > |VP| – |VGS| 3 = VDD – 30
VDS > -3 VDD = 33 V.
15 – 3mA*RD > -3
-3mA*RD > -18 5. To bias a e-MOSFET ___________
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RD < 6kΩ. a) we can use either gate bias or a voltage

divider bias circuit
4. Consider the circuit shown. VDS=3 V. If b) we can use either gate bias or a self bias
circuit
IDS=2mA, find VDD to bias circuit. c) we can use either self bias or a voltage
divider bias circuit
w

d) we can use any type of bias circuit

Answer: a
Explanation: To bias an e-MOSFET, we
w

cannot use a self bias circuit because the gate

to source voltage for such a circuit is zero.
Thus, no channel is formed and without the
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channel, the MOSFET doesn’t work properly.

If self bias circuit is used, then D-MOSFET
can be operated in depletion mode.

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6. Consider the following circuit. Process

transconductance parameter = 0.50 mA/V2,
W/L=1, Threshold voltage = 3V, VDD = 20V.
Find the operating point of circuit.

om
.c
a) -3.83V, 0.766mA
b) -2.345V, 0.469mA

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c) 3.83V, 0.469mA
d) 2.3V, 0.7mA
a) 20V, 25mA pa Answer: b
b) 13V, 22mA Explanation: When VGS = VP then IDSS =
c) 12.72V, 23.61mA
d) 20V, 23.61mA IDS = 10mA
Also, in above circuit, VGS = -IDSRS = –
Answer: c IDSx5k
Explanation: IDS = [k’W/L(VGS – VT)2]/2
jin
Thus, IDS = IDSS(1-VGS/VP)2
VGS = 20 x 35 / 55 = 12.72 V Solving we get, IDS = 0.766mA, 0.469mA
IDS = 0.25 (9.72)2 Thus we get VGS = -3.83V, -2.345V
IDS = 23.61 mA. However, VGS should lie between 0 and VP.
.re

7. Given VDD = 25V, VP = -3V. When VGS = 8. Consider the following circuit. IDSS =
-3V, IDS = 10mA. Find the operating point of 2mA, VDD = 30V. Find R, given that VP = –
the circuit. 2V.
w
w
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IDS is stable due to the presence of source

resistance RS in the circuit. The source
resistance helps provide negative feedback to
keep current stable. Capacitor CS is a bypass
capacitor to prevent decrease in voltage gain.

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10. For a MOSFET, the pinch-off voltage is
-3V. Gate to source voltage is 20V. W/L ratio
is 5. Process transconductance parameter is
40μA/V2. Find drain to source current in
saturation.
a) 0.10 mA

.c
b) 0.05mA
c) – 0.05mA
d) – 50A

ul
a) 10kΩ Answer: c
b) 4kΩ Explanation: ISD = k’W(VSG – |VT|)2/2L
c) 2kΩ pa ISD = 20*5*(-20-3)2 = 52900μA = 0.05mA.
d) 5kΩ

Answer: b TOPIC 1.8 MOSFET BIASING

Explanation: IDSS = 2mA
IDS = (VDD – 15)/50k = 0.3mA 1. Which of the following statements are
jin
VGS = VP [1 – √
IDS
] true?
DSS
P: JFET is biased to operate it in active region
VGS = -2 x (1 – √.15) = – 1.22V Q: MOSFET is biased to operate it in
Thus VGS + IDS x (R) = 0 saturation region
a) Both P and Q are correct
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R = 1.22/0.3mA = 4kΩ.
b) P is correct and Q is incorrect
9. Which of the following statements are c) P is incorrect and Q is correct
true? d) Both P and Q are incorrect
A: In a self bias circuit, the current IDS is not
stable. Answer: c
Explanation: While transistors are biased to
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B: Source capacitance, CS, parallel to RS,

reduces stability. work in the active region, to act as amplifiers,
a) Both statements are correct and B is the FET devices are instead biased in the
correct reasoning saturation region to work as an amplifier,
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b) Both statements are correct but B is not the whether it be a JFET or a MOSFET. In
correct reason for it saturation, current IDS changes with respect
c) Statement A is correct while statement B is to VGS, and small changes in VGS cause
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wrong proportionate changes in IDS, and the device

d) Both statements are incorrect can act as an amplifier.
Answer: d 2. In the given situation for n-channel JFET,
Explanation: In a self bias circuit, the current we get drain-to-source current is 5mA. What

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is the current when VGS = – 6V? c) RD > 4kΩ

d) RD < 4kΩ

Answer: a
Explanation: In given circuit, VGS = -5V
VDS = VDD – IDSRD

om
To bias properly VDS > |VP| – |VGS|
VDS > -3
15 – 3mA*RD > -3
-3mA*RD > -18
RD < 6kΩ.

.c
a) 5 mA
b) 0.5A 4. Consider the circuit shown. VDS=3 V. If
c) 0.125 A IDS=2mA, find VDD to bias circuit.
d) 0.5A

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Answer: c
Explanation: IDS = IDSS(1-VGS/VP)2pa
When VGS = 0, IDSS = IDS = 5mA
When VGS = -6V, IDS = 5mA(1 + 4)2
IDS = 5 x 25 = 125 mA.

3. Consider the following circuit. Given that

jin
VDD = 15V, VP = 2V, and IDS = 3mA, to bias
the circuit properly, select the proper
statement.
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a) -30V
b) 30V
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c) 33V
d) Any value of voltage less than 12 V

Answer: c
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Explanation: VDS = VDD – IDS(10k + 5k)

3 = VDD – 2(15)
3 = VDD – 30
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VDD = 33 V.

a) RD < 6kΩ 5. To bias a e-MOSFET ___________

b) RD > 6kΩ a) we can use either gate bias or a voltage
divider bias circuit

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b) we can use either gate bias or a self bias 7. Given VDD = 25V, VP = -3V. When VGS =
circuit -3V, IDS = 10mA. Find the operating point of
c) we can use either self bias or a voltage the circuit.
divider bias circuit
d) we can use any type of bias circuit

om
Answer: a
Explanation: To bias an e-MOSFET, we
cannot use a self bias circuit because the gate
to source voltage for such a circuit is zero.
Thus, no channel is formed and without the
channel, the MOSFET doesn’t work properly.
If self bias circuit is used, then D-MOSFET

.c
can be operated in depletion mode.

6. Consider the following circuit. Process

transconductance parameter = 0.50 mA/V2,

ul
W/L=1, Threshold voltage = 3V, VDD = 20V.
a) -3.83V, 0.766mA
Find the operating point of circuit.
b) -2.345V, 0.469mA
c) 3.83V, 0.469mA
pa d) 2.3V, 0.7mA

Answer: b
Explanation: When VGS = VP then IDSS =
IDS = 10mA
jin
Also, in above circuit, VGS = -IDSRS = –
IDSx5k
Thus, IDS = IDSS(1-VGS/VP)2
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Solving we get, IDS = 0.766mA, 0.469mA

Thus we get VGS = -3.83V, -2.345V
However, VGS should lie between 0 and VP.
a) 20V, 25mA
b) 13V, 22mA 8. Consider the following circuit. IDSS =
w

c) 12.72V, 23.61mA 2mA, VDD = 30V. Find R, given that VP = –

d) 20V, 23.61mA 2V.
Answer: c
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Explanation: IDS = [k’W/L(VGS – VT)2]/2

VGS = 20 x 35 / 55 = 12.72 V
IDS = 0.25 (9.72)2
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IDS = 23.61 mA.

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IDS is stable due to the presence of source

resistance RS in the circuit. The source
resistance helps provide negative feedback to
keep current stable. Capacitor CS is a bypass
capacitor to prevent decrease in voltage gain.

om
10. For a MOSFET, the pinch-off voltage is
-3V. Gate to source voltage is 20V. W/L ratio
is 5. Process transconductance parameter is
40μA/V2. Find drain to source current in
saturation.
a) 0.10 mA

.c
b) 0.05mA
c) – 0.05mA
d) – 50A

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a) 10kΩ Answer: c
b) 4kΩ Explanation: ISD = k’W(VSG – |VT|)2/2L
c) 2kΩ pa ISD = 20*5*(-20-3)2 = 52900μA = 0.05mA.
d) 5kΩ

Answer: b TOPIC 1.9 BIASING FET

Explanation: IDSS = 2mA SWITCHING CIRCUITS.
IDS = (VDD – 15)/50k = 0.3mA
jin
VGS = VP [1 – √
IDS
] 1. Which of the following relation is true
DSS
about gate current?
VGS = -2 x (1 – √.15) = – 1.22V a) IG=ID+IS
Thus VGS + IDS x (R) = 0 b) ID=IG
R = 1.22/0.3mA = 4kΩ.
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c) IS= IG
9. Which of the following statements are d) IG=0
true?
A: In a self bias circuit, the current IDS is not Answer: d
stable. Explanation: The FET physical structure
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B: Source capacitance, CS, parallel to RS, which contains silicon dioxide provides
reduces stability. infinite resistance. Hence no current will flow
a) Both statements are correct and B is the through the gate terminal.
correct reasoning
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b) Both statements are correct but B is not the 2. Which of the following equations gives the
correct reason for it relation between ID and Vgs?
c) Statement A is correct while statement B is a) ID=IDSS (1-Vgs/Vp)2
w

wrong
b) ID=IDSS (1-Vgs/Vp)1
d) Both statements are incorrect
c) ID=IDSS (1-Vgs/Vp)3
Answer: d
d) ID=IDSS (1-Vgs/Vp)4
Explanation: In a self bias circuit, the current

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Answer: a ButVRs+Vgs=0
Explanation: The above equation called as Vgs=-ID Rs.
Shockley’s equation depicts the relation
between ID and Vgs. When Vgs becomes 6. For a self-bias circuit, find drain to source
equal toVp, the current will become zero, voltage if VDD=12V, ID=1mA, Rs=RD=1KΩ?
which clearly satisfies the physical nature of a) 1V

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FET. b) 2V
c) 10V
3. For a fixed bias circuit the drain current d) 5V
was 1mA, what is the value of source
current? Answer: c
a) 0mA Explanation: VDS=VDD-ID (RD+Rs)

.c
b) 1mA =>VDS=12-1mA(1KΩ+1KΩ)
c) 2mA
d) 3mA =>VDS=10V.

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Answer: c 7. Find the gate voltage for voltage divider
Explanation: We know that for an FET same having R1=R2=1KΩ and VDD=5V?
current flows through the gate and source a) 1V
terminal, Hence source current=1mA. pa b) 5V
c) 3V
4. For a fixed bias circuit the drain current d) 2.5V
was 1mA, VDD=12V, determine drain
resistance required if VDS=10V? Answer: d
Explanation: VG = R2×VDD/R1+R2
a) 1KΩ
jin
b) 1.5KΩ =>VG=1×5/2
c) 2KΩ => VG= 2.5V.
d) 4KΩ
8. Find the gate to source voltage for voltage
Answer: c divider having R1=R2=2KΩ and VDD=12V,
.re

Explanation: VDS=VDD-ID RD
ID=1mA and RS=4KΩ?
=>10=12-RD×1mA
a) 3V
=>RD=2/1mA=2 KΩ. b) 2V
c) 0V
5. Which of the following equation brings the d) 1V
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relation between gate to source voltage and

drain current in Self Bias? Answer: b
a) Vgs=VDD Explanation: VG = R2×VDD/R1+R2
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b) Vgs=-ID Rs =>VG=2×12/4
c) Vgs=0 =>VG=6V
d) Vgs=1+ID Rs =>VGS=VG-ID Rs
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=>VGS=2V.
Answer: b
Explanation: VRs=ID Rs 9. What will happen if values of Rs increase?
a) Vgs Increases

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b) Vgs Decreases For small a.c. signal, transistor behaves as

c) Vgs Remains the same linear device. Under such circumstances the
d) Vgs=0 a.c. signal operation of a transistor can be
described in terms of h-parameters.
Answer: b 2. For what type of signals does a transistor
Explanation: Increasing values of Rs result in

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behaves as linear device?
lower quiescent values of ID and more a) small signals only
negative values of Vgs. b) large signals only
c) both large and small signal
10. What is the current flowing through the d) no signal
R1 resistor for voltage divider (R1=R2=1KΩ,
Answer: a

.c
VDD=10V)? Explanation: The small variation in the total
a) 5mA voltage and current due to an application of
b) 3mA signal moves the point up and down just by a
c) 1mA bit and that whole up and down dynamics of

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d) 2mA the operating point from its DC value point
can be approximated to be along a straight
Answer: a line. Whole analysis can be done with same
Explanation: IR1=IR2 =VDD/R1+R2
=>IR1 = 10/2KΩ
=>IR1 = 5mA.
pa assumption of linearity with the limit of
signal being in the same vicinity of the DC
operating point.
That’s how we get all those equations for
linear operation and also its small signal
equivalent model using h-parameters.
jin
UNIT II BJT AMPLIFIERS 3. How many h-parameters are there for a
transistor?
a) two
TOPIC 2.1 SMALL SIGNAL b) three
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HYBRID π EQUIVALENT c) four

d) five
CIRCUIT OF BJT
Answer: c
1. The h-parameters analysis gives correct Explanation: A transistor has four h-
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results for __________ parameters –

a) large signals only H11 = V1/i1 (Input Impedance with output
b) small signals only short circuited)
c) both large and small
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H21 = i2/i1 (Current gain with output short

d) not large nor small signals
circuited)
Answer: b H12 = V1/V2 (Voltage gain with feedback
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Explanation: Every linear circuit is ratio with input terminals open)

associated with h –parameters. When this H22 = i2/V2 (Output Admittance with input
linear circuit is terminated with load rL, we terminals open).
can find input impedance, current gain,
voltage gain, etc in terms of h-parameters.

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4. The dimensions of hie parameters are 7. If temperature changes, h parameters of a

_______ transistor _____
a) MHO a) also change
b) OHM b) does not change
c) Farad c) remains same
d) Ampere d) may or may not change

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Answer: b Answer: a
Explanation: hie = vBE/ib; common emitter Explanation: It is very difficult to get exact
input impedance values of h parameters for a particular
For VCE = 0 i.e. output short circuited transistor. It is because these parameters are
subject to considerable variation unit to unit
Where vBE = Base emitter voltage i.e. input variation, variation due to change in

.c
voltage temperature and variation due to the operating
ib = Base current i.e. input current point.
We know that V/I = R. Its unit is ohm.
8. In CE arrangement, the value of input

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5. The hfe parameter is called _______ in CE impedance is approximately equal to _____
arrangement with output short circuited. a) HIE
a) Voltage Gain pa b) HIB
b) Current gain c) HOE
c) Input impedance d) HRE
d) Output impedance
Answer: a
Answer: b
Explanation: hie = vBE/ib; common emitter
jin
Explanation: hfe in CE arrangement is given
input impedance
as
For VCE = 0 i.e. output short circuited
Hfe = Ic/Ib for VCE = 0 short circuited
Where vBE =Base emitter voltage i.e. input
So, this is current gain as it is then output to
input current ratio. voltage
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ib = Base current i.e. input current.

6. What happens to the h parameters of a
transistor when the operating point of the 9. How many h-parameters of a transistor are
transistor changes? dimensionless?
a) It also changes a) Four
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b) Does not change b) Two

c) May or may not change c) Three
d) Nothing happens d) One
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Answer: a Answer: b
Explanation: It is very difficult to get exact Explanation: (i) H11 = V1/I1; for V2 = 0
values of h parameters for a particular (output short circuited)
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transistor. It is because these parameters are This parameter is input impedance with
subject to considerable variation unit to unit output short.
variation, variation due to change in Its unit is ohm.
temperature and variation due to the operating (ii) H21 = i2/i1; for V2 = 0 (output short
point. circuited)

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This parameter is Current gain ratio with

TOPIC 2.2 EARLY EFFECT -
output short.
It is unit less or dimensionless. ANALYSIS OF CE CC AND CB
(iii) H12 = V1/V2; for i1 = 0 (input open
circuited) 1. Ignoring early effect, if R1 is the total
This is voltage gain feedback ratio with resistance connected to the base and R2 is the

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terminals open. total resistance connected at the collector,
And it is unit less or dimensionless. what could be the approximate input pole of a
(iv) H22 = i2/v2; for i1 = 0 (input open simple C.E. stage?
circuited) a) 1 / [R1 * (Cµ(2+gm*R2) + Cπ)]
This is output admittance with input terminals b) 1 / [R1 * (Cµ(1+2*gm*R2) + Cπ)]
open.
c) 1 / [R1 * (Cµ(1+gm*R2) + Cπ)]

.c
Its unit is ohm-1 or mho.
d) 1 / [R1 * (Cµ(1-gm*R2) + Cπ)]
Thus there are two h-parameters which are
unit less or dimensionless.
Answer: c

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10. The values of h-parameters of a transistor Explanation: The input pole can be
in CE arrangement are ________ approximately calculated by observing the
arrangement. input node. The input node is the node where
a) same as for CB the base of the B.J.T. is connected to the input
b) same as for CC
c) different from that in CB
pa voltage. The product of total resistance and
capacitance connected at that particular node
d) similar to no is R1 * Cin and Cin is Cµ(1+gm*R2) + Cπ- the
inverse of this product gives us the input pole.
Answer: c Thus the correct option is 1 / [R1 *
jin
Explanation: The values of h-parameter in (Cµ(1+gm*R2) + Cπ)].
CE arrangement:
Hie = Vbe/Ib; for Vce = 0 (output short 2. Ignoring early effect, if R2 is the total
circuited) resistance at the collector, what could be the
Hfe = ic/ib; for Vce = 0 (output short circuited)
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approximate output pole of a simple C.E.

Hre = Vbe/Vce; for ib = 0 (input open stage?
circuited) a) 1 / [R2 * (Ccs + Cµ*(1 + 2/gm*R2))]
Hoe = ic/vce; for ib = 0 (input open circuited) b) 1 / [R2 * (Ccs – Cµ*(1 + 1/gm*R2))]
c) 1 / [R2 * (Ccs + Cµ*(1 – 1/gm*R2))]
The values of h-parameter in CB
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d) 1 / [R2 * (Ccs + Cµ*(1 + 1/gm*R2))]

arrangement:
Hib = Vbe/Ie; for Vbc = 0 (output short
Answer: d
circuited)
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Explanation: The output pole can be

Hfb = ic/Ie; for Vbc = 0 (output short approximately calculated by observing the
circuited) output node. For a C.E. stage, the output node
Hrb = Vbe/Vbc; for ie = 0 (input open is the node where the Collector of the B.J.T.
w

circuited) is connected to the output measuring device.

Hob = ic/vbe; for ie = 0 (input open circuited). The product of total resistance and
capacitance connected at that particular node
is R2 * Cout and Cout is (Ccs + Cµ*(1 +

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1/gm*R2). The inverse of this product gives emitter of the B.J.T. is 1/gm. The capacitance
us the output pole. Thus the correct option is connected to the input node is C1 (as
1 / [R2 * (Ccs + Cµ*(1 + 1/gm*R2))]. mentioned). The inverse product of these two
provides us the input pole of the C.B. stage.
3. If the load resistance of a C.E. stage
increases by a factor of 2, what happens to the 6. Ignoring early effect, if R1 is the total

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high frequency response? resistance connected to the collector; what is
a) The 3 db roll off occurs faster the output pole of a simple C.B. stage?
b) The 3 db roll off occurs later a) 1/[R1 * (Ccs + Cµ)]
c) The input pole shifts towards origin
b) 1/[R1* (Ccs + 2*Cµ)]
d) The input pole becomes infinite
c) 1/[R1 * (2*Ccs + Cµ)]
Answer: a d) 1/[R1 * 2*(Ccs + Cµ)]

.c
Explanation: If the load resistance increases
by a factor of 2, the output pole decreases Answer: a
since it’s inversely proportional to the load Explanation: The output pole is calculated,

ul
resistance. Hence the C.E. stage experiences a approximately, by the inverse product of the
faster roll off due to the pole. total resistance and the capacitance connected
at the output node. We find that the total
4. During high frequency applications of a
pa resistance connected to the output node is R1
B.J.T., which of the following three stages do
while the total capacitance is Ccs + Cµ. In
not get affected by Miller’s approximation?
a) C.E. absence of early effect, 1/[R1 * (Ccs + Cµ)]
b) C.B. becomes the output pole.
c) C.C.
7. If early effect is included, and R1 is the
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d) Follower
total resistance connected at the collector.
Answer: b What is the output pole of a simple C.B.
Explanation: During the C.B. stage, the stage?
capacitance between the base and the a) 1/[(R1 || ro) * 2(Ccs + Cµ)]
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collector doesn’t suffer from Miller b) 1/[(R1 || ro) * (Ccs + Cµ)]

approximation since the input is applied to
c) 1/[(R1 || ro) * (2*Ccs + Cµ)]
the emitter of the B.J.T. There are no
capacitors connected between two nodes d) 1/[(R1 || ro) * 2*(Ccs + 2*Cµ)]
having a constant gain. Hence the C.B. stage
doesn’t get affected by miller approximation. Answer: b
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Explanation: The output pole is calculated,

5. Ignoring early effect, if C1 is the total approximately, by the inverse product of the
capacitance tied to the emitter, what is the total resistance and the capacitance connected
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input pole of a simple C.B. stage? at the output node. We find that the total
a) 1/gm * C1 resistance connected to the output node is R1
b) 2/gm * C1 in parallel with ro, due to early effect, while
the total capacitance is C2 ie Ccs + Cµ. Thus,
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c) gm * C1
d) gm * 2C1 the correct option is 1/[(R1 || ro) * (Ccs +
Cµ)].
Answer: a
Explanation: The resistance looking into the

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8. In a simple follower stage, C2 is a parasitic sensed at the collector of the B.J.T. We

capacitance arising due to the depletion observe that the only capacitance connected
region between the collector and the between two nodes- where there is an
substrate. What is the value of C2? amplification unit between the nodes, is Cπ.
a) 0 Hence, the correct option is Cπ.
b) Infinite

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c) Ccs 11. If 1/h12 = 10 for a C.E. stage- what is the
d) 2*Ccs value of the base to collector capacitance,
after Miller multiplication, at the output side?
Answer: a a) 1.1Cµ
Explanation: During the high frequency b) 1.2Cµ
response, the capacitor between the collector c) 2.1Cµ

.c
and the substrate gets shorted to A.C. ground
d) 2.2Cµ
at both of its terminals. Hence, C2=0. The
answer would have been Ccs for any other Answer: a

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stage of B.J.T. Explanation: At the output side of a C.E.
stage, Cµ gets multiplied by a factor of
9. For a cascode stage, with input applied to (1+1/Av) where Av is the voltage gain. 1/h12
the C.B. stage, the input capacitance gets
pa
multiplied by a factor of ____ is nothing but Av. Hence, the value changes
a) 0 to 1.1Cµ.
b) 1
c) 3 12. If 1/h12 = 4, for a C.E. stage- what is the
d) 2 value of the base to collector capacitance,
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after Miller multiplication, at the input side?
Answer: d a) 4Cµ
Explanation: The small signal gain, of the
b) 5Cµ
C.B. stage, in a cascode stage is
approximately equal to the ratio of the c) 6Cµ
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transconductances of the two B.J.T.’s. Since d) 1.1Cµ

they are roughly same, the gain is 1. Miller
multiplication leads to multiplying the Answer: c
capacitance, between base and collector, by a Explanation: The capacitor, Cµ, gets
factor of (1 + small signal gain) which is 2. multiplied by a factor of (1 + Av), at the input
Hence, the correct option is 2.
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side of a C.E. stage. 1/h12 is equal to Av since

10. If the B.J.T. is used as a follower, which h12 is the reverse voltage amplification factor.
capacitor experiences Miller multiplication? Hence, the final value becomes 5Cµ.
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a) Cπ
b) Cµ 13. The transconductance of a B.J.T.is 5mS
c) Ccs (gm) while a 2KΩ (Rl) load resistance is
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d) Cb connected to the C.E. stage. Neglecting Early

effect, what is the Miller multiplication factor
Answer: a for the input side?
Explanation: We find that the input is given a) 21
to the base of the B.J.T. while the output is b) 11

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c) 20 can be approximated to be along a straight

d) 0 line. Whole analysis can be done with same
assumption of linearity with the limit of
Answer: b signal being in the same vicinity of the DC
Explanation: The Miller multiplication factor operating point.
for the input side of a C.E. stage is (1+Av). That’s how we get all those equations for

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Now, Av is the small signal low frequency linear operation and also its small signal
gain of the C.E. stage which is gm*RL=10. equivalent model using h-parameters.
Hence, the Miller multiplication factor is 11.
3. How many h-parameters are there for a
transistor?
TOPIC 2.3 AMPLIFIERS USING a) two
HYBRID π EQUIVALENT b) three

.c
CIRCUITS - AC LOAD LINE c) four
d) five
ANALYSIS
Answer: c

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1. The h-parameters analysis gives correct Explanation: A transistor has four h-
results for __________ parameters –
a) large signals only pa H11 = V1/i1 (Input Impedance with output
b) small signals only short circuited)
c) both large and small H21 = i2/i1 (Current gain with output short
d) not large nor small signals circuited)
H12 = V1/V2 (Voltage gain with feedback
Answer: b
Explanation: Every linear circuit is ratio with input terminals open)
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associated with h –parameters. When this H22 = i2/V2 (Output Admittance with input
linear circuit is terminated with load rL, we terminals open).
can find input impedance, current gain,
voltage gain, etc in terms of h-parameters. 4. The dimensions of hie parameters are
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For small a.c. signal, transistor behaves as _______

linear device. Under such circumstances the a) MHO
a.c. signal operation of a transistor can be b) OHM
described in terms of h-parameters. c) Farad
d) Ampere
2. For what type of signals does a transistor
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behaves as linear device? Answer: b

a) small signals only Explanation: hie = vBE/ib; common emitter
b) large signals only input impedance
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c) both large and small signal For VCE = 0 i.e. output short circuited
d) no signal Where vBE = Base emitter voltage i.e. input
Answer: a voltage
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Explanation: The small variation in the total ib = Base current i.e. input current
voltage and current due to an application of We know that V/I = R. Its unit is ohm.
signal moves the point up and down just by a
bit and that whole up and down dynamics of 5. The hfe parameter is called _______ in CE
the operating point from its DC value point arrangement with output short circuited.

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a) Voltage Gain b) HIB

b) Current gain c) HOE
c) Input impedance d) HRE
d) Output impedance

Answer: b Answer: a
Explanation: hie = vBE/ib; common emitter

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Explanation: hfe in CE arrangement is given
as input impedance
Hfe = Ic/Ib for VCE = 0 short circuited For VCE = 0 i.e. output short circuited
So, this is current gain as it is then output to Where vBE =Base emitter voltage i.e. input
input current ratio. voltage
ib = Base current i.e. input current.
6. What happens to the h parameters of a

.c
transistor when the operating point of the 9. How many h-parameters of a transistor are
transistor changes? dimensionless?
a) It also changes a) Four

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b) Does not change b) Two
c) May or may not change c) Three
d) Nothing happens d) One

Answer: a
pa
Explanation: It is very difficult to get exact
values of h parameters for a particular
Answer: b
Explanation: (i) H11 = V1/I1; for V2 = 0
(output short circuited)
transistor. It is because these parameters are This parameter is input impedance with
subject to considerable variation unit to unit output short.
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variation, variation due to change in Its unit is ohm.
temperature and variation due to the operating (ii) H21 = i2/i1; for V2 = 0 (output short
point.
circuited)
7. If temperature changes, h parameters of a This parameter is Current gain ratio with
output short.
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transistor _____
a) also change It is unit less or dimensionless.
b) does not change (iii) H12 = V1/V2; for i1 = 0 (input open
c) remains same circuited)
d) may or may not change This is voltage gain feedback ratio with
terminals open.
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Answer: a And it is unit less or dimensionless.

Explanation: It is very difficult to get exact (iv) H22 = i2/v2; for i1 = 0 (input open
values of h parameters for a particular circuited)
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transistor. It is because these parameters are This is output admittance with input terminals
subject to considerable variation unit to unit open.
variation, variation due to change in
Its unit is ohm-1 or mho.
temperature and variation due to the operating
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Thus there are two h-parameters which are

point. unit less or dimensionless.
8. In CE arrangement, the value of input
10. The values of h-parameters of a transistor
impedance is approximately equal to _____
in CE arrangement are ________
a) HIE

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arrangement. 2. Consider the circuit shown below where

a) same as for CB hfe=50
b) same as for CC
c) different from that in CB
d) similar to no

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Answer: c
Explanation: The values of h-parameter in
CE arrangement:
Hie = Vbe/Ib; for Vce = 0 (output short
circuited)
Hfe = ic/ib; for Vce = 0 (output short circuited)

.c
Hre = Vbe/Vce; for ib = 0 (input open
circuited)
Hoe = ic/vce; for ib = 0 (input open circuited) Calculate the input resistance of the network.
a) 255 kΩ

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The values of h-parameter in CB b) 13 MΩ
arrangement: c) 5 MΩ
Hib = Vbe/Ie; for Vbc = 0 (output short
pa d) 250 kΩ
circuited)
Hfb = ic/Ie; for Vbc = 0 (output short Answer: b
Explanation: The load for the first transistor
circuited)
in the figure is the input resistance of the
Hrb = Vbe/Vbc; for ie = 0 (input open
second.
circuited) RE1 = (1+hfe)5k = 255kΩ
jin
Hob = ic/vbe; for ie = 0 (input open circuited).
Net input resistance, RI = (1+hfe)RE1=
(1+hfe)25k = 13005k = 13MΩ.
TOPIC 2.4 DARLINGTON
AMPLIFIER - BOOTSTRAP 3. Given the following circuit
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TECHNIQUE - CASCADE,
CASCODE CONFIGURATIONS

1. Which of these are incorrect about

Darlington amplifier?
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a) It has a high input resistance

b) The output resistance is low
c) It has a unity voltage gain
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d) It is a current buffer

Answer: d It is given that hfe=55, hie=1kΩ, hoe=25μΩ-1.

Explanation: A Darlington amplifier has a Calculate the net current gain and the voltage
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very high input resistance, low output gain of the network.

resistance, unity voltage gain and a high a) AI=192.6, Av=220
current gain. It is a voltage buffer, not a b) AI=1, AV=220
current buffer.

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c) AI=192.6, AV=1 c) To prevent a decrease in the input

d) AI=192.6, AV=55 resistance due to the presence of multiple BJT
amplifiers
Answer: c d) To prevent a decrease in the input
Explanation: AI=A1xA2 resistance due to the biasing network
AI = [1+hfe/1+hoehfeRE]x[1+hfe] AI =

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Answer: b
51×51/(1+25x50x10x10-3) = 192.6. Explanation: A bootstrap biasing network is
a special biasing circuit used in Darlington
4. In a Darlington pair, the overall amplifier to prevent the decrease in input
β=15000.β1=100. Calculate the collector resistance due to the biasing network being
current for Q2 given base current for Q1 is 20 used. Capacitors and resistors are added to the
μA. circuit to prevent it from happening.

.c
7. Consider a Darlington amplifier. In the self
bias network, the biasing resistances are
220kΩ and 400 kΩ. What can be the correct

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value of input resistance if hfe=50 and emitter
resistance = 10kΩ.
pa a) 141 kΩ
b) 15 MΩ
a) 300 mA
c) 20 MΩ
b) 298 mA
d) 200 kΩ
c) 2 mA
d) 200mA Answer: a
Explanation: R’ = 220k||400k = 142 kΩ
jin
Answer: b
Explanation: IB = 20 μA RI = (1+hfe)2RE = 26MΩ
IC = β.IB = 15000 x 20μ = 300 mA RI’ = 26M||142k = 141.22 K.
IC1 = β1.IB = 100.20μ = 2mA
8. What is a cascode amplifier?
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IC2 = 300 – 2 = 298mA. a) A cascade of two CE amplifiers

b) A cascade of two CB amplifiers
5. Darlington amplifier is an emitter follower. c) A cascade of CE and CB amplifiers
a) True d) A cascade of CB and CC amplifiers
b) False
Answer: c
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Answer; a Explanation: A cascode amplifier is a

Explanation: Darlington pair is an emitter cascade network of CE and CB amplifiers, or
follower circuit, in which a darling pair is CS and CG amplifiers.
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used in place of a single It is used as a wide-band amplifier.

transistor. It also provides a large β as per
requirements.
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6. What is the need for bootstrap biasing?

a) To prevent a decrease in the gain of
network
b) To prevent an increase in the input
resistance due to the biasing network

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9. Consider the figure shown. a) 30mΩ-1

b) 10mΩ-1
c) 1mΩ-1
d) 20mΩ-1

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Answer: a
Explanation: For a MOSFET cascode
amplifier, the net transconductance in the
above network shown is equal to the
transconductance of MOSFET M1 that is
equal to 30mΩ-1.

.c
11. In the given circuit, hfe = 50 and hie =
Given that gm1 = 30mΩ-1 and gm2 =50mΩ-1, 1000Ω, find overall input and output
resistance.
α1 = 1.1, α2 = 1.5 what is the

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transconductance of the entire network?
a) 80 mΩ-1
b) 75 mΩ-1 pa
c) 33 mΩ-1
d) 55 mΩ-1

Answer: d
Explanation: The above circuit is a cascode
jin
pair. For this circuit, the overall
transconductance is
gm = α1gm2
gm = 1.1 gm2 = 55mΩ-1.
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a) RI=956Ω, RO=1.6 kΩ
10. Find the transconductance of the network
b) RI=956 kΩ, RO=2 kΩ
given below, provided that gm1 = 30mΩ-1. VT
c) RI=956 Ω, RO=2 kΩ
= 25mV, VBias > 4V.
d) RI=900Ω, RO=10 kΩ
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Answer: c
Explanation: RO = RC = 2kΩ
Input resistance = hie||50k||40k = 0.956 kΩ.
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TOPIC 2.5 DIFFERENTIAL

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AMPLIFIER, BASIC BJT

DIFFERENTIAL PAIR

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1. A Differential Amplifier should have Answer: a

collector resistor’s value (RC1 & RC2) as Explanation: When two input signals are
a) 5kΩ, 5kΩ applied to base of transistor, it is said to be
b) 5Ω, 10kΩ Dual Input. When both collectors are at same
c) 5Ω, 5kΩ DC potential with respect to ground, then it is
d) 5kΩ, 10kΩ said to be Balance Output.

om
Answer: a 5. A differential amplifier is capable of
Explanation: The values of collector current amplifying
will be equal in differential amplifier a) DC input signal only
(RC1=RC2). b) AC input signal only
c) AC & DC input signal
2. A Differential Amplifier amplifies d) None of the Mentioned

.c
a) Input signal with higher voltage
b) Input voltage with smaller voltage Answer: c
c) Sum of the input voltage Explanation: Direct connection between
d) None of the Mentioned stages removes the lower cut off frequency

ul
imposed by coupling capacitor; therefore it
Answer: d can amplify both AC and DC signal.
Explanation: The purpose of differential
amplifier is to amplify the difference between 6. In ideal Differential Amplifier, if same
two signals.
pa signal is given to both inputs, then output will
be
3. The value of emitter resistance in Emitter a) Same as input
Biased circuit are RE1=25kΩ & RE2=16kΩ. b) Double the input
Find RE c) Not equal to zero
jin
a) 9.756kΩ d) Zero
b) 41kΩ
c) 9.723kΩ Answer: d
d) 10kΩ Explanation: In ideal amplifier, Output
voltage
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Answer: a ⇒ Vout = Vin1-Vin2.

Explanation: In emitter biased circuit, RE1
& RE2 is connected in parallel combination. 7. Find the Single Input Unbalance Output
⇒ RE = RE1 II RE2 = (RE1× configuration in following circuit diagrams :
RE2)/(RE1+RE2) =
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(25kΩ×16kΩ)/(25kΩ+16kΩ) = 9.7561kΩ.

4. If output is measured between two

collectors of transistors, then the Differential
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amplifier with two input signal is said to be

configured as
a) Dual Input Balanced Output
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b) Dual Input Unbalanced Output

c) Single Input Balanced Output a)
d) Dual Input Unbalanced Output

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⇒ IE = (VEE-VBE)/(2RE) = (20v-
07v)/(2×1.3kΩ) = 7.42mA.

9. Find IC, given VCE=0.77v, VCC=10v,

VBE=0.37v and RC=2.4kΩ in Dual Input
Balanced Output differential amplifier

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a) 0.4mA
b) 0.4A
c) 4mA
b) d) 4A

Answer: c
Explanation: Substitute the values in

.c
collector to emitter voltage equation,
VCE= VCC+ VBE-RC IC
⇒IC = (VCC-VCE+VBE)/RC = (10v-

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0.77v+0.37v)/2.4kΩ = 4mA

10. Find the correct match

c)
pa Configuration
Voltage gain and
Input resistance
i. Ad = Rc/re , Ri1 Ri2
1. Single Input
Unbalanced Output = 2βacRE
2. Dual Input ii. Ad= Rc/2re , Ri1 Ri2 =
jin
Balanced Output 2βacRE

3. Single Input iii. Ad= Rc/re , Ri =

Balanced Output 2βacRE
d)
.re

4. Dual Input iv. Ad = Rc/2re , Ri =

Answer: c Unbalanced Output 2βacRE
Explanation: Circuit c has only single input
(V1) and output is measure only at one of the a) 1-i , 2-iii, 3-iv, 4-ii
collector with respect to ground. b) 1-iv, 2-ii, 3-iii, 4-i
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c) 1-ii, 2-iv, 3-i , 4-iii

8. An emitter bias Dual Input Balanced d) 1-iii, 2-i, 3-ii, 4-iv
Output differential amplifier has VCC=20v,
β=100, VBE=0.7v, RE=1.3kΩ. Find IE Answer: d
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a) 7.42mA Explanation: Properties of differential

b) 9.8mA amplifier circuit configuration.
c) 10mA
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d) 8.6mA 11. Obtain the collector voltage, for collector

resistor (RC) =5.6kΩ, IE=1.664mA and
Answer: a VCC=10v for single input unbalanced output
Explanation: Emitter current can be found differential amplifier
out by substituting the values in the equation, a) 0.987v

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b) 0.682v c) 38
c) 0.555v d) 61
d) None of the mentioned
Answer: a
Answer: b Explanation: In single Input Balance Output
Explanation: Substitute the given values in amplifier,

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collector voltage equation, ⇒ IE = (VEE-VBE)/2RE
VC= VCC – RC×IC =(15v-0.7v)/(2×3.9kom)= 1.83mA
⇒ VC= 10v – 5.6kΩ×1.664mA (∵ IC ≅ IE ) (∵VCC=VEE)
⇒ VC= 0.682v. From the equation, VCE = VCC +VBE-
RC×IC
12. For the circuit shown below, determine ⇒ RC = (14.3v – 2.4v)/1.83mA = 6.5kΩ
the Output voltage (Assume β=5, differential The voltage gain, Vo

.c
input resistance=12 kΩ) ⇒ Vo = RC/re
= 6.5kΩ/250Ω = 26(no units).

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TOPIC 2.6 SMALL SIGNAL
ANALYSIS AND CMRR.
pa 1. For the difference amplifier which of the
following is true?
a) It responds to the difference between the
two signals and rejects the signal that are
common to both the signal
jin
b) It responds to the signal that are common
a) 4.33v to the two inputs only
b) 2.33v c) It has a low value of input resistance
c) 3.33v d) The efficacy of the amplifier is measured
d) 1.33v by the degree of its differential signal to the
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preference of the common mode signal

Answer: c
Explanation: From the circuit dig, Answer: a
RC=10kΩ, Vin1= 1.3v and Vin2=0.5v, Explanation: All the statements are not true
Differential input resistance = 2 βre, except for the fact that it responds only when
there is difference between two signals only.
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⇒ 12kΩ = 2×5×Re
⇒ Re = 1.2 kΩ
2. If for an amplifier the common mode input
Output voltage Vo = RC/2Re(Vin1-Vin2) signal is vc, the differential signal id vd and
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⇒ Vo = 10kΩ/(2 ×1.2kΩ) × (1.3v-0.5v)

Ac and Ad represent common mode gain and
⇒ Vo = 3.33v.
differential gain respectively, then the output
13. In a Single Input Balanced Output voltage v0 is given by
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Differential amplifier, given VCC=15v, RE = a) v0 = Ad vd – Ac vc

3.9kΩ, VCE=2.4 v and re=250Ω. Determine b) v0 = – Ad vd + Ac vc
Voltage gain c) v0 = Ad vd + Ac vc
a) 26
b) 56 d) v0 = – Ad vd – Ac vc

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Answer: c
Explanation: It is a standard mathematical
expression.

3. If for an amplifier v1 and v2 are the input

signals, vc and vd represent the common

om
mode and differential signals respectively,
then the expression for CMRR (Common
Mode Rejection Ratio) is
a) 20 log (|Ad| / |Ac|)
b) -10 log (|Ac| / |Ad|)2
c) 20 log (v2 – v1 / 0.5(v2 + v1))

.c
a) 20 log [K+1/4ε].
d) All of the mentioned b) 20 log [K+1/2ε].
c) 20 log [K+1/ε].
Answer: d d) 20 log [2K+2/ε].

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Explanation: Note that all the expressions are
identical. Answer: a
Explanation: None.
4. The problem with the single operational
pa
difference amplifier is its 6. For the circuit given below determine the
a) High input resistance input common mode resistance.
b) Low input resistance
c) Low output resistance
d) None of the mentioned
jin
Answer: b
Explanation: Due to low input resistance a
large part of the signal is lost to the source’s
internal resistance.
.re

5. For the difference amplifier as shown in

the figure show that if each resistor has a
tolerance of ±100 ε % (i.e., for, say, a 5%
resistor, ε = 0.05) then the worst-case CMRR
is given approximately by (given K = R2/R1 a) (R1 + R3) || (R2) || + (R4)
w

= R4/R3) b) (R1 + R4) || (R2 + R3)

c) (R1 + R2) || (R3 + R4)
d) (R1 + R3) || (R2 + R4)
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Answer: c
Explanation: Parallel combination of series
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combination of R1 & R3 with the series

combination of R3 and R4 is the required
answer as is visible by the circuit.

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7. For the circuit shown below express v0 as a 9. Determine Ad and Ac for the given circuit.
function of v1 and v2.

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a) v0 = v1 + v2 a) Ac = 0 and Ad = 1

.c
b) v0 = v2 – v1 b) Ac ≠ 0 and Ad = 1
c) v0 = v1 – v2 c) Ac = 0 and Ad ≠ 1
d) v0 = -v1 – v2 d) Ac ≠ 0 and Ad ≠ 1

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Answer: b Answer: a
Explanation: Considering the fact that the Explanation: Consider the fact that the
potential at the input terminals are identical potential at the input terminals are identical
pa
and proceeding we obtain the given result. and obtain the values of V1 and V2. Thus
obtain the value of Vd and Vc.
8. For the difference amplifier shown below,
let all the resistors be 10kΩ ± x%. The 10. Determine the voltage gain for the given
expression for the worst-case common-mode circuit known that R1 = R3 = 10kΩ abd R2 =
jin
gain is R4 = 100kΩ.
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a) x / 50
b) x / 100
c) 2x / (100 – x)
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d) 2x / (100 + x)
a) 1
Answer: d b) 10
Explanation: None. c) 100
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d) 1000

Answer: b
Explanation: Voltage gain is 100/10. 

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3. The slope obtained in VGS vs ID was

0.002. What is the value ofgm?
UNIT III SINGLE STAGE a) 1
b) 2
FET, MOSFET c) 0.002
AMPLIFIERS d) 0

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Answer: c
TOPIC 3.1 SMALL SIGNAL Explanation: gm = change in drain current/
HYBRID π EQUIVALENT change in gate to source voltage gm = slope
CIRCUIT OF FET AND MOSFET of VGS vs ID gm = 0.002.

.c
1. What is trans-conductance? 4. Which of the following is an expression for
a) Ratio of change in drain current to change gm0?
in collector current a) gm0 = IDSS/Vp

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b) Ratio of change in drain current to change b) gm0 = 2IDSS/|Vp|
in gate to source voltage
c) gm0 = IDSS/5Vp
c) Ratio of change in collector current to
change in drain current pa d) gm0 = IDSS/2Vp
d) Ratio of change in collector current to
change in gate to source voltage Answer: b
Explanation: gm0 is the value of gm when
Answer: b VGS=0, we have seen that trans conductance
Explanation: The change in drain current
is the ratio of drain current to change in gate
which is resulted due to change in gate to
jin
to source voltage, but this is an exceptional
source voltage in a FET is measured by trans-
case, here the transistor will be working in cut
conductance. This is termed as trans because
off region.
it provides relationship between input and
output quantity. 5. Find the maximum value of gm for FET
.re

2. For a FET, graph is drawn by taking with IDSS=10mA, Vp=-2V, VGS=5V?

voltage VGS in X axis and drain current in Y a) 10mS
axis, if the value of X changes from 10 to 20 b) 20mS
results in change in value of Y axis from 2 to c) 1mS
3. What is the value of trans conductance? d) 0
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a) 1
Answer: a
b) 2
Explanation: gm0=2IDSS/|Vp|
c) 0.1
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d) 0.01 gm0=2×10mA/2V gm0=10mS.

Answer: c 6. Find the value of gm for FET with

Explanation: Trans-conductance= change in IDSS=8mA, Vp=4V, VGS=-0.5V?
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drain current/ change in gate to source

a) 1mS
voltage b) 2mS
trans conductance=3-2/20-10=1/10 c) 3mS
trans conductance=0.1. d) 3.5mS

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Answer: d Answer: b
Explanation: For FET, the voltage is applied
across the gate and source to control the drain
current, hence while writing small signal
model of an FET, on the output side gm VGS
represents a current source which can be

om
controlled by the input voltage VGS.
Explanation:
10. Given yfs = 3.6mS and yos = 0.02mS,
7. A FET has IDSS=4ID and gm0 = 10mS then
determine r0?
gm = _________________________
a) 100Kohm
a) 10mS b) 50Mohm

.c
b) 20mS c) 50Kohm
c) 5mS d) 20Kohm
d) 14mS
Answer: c

ul
Answer: c Explanation: r0=1/yos
Explanation:
It is independent of yfs. => r0=1/20mS
pa r0=50Kohm.

TOPIC 3.3 AMPLIFIERS USING

HYBRID π EQUIVALENT
CIRCUITS
jin
1. Which of the following statement is
8. Determine the value of output impedance
incorrect?
for JFET, if the value of gm =1mS?
a) Output of CE amplifier is out of phase with
a) 1Kohm respect to its input
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b) 0 b) CC amplifier is a voltage buffer

c) 100Kohm c) CB amplifier is a voltage buffer
d) 5Kohm d) CE amplifier is used as an audio (low
frequency) amplifier
Answer: a
Explanation: Output impedance=inverse of
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Answer: c
trans conductance Explanation: The output of the CE amplifier
Output impedance=1/1mS
has a phase shift of 180o with respect to the
Output impedance=1Kohm.
input. The CC amplifier has AV≅1, thus it is
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9. In a small signal equivalent model of an a voltage buffer. However, the CB amplifier

FET, What does gm VGS stand for? has a large voltage gain, and its current gain
AI≅1, thus it is a current buffer. CE amplifier
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a) A pure resistor
b) Voltage controlled current source has an application has an audio amplifier.
c) Current controlled current source
d) Voltage controlled voltage source 2. Consider the following circuit.
__________ provides DC isolation.

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_____________ prevents a decrease in hoRL’) where RL’ = 2kΩ||4kΩ

voltage gain. _____________ is used to RL’ = 1.33kΩ.
control the bandwidth. Thus AI = – 60 / (1 + 0.0266) = -58.4453.

4. Consider the circuit. Given hfe = 50, hie =

om
1200Ω. Find voltage gain.

a) C3, C1, C4

.c
b) C4, C1, C2
c) C2, C3, C2
d) C4, C3, C2

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a) – 278
Answer: b b) -277.9
Explanation: Capacitor C3 and C4, are the c) – 300
blocking capacitor and coupling capacitor d) – 280
respectively, both providing DC isolation to
pa
biasing circuit. Capacitor C1 is the emitter
bypass capacitor, to prevent decrease in
Answer: a
Explanation: Voltage gain = AV = -
voltage gain by avoiding negative feedback.
hfeRL’/hie
Capacitor C2 is the shunt capacitor, used to
control the bandwidth, wherein the bandwidth RL’ = 20k||10k = 6.67kΩ
jin
is inversely proportional to C2. AV = -50 * 6.67k/1.2k = -277.9 ≅ – 278.

3. Given hfe = 60, hie=1000Ω, hoe = 20μ Ω–, 5. Given that IB = 5mA and hfe = 55, find
hre = 2 * 10-4. Find the current gain of the load current.
.re

BJT, correct up to two decimal points.

w
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a) 28mA
a) – 58.44 b) 280mA
b) -59.21 c) 2.5A
c) – 60.10
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d) 2A
d) – 60.00
Answer: b
Answer: a Explanation: In given circuit, which is an
Explanation: Current gain, AI = – hf / (1 + emitter follower, current gain = 1 + hfe

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IL = IB (1+hfe)
IL = 5mA(56) = 280 mA.

6. Consider the following circuit, where

source current = 10mA, hfe = 50, hie =
1100Ω, then for the transistor circuit, find

om
output resistance RO and input resistance RI.

a) RI = 20Ω, RO = ∞

.c
b) RI = 20Ω, RO = 2kΩ
c) RI = 59Ω, RO = ∞
d) RI = 59Ω, RO = 2kΩ

ul
Answer: c
Explanation: RI = 20k = hie/(1+hfe) = hie/51
a) RO = 0, RI = 21Ω hie =1020 Ω
b) RO = ∞, RI = 0Ω
c) RO = ∞, RI = 21Ω
pa Hence, after adding base resistance, RI’=
(hie+RB)/(1+hfe) = (1020+2000) / 51 ≅ 59Ω
d) RO = 10, RI = 21Ω There is no change in output resistance or
current gain due to an extra base resistance.
jin
Answer: c RO’ = ∞.
Explanation: Since hoe is not given, we can
consider it to be small; i.e 1/hoe is neglected, 8. Consider its input resistance to be R1.
open circuited. Hence output resistance RO = Now, the bypass capacitor is attached, so that
the new input resistance is R2. Given that hie
∞.
.re

Input resistance = hie/(1 + hfe) = 1100/51 ≅ = 1000Ω and hfe = 50, find R1-R2.
21Ω.

7. For the given circuit, input resistance RI =

20Ω, hfe = 50. Output resistance = ∞. Find
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the new values of input and output resistance,

if a base resistance of 2kΩ is added to the
circuit.
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a) 112.2Ω
b) 0Ω
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c) 110Ω
d) 200Ω

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Answer: a gain with respect to transistor input. However

Explanation: For the circuit, CE amplifier when RS=0 then AVS = AV.
without bypass capacitor, input resistance,
R1=hie + (1+hfe)RE
R1 = 1000 + 51*2.2 = 1000 + 112.2 =
TOPIC 3.4 BASIC FET
1112.2Ω DIFFERENTIAL PAIR- BICMOS

om
With a bypass capacitor attached, input CIRCUITS.
resistance, R2 = hie = 1000Ω
Thus R1 – R2 = 112.2Ω. 1. The difference output of the basic
differential amplifier is taken at ___________
9. Given that for a transistor, hie = 1100Ω, hfe a) At X and ground
= 50, hre = 2*10-4 and hoe = 2μΩ-1. Find CB b) At Y and ground

.c
c) Difference of the voltages at the gates of
h-parameters.
M1 and M2
a) hfb = 1, hib = 22, hob = 3μΩ-1, hrb = d) Difference of the voltages between X and
-1.5×10-4 Y

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b) hfb = -0.98, hib = -21.56, hob = 0.03μΩ-1,
Answer: d
hrb = 1.5×10-4 Explanation: None.
c) hfb = -0.98, hib = 21.56, hob = 0.03μΩ-1,
hrb = -1.5×10-4
pa 2. The Differential output of the difference
amplifier is the amplification of __________
d) hfb =1, hib = -21.56, hob = 0.03μΩ-1, hrb = a) Difference between the voltages of input
signals
-2×10-4 b) Difference between the output of the each
jin
transistor
Answer: c c) Difference between the supply and the
Explanation: hfb = -hfe/(1+hfe) = -50/51= output of the each transistor
-0.98 d) All of the mentioned
hib = hie/(1+hfe) = 21.56Ω
.re

Answer: a
hob = hoe/(1+hfe) = 0.03 μΩ-1
Explanation: None.
hrb = (hiehoe/1+hfe) – hre = -1.5×10-4.
3. The inputs to the differential amplifier are
10. If source resistance in an amplifier circuit applied at __________
is zero, then voltage gain (output to input a) At X and Y
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voltage ratio) and source voltage gain (output b) At the gates of M1 and M2
to source voltage ratio) are the same. c) All of the mentioned
a) True d) None of the mentioned
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b) False
Answer: b
Answer: a Explanation: None.
Explanation: When a source resistance RS is
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4. The Maximum and minimum output of the

present, the voltage gain with respect to
Differential amplifiers is defined as:
source becomes
a) Vmax = VDD, Vmin = -VDD
AVS = AVRI’/(RS+RI’), where AV is voltage
b) Vmax = VDD, Vmin = Rd.Iss

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c) Vmax = VDD, Vmin = VDD – Rd.Iss TOPIC 4.1 AMPLIFIER

d) None of the mentioned
FREQUENCY RESPONSE
Answer: c
Explanation: None. 1. Consider a voltage amplifier having a
frequency response of the low-pass STC type

om
5. In Common Mode Differential Amplifier, with a dc gain of 60 dB and a 3-dB frequency
the outputs Vout1 and Vout2 are related as: of 1000 Hz. Then the gain db at
a) Vout2 is in out of phase with Vout1 with a) f = 10 Hz is 55 db
same amplitude b) f = 10 kHz is 45 db
b) Vout2 and Vout1 have same amplitude but c) f = 100 kHz is 25 db
the phase difference is 90 degrees d) f = 1Mhz is 0 db
c) Vout1 and Vout2 have same amplitude and

.c
are in phase with each other and their Answer: d
respective inputs Explanation: Use standard formulas for
d) Vout1 and Vout2 have same amplitude and frequency response and voltage gain.
are in phase with each other but out of phase

ul
with their respective inputs 2. STC networks can be classified into two
categories: low-pass (LP) and high-pass (HP).
Answer: d Then which of the following is true?
Explanation: None.
pa
6. In a small signal differential gain vs input
a) HP network passes dc and low frequencies
and attenuate high frequency and opposite for
LP network
CM level graph, the gain decreases after V2 b) LP network passes dc and low frequencies
due to: and attenuate high frequency and opposite for
a) As the input voltage increases, the output HP network
jin
will be clipped c) HP network passes dc and high frequencies
b) When the input voltage to the transistors and attenuate low frequency and opposite for
are high, the transistor enters saturation LP network
region and increases the current, which inturn d) LP network passes low frequencies only
decreases the output voltage = VDD – Rd.Iss
.re

and attenuate high frequency and opposite for

c) When Common Mode voltage is greater HP network
than or equal to V2, the input transistors enter
triode region, the gain begins to fall Answer: b
d) Increasing the input voltage beyond V2 Explanation: By definition a LP network
causes the gate oxide to conduct and the gain allows dc current (or low frequency current)
w

is reduced and an LP network does the opposite, that is,

allows high frequency ac current.
Answer: c
Explanation: None. 3. Single-time-constant (STC) networks are
w

those networks that are composed of, or can

be reduced to
a) One reactive component (L or C) and a
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resistance (R)
UNIT IV FREQUENCY b) Only capacitive component (C) and
RESPONSE OF resistance (R)
c) Only inductive component (L) and
AMPLIFIERS resistance (R)

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d) Reactive components (L, C or both L and

C) and resistance (R)

Answer: a
Explanation: STC has only one reactive
component and one resistive component.

om
4. The signal whose waveform is not effected
by a linear circuit is
a) Triangular Waveform signal
b) Rectangular waveform signal
c) Sine/Cosine wave signal a) C1R1 = C2R2
d) Sawtooth waveform signal b) C1R2 = C2R1

.c
c) C1C2 = R1R2
Answer: c d) R1 = 0
Explanation: Only sine/cosine wave are not
affected by a linear circuit while all other Answer: a

ul
waveforms are affected by a linear circuit. Explanation: Standard condition of a
compensated attenuator. Here is the
5. Which of the following is not a derivation for the same.
classification of amplifiers on the basis of
their frequency response?
a) Capacitively coupled amplifier
pa
b) Direct coupled amplifier
c) Bandpass amplifier
d) None of the mentioned
jin
Answer: d
Explanation: None of the options provided
are correct.
.re

6. General representation of the frequency

response curve is called
a) Bode Plot
b) Miller Plot
c) Thevenin Plot
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d) Bandwidth Plot

Answer: a
Explanation: General representation of
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frequency response curves are called Bode

plot. Bode plots are also called semi
logarithmic plots since they have logarithmic
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values values on one of the axes. 8. When a circuit is called compensated

attenuator?
7. Under what condition can the circuit shown a) Transfer function is directly proportional to
be called a compensated attenuator. the frequency
b) Transfer function is inversely proportional

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to the frequency b) Ccs

c) Transfer function is independent of the c) Cb
frequency d) Ccs and Cb
d) Natural log of the transfer function is
proportional to the frequency
Answer: a
Explanation: There are two capacitors which

om
Answer: c
Explanation: Transfer function does not has arise between bases and emitter. One is Cje
frequency in its mathematical formula. due to depletion region associated between
base and emitter. Cb is another capacitor
9. Which of the following is true? which arises due to the accumulation of
a) Coupling capacitors causes the gain to fall electrons in the base which further results into
off at high frequencies the concentration gradient within the base of

.c
b) Internal capacitor of a device causes the the transistor.
gain to fall off at low frequencies
c) All of the mentioned 2. During high frequency applications of a
d) None of the mentioned B.J.T., which parasitic capacitors arise

ul
between the collector and the emitter?
Answer: d a) No capacitor arises
Explanation: Both the statements are false.
pa b) Ccs
c) Cb
10. Which of the following is true?
a) Monolithic IC amplifiers are directly d) Ccs and Cb
coupled or dc amplifiers
b) Televisions and radios use tuned amplifiers Answer: a
c) Audio amplifiers have coupling capacitor Explanation: The emitter and the collector
jin
amplifier are far away from each other when the B.J.T.
d) All of the mentioned is being constructed. Hence, we find that they
don’t share a common junction where charges
Answer: d can accumulate. Thus, no such parasitic
Explanation: These all are practical capacitors appear.
.re

applications of different types of amplifiers.

3. During high frequency applications of a
B.J.T, which parasitic capacitors arise
TOPIC 4.2 FREQUENCY between the collector and the base?
RESPONSE OF TRANSISTOR a) Cje and Cb
AMPLIFIERS WITH CIRCUIT
w

b) Ccs
CAPACITORS c) Cπ
d) Cµ
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TOPIC 4.3 BJT FREQUENCY

Answer: d
RESPONSE Explanation: Only one capacitor up between
the base and the collector. This is due to the
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1. During high frequency applications of a depletion region present between the base and
B.J.T., which parasitic capacitors arise the collector region.
between the base and the emitter?
a) Cje and Cb 4. Which parasitic capacitors are present at
the collector terminal of the B.J.T.?

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a) Cje and Cb a) Ccs

b) Ccs and Cµ b) Ccs and Cb
c) Cb c) Cb
d) Ccs and Cb d) Ccs and Cµ

om
Answer: b Answer: a
Explanation: There are two capacitors Explanation: In the follower stage, the load
attached to the collector terminal. The is present at the emitter. The parasitic
collector-base junction provides a depletion capacitors present between the collector and
capacitance (Cµ) while the collector substrate the substrate i.e. Cµ gets deactivated. This is
junction provides a certain capacitance (Ccs). observed from the small signal analysis where
both the terminals of this capacitor get

.c
5. Which parasitic capacitors do not affect the shorted to A.C. ground.
frequency response of the C.E. stage, of the
B.J.T.? 8. If the transconductance of the B.J.T
increases, the transit frequency ______

ul
a) Cje and Cb
b) Ccs and Cµ a) Increases
b) Decreases
c) Cb and Cµ pa c) Doesn’t get affected
d) No parasitic capacitor gets deactivated d) Doubles

Answer: d Answer: a
Explanation: While observing the frequency Explanation: The transit frequency is directly
response of a C.E. stage, we find that all the proportional to the transconductance of the
parasitic capacitances of the B.J.T. end up B.J.T. Hence, the correct option is increases.
jin
slowing the speed of the B.J.T. The frequency Since it hasn’t been mentioned that whether
response of this stage is affected by all the the transconductance has been doubled or not,
parasitic capacitors. we cannot conclude the option “doubles” as
an answer.
6. Which parasitic capacitors don’t affect the
.re

frequency response of the C.B. stage of the 9. If the total capacitance between the base
B.J.T.? and the emitter increases by a factor of 2, the
a) None of the parasitic capacitances transit frequency __________
b) All the parasitic capacitances a) reduces by 2
c) Some of the coupling capacitors b) increases by 2
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d) Ccs and Cb c) reduces by 4

d) increases by 4
Answer: b
Explanation: All the parasitic capacitors of a Answer: a
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B.J.T. affect the C.B. stage. None of the Explanation: The transit frequency is almost
parasitic capacitors gets deactivated and they inversely proportional to the total capacitance
end up behaving as a pole during the between the base and the emitter of the B.J.T.
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frequency response of the C.B. stage. Hence, the transit frequency will
approximately reduce by 2 and the correct
7. Which parasitic capacitors don’t affect the option becomes reduces by 2.
frequency response of the C.C. stage of the
B.J.T.?

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10. Which effect plays a critical role in the C.E. stage is gmRl. By the application of
producing changes in the frequency response miller effect, we find that the capacitance
of the B.J.T.? between the base and the collector, looking
a) Thevenin’s effect from the output side, will be increased by a
b) Miller effect factor of 1 + 1/gmRl. Hence, the correct
c) Tellegen’s effect
option is 1 + 1/ gmRl.

om
d) Norton’s effect

Answer: a 13. If a C.E. stage with early effect has a load

Explanation: The miller effect results in a Rl and transconductance gm, what is the
change in the capacitance seen between the factor by which the capacitance between the
base and the collector. This is why, it affects base and the collector at the output side, gets
the frequency response of the B.J.T. deeply multiplied?

.c
by changing the poles and affecting the high a) 1 + 2/gm*(Rl || ro)
frequency voltage gain stage. b) 1 – 1/gm*(Rl || ro)
c) 1 + 1/gm*(Rl || ro)
11. If a C.E. stage has a load Rl and

ul
d) 1 – 2/gm*(Rl || ro)
transconductance gm, what is the factor by
which the capacitance between the base and Answer: c
the collector at the input side gets multiplied?
pa Explanation: If the early effect is considered,
a) 1 + gmRl the low frequency response of the C.E. stage
b) 1 – gmRl becomes gm*(Rl || ro). Thereby, miller
c) 1 + 2*gmRl approximation shows that the capacitance
d) 1 – 2*gmRl between the base and the collector, looking
from the output side, will be increased by a
jin
Answer: a factor of 1 + 1/gm*(Rl || ro). Hence the
Explanation: The low frequency gain of the correct option is 1 + 1/ gm*(Rl || ro).
C.E. stage is gmRl. By the application of
miller effect, we find that the capacitor 14. For a high frequency response of a simple
.re

between the base and the collector, looking C.E. stage with a transconductance of gm,
into the input of the C.E. stage, will be what is Cin?
increased by a factor of 1 + gmRl. a) Cµ(1 + gm*R2) – Cπ
b) Cµ(1 + gm*R2) + Cπ
12. If a C.E. stage has a load Rl and
c) Cµ(1 – 2*gm*R2) + Cπ
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transconductance gm, what is the factor by

d) Cµ(1 + 2*gm*R2) – Cπ
which the capacitance between the base and
the collector at the output side gets
Answer: b
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multiplied?
a) 1 + 1/gmRl Explanation: The input capacitance is an
equivalent of the base to emitter capacitance
b) 1 – 1/gmRl in parallel to the miller approximation of the
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c) 1 + 2/gmRl base to collector capacitance. Due to miller

d) 1 – 2/gmRl approximation, the base to collector
capacitance becomes Cµ(1+gm*R2) while the
Answer: a base to emitter capacitance is Cπ. Capacitors
Explanation: The low frequency response of

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get added, when in parallel and thus ignored as. Instead of h-parameter model, we
Cµ(1+gm*R2) + Cπ is correct. use π-model.

15. For a high frequency response of a simple 2. Consider a CE circuit, where trans-
C.E. stage with a transconductance of gm, conductance is 50mΩ-1, diffusion capacitance
what is Cout? is 100 pF, transition capacitance is 3 pF. IB =

om
a) Ccs – Cµ*(2 + 1/gm*R2) 20μA. Given base emitter dynamic resistance,
b) Ccs + Cµ*(1 + 2/gm*R2) rbe = 1000 Ω, input VI is 20*sin(107t). What
c) Ccs – Cµ*(1 + 1/gm*R2) is the short circuit current gain?
a) 30
d) Ccs + Cµ*(1 + 1/gm*R2)
b) 35
c) 40

.c
Answer: d
d) 100
Explanation: We have a capacitor from the
collector to substrate, Ccs, which comes in Answer: b
parallel to the miller approximation of the Explanation: AI = IL/IB

ul
capacitance from base to collector. The miller IL = -gmVb’e
approximation defines the latter as Cµ*(1 +
Vb’e = Ib rb’e / (1+jωCrb’e)
1/gm*R2). Since capacitors gets added, when
C = CD + CT = 103pF

1/gm*R2).
pa
in parallel, the correct option is Ccs + Cµ*(1+
Vb’e = 20μ.1k/(1+j.107.103.10-12.1000)
AI = IL/IB = 50m.1k/(1+j.107.103.10-12.1000)
AI = 35 (approx).
TOPIC 4.4 SHORT CIRCUIT
jin
CURRENT GAIN 3. Given that transition capacitance is 5 pico
F and diffusion capacitance is 80 pico F, and
TOPIC 4.5 CUT OFF base emitter dynamic resistance is 1500 Ω,
find the β cut-off frequency.
FREQUENCY - Fα, Fβ AND
a) 7.8 x 106 rad/s
.re

UNITY GAIN BANDWIDTH

b) 8.0 x 106 rad/s
c) 49.2 x 106 rad/s
1. We cannot use h-parameter model in high
frequency analysis because ____________ d) 22.7 x 106 rad/s
a) They all can be ignored for high
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Answer: a
frequencies
b) Junction capacitances are not included in it Explanation: The frequency in radians is
c) Junction capacitances have to be included calculated by
ωβ = 1/C.rbe
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in it
d) AC analysis is difficult for high frequency ωβ = 7.8 x 106.
using it
4. For given BJT, β=200. The applied input
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Answer: b frequency is 20 Mhz and net internal

Explanation: The effect of smaller capacitors capacitance is 100 pF. What is the CE short
is considerable in high frequency analysis of circuit current gain at β cut-off frequency?
analog circuits, and hence they cannot be a) 200
b) 100

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c) 141.42 Bandwidth Product of BJT

d) 440.2 c) Gain of BJT decreases at higher
frequencies due to junction capacitances
Answer: c d) β- cut-off frequency is one where the CE
Explanation: The current gain for the CE short circuit current gain becomes β/2
β
circuit is A =

om
√1+(
f

f
β
2
) Answer: d
β Explanation: At unity gain frequency the
At f = fβ, A = √2 current gain is 1 is a correct statement. The
Hence A = 141.42. same frequency is fT = βfβ which is the gain
bandwidth product of BJT. Gain of BJT at
5. Given that β=200, input frequency is f= high frequency decreases due to the junction
20Mhz and short circuit current gain is capacitance. However, at β cut-off frequency,

.c
A=100. What is the unity gain frequency?
current gain becomes β .
a) 2300 Mhz √2

b) 2000 Mhz
c) 2500 Mhz 8. Given a MOSFET where gate to source

ul
d) 3000 Mhz capacitance is 300 pF and gate to drain
capacitance is 500 pF. Calculate the gain
Answer: a bandwidth product if the transconductance is
β
30 mΩ-1.
Explanation: A =

1 + (20/f)2 = 4
√ 1+(20M hz/f β)
2
paa) 5.98 Mhz
b) 4.9 Mhz
20/f = 1.732 c) 6.5Mhz
fβ = 11.54 Mhz d) 5.22Mhz
Unity gain frequency = βfβ = 200 x 11.54Mhz
jin
= 2308 Mhz. Answer: a
Explanation: Gain bandwidth product for
6. Gain bandwidth frequency is GBP= 3000 any MOSFET is fT = gm/2π(Cgs+Cgd)
Mhz. The cut-off frequency is f=10Mhz. Thus GBP is approximately 5.9 Mhz.
.re

What is the CE short circuit current gain at

the β cutoff frequency? 9. In an RC coupled CE amplifier, when the
a) 212 input frequency increases, which of these are
b) 220 incorrect?
c) 300 a) Reactance CSH decreases
d) 200 b) Voltage gain increases
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c) Voltage gain decreases due to shunt

Answer: a capacitance
Explanation: fT = 3000Mhz d) An RC coupled amplifier behaves like a
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βfβ = 3000Mhz low pass filter

β = 3000/10 = 300
β Answer: b
A= = 212.13. Explanation: When frequency increases,
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√2

shunt reactance decreases. The voltage drop

7. Which of the statement is incorrect? across shunt capacitance decreases and net
a) At unity gain frequency the CE short voltage gain decrease. RC coupled amplifier
circuit current gain becomes 1 acts as a low pass filter at high frequencies.
b) Unity gain frequency is the same as Gain

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TOPIC 4.6 MILLER EFFECT -

FREQUENCY RESPONSE OF
FET

1. In Miller’s theorem, what is the constant

om
K?
a) Total voltage gain
b) Internal voltage gain
c) Internal current gain
d) Internal power gain

Answer: b a) 27.68

.c
Explanation: The constant K=V2/V1, which b) -22
c) 30.55
is the internal voltage gain of the network.
d) -27.68
Thus resistance RM=R/1-K

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RN=R/1-K-1. Answer: d
Explanation: Apply millers theorem to
2. When applying miller’s theorem to
pa resistance between input and output.
resistors, resistance R1 is for node 1 and R2 At input, RM=100k/1-K = RI
for node 2. If R1>R2, then for same circuit, Output, RN=100k/1-K-1 ≈ 100k
then for capacitance for which the theorem is
Internal voltage gain , K = -hfeRL’/hie
applied, which will be larger, C1 or C2?
a) C1 K = – 50xRc||100k/1k = – 50x4x100/104= –
b) C2 192
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c) Both are equal RI = 100k/1+192 = 0.51kΩ
d) Insufficient data RI’ = RI||hie = 0.51k||1k = 0.51×1/1.51 =
0.337kΩ
Answer: a
Net voltage gain = K.RI’/RS+RI’ = – 192 x
.re

Explanation: Given R1>R2

0.337/2k + 0.337k = -27.68.
R/1-K > R/1-K-1, and so 1-K-1>1-K
Thus K2>1, K>1, K<-1 (correct) 4. Given that capacitance w.r.t the input node
Thus, C1=C(1-K) and C2=C(1-K-1) is 2pF and output node is 4pF, find
Hence C1>C2 capacitance between input and output node.
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a) 0.67 pF
3. Find net voltage gain, given hfe = 50 and b) 1.34pF
hie = 1kΩ. c) 0.44pF
d) 2.2pF
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Answer: a
Explanation: C1=C(1-K), C2=C(1-K-1)
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C1=2pF
C2=4pF
C1/C2=1/2=1-K/1-K-1
K = -2

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C1 = C(1+2) = 3C a) 22.73 Hz
C = C1/3 = 2/3pF = 0.67 pF. b) 612 Hz
c) 673Hz
5. Consider an RC coupled amplifier at low d) 317 Hz
frequency. Internal voltage gain is -120. Find
the voltage gain magnitude, when given that Answer: b

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collector resistance = 1kΩ, load = 9kΩ, Explanation: RC = 2kΩ, RL = 5kΩ, CC =
collector capacitance is 0. is 0.1μF, and input 1μF, CB = 10μF, CE = 20μF, RS = 2 kΩ
frequency is 20Hz.
hie = 1kΩ, IC = 2mA
a) 120
b) 12 fL1 = 1/2πCC(RC+RL) = 22.73 Hz
c) 15 fL2 = gm/2πCE = IC/2πCEVT = 612 Hz
d) -12 Since fL2 > 4fL1, hence fL2 is the correct

.c
answer.
Answer: c
Explanation: AV = -120 8. Consider the circuit shown.

ul
fL = 1/2πCC(RC+RL) = 1/2π*0.001 = 1000/2π
= 159.15Hz
AV’ = |AV |

√1
+ (
fL
)
f
2

pa
AV’ = 120/8.02 ≈ 15.

6. Find the 3-dB frequency given that the gain

of RC coupled amplifier is 150, the low
frequency voltage gain is 100 and the input
frequency is 50Hz. hfe = 50, hie = 1000Ω. Find magnitude of
jin
a) 50.8 Hz voltage gain at input frequency 10Hz.
b) 55.9 Hz a) 100
c) 60Hz b) 133
d) 100Hz c) 166
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d) 220
Answer: b
Explanation: AVM = 150 Answer: b
AVL = 100 Explanation: Net load = 10k||10k = 5kΩ =
RL’
f = 50Hz
AVM = -hfeRL’/hie = -50×5/1 = -250
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100 = 150 fL 2
+ ( )
√1 50
fL = 1/2πCC(RC+RL) = 15.9 Hz
1+f2/2500 =1.52
AVL = AV M
+ (
fL 2
) = 133.
f2 = 2500*1.25 = 3125 √1 f
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f = 55.90 Hz.
9. What is the phase shift in RC coupled CE
7. Given collector resistance = 2kΩ, load amplifier at lower 3dB frequency?
resistance = 5kΩ, collector capacitance = 1μF, a) 180°
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emitter capacitance = 20μF, collector current b) 225°

= 2mA, source resistance = 2kΩ. If the effect c) 270°
of blocking capacitor is ignored, find the d) 100°
applicable cut-off frequency.

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Answer: b 20μA. Given base emitter dynamic resistance,

Explanation: Total phase shift = 180°+ tan- rbe = 1000 Ω, input VI is 20*sin(107t). What
1(f /f) is the short circuit current gain?
L
At 3dB frequency fL/f = 1 a) 30
Total phase shift = 180° + 45° = 225°. b) 35
c) 40

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10. Consider that the phase shift of an RC d) 100
coupled CE amplifier is 260°. Find the low
frequency gain when the voltage gain of the Answer: b
Explanation: AI = IL/IB
transistor is -150.
a) 100 IL = -gmVb’e
b) 26 Vb’e = Ib rb’e / (1+jωCrb’e)

.c
c) 40 C = CD + CT = 103pF
d) 55
Vb’e = 20μ.1k/(1+j.107.103.10-12.1000)
Answer: b AI = IL/IB = 50m.1k/(1+j.107.103.10-12.1000)

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Explanation: 180° + tan-1(fL/f) = 260° AI = 35 (approx).
fL/f = tan(80) = 5.67
A= 150
+ 5.672 = 26.05.
pa 3. Given that transition capacitance is 5 pico
F and diffusion capacitance is 80 pico F, and
√1

base emitter dynamic resistance is 1500 Ω,

TOPIC 4.7 HIGH FREQUENCY find the β cut-off frequency.
ANALYSIS OF CE AND MOSFET a) 7.8 x 106 rad/s
CS AMPLIFIER b) 8.0 x 106 rad/s
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c) 49.2 x 106 rad/s
1. We cannot use h-parameter model in high d) 22.7 x 106 rad/s
frequency analysis because ____________
a) They all can be ignored for high Answer: a
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frequencies Explanation: The frequency in radians is

b) Junction capacitances are not included in it calculated by
c) Junction capacitances have to be included ωβ = 1/C.rbe
in it ωβ = 7.8 x 106.
d) AC analysis is difficult for high frequency
using it
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4. For given BJT, β=200. The applied input

Answer: b frequency is 20 Mhz and net internal
Explanation: The effect of smaller capacitors capacitance is 100 pF. What is the CE short
circuit current gain at β cut-off frequency?
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is considerable in high frequency analysis of

analog circuits, and hence they cannot be a) 200
ignored as. Instead of h-parameter model, we b) 100
use π-model. c) 141.42
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d) 440.2
2. Consider a CE circuit, where trans-
Answer: c
conductance is 50mΩ-1, diffusion capacitance Explanation: The current gain for the CE
is 100 pF, transition capacitance is 3 pF. IB =

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circuit is A = β Answer: d
√1+(
f

f
β
2
) Explanation: At unity gain frequency the
β current gain is 1 is a correct statement. The
At f = fβ, A = same frequency is fT = βfβ which is the gain
√2

Hence A = 141.42. bandwidth product of BJT. Gain of BJT at

high frequency decreases due to the junction

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5. Given that β=200, input frequency is f= capacitance. However, at β cut-off frequency,
20Mhz and short circuit current gain is
current gain becomes β .
A=100. What is the unity gain frequency? √2

a) 2300 Mhz
b) 2000 Mhz 8. Given a MOSFET where gate to source
c) 2500 Mhz capacitance is 300 pF and gate to drain
d) 3000 Mhz capacitance is 500 pF. Calculate the gain

.c
bandwidth product if the transconductance is
Answer: a 30 mΩ-1.
β
Explanation: A = a) 5.98 Mhz
√ 1+(20M hz/f β)
2

b) 4.9 Mhz

ul
1+ (20/f)2 =4 c) 6.5Mhz
20/f = 1.732 d) 5.22Mhz
fβ = 11.54 Mhz pa
Unity gain frequency = βfβ = 200 x 11.54Mhz Answer: a
= 2308 Mhz. Explanation: Gain bandwidth product for
any MOSFET is fT = gm/2π(Cgs+Cgd)
6. Gain bandwidth frequency is GBP= 3000 Thus GBP is approximately 5.9 Mhz.
Mhz. The cut-off frequency is f=10Mhz.
9. In an RC coupled CE amplifier, when the
jin
What is the CE short circuit current gain at
the β cutoff frequency? input frequency increases, which of these are
a) 212 incorrect?
b) 220 a) Reactance CSH decreases
c) 300 b) Voltage gain increases
.re

d) 200 c) Voltage gain decreases due to shunt

capacitance
Answer: a d) An RC coupled amplifier behaves like a
Explanation: fT = 3000Mhz low pass filter
βfβ = 3000Mhz
Answer: b
w

β = 3000/10 = 300
β Explanation: When frequency increases,
A= √2
= 212.13. shunt reactance decreases. The voltage drop
across shunt capacitance decreases and net
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7. Which of the statement is incorrect? voltage gain decrease. RC coupled amplifier

a) At unity gain frequency the CE short acts as a low pass filter at high frequencies.
circuit current gain becomes 1
b) Unity gain frequency is the same as Gain
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Bandwidth Product of BJT TOPIC 4.8 TRANSISTOR

c) Gain of BJT decreases at higher SWITCHING TIMES
frequencies due to junction capacitances
d) β- cut-off frequency is one where the CE
short circuit current gain becomes β/2

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1. The collector current will not reach the 3. The technique used to quickly switch off a
steady state value instantaneously because transistor is by_________
of_________ a) reverse biasing its emitter to collector
a) stray capacitances junction
b) resistances b) reverse biasing its base to collector
c) input blocking capacitances junction

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d) coupling capacitance c) reverse biasing its base to emitter junction
d) reverse biasing any junction
Answer: a
Explanation: When a pulse is given, the Answer: c
collector current will not reach the steady Explanation: The technique used to quickly
state value instantaneously because of stray switch off a transistor is by reverse biasing its
capacitances. The charging and discharging base to collector junction. It is demonstrated

.c
of capacitance makes the current to reach a in a high voltage switching circuit. The
steady state value after a given time constant. advantage of this circuit is that it is not
necessary to have high voltage control signal.
2. For the BJT, β=∞, VBEon=0.7V

ul
VCEsat=0.7V. The switch is initially closed. 4. The disadvantage of using the method of
reverse biasing base emitter junction
At t=0, it is opened. At which time the BJT
is_________
leaves the active region? pa a) high voltage control signal
b) low voltage control signal
c) output swing
d) incomplete switching of output

Answer: d
jin
Explanation: This method is used to quickly
switch off a transistor is by reverse biasing its
base to collector junction. It is demonstrated
in a high voltage switching circuit. The
disadvantage of using the method of reverse
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biasing base emitter junction is that the output

does not switch completely to GND due to
a) 20ms forward voltage drop of the diode.
b) 50ms
c) 60ms 5. Which of the following circuits helps in the
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d) 70ms applications of switching times?

Answer: b
Explanation: At t < 0, the BJT is OFF in cut
w

off region. IB=0 as β=∞, so IC=IE. When t >

0, switch opens and BJT is ON. The voltage
across capacitor increases. From the input
w

loop, -5-VBE-I(4.3K)+10=0 and gives

I=1mA. IC1=1-0.5=0.5mA.
VC1=0.7+4.3+10=-5V. IC1=C1dVC1/dt. From
this equation, we get t=50ms.

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om
.c
ul
a)
c)

pa
jin
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b) d)
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Answer: b
Explanation: This is an inverter, in which the
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transistor in the circuit is switched between

cut off and saturation. The load, for example,
can be a motor or a light emitting diode or
any other electrical device.
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6. Which of the following helps in reducing

the switching time of a transistor?
a) a resistor connected from base to ground
b) a resistor connected from emitter to ground

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c) a capacitor connected from base to ground c) less than 0.7V

d) a capacitor connected from emitter to d) cannot be predicted
ground
Answer: c
Answer: a Explanation: From the cut off characteristics,
Explanation: Connecting a resistor connected the base emitter voltage (VBE) in a cut off

om
from base of a transistor to ground/negative region is less than 0.7V. The cut off region
voltage helps in reducing the switching the can be considered as ‘off mode’. Here, VBE <
switching time of the transistor. When 0.7 and IC=0. For a PNP transistor, the
transistor saturate, there is stored charge in
the base that must be removed before it turns emitter potential must be negative with
off. respect to the base.

.c
7. The time taken for a transistor to turn from 10. Switching speed of P+ junction depends
saturation to cut off is _________ on _________
a) inversely proportional to charge carriers a) Mobility of minority carriers in P junction
b) directly proportional to charge carriers b) Life time of minority carriers in P junction

ul
c) charging time of the capacitor c) Mobility of majority carriers in N junction
d) discharging time of the capacitor d) Life time of minority carriers in N junction

Answer: b Answer: d
pa
Explanation: When sufficient charge carriers
exist, the transistor goes into saturation.
Explanation: Switching leads to move holes
in P region to N region as minority carriers.
When the switch is turned off, in order to go Removal of this accumulation determines
into cut off, the charge carriers in the base switching speed. P+ regards to a diode in
region need to leave. The longer it takes to which the p type is doped excessively.
jin
leave, the longer it takes for a transistor to
turn from saturation to cut off.

8. The switching of power with a PNP

transistor is called _________ UNIT V POWER
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a) sourcing current SUPPLIES AND

b) sinking current
c) forward sourcing ELECTRONIC DEVICE
d) reverse sinking TESTING
w

Answer: a
Explanation: Sometimes DC current gain of TOPIC 5.1 LINEAR MODE
a bipolar transistor is too low to directly POWER SUPPLY
switch the load current or voltage, so multiple
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switching transistors is used. The load is

connected to ground and the transistor 1. What is done in switching regulators to
switches the power to it. minimize its power dissipation during
switching?
w

9. The base emitter voltage in a cut off region a) Uses external transistor
is _________ b) Uses 1mH choke
a) greater than 0.7V c) Uses external transistor and 1mH choke
b) equal to 0.7V d) None of the mentioned

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Answer: c 5. The switching regulators can operate in

Explanation: To minimize power dissipation a) Step up
during switching, the external transistor must b) Step down
be a switching power transistor and a 1mH c) Polarity inverting
choke smooth out the current pulses delivered d) All the mentioned
to the load.

om
Answer: d
2. Fixed voltage regulators and adjustable Explanation: The switching regulators can
regulators are often called as operate in any one of the three modes
a) Series dissipative regulators depending on the way in which the
b) Shunt dissipative regulators components are connected.
c) Stray dissipative regulators
d) All the mentioned 6. Find the diagrammatic representation of

.c
basic switching regulator?
Answer: a
Explanation: Series dissipative regulators
simulate a variable resistance between the

ul
input voltage & the load and hence functions
in a linear mode.

3. Linear series regulators are suited for

application with
a) High current
pa
b) Medium current Answer: a
c) Low current Explanation: Basic switching regulators
d) None of the mentioned consist of four major components;
jin
1) Voltage source
Answer: b 2) Switch
Explanation: In series dissipative regulator, 3) Pulse generator
conversion efficiency decreases as the input 4) Filters as mentioned in the diagram.
or output voltage differential increases and
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vice versa. So, linear series regulators are 7. What are the conditions to be satisfied by a
suited for medium current application with a voltage source for using it in switching
small voltage differential. regulator.
1. It must supply the required output power
4. A series switching regulators and the losses associated with the switching
regulator
w

a) Improves the efficiency of regulators

b) Improves the flexibility of switching 2. It must be large enough to supply sufficient
c) Enhance the response of regulators dynamic range line and load variations
d) All of the mentioned 3. It must be sufficient high to meet the
w

minimum requirement of the regulator system

Answer: a to be designed
Explanation: A series switching regulators is 4. It may be required to store energy for a
specified amount of time during power failure
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constructed such that, a series pass transistor

is used as a switch rather than as a variable especially if the system is designed for a
resistance in linear mode. computer power supply.
a) 1 and 3
b) 1,2,3 and 4

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c) 2,3 and 4 11. Which of the following is considered to

d) 1,3 and 4 be the most important components of the
switching regulator?
Answer: b a) RC or RLC filter
Explanation: A voltage source must satisfy b) RL or RLC filter
the entire given requirement to be used in c) ORC or RL filter

om
switching regulator. d) RC, RLC or RL filter
8. Which among the following act as a switch Answer: b
in switching regulator? Explanation: RL or RLC filter is the most
a) Rectifiers important components of the switching
b) Diode regulator, because there are several areas that
c) Transistors are affected by the choke of inductor

.c
d) Relays including energy storage for the regulators
output ripple, transient, response etc.
Answer: c
Explanation: A transistor is connected as 12. Which is the most commonly used low

ul
power switch and is operated in the saturated voltage switching regulators?
mode.Thus, the pulse generator output a) Powdered Permalloy toroids
alternatively turns the switch ON and OFF in b) Fermite EI, U and toroid cores
switching regulator.
pa
9. What should be the frequency range of
c) Silicon steel EI butt stacks
d) None of the mentioned

pulse generator? Answer: c

a) 250 kHz Explanation: The silicon steel EI butt stack
b) 40 kHz exhibits high permeability high flux density
jin
c) 120 kHz and ease of construction and mounting
d) 20 kHz therefore, it is most commonly used in low
voltage switching regulators.
Answer: d
Explanation: The most effective frequency 13. Find the value of Rsc, L and Co for a
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range for pulse generator for optimum µA7840 switching regulator to provide +5 v
efficiency and component size is 20kHz. at 3A, using the following specifications:
toff= 24µs, ripple voltage = 400mA and
10. Filter used in switching regulator’s are
also as called ton=26µs.
a) Rsc = 55 mΩ , L = 25µH & Co = 750µF
w

a) DC – AC transformers
b) AC – DC transformers b) Rsc = 550 mΩ , L = 25µH & Co = 75µF
c) DC transformer c) Rsc = 650 mΩ , L = 25µH & Co = 65µF
d) AC transformer
w

d) Rsc = 720 mΩ , L = 25µH & Co = 250µF

Answer: c
Explanation: Filter converts the pulse Answer: a
Explanation: Peak current,Ipk= 400mA× 1.5
w

waveform from the output of the switch into a

dc voltage. Since this switching mechanism (since Ipk = 1.5 A for peak current)
allows a conversion similar to transformers, ∴ Rsc = 0.33ohm/Ipk = 0.33ohm/6 =
the switching regulators is often referred to as 0.055ohm.
a DC transformer. => L= [(Vo +Vp) / I pk]×toff =[(5+1.25) /6 ]×

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24×10-6 =25µH. a) 1- iii , 2- i , 3- ii

=> Co = [Ipk (Ton +Toff)]/[8×Vripple] ∵T = b) 1- i , 2- ii , 3- iii
c) 1- iii , 2- ii , 3- i
[ton + toff] = 26µs + 24µs = 50µs
d) 1- iii , 2- ii , 3- i
=> Co = [ (6×50µs)]/(8×50mA) = 7.5×10-4 =
750µF. Answer: b

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Explanation: Characteristics and design
14. Calculate the efficiency of the step down formula for step up, step down and converting
switching regulator given the input voltage mode of switching regulator.
Vin= 13.5v and output voltage =6v. Assume
the saturating Voltage Vs=1.1v and the TOPIC 5.2 RECTIFIERS -
forward voltage drop Vd = 1.257v FILTERS - HALF-WAVE

.c
a) η = 75% RECTIFIER POWER SUPPLY
b) η = 48.5%
c) η = 63.9%
1. The diode in a half wave rectifier has a
d) η = 80.5%

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forward resistance RF. The voltage is
Answer: d Vmsinωt and the load resistance is RL. The
Explanation: Efficiency of the step down DC current is given by _________
switching regulator, η = {[(Vin-Vs+Vd)]/ a) Vm/√2RL
[Vin]}×(Vo) / [(Vo+Vd)] = {[(13.5v-
pa
1.1v+1.257v)/13.5v]} ×[(6/(6 ×1.257)] =>
b) Vm/(RF+RL)π
c) 2Vm/√π
Efficiency of switching regulator, η = d) Vm/RL
(1.012×0.7955)×100 = 0.8051×100 = 80.5%.
jin
Answer: b
15. Match the characteristics for various Explanation: For a half wave rectifier, the
switching regulators. IDC=IAVG=Im/π
I= Vmsinωt/(RF+RL)=Imsinωt
Switching
Characteristics Im =Vm/ RF+RL So, IDC=Im/π=Vm/(RF+RL).
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regulator
(i) [ton / toff ] = [ Vo
2. The below figure arrives to a conclusion
1. + Vd] / [Vin -Vs - that _________
Inverting Vd]; Rsc = ( 0.33/
Ipk)
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(ii) [ton / toff ] = [

2. step Vo + Vd -Vin] /
down [Vin-Vs] ; Rsc = (
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0.33/ Ipk)
(iii) [ton / toff ] = [
w

Modulus Vo +Vd] / a) for Vi > 0, V0=-(R2/R1)Vi

3. step up
(Vin-Vs); Rsc = ( b) for Vi > 0, V0=0
0.33/ Ipk c) Vi < 0, V0=-(R2/R1)Vi
d) Vi < 0, V0=0

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Answer: b information with this equation, Vm =50.

Explanation: The given op-amp is in
Power=Vm2/RL=50*50/1000=2.5V.
inverting mode and this makes the output
voltage to have a phase shift of 180°. The
output voltage is now negative. So, the diode 5. In a half wave rectifier, the sine wave input
is 200sin300t. The average value of output
1 is reverse biased and diode 2 is forward
voltage is?

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biased. Then output is clearly zero.
a) 57.876V
3. What is the output as a function of the b) 67.453V
input voltage (for positive values) for the c) 63.694V
given figure. Assume it’s an ideal op-amp d) 76.987V
with zero forward drop (Di=0)
Answer: c

.c
Explanation: Comparing with the standard
equation, Vm=200V.
Average value is given by, Vavg=Vm/π.
So, 200/π=63.694.

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6. Efficiency of a half wave rectifier is
pa a) 50%
b) 60%
c) 40.6%
a) 0 d) 46%
b) -Vi
c) Vi Answer: c
Explanation: Efficiency of a rectifier is the
jin
d) 2Vi
effectiveness to convert AC to DC. For half
wave it’s 40.6%. It’s given by, Vout/Vin*100.
Answer: c
Explanation: When the input of the inverted
7. If peak voltage for a half wave rectifier
mode op-amp is positive, the output is
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circuit is 5V and diode cut in voltage is 0.7,

negative.
then peak inverse voltage on diode will be?
The diode is reverse biased. The input a) 5V
appears at the output. b) 4.9V
4. In a half wave rectifier, the sine wave input c) 4.3V
d) 6.7V
is 50sin50t. If the load resistance is of 1K,
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then average DC power output will be? Answer: c

a) 3.99V Explanation: PIV is the maximum reverse
b) 2.5V
bias voltage that can be appeared across a
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c) 5.97V
diode in the given circuit, If the PIV rating is
d) 6.77V
less than this value of breakdown of diode
Answer: b will occur. For a rectifier, PIV=Vm-Vd=5-
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Explanation: The standard form of a sine 0.7=4.3V.

wave is Vmsinωt. BY comparing the given
8. Transformer utilisation factor of a half
wave rectifier is _________
a) 0.234

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b) 0.279 1. Efficiency of a centre tapped full wave

c) 0.287 rectifier is _________
d) 0.453 a) 50%
b) 46%
Answer: c c) 70%
Explanation: Transformer utilisation factor is d) 81.2%

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the ratio of AC power delivered to load to the
DC power rating. This factor indicates Answer: d
effectiveness of transformer usage by Explanation: Efficiency of a rectifier is the
rectifier. For a half wave rectifier, it’s low and effectiveness to convert AC to DC. It’s
equal to 0.287. obtained by taking ratio of DC power output
to maximum AC power delivered to load. It’s
9. If the input frequency of a half wave usually expressed in percentage. For centre

.c
rectifier is 100Hz, then the ripple frequency tapped full wave rectifier, it’s 81.2%.
will be_________
a) 150Hz 2. A full wave rectifier supplies a load of
b) 200Hz 1KΩ. The AC voltage applied to diodes is

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c) 100Hz 220V (rms). If diode resistance is neglected,
d) 300Hz what is the ripple voltage?
a) 0.562V
Answer: c
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Explanation: The ripple frequency of the
output and input is same. This is because, one
b) 0.785V
c) 0.954V
d) 0.344V
half cycle of input is passed and other half
cycle is seized. So, effectively the frequency Answer: c
is the same. Explanation: The ripple voltage is
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(Vϒ)RMS=ϒVDC /100.
10. Ripple factor of a half wave rectifier VDC=0.636*VRMS* √2=0.636*220*
is_________(Im is the peak current and RL is
√2=198V and ripple factor ϒ for full wave
load resistance) rectifier is 0.482.
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a) 1.414 Hence, (Vϒ)RMS=0.482*198 /100=0.954V.

b) 1.21
c) 1.4
3. A full wave rectifier delivers 50W to a load
d) 0.48 of 200Ω. If the ripple factor is 2%, calculate
the AC ripple across the load.
Answer: b
a) 2V
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Explanation: The ripple factor of a rectifier

b) 5V
is the measure of disturbances produced in
c) 4V
the output. It’s the effectiveness of a power
d) 1V
supply filter to reduce the ripple voltage. The
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ratio of ripple voltage to DC output voltage is Answer: a

ripple factor which is 1.21.
Explanation: We know that, PDC=VDC2/RL.
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TOPIC 5.3 FULL-WAVE So, VDC=(PDC*RL)1/2=100001/2=100V.

RECTIFIER POWER SUPPLY Here, ϒ=0.02
ϒ=VAC/VDC=VAC/100.So,
VAC=0.02*100=2V.

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4. A full wave rectifier uses load resistor of 6. If input frequency is 50Hz for a full wave
1500Ω. Assume the diodes have Rf=10Ω, rectifier, the ripple frequency of it would be
Rr=∞. The voltage applied to diode is 30V _________
a) 100Hz
with a frequency of 50Hz. Calculate the AC
b) 50Hz
power input.
c) 25Hz
a) 368.98mW

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d) 500Hz
b) 275.2mW
c) 145.76mW Answer: a
d) 456.78mW Explanation: In the output of the centre
tapped rectifier, one of the half cycle is
Answer: b
Explanation: The AC power input repeated. The frequency will be twice as that
of input frequency. So, it’s 100Hz.

.c
PIN=IRMS2(RF+Rr).
IRMS=Im/ 7. Transformer utilization factor of a centre
√2=Vm/(Rf+RL)√2=30/(1500+10)*1.414=13.5mA tapped full wave rectifier is_________
So, PIN=(13.5*10-3)2*(1500+10)=275.2mW. a) 0.623

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b) 0.678
c) 0.693
5. In a centre tapped full wave rectifier,
d) 0.625
RL=1KΩ and for diode Rf=10Ω. The primary
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voltage is 800sinωt with transformer turns
ratio=2. The ripple factor will be _________
Answer: c
Explanation: Transformer utilisation factor is
the ratio of AC power delivered to load to the
DC power rating. This factor indicates
effectiveness of transformer usage by
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rectifier. For a half wave rectifier, it’s low and
equal to 0.693.

8. In the circuits given below, the correct full

wave rectifier is _________
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a) 54%
b) 48%
c) 26%
d) 81%

Answer: b
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Explanation: The ripple factor ϒ=

[(IRMS/IAVG)2 – 1]1/2. IRMS =Im /
√2=Vm/(Rf+RL)√2=200/1.01=198.
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(Secondary line to line voltage is 800/2=400.

Due to centre tap Vm=400/2=200)
a)
IRMS=198/√2=140mA, IAVG=2*198/
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π=126mA. ϒ=[(140/126)2-1]1/2=0.48. So,

ϒ=48%.

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9. If the peak voltage on a centre tapped full

wave rectifier circuit is 5V and diode cut in
voltage is 0.7. The peak inverse voltage on
diode is_________
a) 4.3V
b) 9.3V

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c) 5.7V
d) 10.7V

Answer: b
Explanation: PIV is the maximum reverse
bias voltage that can be appeared across a
b)
diode in the given circuit, if PIV rating is less

.c
than this value of breakdown of diode will
occur. For a rectifier, PIV=2Vm-Vd = 10-0.7
= 9.3V.

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10. In a centre tapped full wave rectifier, the
input sine wave is 250sin100t. The output
pa ripple frequency will be _________
a) 50Hz
b) 100Hz
c) 25Hz
d) 200Hz
c)
Answer: b
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Explanation: The equation of sine wave is in
the form Vmsinωt. So, by comparing we get
ω=100. Frequency, f =ω/2=50Hz. The output
of centre tapped full wave rectifier has double
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the frequency of inpu. Hence, fout = 100Hz.

TOPIC 5.4 VOLTAGE

REGULATORS: VOLTAGE
REGULATION - LINEAR
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SERIES SHUNT AND

d) SWITCHING VOLTAGE
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Answer: c REGULATORS
Explanation: When the input is applied, a
full wave rectifier should have a current flow. 1. What is done in switching regulators to
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The flow should be in the same direction for minimize its power dissipation during
both positive and negative half cycles. Only switching?
the third circuit satisfies the above condition. a) Uses external transistor
b) Uses 1mH choke

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c) Uses external transistor and 1mH choke is used as a switch rather than as a variable
d) None of the mentioned resistance in linear mode.

Answer: c 5. The switching regulators can operate in

Explanation: To minimize power dissipation a) Step up
during switching, the external transistor must b) Step down

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be a switching power transistor and a 1mH c) Polarity inverting
choke smooth out the current pulses delivered d) All the mentioned
to the load.
Answer: d
2. Fixed voltage regulators and adjustable Explanation: The switching regulators can
regulators are often called as operate in any one of the three modes
a) Series dissipative regulators depending on the way in which the

.c
b) Shunt dissipative regulators components are connected.
c) Stray dissipative regulators
d) All the mentioned 6. Find the diagrammatic representation of
basic switching regulator?

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Answer: a
Explanation: Series dissipative regulators
simulate a variable resistance between the
input voltage & the load and hence functions
in a linear mode.
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3. Linear series regulators are suited for
application with
a) High current
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b) Medium current Answer: a
c) Low current Explanation: Basic switching regulators
d) None of the mentioned consist of four major components;
1) Voltage source
Answer: b 2) Switch
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Explanation: In series dissipative regulator, 3) Pulse generator

conversion efficiency decreases as the input 4) Filters as mentioned in the diagram.
or output voltage differential increases and
vice versa. So, linear series regulators are 7. What are the conditions to be satisfied by a
suited for medium current application with a voltage source for using it in switching
regulator.
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small voltage differential.

1. It must supply the required output power
4. A series switching regulators and the losses associated with the switching
a) Improves the efficiency of regulators regulator
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b) Improves the flexibility of switching 2. It must be large enough to supply sufficient

c) Enhance the response of regulators dynamic range line and load variations
d) All of the mentioned 3. It must be sufficient high to meet the
minimum requirement of the regulator system
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Answer: a to be designed
Explanation: A series switching regulators is 4. It may be required to store energy for a
constructed such that, a series pass transistor specified amount of time during power failure
especially if the system is designed for a

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computer power supply. allows a conversion similar to transformers,

a) 1 and 3 the switching regulators is often referred to as
b) 1,2,3 and 4 a DC transformer.
c) 2,3 and 4
d) 1,3 and 4 11. Which of the following is considered to
be the most important components of the

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Answer: b switching regulator?
Explanation: A voltage source must satisfy a) RC or RLC filter
the entire given requirement to be used in b) RL or RLC filter
switching regulator. c) ORC or RL filter
d) RC, RLC or RL filter
8. Which among the following act as a switch
in switching regulator? Answer: b

.c
a) Rectifiers Explanation: RL or RLC filter is the most
b) Diode important components of the switching
c) Transistors regulator, because there are several areas that
d) Relays are affected by the choke of inductor

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including energy storage for the regulators
Answer: c output ripple, transient, response etc.
Explanation: A transistor is connected as
power switch and is operated in the saturated 12. Which is the most commonly used low
pa
mode.Thus, the pulse generator output
alternatively turns the switch ON and OFF in
voltage switching regulators?
a) Powdered Permalloy toroids
switching regulator. b) Fermite EI, U and toroid cores
c) Silicon steel EI butt stacks
9. What should be the frequency range of d) None of the mentioned
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pulse generator?
a) 250 kHz Answer: c
b) 40 kHz Explanation: The silicon steel EI butt stack
c) 120 kHz exhibits high permeability high flux density
d) 20 kHz and ease of construction and mounting
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therefore, it is most commonly used in low

Answer: d voltage switching regulators.
Explanation: The most effective frequency
range for pulse generator for optimum 13. Find the value of Rsc, L and Co for a
efficiency and component size is 20kHz. µA7840 switching regulator to provide +5 v
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at 3A, using the following specifications:

10. Filter used in switching regulator’s are toff= 24µs, ripple voltage = 400mA and
also as called
ton=26µs.
a) DC – AC transformers
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b) AC – DC transformers a) Rsc = 55 mΩ , L = 25µH & Co = 750µF

c) DC transformer b) Rsc = 550 mΩ , L = 25µH & Co = 75µF
d) AC transformer c) Rsc = 650 mΩ , L = 25µH & Co = 65µF
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Answer: c d) Rsc = 720 mΩ , L = 25µH & Co = 250µF

Explanation: Filter converts the pulse
waveform from the output of the switch into a Answer: a
dc voltage. Since this switching mechanism Explanation: Peak current,Ipk= 400mA× 1.5

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(since Ipk = 1.5 A for peak current) Modulus Vo +Vd] /

∴ Rsc = 0.33ohm/Ipk = 0.33ohm/6 = (Vin-Vs); Rsc = (
0.055ohm. 0.33/ Ipk
=> L= [(Vo +Vp) / I pk]×toff =[(5+1.25) /6 ]×
24×10-6 =25µH. a) 1- iii , 2- i , 3- ii

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=> Co = [Ipk (Ton +Toff)]/[8×Vripple] ∵T = b) 1- i , 2- ii , 3- iii
[ton + toff] = 26µs + 24µs = 50µs c) 1- iii , 2- ii , 3- i
d) 1- iii , 2- ii , 3- i
=> Co = [ (6×50µs)]/(8×50mA) = 7.5×10-4 =
750µF. Answer: b
Explanation: Characteristics and design
14. Calculate the efficiency of the step down formula for step up, step down and converting

.c
switching regulator given the input voltage mode of switching regulator.
Vin= 13.5v and output voltage =6v. Assume
the saturating Voltage Vs=1.1v and the TOPIC 5.5 OVER VOLTAGE

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forward voltage drop Vd = 1.257v PROTECTION - BJT AND
a) η = 75% MOSFET
b) η = 48.5%
c) η = 63.9%
d) η = 80.5%
pa 1. The MOSFET combines the areas of
_______ & _________
a) field effect & MOS technology
Answer: d
Explanation: Efficiency of the step down b) semiconductor & TTL
switching regulator, η = {[(Vin-Vs+Vd)]/ c) mos technology & CMOS technology
d) none of the mentioned
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[Vin]}×(Vo) / [(Vo+Vd)] = {[(13.5v-
1.1v+1.257v)/13.5v]} ×[(6/(6 ×1.257)] => Answer: a
Efficiency of switching regulator, η = Explanation: It is an enhancement of the
(1.012×0.7955)×100 = 0.8051×100 = 80.5%. FET devices (field effect) using MOS
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technology.
15. Match the characteristics for various
switching regulators. 2. Which of the following terminals does not
belong to the MOSFET?
Switching a) Drain
Characteristics
regulator b) Gate
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(i) [ton / toff ] = [ Vo c) Base

+ Vd] / [Vin -Vs - d) Source
1.
Inverting Vd]; Rsc = ( 0.33/ Answer: c
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Ipk) Explanation: MOSFET is a three terminal

(ii) [ton / toff ] = [ device D, G & S.
Vo + Vd -Vin] /
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2. step 3. Choose the correct statement

down [Vin-Vs] ; Rsc = ( a) MOSFET is a uncontrolled device
0.33/ Ipk) b) MOSFET is a voltage controlled device
c) MOSFET is a current controlled device
3. step up (iii) [ton / toff ] = [

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d) MOSFET is a temperature controlled Answer: b

device Explanation: The arrow is to indicate the
direction of electrons (opposite to the
Answer: b direction of conventional current flow).
Explanation: It is a voltage controlled
device. 7. The controlling parameter in MOSFET is

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a) Vds
4. Choose the correct statement(s) b) Ig
i) The gate circuit impedance of MOSFET is c) Vgs
higher than that of a BJT d) Is
ii) The gate circuit impedance of MOSFET is
lower than that of a BJT Answer: b
iii) The MOSFET has higher switching losses Explanation: The gate to source voltage is

.c
than that of a BJT the controlling parameter in a MOSFET.
iv) The MOSFET has lower switching losses
than that of a BJT 8. In the internal structure of a MOSFET, a
a) Both i & ii parasitic BJT exists between the

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b) Both ii & iv a) source & gate terminals
c) Both i & iv b) source & drain terminals
d) Only ii c) drain & gate terminals
d) there is no parasitic BJT in MOSFET
Answer: c
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Explanation: MOSFET requires gate signals Answer: b
with lower amplitude as compared to BJTs & Explanation: Examine the internal structure
has lower switching losses. of a MOSFET, notice the n-p-n structure
between the drain & source. A p-channel
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5. Choose the correct statement MOSFET will have a p-n-p structure.
a) MOSFET is a unipolar, voltage controlled,
two terminal device 9. In the transfer characteristics of a
b) MOSFET is a bipolar, current controlled, MOSFET, the threshold voltage is the
three terminal device measure of the
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c) MOSFET is a unipolar, voltage controlled, a) minimum voltage to induce a n-channel/p-

three terminal device channel for conduction
d) MOSFET is a bipolar, current controlled, b) minimum voltage till which temperature is
two terminal device constant
c) minimum voltage to turn off the device
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Answer: c d) none of the above mentioned is true

Explanation: MOSFET is a three terminal
device, Gate, source & drain. It is voltage Answer: a
controlled unlike the BJT & only electron Explanation: It is the minimum voltage to
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current flows. induce a n-channel/p-channel which will

allow the device to conduct electrically
6. The arrow on the symbol of MOSFET through its length.
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indicates
a) that it is a N-channel MOSFET 10.The output characteristics of a MOSFET,
b) the direction of electrons is a plot of
c) the direction of conventional current flow a) Id as a function of Vgs with Vds as a
d) that it is a P-channel MOSFET parameter

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b) Id as a function of Vds with Vgs as a Answer: c

parameter Explanation: SMPS has higher output ripple
c) Ig as a function of Vgs with Vds as a and its regulation is worse.
parameter
d) Ig as a function of Vds with Vgs as a 4. _________ is used for critical loads where
parameter temporary power failure can cause a great

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deal of inconvenience.
Answer: b a) SMPS
Explanation: It is Id vs Vds which are plotted b) UPS
for different values of Vgs (gate to source c) MPS
voltage). d) RCCB

Answer: b

.c
TOPIC 5.6 SWITCHED MODE Explanation: Uninterruptible Power Supply
POWER SUPPLY (SMPS) is used where loads where temporary power
failure can cause a great deal of
1. SMPS is used for inconvenience.

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a) obtaining controlled ac power supply
b) obtaining controlled dc power supply 5. __________ is used in the rotating type
c) storage of dc power UPS system to supply the mains.
a) DC motor

Answer: b
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d) switch from one source to another
b) Self excited DC generator
c) Alternator
Explanation: SMPS (Switching mode power d) Battery bank
supply) is used for obtaining controlled dc
power supply. Answer: c
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Explanation: When the supply is gone, the
2. SPMS are based on the ________ diesel engine is started, which runs the
principle. alternator and the alternator supplies power to
a) Phase control the mains. Non-rotating type UPS are not
b) Integral control used anymore.
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c) Chopper
d) MOSFET 6. Static UPS requires __________
a) only rectifier
Answer: c b) only inverter
Explanation: SMPS (Switching mode power c) both inverter and rectifier
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supply) are based on the chopper principle. d) none of the mentioned

The output dc voltage is controlled by
varying the duty cycle of the chopper circuit. Answer: c
Explanation: Rectifier to converter the dc
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3. Choose the incorrect statement. from the battery to ac. Inverter to charge the
a) SMPS is less sensitive to input voltage battery from mains.
variations
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b) SMPS is smaller as compared to rectifiers 7. No discontinuity is observed in case of

c) SMPS has low input ripple a) short break static UPS configuration
d) SMPS is a source of radio interference b) long break static UPS configuration
c) no break static UPS configuration
d) rotating type UPS configuration

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Answer: c 1. Which of the following can be a source of

Explanation: No dip or discontinuity is supply in dc power supplies?
observed in case of no break static UPS a) Battery
configuration, as the battery inverter set b) Dry cell
immediately takes over the mains. c) Full wave rectifier
d) All of the mentioned

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8. Usually __________ batteries are used in
the UPS systems. Answer: d
a) NC Explanation: Source of supply will be a
b) Li-On battery, dry cell or full wave rectifier etc.
c) Lead acid
d) All of the mentioned 2. Which of the application’s filters used for?
a) Reducing ripples

.c
Answer: c b) Increasing ripples
Explanation: Lead acid batteries are cheaper c) Increasing phase change
and have certain advantages over the other d) Increasing amplitude
types. NC batteries would however be the

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best, but are three to four times more Answer: a
expensive than Lead Acid. Explanation: Ripples are ac components and
filters are used for eliminating ac components
9. HVDC transmission has ___________ as from a signal.
compared to HVAC transmission.
a) smaller transformer size
pa 3. Which of the following represent a change
b) smaller conductor size of output voltage when load current is
c) higher corona loss increased?
d) smaller power transfer capabilities a) Line regulation
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b) Load regulation
Answer: b c) Current regulation
Explanation: The conductor size is smaller as d) Voltage regulation
there is no sink effect, and the whole
conductor is utilized for transmitting power. Answer: b
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Explanation: Load regulation is the process

10. The negative polarity is used in the of fractional change of output voltage when
monopolar link because it load current is increased from zero to
a) uses less conductor size maximum value.
b) is safer
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c) produces less radio interference 4. Which of the following generate output

d) has less resistance voltage much closer to true value?
a) True generator
Answer: c b) Precision generator
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Explanation: The monopolar link uses just a c) Output generator

single conductor, which is usually negative as d) Accurate generator
it produces less radio interference and corona.
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Answer: b
Explanation: Precision generators are one
TOPIC 5.8 DESIGN OF which generates output voltage much closer
REGULATED DC POWER to the true value.
SUPPLY

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5. Why zener diodes are provided in dc 8. For instrumentation system, precision

supply? variable voltage-reference system is
a) For forward conduction necessary.
b) For reverse conduction a) True
c) For reference voltage b) False
d) For increasing amplitude

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Answer: a
Answer: c Explanation: Precision variable voltage
Explanation: Zener diodes in dc power reference system is used for comparing
supplies are used for providing a reference voltage with a reference voltage and can be
voltage used for comparison. used in the instrumentation system.

6. Stability of output voltage is entirely 9. Which of the following can be used as a

.c
depended on ______________ comparator?
a) Stability of transformer a) Zener diode
b) Stability of zener diode b) Diode
c) Quality of wires c) Operational amplifier

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d) Capacitor values d) All of the mentioned

Answer: b Answer: c
Explanation: Stability of zener diodes used is Explanation: Operational amplifier can be
pa
an important factor in determining the
stability of output voltage in dc power supply.
used as a comparator circuit.

10. Which of the following are not the

7. For excellent stability, the zener diode is standard value of Zener diodes?
kept in temperature controlled casket. a) 5.1 V
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a) True b) 5.6 V
b) False c) 5.8V
d) 6.2V
Answer: a
Explanation: Zener diode is kept on Answer: c
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temperature controlled casket due to its low Explanation: Standard values of zener
temperature coefficient which may lead to voltages are 5.1V, 5.6V, 6.2V and 9.1V etc.
less stability.
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