www.rejinpaul.

com

processor is faster?
a) A
EC8552 b) B
c) Both take the same time
COMPUTER d) Insufficient information

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ARCHITECTURE Answer: a
Explanation: The performance of a system
AND can be found out using the Basic performance
formula.
ORGANIZATION 3. A processor performing fetch or decoding
of different instruction during the execution

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of another instruction is called ______
a) Super-scaling
b) Pipe-lining
UNIT I COMPUTER

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c) Parallel Computation
d) None of the mentioned
ORGANIZATION &
INSTRUCTIONS pa Answer: b
Explanation: Pipe-lining is the process of
improving the performance of the system by
TOPIC 1.1 BASICS OF A processing different instructions at the same
COMPUTER SYSTEM: time, with only one instruction performing
EVOLUTION, IDEAS, one specific operation.
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TECHNOLOGY, 4. For a given FINITE number of instructions
PERFORMANCE, POWER to be executed, which architecture of the
WALL processor provides for a faster execution?
a) ISA
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1. During the execution of the instructions, a b) ANSA

copy of the instructions is placed in the c) Super-scalar
______ d) All of the mentioned
a) Register
b) RAM Answer: c
c) System heap Explanation: In super-scalar architecture, the
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d) Cache instructions are set in groups and they’re

decoded and executed together reducing the
Answer: d amount of time required to process them.
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Explanation: None.
5. The clock rate of the processor can be
2. Two processors A and B have clock improved by _________
frequencies of 700 Mhz and 900 Mhz a) Improving the IC technology of the logic
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respectively. Suppose A can execute an circuits

instruction with an average of 3 steps and B b) Reducing the amount of processing done in
can execute with an average of 5 steps. For one step
the execution of the same instruction which c) By using the overclocking method
d) All of the mentioned

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Answer: d b) SUN SPARC

Explanation: The clock rate(frequency of the c) SUN II
processor) is the hardware dependent quantity d) None of the mentioned
it is fixed for a given processor.
Answer: a
6. An optimizing Compiler does _________ Explanation: In SPEC system of measuring a

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a) Better compilation of the given piece of system’s performance, a system is used as a
code reference against which other systems are
b) Takes advantage of the type of processor compared and performance is determined.
and reduces its process time
c) Does better memory management 10. When Performing a looping operation, the
d) None of the mentioned instruction gets stored in the ______
a) Registers

.c
Answer: b b) Cache
Explanation: An optimizing compiler is a c) System Heap
compiler designed for the specific purpose of d) System stack
increasing the operation speed of the

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processor by reducing the time taken to Answer: b
compile the program instructions. Explanation: When a looping or branching
operation is carried out the offset value is
7. The ultimate goal of a compiler is to stored in the cache along with the data.
________
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a) Reduce the clock cycles for a programming 11. The average number of steps taken to
task execute the set of instructions can be made to
b) Reduce the size of the object code be less than one by following _______
c) Be versatile a) ISA
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d) Be able to detect even the smallest of b) Pipe-lining
errors c) Super-scaling
d) Sequential
Answer: a
Explanation: None. Answer: c
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Explanation: The number of steps required to

8. SPEC stands for _______ execute a given set of instructions is
a) Standard Performance Evaluation Code sufficiently reduced by using super-scaling.
b) System Processing Enhancing Code In this method, a set of instructions are
c) System Performance Evaluation grouped together and are processed.
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Corporation
d) Standard Processing Enhancement 12. If a processor clock is rated as 1250
Corporation million cycles per second, then its clock
period is ________
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Answer: c a) 1.9 * 10-10 sec

Explanation: SPEC is a corporation that b) 1.6 * 10-9 sec
started to standardize the evaluation method
c) 1.25 * 10-10 sec
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of a system’s performance.
d) 8 * 10-10 sec
9. As of 2000, the reference system to find
the performance of a system is _____ Answer: d
a) Ultra SPARC 10 Explanation: None.

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13. If the instruction, Add R1, R2, R3 is Answer: d

executed in a system that is pipe-lined, then Explanation: The microprocessors or
the value of S is (Where S is a term of the processing unit is used as a node in
Basic performance equation)? interconnection topologies. They may also
a) 3 work as stand-alone processors or
b) ~2 subprocessing units, under the control of

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c) ~1 other microprocessors or processing units.
d) 6
2. The feature of the multi-microprocessor
Answer: c architecture is
Explanation: S is the number of steps a) task dependent
required to execute the instructions. b) single bus provider for many processors
c) design is for a specific task

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14. CISC stands for _______ d) all of the mentioned
a) Complete Instruction Sequential
Compilation Answer: d
b) Computer Integrated Sequential Compiler Explanation: The main feature of multi-

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c) Complex Instruction Set Computer microprocessor is that it is task dependent. If
d) Complex Instruction Sequential it is designed for a specific task, then it may
Compilation pa not be useful for other tasks.

Answer: c 3. The main objective in building the multi-

Explanation: CISC is a type of system microprocessor is
architecture where complex instructions are a) greater throughput
grouped together and executed to improve b) enhanced fault tolerance
system performance. c) greater throughput and enhanced fault
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tolerance
15. As of 2000, the reference system to find d) none of the mentioned
the SPEC rating are built with _____
Processor. Answer: c
a) Intel Atom SParc 300Mhz Explanation: Greater throughput and
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b) Ultra SPARC -IIi 300MHZ enhanced fault tolerance are the main
c) Amd Neutrino series objectives of the multi-microprocessor
d) ASUS A series 450 Mhz system. These systems incorporate a
multiplicity of hardware and software, for the
Answer: b purpose.
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Explanation: None.
4. An interface between the user or an
application program, and the system
TOPIC 1.2 UNIPROCESSORS TO resources are
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MULTIPROCESSORS a) microprocessor
b) microcontroller
1. The interconnection topologies are c) multi-microprocessor
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implemented using _________ as a node. d) operating system

a) control unit
b) microprocessor Answer: d
c) processing unit Explanation: The operating system acts as an
d) microprocessor or processing unit

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interface, and is an important program that b) optimize the system performance

resides in the computer memory. c) handling structural or architectural changes
d) all of the mentioned
5. An operating system provides
a) hardware and software resource Answer: d
management Explanation: A multiprocessor operating

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b) input/output management system should have a mechanism to split a
c) memory management task, optimise system performance, and
d) all of the mentioned should handle structural changes.

Answer: d 9. An operating system must possess

Explanation: An operating system provides a a) process-processor allocation strategies
means of hardware and software resource b) mechanism to collect results of subtasks

.c
management including input/output and c) software to improve overall performance
memory management. d) all of the mentioned

6. Distributed systems are designed to run Answer: d

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a) serial process Explanation: An operating system must have
b) parallel process process-processor allocation strategies, a
c) serial and parallel process mechanism to collect results of subtasks and
d) none of the mentioned software to improve overall performance.

Answer: d
pa 10. A multiprocessor operating system must
Explanation: Distributed systems are take care of
designed to run a parallel process. It is a) authorized data access and data protection
essential that a proper environment exists for b) unauthorized data access and data
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concurrent processes to communicate and protection
cooperate, in order to complete the allotted c) authorized data access
task. d) data protection

7. A distributed operating system must Answer: b

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provide a mechanism for Explanation: A multiprocessor operating

a) intraprocessor communication system must take care of unauthorized data
b) intraprocess and intraprocessor access and data protection.
communication
c) interprocess and interprocessor
TOPIC 1.3 ADDRESSING AND
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communication
d) interprocessor communication ADDRESSING MODES

Answer: c 1. The instruction, Add #45,R1 does _______

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Explanation: A distributed operating system a) Adds the value of 45 to the address of R1

must provide a mechanism for interprocess and stores 45 in that address
and interprocessor communication. b) Adds 45 to the value of R1 and stores it in
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R1
8. A multiprocessor operating system should c) Finds the memory location 45 and adds
perform that content to that of R1
a) a mechanism to split a task into concurrent d) None of the mentioned
subtasks

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Answer: b c) EA = [R1]
Explanation: The instruction is using d) EA = 5+[R1]
immediate addressing mode hence the value
is stored in the location 45 is added. Answer: d
Explanation: This instruction is in Base with
2. In the case of, Zero-address instruction offset addressing mode.

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method the operands are stored in _____
a) Registers 6. The addressing mode/s, which uses the PC
b) Accumulators instead of a general purpose register is
c) Push down stack ______
d) Cache a) Indexed with offset
b) Relative
Answer: c c) Direct

.c
Explanation: In this case, the operands are d) Both Indexed with offset and direct
implicitly loaded onto the ALU.
Answer: b
3. Add #45, when this instruction is executed Explanation: In this, the contents of the PC

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the following happen/s _______ are directly incremented.
a) The processor raises an error and requests
for one more operand 7. When we use auto increment or auto
b) The value stored in memory location 45 is decrements, which of the following is/are
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retrieved and one more operand is requested
c) The value 45 gets added to the value on the
true?
1) In both, the address is used to retrieve the
stack and is pushed onto the stack operand and then the address gets altered
d) None of the mentioned 2) In auto increment, the operand is retrieved
first and then the address altered
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Answer: b 3) Both of them can be used on general
Explanation: None. purpose registers as well as memory locations
a) 1, 2, 3
4. The addressing mode which makes use of b) 2
in-direction pointers is ______ c) 1, 3
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a) Indirect addressing mode d) 2, 3

b) Index addressing mode
c) Relative addressing mode Answer: d
d) Offset addressing mode Explanation: In the case of, auto increment
the increment is done afterward and in auto
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Answer: a decrement the decrement is done first.

Explanation: In this addressing mode, the
value of the register serves as another 8. The addressing mode, where you directly
memory location and hence we use pointers specify the operand value is _______
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to get the data. a) Immediate

b) Direct
5. In the following indexed addressing mode c) Definite
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instruction, MOV 5(R1), LOC the effective d) Relative

address is ______
a) EA = 5+R1 Answer: a
b) EA = R1 Explanation: None.

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9. The effective address of the following write assignment statement?

instruction is MUL 5(R1,R2). a) y <= “1001”
a) 5+R1+R2 b) y := “1001”
b) 5+(R1*R2) c) y <= ‘1’, ‘0’, ‘0’, ‘1’
c) 5+[R1]+[R2] d) y => “1001”
d) 5*([R1]+[R2])

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Answer: b
Answer: c Explanation: To assign values to any
Explanation: The addressing mode used is variable, the := operator is used. Since, y is a
base with offset and index. VARIABLE STD_LOGIC_VECTOR type,
we can only use := operator and not <=
10. _____ addressing mode is most suitable to operator. => can be used, but while assigning
change the normal sequence of execution of individual elements of a vector.

.c
instructions.
a) Relative 3. Refer to the VHDL code given below,
b) Indirect which is the legal assignment statement?
c) Index with Offset

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d) Immediate SIGNAL x: STD_LOGIC;
SIGNAL y: STD_LOGIC_VECTOR(3 DOWNTO 0);
Answer: a
Explanation: The relative addressing mode is
pa a) y <= (1 => ‘1’, OTHERS => ’0’);
b) y := “0100”;
used for this since it directly updates the PC.
c) y => “0100”;
d) y => x;
TOPIC 1.4 OPERATIONS AND
OPERANDS Answer: a
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Explanation: To assign a value to a SIGNAL,
either <= or => can be used only. But, if we
1. Which of the following is not an want to use =>, then values need to be
assignment operator? assigned to individual elements. => is used
a) <= with OTHERS. Y<= (1<=’1’, OTHERS
b) :=
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=>’0’) means that the value assigned to y is

c) => 0100.
d) =
4. Which of the following logical operator has
Answer: d the highest precedence?
Explanation: Assignment operators are used a) NAND
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to assign some value to a data object. <= b) NOR

operator is used to assign values to a c) NOT
SIGNAL. := operator is used to assign values d) EXOR
to VARIABLE, CONSTANTS and
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GENERICS; this operator is also used for Answer: c

assigning initial values. Another assignment Explanation: NOT is the logical operator
operator is =>, used to assign values to which has highest precedence. If there are
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individual vector elements or others. more than one logical operator in the same
statement, then NOT will be given highest
2. A VARIABLE y is declared of preference. If there is any () in the statement
STD_LOGIC_VECTOR type of 4 bits, if you then first preference will be given to () and
want to assign 1001 to y, then what is the then to NOT operator.

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5. In the following statements, y and z are number and similarly, when used with two
equivalent to________ operands then the result is difference of two
operands.
y <= NOT a AND b;
z <= NOT (a AND b); 8. The operator ‘&’ is called the_____
operator.
a) y <= a’+b’ and z <= (a.b)’

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a) Logical AND operator
b) y <= (a+b)’ and z <= a’+b’ b) Bitwise AND operator
c) y <= a’+b and z <= a’+b’ c) Arithmetic addition operator
d) y <= a+b’ and z <= a.b d) Concatenation operator
Answer: c Answer: d
Explanation: As discussed above, NOT will Explanation: ‘&’ is called the concatenation

.c
be given highest preference. So, y becomes operator and is a binary operator. It needs two
((NOT a)AND b) which is a’+b. similarly, in operands and both of them must be arrays. It
z first of all () will be solved i.e.(a AND b)’
combines two arrays and produces one array
which is (a.b)’. By, De Morgan’s law, (a.b)’ =
of the size equal to the sum of sizes of two

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a’+b’. Therefore, y = a’+b and z = a’+b’.
arrays.
6. Which of the following VHDL statement is
9. What is the type of result of MOD
equivalent to NAND operation, if y, a and b
pa operator?
are SIGNALS?
a) Numeric
a) y <= NOT a AND b
b) Integer
b) y <= NOT a OR NOT b
c) Array
c) y <<= NOT a AND NOT b
d) Bit
d) y <<= NOT (a OR b)
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Answer: b
Answer: b
Explanation: The MOD operator is called the
Explanation: Logic NAND operation is
modulo operator which gives the remainder
(a.b)’ which is equivalent to a’ + b’ by using
of the division of two integers and hence the
De Morgan’s law. NOT a AND b is
result is of integer type. For example, y <= a
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equivalent to (a’.b). NOT a AND NOT b is

MOD b; will return the value of remainder
equivalent to (a’.b’). Similarly, NOT (a OR b)
when a is divided by b. suppose a= 12 and b=
is (a+b)’. 5 then the value of y will be 2.
7. ______ operator is unary as well as binary
10. The operators like =, /=, <, >, >= are
operator.
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called _________
a) – a) Arithmetic operators
b) * b) Concatenation operators
c) / c) Logical operators
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d) ** d) Relational operators
Answer: a
Answer: d
Explanation: Unary operator is the one
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Explanation: These operators are relational

which needs only one operand and Binary operators or Comparison operators since they
operator needs two operands. ‘–’ is the only are used to compare two operands. The =
operator which can be used with one as well refers to equal to, /= refers to not equal to
as two operands. When used with single operator. Similarly,<, >, <=, >= are called less
operand, the result is negative of the same

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than, greater than, less than or equal to, VHDL is represented by two asterisk signs.
greater than or equal to operators. So, ** is the exponentiation operator which
comes under the category of arithmetic
11. What is the type of result for comparison operators. In VHDL, a**b means a^b.
operators?
a) Boolean
TOPIC 1.5 REPRESENTING

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b) Integer
c) Numeric INSTRUCTIONS
d) Array
1. In which of these modes, the immediate
Answer: a operand is included in the instruction itself?
Explanation: Comparison operators are used a) register operand mode
for the comparison of two operands and the b) immediate operand mode

.c
result is of Boolean type i.e. true or false. For c) register and immediate operand mode
example, b:= “0010” < “0001”; In this d) none of the mentioned
statement, the value assigned to b will be
FALSE, since this means 2 < 1, which is not Answer: b

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true. Explanation: In immediate operand mode,
the immediate operand is included in the
12. ABS operator is used to _________ instruction itself.
a) Shift the operand

c) Give the result as nearest integer

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b) Gives absolute value for the operand 2. In register address mode, the operand is
stored in
d) To synthesize the result a) 8-bit general purpose register
b) 16-bit general purpose register
Answer: b c) si or di
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Explanation: ABS operator is a unary d) all of the mentioned
operator which returns the absolute value. We
can use this operator to increase the reliability Answer: d
of code. For example, we need to use π, then Explanation: In register address mode, the
the value of the same is 22/7 or 3.14. In operand is stored either in one of the 8-bit or
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VHDL, if we use following statements: pi = 16-bit general purpose registers or in SI, DI,
22/7; IF(pi = 3.14) THEN WAIT; Then we BX or BP.
might not get the result as we want. It will be
unreliable. If we use ABS operator along with 3. In which of the following addressing mode,
it, then it will be better. Like, the offset is obtained by adding displacement
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IF(abs(pi)=3.14) THEN WAIT; this will give and contents of one of the base registers?
the desired result. a) direct mode
b) register mode
13. Which of the following is exponentiation c) based mode
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operator? d) indexed mode

a) ^
b) * Answer: c
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c) /= Explanation: In a based mode, the offset is

d) ** obtained by adding displacement and contents
of one of the base registers, either BX or BP.
Answer: d
Explanation: Exponentiation operator in

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4. In which of the following addressing mode, 7. The representation of 8-bit or 16-bit signed
the offset is obtained by adding displacement, binary operands using 2’s complement is a
with the contents of SI? data type of
a) direct mode a) Ordinal
b) register mode b) ASCII
c) based mode c) Packed BCD

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d) indexed mode d) integer

Answer: d Answer: d
Explanation: In an indexed mode, the offset Explanation: In integer data type, 8-bit or 16-
is obtained by adding displacement, with bit signed binary operands are represented
contents of an index register, either SI or DI. using 2’s complement.

.c
5. The address of a location of the operand is 8. The instruction that pushes the general
calculated by adding the contents of any of purpose registers, pointer and index registers
the base registers, with the contents of any of on to the stack is
index registers in a) POPF

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a) based indexed mode with displacement b) PUSH Imd
b) based indexed mode c) PUSH*A
c) based mode pa d) PUSHF
d) indexed mode
Answer: c
Answer: b Explanation: The PUSH*A instruction,
Explanation: In a based indexed mode, the pushes the general purpose registers, AX,
operand is stored at a location, whose address CX, DX and BX, pointer and index registers,
is calculated by adding the contents of any of SP, BP, SI, DI, on to the stack.
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the base registers, with the contents of any of
the index registers. 9. While executing the PUSH*A instruction,
the stack pointer is decremented by
6. Which of the following is not a data type of a) 1 bit
80286? b) 2 bits
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a) Ordinal or unsigned c) 4 bits

b) ASCII d) 16 bits
c) Packed BCD
d) None of the mentioned Answer: b
Explanation: The stack pointer is
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Answer: d decremented by 16 (eight 2-byte registers).

Explanation: The 80286 supports seven data
types. They are 10. The statement that is true for the
1. integer instruction POP*A is
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2. Ordinal (unsigned) a) flags are unaffected

3. pointer b) no operands are required
4. string c) exceptions generated are same as that of
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5. ASCII PUSH*A
6. BCD d) all of the mentioned
7. Packed BCD.
Answer: d
Explanation: The POP*A instruction, pops

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all the contents of the registers DI, SI, BP, SP, basis, except for NOT that is performed on a
BX, DX, CX and AX from the stack in this single image.
sequence, that is exactly opposite to that of
pushing. 2. Which of the following logical operator(s)
is/are functionally complete?
11. The instruction that multiplies the content a) AND

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of AL with a signed immediate operand is b) OR
a) MUL c) NOT
b) SMUL d) All of the mentioned
c) IMUL
d) None of the mentioned Answer: d
Explanation: All the three logical operators
Answer: c given are functionally complete because all

.c
Explanation: The IMUL instruction other logical operators can be implemented
multiplies the content of AL with a signed using these three.
immediate operand, and the signed 16-bit
result is stored in AX. 3. While implementing logic operation on

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gray-scale images, the processing of pixel
12. The instruction that represents the ‘rotate values is done as __________
source, count’ is a) String of integer numbers
a) RCL b) String of floating numbers
b) RCR
c) ROR
pa c) String of binary numbers
d) None of the mentioned
d) All of the mentioned
Answer: c
Answer: d Explanation: Logic operation on gray-scale
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Explanation: The rotate source, count is a images are done by processing of pixel values
group of four instructions containing RCL, as string of binary numbers.
RCR, ROL, ROR.
4. What is the equivalent for a black, 8-bit
pixel to be processed under logic operation on
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TOPIC 1.6 LOGICAL gray scale image?

OPERATION a) A string: 00000000
b) A string: 11111111
1. Logic operations between two or more c) A string: 10000000
images are performed on pixel-by-pixel basis, d) A string: 01111111
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except for one that is performed on a single

image. Which one is that? Answer: a
a) AND Explanation: Logic operation on gray-scale
b) OR images are done by processing of pixel values
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c) NOT as string of binary numbers, so, a black, 8-bit

d) None of the mentioned pixel is processed as a string of eight 0’s.
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Answer: c 5. Which of the following operation(s) is/are

Explanation: Although all the equivalent to negative transformation?
Arithmetic/Logic operations between two or a) AND
more images are performed on pixel-by-pixel b) OR

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c) NOT TOPIC 1.7 CONTROL

d) All of the mentioned
OPERATIONS.
Answer: c
Explanation: Applying NOT operator on a 1. An automatic apparatus or device that
black, 8-bit pixel gives a white, 8-bit pixel, performs functions ordinarily ascribed to

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so, is equivalent to negative transformation. humans or operate with what appears to be
almost human intelligence is called ________
6. Which of the following operations are used a) Robot
for masking? b) Human
a) AND, OR c) Animals
b) AND, NOT d) Reptiles
c) NOT, OR

.c
d) All of the mentioned Answer: a
Explanation: Robot is an automatic
Answer: c apparatus or device that performs functions
Explanation: AND, OR operators are used ordinarily ascribed to humans or operate with

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for masking, while NOT works as negative what appears to be almost human
transformation. intelligence.
7. Two images having one pixel gray value
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01010100 and 00000101 at the same location,
are operated against AND operator. What
2. The laws of Robotics are:
a) A robot may not injure a human being
b) A robot must abbey the order given by
would be the resultant pixel gray value at that human except when conflict with the first law
location in the enhanced image? c) A robot must protect its own existence
a) 10100100 except when it is violating first and second
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b) 11111011 law
c) 00000100 d) Both b and c
d) 01010101
Answer: d
Answer: c Explanation: A robot may not injure a
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Explanation: For AND operation results in 1 human being or through in action, allow
only for 1AND 1, else 0. human being to be harmed.
All the bits of the given gray value are
operated similar resulting in 00000100. 3. The basic components of robot are:
a) The mechanical linkage
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8. Which of the following arithmetic operator b) Sensors and controllers

is primarily used as a masking operator in c) User interface and power conversion unit
enhancement? d) All of the mentioned
a) Addition
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b) Subtraction Answer: d
c) Multiplication Explanation: The basic components of robot
d) Division are the mechanical linkage, sensors and
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controllers, User interface and power

Answer: c conversion unit.
Explanation: Multiplication of one image by
another is used as a gray-level mask. 4. Assertion (A): Degree of freedom is
defined as the number of variables to define

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motion in the body in space. b) Both A and R are true but R is not correct
Reason (R): Maximum degree of freedom can explanation of A.
be six in a robot. c) A is true but R is false
a) Both A and R are true and R is not correct d) A is false but R is true
explanation of A.
b) Both A and R are true but R is not correct Answer: a

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explanation of A. Explanation: The system provides the
c) A is true but R is false theoretical position values for each step and
d) A is false but R is true continuously measures the actual position
during movement.
Answer: b
Explanation: Degree of freedom defines the 8. Hierarchical level control involves :
variables responsible for the motion of the a) Level 1: Actuator control controls

.c
robot and allows robot to reach all positions individual robot actuators
and orientations. b) Level 2: Path control coordinates robot
path movement
5. A _________ is connection between parts c) Level 3: Main control high level

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or links in a robot that allow motion. instruction interpreter
a) Hinge d) All of the mentioned
b) Joint
Answer: d
c) Dis joint
d) None of the mentioned
pa Explanation: Hierarchy refers to the system
where some form of levels are used as higher
Answer: b to lower or vice versa and this level control
Explanation: A joint is connection between mainly involves actuator control, path control
parts or links in a robot that allow motion. It and main control for various functioning of
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has translator and rotatory motion. the parts of the robot.

6. Classification of Robot is based on: 9. Non servo robots are also called as:
a) Geometry and geometric classification a) Pick and place
b) Left right classification b) Fixed stop robot
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c) Based on control system c) Both of the mentioned

d) All of the mentioned d) None of the mentioned

Answer: d Answer: c
Explanation: Robots can be classified on the Explanation: Non servo robots are simplest
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basis of the movement their structure and robots as they are the least complex structures
geometry as humanoid robots and gantry and they are made to do some specific and
robots. less jobs and it is an open loop system.
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7. Assertion (A): The control system of an 10. Characteristics of non-servo robot are:
industrial robot determine its flexibility and a) Relatively inexpensive compared to servo
efficiency, within the limits set beforehand by robots
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the design of the mechanical structure. b) Simple, understand and operate

Reason (R): The control system provides a c) Precise and reliable
logical sequence for the robot to follow. d) Closed loop system.
a) Both A and R are true and R is not correct
explanation of A.

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Answer: d Answer: b
Explanation: Non-servo robots are open loop Explanation: The binary point between the
system and less costly and they are less digits b0 and b1 does not exist physically in
complex and can be used once or twice for the computer. Simply, the logic circuits of the
some work and they are less reliable. computer are designed such that the
computations result in numbers that

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correspond to the assumed location of this
point.
UNIT II ARITHMETIC 4. What is the resolution to cover a range of
numbers xmax-xmin with ‘b’ number of bits?
TOPIC 2.1 FIXED POINT a) (xmax+xmin)/(2b-1)

.c
ADDITION b) (xmax+xmin)/(2b+1)
c) (xmax-xmin)/(2b-1)
1. If (101.01)2=(x)10, then what is the value
d) (xmax-xmin)/(2b+1)

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of x?
a) 505.05
Answer: c
b) 10.101
c) 101.01
pa Explanation: A fixed point representation of
d) 5.25 numbers allows us to cover a range of
numbers, say, xmax-xmin with a resolution
Answer: d Δ=(xmax-xmin)/(m-1)
Explanation: where m=2b is the number of levels and ‘b’ is
(101.01)2=1*22+0*21+1*20+0*2-1+1*2-2= the number of bits.
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(5.25)10
=>x=5.25. 5. What are the mantissa and exponent
required respectively to represent ‘5’ in
2. If X is a real number with ‘r’ as the radix, binary floating point representation?
a) 011,0.110000
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A is the number of integer digits and B is the

number of fraction digits, then X= b) 0.110000,011
∑
B
b r .
−i c) 011,0.101000
i=−A i
d) 0.101000,011
a) True
b) False Answer: d
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Explanation: We can represent 5 as

Answer: a
Explanation: A real number X can be 5=0.625*8=0.625*23
The above number can be represented in
represented as X=∑ B
b r
−i
where bi
binary float point representation as
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i=−A i

represents the digit, ‘r’ is the radix or base, A

0.101000*2011
is the number of integer digits, and B is the
Thus Mantissa=0.101000, Exponent=011.
number of fractional digits.
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6. If the two numbers are to be multiplied, the

3. The binary point between the digits b0 and
mantissa are multiplied and the exponents are
b1 exist physically in the computer. added.
a) True a) True
b) False b) False

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Answer: a a) Always positive

Explanation: Let us consider two numbers b) Always negative
X=M.2E and Y=N.2F c) Zero
If we multiply both X and Y, we get X.Y= d) None of the mentioned
(M.N).2E+F
Answer: b
Thus if we multiply two numbers, the

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Explanation: For a two’s complement
mantissa are multiplied and the exponents are
representation, the truncation error is always
added.
negative and falls in the range
7. What is the smallest floating point number -(2-b-2-bm) ≤ Et ≤ 0.
that can be represented using a 32-bit word?
a) 3*10-38 10. Due to non-uniform resolution, the
corresponding error in a floating point

.c
b) 2*10-38
representation is proportional to the number
c) 0.2*10-38 being quantized.
d) 0.3*10-38 a) True

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b) False
Answer: d
Explanation: Let the mantissa be represented Answer: a
by 23 bits plus a sign bit and let the exponent
pa Explanation: In floating point representation,
be represented by 7 bits plus a sign bit. the mantissa is either rounded or truncated.
Thus, the smallest floating point number that Due to non-uniform resolution, the
can be represented using the 32 bit number is corresponding error in a floating point
(1/2)*2-127=0.3*10-38 representation is proportional to the number
Thus, the smallest floating point number that being quantized.
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can be represented using the 32 bit number is
(1-2-23)*2127=1.7*1038. TOPIC 2.2 FIXED POINT
SUBTRACTION
8. If 0<E<255, then which of the following
statement is true about X?
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a) Fractional number This set of Digital Electronics/Circuits

b) Infinity Multiple Choice Questions & Answers
c) Mixed number (MCQs) focuses on “Arithmetic Operation”
d) Zero
1. What is the addition of the binary numbers
11011011010 and 010100101?
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Answer: c
Explanation: According to the IEEE 754 a) 0111001000
standard, for a 32-bit machine, single b) 1100110110
precision floating point number is represented c) 11101111111
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d) 10011010011
as X=(-1)s.2E-127(M).
From the above equation we can interpret Answer: c
that, Explanation: The rules for Binary Addition
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If 0<E<255, then X=(-1)s.2E-127(1.M)=>X is are :

a mixed number. 0+0=0
0+1=1
9. For a twos complement representation, the 1+0=1
truncation error is ____________ 1 + 1 = 0 ( Carry 1)

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1 ____________
0 1 1 0 1 0
1 1 0 1 1 0 1 1 0 1 0 _____________

+ 0 0 0 1 0 1 0 0 1 0 1 Therefore, The subtraction of 101111 –

_______________________ 010101 = 011010.
1 1 1 0 1 1 1 1 1 1 1

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_______________________
4. Binary subtraction of 100101 – 011110 is
2. Perform binary addition: 101101 + 011011 a) 000111
=? b) 111000
a) 011010 c) 010101
b) 1010100 d) 101010
c) 101110
Answer: a

.c
d) 1001000
Explanation: The rules for Binary
Answer: d Subtraction are :
Explanation:The rules for Binary Addition 0–0=0

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are : 0 – 1 = 1 ( Borrow 1)
0+0=0 1–0=1
0+1=1 1–1=0
1+0=1
1 + 1 = 0 ( Carry 1)
1 1 1 1 1 1
pa 1 0 0 1 0 1
- 0 1 1 1 1 0
___________
0 0 0 1 1 1
1 0 1 1 0 1 ___________
+ 0 1 1 0 1 1
_______________
Therefore, The subtraction of 100101 –
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1 0 0 1 0 0 0
_______________ 011110 = 000111.

Therefore, the addition of 101101 + 011011 = 5. Perform multiplication of the binary

1001000. numbers: 01001 × 01011 = ?
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a) 001100011
3. Perform binary subtraction: 101111 – b) 110011100
010101 = ? c) 010100110
a) 100100 d) 101010111
b) 010101
c) 011010 Answer: a
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d) 011001 Explanation: The rules for binary

multiplication are:
Answer: c 0*0=0
0*1=0
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Explanation: The rules for Binary

Subtraction are : 1*0=0
0–0=0 1*1=1
0 – 1 = 1 ( Borrow 1)
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0 1 0 0 1
1–0=1 x 0 1 0 1 1
1–1=0 ____________
0 1 0 0 1
1 0 1 1 1 1 0 1 0 0 1 0
- 0 1 0 1 0 1 0 0 0 0 0 0 0

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0 1 0 0 1 0 0 0 __________
0 0 0 0 0 0 0 0 0 1 0 1 0
___________________ 0 0 0 0 0
0 0 1 1 0 0 0 1 1 1 0 1 0 0 0
___________________ 0 0 0 0 0 0 0
_______________
Therefore, 01001 × 01011 = 001100011. 0 1 1.0 0 1 0

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_________________
6. 100101 × 0110 = ?
a) 1011001111 Therefore, 10.10 x 01.01 = 011.0010.
b) 0100110011
8. Divide the binary numbers: 111101 ÷ 1001
c) 101111110
and find the remainder
d) 0110100101
a) 0010

.c
Answer: c b) 1010
Explanation: The rules for binary c) 1100
multiplication are: d) 0011
0*0=0

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Answer: d
0*1=0
Explanation: Binary Division is
1*0=0
accomplished using long division method.
1*1=1 pa 1 0 0 1 ) 1 1 1 1 0 1 ( 1 1
1 0 0 1 0 1 1 0 0 1
x 0 1 1 0 __________
___________ 0 1 1 0 0
0 0 0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 ___________
1 0 0 1 0 1 0 0
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0 1 1 1
0 0 0 0 0 0 0 0 0
__________________
0 1 1 0 1 1 1 1 0 Therefore, the remainder of 111101 ÷ 1001 =
___________________ 0111.

9. Divide the binary number (011010000) by

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Therefore, 100101 x 0110 = 011011110.

(0101) and find the quotient
7. On multiplication of (10.10) and (01.01), a) 100011
we get b) 101001
a) 101.0010 c) 110010
b) 0010.101 d) 010001
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c) 011.0010
d) 110.0011 Answer: b
Explanation:
Answer: c
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0 1 0 1 ) 0 1 1 0 1 0 0 0 0 ( 0 1 0 1 1 1
Explanation: The rules for binary
0 0 0 0
multiplication are: _____________________
0*0=0 0 1 1 0 1
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0*1=0 0 0 1 0 1
1*0=0 ______________
0 1 0 0 0 0
1*1=1
0 0 0 0 0 0
1 0.1 0 ______________________
x 0 1.0 1 1 0 0 0 0

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0 0 1 0 1 c) 11110000
____________________ d) 11001100
0 1 0 1 1 0
0 0 0 1 0 1
____________________ Answer: a
1 0 0 0 1 0 Explanation: The above operation is
0 0 0 1 0 1 performed using binary multiplication.

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________________________
1 1 1 0 1 0 2. We make use of ______ circuits to
0 0 0 1 0 1
________________________
implement multiplication.
1 0 1 0 1 a) Flip flops
0 0 1 0 1 b) Combinatorial
________________________ c) Fast adders
1 0 0 0 0 d) None of the mentioned

.c
Therefore, the quotient of 011010000 ÷ 1001 Answer: c
= 101001. Explanation: The fast adders are used to add
the multiplied numbers.

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10. Binary subtraction of 101101 – 001011 =
? 3. The multiplier is stored in ______
a) 100010 a) PC Register
b) 010110 b) Shift register
c) 110101
d) 101100
pa c) Cache
d) None of the mentioned
Answer: a Answer: b
Explanation: The rules for binary subtraction Explanation: The value is stored in a shift
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are: register so that each bit can be accessed
0–0=0 separately.
0 – 1 = 1 ( Borrow 1)
1–0=1 4. The ______ is used to coordinate the
1–1=0 operation of the multiplier.
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a) Controller
1 0 1 1 0 1
- 0 0 1 0 1 1 b) Coordinator
____________ c) Control sequencer
1 0 0 0 1 0 d) None of the mentioned
____________
Answer: c
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Therefore, the subtraction of 101101 – Explanation: This performs the required

001011 = 100010. sequencing of the various parts of the circuit.
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TOPIC 2.3 FIXED POINT 5. The multiplicand and the control signals
are passed through to the n-bit adder via
MULTIPLICATION _____
a) MUX
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1. The product of 1101 & 1011 is ______ b) DEMUX

a) 10001111 c) Encoder
b) 10101010 d) Decoder

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Answer: a c) Computer Service Architecture

Explanation: None. d) None of the mentioned

6. The product of -13 & 11 is Answer: a

______________ Explanation: The CSA is used to speed up
a) 1100110011 the addition of multiplicands.

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b) 1101110001
c) 1010101010
d) 1111111000
TOPIC 2.4 FIXED POINT
DIVISION
Answer: b
Explanation: None. 1. Perform binary addition of 1101 + 0010 is
________

.c
7. The method used to reduce the maximum a) 1110
number of summands by half is _______ b) 1111
a) Fast multiplication c) 0111
b) Bit-pair recording d) 1,1101

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c) Quick multiplication
d) None of the mentioned Answer: b
Explanation: The addition is performed as :
Answer: b

summands by concatenating them.

pa
Explanation: It reduces the number of
1101
+ 0010
_______
1111
8. The bits 1 & 1 are recorded as _______ in Therefore, the result is 1111.
bit-pair recording.
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a) -1 2. The addition 1+1 gives 0 as a result.
b) 0 a) True
c) +1 b) False
d) both -1 and 0
Answer: a
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Answer: d Explanation: The two result obtained is 0

Explanation: Its ‘-1’ when the previous bit is with a carry of 1. This carry is transferred to
0 and ‘0’ when the previous bit is 1. the next higher column.
9. The multiplier -6(11010) is recorded as 3. The result of 0*1 in binary is
_______
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____________
a) 0-1-2 a) 0
b) 0-1+1-10 b) 1
c) -2-10 c) invalid
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d) None of the mentioned d) 10

Answer: a Answer: a
Explanation: None.
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Explanation: The binary multiplication of

any number with 0 will give the result 0 itself.
10. CSA stands for? Any binary number when multiplied by 0
a) Computer Speed Addition gives 0 only. e.g. 1101 * 0000 = 0000.
b) Carry Save Addition

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4. The multiplication of 110 * 111 is a) Multipliers

performed. What is a general term used for b) Mid terms
111? c) Partial Products
a) Dividend d) Multiplicands
b) Quotient
c) Multiplicand Answer: c

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d) Multiplier Explanation: The intermediate terms are
called partial terms. The mid terms obtained
Answer: d in the binary multiplications are the partial
Explanation: 111 is called the multiplier. ones whereas the answer obtained is called
Whenever a multiplication is performed the the final product.
second term is called the multiplier whereas
the first term is called the multiplicand. 8. The result that is smaller than the smallest

.c
number obtained is referred to as
5. The result obtained on binary ___________
multiplication of 1010 * 1100 is a) NaN
_____________ b) Underflow

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a) 0001111 c) Smallest
b) 0011111 d) Mantissa
c) 1111100
Answer: b
d) 1111000

Answer: d
pa Explanation: It is referred to as underflow.
Nan stands for not a number. Mantissa is the
Explanation: The solution is as follows : part after the decimal.
1010 9. The number of sign bits in a 32-bit IEEE
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* 1100
________
format is _______
0000 a) 1
0000 b) 11
1010 c) 9
1010 d) 23
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_______
1111000
Answer: a
6. Which of the following is often called the Explanation: There is only 1 sign bit in all
double precision format? the standards. In a 32-bit format, there is 1
a) 64-bit sign bit, 8 bits for the exponent and 23 bits
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b) 8-bit for the mantissa.

c) 32-bit
d) 128-bit 10. Express the decimal format of the signed
binary number (101010)2 .
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Answer: a a) 10
Explanation: The 64-bit format is referred to b) 12
as the double precision format. It has 1 sign c) -12
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bit, 8 exponent bits and 23 bits for the d) -10

mantissa.
Answer: d
7. What do you call the intermediate terms in Explanation: The first bit is the sign bit
binary multiplication? whereas the rest of the bits are magnitude

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bits. So the number is: 01010 =23 * 1 + 21 * 1 b) Significant digits

=8+2 =10. c) Scale factor
But , the sign bit is 1, d) All of the mentioned
Therefore the answer is : (-2)10.
Answer: d
Explanation: The following factors are

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TOPIC 2.5 FLOATING POINT responsible for the representation of the
ARITHMETIC number.

5. The sign followed by the string of digits is

1. The decimal numbers represented in the called as ______
computer are called as floating point a) Significant
numbers, as the decimal point floats through b) Determinant

.c
the number. c) Mantissa
a) True d) Exponent
b) False
Answer: c

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Answer: a Explanation: The mantissa also consists of
Explanation: By doing this the computer is the decimal point.
capable of accommodating the large float
numbers also. 6. In IEEE 32-bit representations, the
pa
2. The numbers written to the power of 10 in
mantissa of the fraction is said to occupy
______ bits.
the representation of decimal numbers are a) 24
called as _____ b) 23
a) Height factors c) 20
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b) Size factors d) 16
c) Scale factors
d) None of the mentioned Answer: b
Explanation: The mantissa is made to occupy
Answer: c 23 bits, with 8 bit exponent.
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Explanation: These are called as scale factors

cause they’re responsible in determining the 7. The normalized representation of
degree of specification of a number. 0.0010110 * 2 9 is _______
a) 0 10001000 0010110
3. If the decimal point is placed to the right of
b) 0 10000101 0110
the first significant digit, then the number is
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c) 0 10101010 1110
called ________
d) 0 11110100 11100
a) Orthogonal
b) Normalized Answer: b
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c) Determinate Explanation: Normalized representation is

d) None of the mentioned done by shifting the decimal point.
Answer: b
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8. The 32 bit representation of the decimal

Explanation: None. number is called as ___________
a) Double-precision
4. ________ constitute the representation of
b) Single-precision
the floating number.
a) Sign

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c) Extended format 2. ALU is the place where the actual

d) None of the mentioned executions of instructions take place during
the processing operation.
Answer: b a) True
Explanation: None. b) False

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9. In 32 bit representation the scale factor as a Answer: a
range of ________ Explanation: ALU is a combinational
a) -128 to 127 electronic circuit which basically performs all
b) -256 to 255 the logical or the bitwise operations and the
c) 0 to 255 arithmetic operations. Therefore, it is the
d) None of the mentioned place where the actual executions of
instructions take place.

.c
Answer: a
Explanation: Since the exponent field has 3. Which of the following is not a bitwise
only 8 bits to store the value. operator?
a) |

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10. In double precision format, the size of the b) ^
mantissa is ______ c) .
a) 32 bit d) <<
b) 52 bit
c) 64 bit
d) 72 bit
pa Answer: c
Explanation: All except the dot(.) operator
are bitwise operators.
Answer: b | : Bitwise OR
Explanation: The double precision format is ^ : Bitwise XOR
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also called as 64 bit representation. << : Shift Left

TOPIC 2.6 HIGH 4. The sign magnitude representation of -1 is

__________
PERFORMANCE ARITHMETIC a) 0001
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b) 1110
1. The ‘heart’ of the processor which c) 1000
performs many different operations d) 1001
_____________
a) Arithmetic and logic unit Answer: d
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b) Motherboard Explanation: The first leftmost bit i.e. the

c) Control Unit most significant bit in the sign magnitude
d) Memory represents if the number is positive or
negative. If the MSB is 1, the number is
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Answer: a negative else if it is 0, the number is positive.

Explanation: The Arithmetic and logic unit Here, +1=0001 and for -1=1001.
performs all the basic operations of the
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computer system. It performs all the 5. IEEE stands for ___________

arithmetic(+,-,*,/,etc) as well as the logical a) Instantaneous Electrical Engineering
operations( AND, OR, NOT, etc.). b) Institute of Emerging Electrical Engineers
c) Institute of Emerging Electronic Engineers

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d) Institute of Electrical and electronics subtract, AND, OR, XOR, Increment,

engineers decrement, shift).

Answer: d 9. Which flag indicates the number of 1 bit

Explanation: The IEEE is an organization of that results from an operation?
professionals in the field of electronics and a) Zero

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electrical engineering. IEEE has given certain b) Parity
standards of its own which are followed in the c) Auxiliary
field of computer science and electrical d) Carry
engineering.
Answer: b
6. The ALU gives the output of the operations Explanation: The parity flag indicates the
and the output is stored in the ________ number of 1 bit in any operation. The

.c
a) Memory Devices resultant bit is called the parity bit. The main
b) Registers aim of the parity bit is to check for errors.
c) Flags
d) Output Unit 10. The bitwise complement of 0 is

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___________
Answer: b a) 00000001
Explanation: Any output generated by the b) 10000000
ALU gets stored in the registers. The registers c) 11111111
pa
are the temporary memory locations within
the processor that are connected by signal
d) 11111110

paths to the CPU. Answer: c

Explanation: Bitwise complement is
7. The process of division on memory spaces basically used to convert all the 0 digits to 1
jin
is called ______________ and the 1s to 0s.
a) Paging So, for 0 = 00000000(in 8-bits) :::
b) Segmentation 11111111(1s complement). The bitwise
c) Bifurcation complement is often referred to as the 1s
d) Dynamic Division complement.
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Answer: b Sanfoundry Global Education & Learning

Explanation: The memory space is divided Series – Computer Fundamentals.
into segments of dynamic size. The
programmer is aware of the segmentation and
TOPIC 2.7 SUBWORD
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can reallocate the segments accordingly.

PARALLELISM
8. Number of bits in ALU is _________
a) 4 1. What shows the brightness of the pixel in a
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b) 8 digital signal processor?

c) 16 a) luminance
d) 2 b) transparent
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c) chrominance
Answer: c d) opaque
Explanation: Arithmetic and Logic Unit
consists of 16bits. They perform certain Answer: a
Arithmetic and bitwise operations (add, Explanation: The color image of a digital

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signal processor have multiple channels. The physically

brightness of the pixel is determined by b) different parts of the program executes
luminance and the color of the pixel is sequentially
determined by chrominance. c) different parts of the program executes
conceptually
2. What is the color format of chrominance in d) different parts of the program executes

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a digital signal processor? sequentially and physically
a) VGBA
b) VIBGYOR Answer: c
c) White Explanation: A concurrent program executes
d) RGBA different parts of the program conceptually, a
parallel program executes different programs
Answer: d physically and a non-concurrent program

.c
Explanation: RGBA colors have four executes the program in sequential order.
channels red, green, blue, and alpha, which is
transparent. 6. Which is an imperative language?
a) C program

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3. Which of the following processor are b) SQL
designed to perform calculations in graphics c) XQuery
rendering? d) Concurrent model of HDL
a) GPU
b) digital signal processor
c) microprocessor
pa Answer: a
Explanation: Imperative language is one
d) microcontroller which executes the program in sequential
order. C program is an example of imperative
Answer: a language, SQL and XQuery are examples of
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Explanation: Graphics processing unit is declarative languages or non-imperative
designed to perform calculations in graphics language. Concurrent model in HDL is a
rendering. Intel, NVIDIA, and AMD are hardware description language which
dominant providers of GPU. executes the program concurrently.
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4. Which of the processor is a good match for 7. Which of the following instructions
applications such as video games? supports parallel execution?
a) GPU a) VLIW
b) VLIW b) TTA
c) Coprocessor c) ALU operation
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d) Microcontroller d) Test-and-set instructions

Answer: a Answer: a
Explanation: GPU is a graphics processing Explanation: VLIW is a very long instruction
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unit. Therefore, more graphical images can be word which receives many instructions and is
created by GPU which is necessary for video executed in one instructed word. VLIW is
games. Therefore, GPU is a good match for majorly designed for instruction-level parallel
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video games. (ILP) that is, it can execute codes

concurrently or parallel in some time. TTA is
5. Which of the following statement is true a transport triggered architecture which is a
for concurrency? type of CPU design which programs
a) different parts of the program executes controlling the internal buses of the processor.

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Test-and-set is used to write to a memory c) Superscalar

location and return its old values. ALU used d) VLIW
to perform arithmetic and logic operations.
Answer: a
8. Who invented VLIW architecture? Explanation: Subword parallelism is a form
a) Josh Fisher of a vector processing. A vector processor is

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b) John Ellis the one whose instruction set includes
c) John Ruttenberg operations on multiple data elements
d) John O’Donnell simultaneously.

Answer: a 12. Which of the following architecture

Explanation: Josh Fisher from Yale supports out-of-order execution?
Universities invented the concept of VLIW a) RISC

.c
architecture. John Ellis described the VLIW b) CISC
compiler. John Ruttenberg develops some c) Superscalar
important algorithms in scheduling. d) Subword parallelism

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9. What is ILP? Answer: c
a) instruction-level parallelism Explanation: Superscalar architecture
b) instruction-level panel support out-of-order execution in which the
c) instruction-language panel instructions later in the stream are executed
d) inter-language parallelism
pa before earlier instructions.

Answer: a 13. Which is an example of superscalar

Explanation: A processor which supports architecture?
instruction-level parallelism can perform a) Pentium 4
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multiple independent operations in every b) 8086
instruction cycle. Basically, there are four c) 80386
types of instructions. These are CISC d) Pentium pro
instructions, subword parallelism,
superscalar, and VLIW. Answer: a
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Explanation: Pentium 4 is a single core CPU

10. Which ILP supports the ALU division? used in desktops, laptops which are proposed
a) Subword parallelism by Intel. It has Netburst architecture.
b) CISC
c) Superscalar 14. Which of the following is a combination
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d) VLIW of several processors on a single chip?

a) Multicore architecture
Answer: a b) RISC architecture
Explanation: In subword parallelism, the c) CISC architecture
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wide ALU is divided into smaller slices d) Subword parallelism

which enable simultaneous arithmetic and
logical operations. Answer: a
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Explanation: The Multicore machine is a

11. Which is a vector processor? combination of many processors on a single
a) Subword parallelism chip. The heterogeneous multicore machine
b) CISC also combines a variety of processor types on
a single chip.

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15. Which is an example of the multi-core a byte of memory from a location to another
processor which possesses 10 cores? location in the computer.
a) Intel Xeon E7-2850
b) AMD Phenom IIX2 3. The operation that does not involves clock
c) Intel core duo cycles is _________
d) AMD Phenom IIX3 a) Installation of a device

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b) Execute
Answer: a c) Fetch
Explanation: Intel Xeon E7-2850 have ten d) Decode
cores whereas AMD Phenom IIx2 and Intel
core duo has two cores and AMD Phenom Answer: a
IIX3 has three cores. Explanation: Normally, several clock cycles
are required to fetch, execute and decode a

.c
particular program.
Installation of a device is done by the system
on its own.
UNIT III THE

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4. The number of clock cycles per second is
PROCESSOR referred as ________
a) Clock speed
b) Clock frequency
TOPIC 3.1 PROCESSOR
INTRODUCTION, LOGIC
pa c) Clock rate
d) Clock timing
DESIGN CONVENTIONS OF
PROCESSOR Answer: a
Explanation: The number of clock cycles per
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second is the clock speed. It is generally
1. Computer has a built-in system clock that
emits millions of regularly spaced electric measured in gigahertz(109 cycles/sec) or
pulses per _____ called clock cycles. megahertz (106 cycles/sec).
a) second
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b) millisecond 5. CISC stands for ____________

c) microsecond a) Complex Information Sensed CPU
d) minute b) Complex Instruction Set Computer
c) Complex Intelligence Sensed CPU
Answer: a d) Complex Instruction Set CPU
Explanation: The regularly spaced electric
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pulses per second are referred to as the clock Answer: b

cycles. All the jobs performed by the Explanation: CISC is a large instruction set
processor are on the basis of clock cycles. computer. It has variable length instructions.
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It also has variety of addressing modes.

2. It takes one clock cycle to perform a basic
operation. 6. Which of the following processor has a
a) True fixed length of instructions?
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b) False a) CISC
b) RISC
Answer: a c) EPIC
Explanation: It takes exactly one clock cycle d) Multi-core
to perform a basic operation, such as moving

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Answer: b required to drive a computer system is

Explanation: The RISC which stands for ________
Reduced Instruction set computer has a fixed a) Memory
length of instructions. It has a small b) ALU
instruction set. Also has reduced references to c) CU
memory to retrieve operands. d) Processor

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7. Processor which is complex and expensive Answer: d
to produce is ________ Explanation: The processor is responsible for
a) RISC processing the basic instructions in order to
b) EPIC drive a computer. The primary functions of a
c) CISC processor are fetch, decode and execute.
d) Multi-core

.c
Answer: c TOPIC 3.2 BUILDING A
Explanation: CISC stands for complex DATAPATH
instruction set computer. It is mostly used in

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personal computers. It has a large instruction 1. ____________ is the raw material used as
set and a variable length of instructions. input and __________ is the processed data
obtained as output of data processing.
8. The architecture that uses a tighter

processor is ____________
pa
coupling between the compiler and the
a) Data, Instructions
b) Instructions, Program
c) Data, Program
a) EPIC d) Program, Code
b) Multi-core
c) RISC Answer: a
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d) CISC Explanation: Data can be assumed as a raw
material which, in turns after processing gives
Answer: a the desired output in the form of instructions.
Explanation: EPIC stands for Explicitly Further, a set of ordered and meaningful
parallel instruction computing. It has a tighter
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instructions is known as a program.

coupling between the compiler and the
processor. It enables the compiler to extract 2. Which of the following is not a
maximum parallelism in the original code. characteristic of a computer?
a) Diligence
9. MAR stands for ___________ b) I.Q.
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a) Memory address register c) Accuracy

b) Main address register d) Versatility
c) Main accessible register
d) Memory accessible register Answer: b
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Explanation: The Computer system has no

Answer: a I.Q. of its own. It does only what it is
Explanation: The MAR stands for memory programmed to do. It cannot take decisions of
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address register. It holds the address of the its own.

active memory location. A computer is diligent because it can work
continuously for hours without getting any
10. A circuitry that processes that responds to errors or without getting grumbled.
and processes the basic instructions that are The accuracy of a computer is consistently

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high and its level of accuracy depends on its The registers act as intermediate storage for
design. A computer can perform any task if, it the data.
can be broken down into a series of logical
steps. Therefore, a computer is versatile. 5. What does MAR stand for?
a) Main Address Register
3. Fill in the blank in the diagram. b) Memory Access Register

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c) Main Accessible Register
d) Memory Address Register

Answer: d
Explanation: MAR is a type of register
which is responsible for the fetch operation.
MAR is connected to the address bus and it

.c
specifies the address for the read and write
operations.

a) Input Unit 6. If the control signals are generated by

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b) Memory Unit combinational logic, then they are generated
c) Control Unit by a type of _______________ controlled
d) I/O Unit unit.
a) Micro programmed
Answer: c
pa
Explanation: The control unit manages and
b) Software
c) Logic
coordinates the operations of a computer d) Hardwired
system. The ALU is responsible for
performing all the arithmetic and bitwise Answer: d
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operations . Therefore, both these units Explanation: The main task of a control unit
combine to form the brain of the computer is to generate control signals. There are two
,which is the central processing unit. main types of control units:
A hardwired control unit generates control
4. The part of a processor which contains signals by using combinational logic circuits
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hardware necessary to perform all the and the Micro programmed control unit
operations required by a computer: generates control signals by using some
a) Data path softwares.
b) Controller
c) Registers 7. Which is the simplest method of
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d) Cache implementing hardwired control unit?

a) State Table Method
Answer: a b) Delay Element Method
Explanation: A processor is a part of the c) Sequence Counter Method
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computer which does all the data d) Using Circuits

manipulation and decision making. A
processor comprises of: Answer: a
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A data path which contains the hardware Explanation: There are 3 ways of
necessary to perform all the operations. A implementing hardwired control unit:
controller tells the data path what needs to be A state table is the simplest method in which
done. a number of circuits are designed based on
the cells in the table.

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A delay element method consists of a case of vertical microinstruction bits are

flowchart drawn for the circuit. A D-flip flop decoded and, the decoder then produces
is used as a delay element. signals.
A sequence counter method used k-modulo
counter as a replacement for k delay
elements.
TOPIC 3.3 AN OVERVIEW OF
PIPELINING

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8. A set of microinstructions for a single
machine instruction is called ___________ 1. ______ have been developed specifically
a) Program for pipelined systems.
b) Command a) Utility software
c) Micro program b) Speed up utilities
d) Micro command c) Optimizing compilers

.c
d) None of the mentioned
Answer: c
Explanation: For every micro-operation, a Answer: c
set of microinstructions are written which Explanation: The compilers which are

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indicate the control signals to be activated. A designed to remove redundant parts of the
set of microinstructions is a micro program. code are called as optimizing compilers.
The address of the next microinstruction is
pa
given by a Micro-program counter. 2. The pipelining process is also called as
______
9. Micro-program consists of a set of a) Superscalar operation
microinstructions which are strings of 0s and b) Assembly line operation
1s. c) Von Neumann cycle
a) True d) None of the mentioned
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b) False
Answer: b
Answer: a Explanation: It is called so because it
Explanation: The computer understands only performs its operation at the assembly level.
binary language. So, the micro-program
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should have instructions which are in the 3. The fetch and execution cycles are
form of 0s and 1s. Each output line of the interleaved with the help of ________
micro-program corresponds to one control a) Modification in processor architecture
signal. b) Clock
c) Special unit
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10. A decoder is required in case of a d) Control unit

______________
a) Vertical Microinstruction Answer: b
b) Horizontal Microinstruction Explanation: The time cycle of the clock is
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c) Multilevel Microinstruction adjusted to perform the interleaving.

d) All types of microinstructions
4. Each stage in pipelining should be
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Answer: a completed within ___________ cycle.

Explanation: There are two types of a) 1
microinstructions: Horizontal and Vertical. b) 2
In a horizontal microinstruction, each bit c) 3
represents a signal to be activated whereas, in d) 4

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Answer: a 9. The contention for the usage of a hardware

Explanation: The stages in the pipelining device is called ______
should get completed within one cycle to a) Structural hazard
increase the speed of performance. b) Stalk
c) Deadlock
5. In pipelining the task which requires the d) None of the mentioned

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least time is performed first.
a) True Answer: a
b) False Explanation: None.

Answer: b 10. The situation wherein the data of

Explanation: This is done to avoid starvation operands are not available is called ______
of the longer task. a) Data hazard

.c
b) Stock
6. If a unit completes its task before the c) Deadlock
allotted time period, then _______ d) Structural hazard
a) It’ll perform some other task in the

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remaining time Answer: a
b) Its time gets reallocated to a different task Explanation: Data hazards are generally
c) It’ll remain idle for the remaining time caused when the data is not ready on the
d) None of the mentioned destination side.

Answer: c
pa TOPIC 3.4 PIPELINED
Explanation: None.
DATAPATH AND CONTROL
7. To increase the speed of memory access in
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pipelining, we make use of _______ 1. ______ have been developed specifically
a) Special memory locations for pipelined systems.
b) Special purpose registers a) Utility software
c) Cache b) Speed up utilities
d) Buffers c) Optimizing compilers
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d) None of the mentioned

Answer: c
Explanation: By using the cache we can Answer: c
reduce the speed of memory access by a Explanation: The compilers which are
factor of 10. designed to remove redundant parts of the
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code are called as optimizing compilers.

8. The periods of time when the unit is idle is
called as _____ 2. The pipelining process is also called as
a) Stalls ______
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b) Bubbles a) Superscalar operation

c) Hazards b) Assembly line operation
d) Both Stalls and Bubbles c) Von Neumann cycle
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d) None of the mentioned

Answer: d
Explanation: The stalls are a type of hazards Answer: b
that affect a pipelined system. Explanation: It is called so because it
performs its operation at the assembly level.

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3. The fetch and execution cycles are c) Cache

interleaved with the help of ________ d) Buffers
a) Modification in processor architecture
b) Clock Answer: c
c) Special unit Explanation: By using the cache we can
d) Control unit reduce the speed of memory access by a

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factor of 10.
Answer: b
Explanation: The time cycle of the clock is 8. The periods of time when the unit is idle is
adjusted to perform the interleaving. called as _____
a) Stalls
4. Each stage in pipelining should be b) Bubbles
completed within ___________ cycle. c) Hazards

.c
a) 1 d) Both Stalls and Bubbles
b) 2
c) 3 Answer: d
d) 4 Explanation: The stalls are a type of hazards

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that affect a pipelined system.
Answer: a
Explanation: The stages in the pipelining 9. The contention for the usage of a hardware
should get completed within one cycle to device is called ______
increase the speed of performance.
pa a) Structural hazard
b) Stalk
5. In pipelining the task which requires the c) Deadlock
least time is performed first. d) None of the mentioned
a) True
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b) False Answer: a
Explanation: None.
Answer: b
Explanation: This is done to avoid starvation 10. The situation wherein the data of
of the longer task. operands are not available is called ______
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a) Data hazard
6. If a unit completes its task before the b) Stock
allotted time period, then _______ c) Deadlock
a) It’ll perform some other task in the d) Structural hazard
remaining time
Answer: a
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b) Its time gets reallocated to a different task

c) It’ll remain idle for the remaining time Explanation: Data hazards are generally
d) None of the mentioned caused when the data is not ready on the
destination side.
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Answer: c
Explanation: None.
TOPIC 3.5 DATA HAZARDS:
7. To increase the speed of memory access in FORWARDING VERSUS
w

pipelining, we make use of _______ STALLING, CONTROL

a) Special memory locations HAZARDS, EXCEPTIONS
b) Special purpose registers

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1. Any condition that causes a processor to ___________

stall is called as _________ a) Control hazard
a) Hazard b) structural hazard
b) Page fault c) Input hazard
c) System error d) None of the mentioned
d) None of the mentioned

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Answer: a
Answer: a Explanation: The control hazard also called
Explanation: An hazard causes a delay in the as instruction hazard is usually caused by a
execution process of the processor. cache miss.

2. The periods of time when the unit is idle is 6. The time lost due to the branch instruction
called as ________ is often referred to as ____________

.c
a) Stalls a) Latency
b) Bubbles b) Delay
c) Hazards c) Branch penalty
d) Both Stalls and Bubbles d) None of the mentioned

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Answer: d Answer: c
Explanation: The stalls are a type of hazards Explanation: This time also retards the
that affect a pipe-lined system. performance speed of the processor.
pa
3. The contention for the usage of a hardware 7. The pipeline bubbling is a method used to
device is called ______ prevent data hazard and structural hazards.
a) Structural hazard a) True
b) Stalk b) False
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c) Deadlock
d) None of the mentioned Answer: a
Explanation: The periods of time when the
Answer: a unit is idle is called a Bubble.
Explanation: The processor contends for the
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usage of the hardware and might enter into a 8. ____________ method is used in
deadlock state. centralized systems to perform out of order
execution.
4. The situation wherein the data of operands a) Scorecard
are not available is called ______ b) Score boarding
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a) Data hazard c) Optimizing

b) Stock d) Redundancy
c) Deadlock
d) Structural hazard Answer: b
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Explanation: In a scoreboard, the data

Answer: a dependencies of every instruction are logged.
Explanation: Data hazards are generally Instructions are released only when the
w

caused when the data is not ready on the scoreboard determines that there are no
destination side. conflicts with previously issued and
incomplete instructions.
5. The stalling of the processor due to the
unavailability of the instructions is called as

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9. The algorithm followed in most of the Answer: a

systems to perform out of order execution is Explanation: ILP stands for Instruction Level
__________ Parallelism.
a) Tomasulo algorithm
b) Score carding 3. The main difference between the VLIW
c) Reader-writer algorithm and the other approaches to improve

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d) None of the mentioned performance is ___________
a) Cost effectiveness
Answer: a b) Increase in performance
Explanation: The Tomasulo algorithm is a c) Lack of complex hardware design
hardware algorithm developed in 1967 by d) All of the mentioned
Robert Tomasulo from IBM. It allows
sequential instructions that would normally Answer: c

.c
be stalled due to certain dependencies to Explanation: The Pipe-lining and super-
execute non-sequentially (out-of-order scalar architectures involved the usage of
execution). complex hardware circuits for the
implementation.

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10. The problem where process concurrency
becomes an issue is called as ___________ 4. In VLIW the decision for the order of
a) Philosophers problem execution of the instructions depends on the
program itself.
b) Bakery problem
c) Bankers problem
d) Reader-writer problem
pa a) True
b) False

Answer: d Answer: a
Explanation: None. Explanation: In other words, the order of
jin
execution of instructions has nothing to do
with the physical hardware implementation of
TOPIC 3.6 PARALLELISM VIA the system.
INSTRUCTIONS.
5. The parallel execution of operations in
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1. VLIW stands for? VLIW is done according to the schedule

a) Very Long Instruction Word determined by __________
b) Very Long Instruction Width a) Task scheduler
c) Very Large Instruction Word b) Interpreter
d) Very Long Instruction Width c) Compiler
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d) Encoder
Answer: a
Explanation: It is the architecture designed to Answer: c
perform multiple operations in parallel. Explanation: The compiler first checks the
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code for interdependencies and then

2. The important feature of the VLIW is determines the schedule for its execution.
_______
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a) ILP 6. The VLIW processors are much simpler as

b) Cost effectiveness they do not require of _________
c) Performance a) Computational register
d) None of the mentioned b) Complex logic circuits

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c) SSD slots Answer: a

d) Scheduling hardware Explanation: None.

Answer: d
Explanation: As the compiler only decides
the schedule of execution the schedule is not
UNIT IV MEMORY AND

om
required here.

7. The VLIW architecture follows _____ I/O ORGANIZATION

approach to achieve parallelism.
a) MISD TOPIC 4.1 MEMORY
b) SISD
c) SIMD HIERARCHY

.c
d) MIMD
1. The standard SRAM chips are costly as
Answer: d _________
Explanation: The MIMD stands for Multiple a) They use highly advanced micro-electronic

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Instructions Multiple Data. devices
b) They house 6 transistor per chip
8. The following instruction is allowed in c) They require specially designed PCB’s
VLIW:
pa
f12 = f0 * f4, f8 = f8 + f12, f0 = dm(i0, m3),
d) None of the mentioned
f4 = b
Answer: pm(i8, m9);
Explanation: As they require a large number
a) True of transistors, their cost per bit increases.
b) False
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2. The drawback of building a large memory
Answer: a
with DRAM is ______________
Explanation: The above mentioned
a) The large cost factor
instruction is a complex 48 bit instruction
b) The inefficient memory organisation
used to perform operations on floating
c) The Slow speed of operation
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numbers.
d) All of the mentioned
9. To compute the direction of the branch the
Answer: c
VLIW uses _____________ Explanation: The DRAM’s were used for
a) Seekers large memory modules for a long time until a
b) Heuristics
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substitute was found.

c) Direction counter
d) Compass 3. To overcome the slow operating speeds of
the secondary memory we make use of faster
w

Answer: b flash drives.

Explanation: None. a) True
b) False
10. EPIC stands for?
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a) Explicitly Parallel Instruction Computing Answer: a

b) External Peripheral Integrating Component Explanation: To improve the speed we use
c) External Parallel Instruction Computing flash drives at the cost of memory space.
d) None of the mentioned

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4. The fastest data access is provided using 8. The last on the hierarchy scale of memory
_______ devices is ______
a) Caches a) Main memory
b) DRAM’s b) Secondary memory
c) SRAM’s c) TLB
d) Registers d) Flash drives

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Answer: d Answer: b
Explanation: The fastest data access is Explanation: The secondary memory is the
provided using registers as these memory slowest memory device.
locations are situated inside the processor.
9. In the memory hierarchy, as the speed of
5. The memory which is used to store the operation increases the memory size also

.c
copy of data or instructions stored in larger increases.
memories, inside the CPU is called _______ a) True
a) Level 1 cache b) False
b) Level 2 cache

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c) Registers Answer: b
d) TLB Explanation: As the speed of operation
increases the cost increases and the size
Answer: a decreases.
pa
Explanation: These memory devices are
generally used to map onto the data stored in 10. If we use the flash drives instead of the
the larger memories. harddisks, then the secondary storage can go
above primary memory in the hierarchy.
6. The larger memory placed between the a) True
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primary cache and the memory is called b) False
______
a) Level 1 cache Answer: b
b) Level 2 cache Explanation: The flash drives will increase
c) EEPROM the speed of transfer but still it won’t be faster
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d) TLB than primary memory.

Answer: b
Explanation: This is basically used to
TOPIC 4.2 MEMORY CHIP
provide effective memory mapping. ORGANIZATION
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7. The next level of memory hierarchy after 1. Any electronic holding place where data
the L2 cache is _______ can be stored and retrieved later whenever
a) Secondary storage required is ____________
w

b) TLB a) memory
c) Main memory b) drive
d) Register c) disk
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d) circuit
Answer: d
Explanation: None. Answer: a
Explanation: Memory is the place where data
can be stored and later retrieved. Memory can

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be of classified into register, cache, main Answer: a

memory, etc. Explanation: The size of the main memory
depends on the size of the address bus of the
2. Cache memory is the onboard storage. CPU. The main memory mainly consists of
a) True RAM and ROM, where RAM contains the
b) False current data and programs and ROM contains

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permanent programs like BIOS.
Answer: a
Explanation: Cache Memory is the memory 6. Which of the following is independent of
closest to the CPU. Registers, Cache and the the address bus?
main memory are the means of onboard a) Secondary memory
storage in the computer system. b) Main memory
c) Onboard memory

.c
3. Which of the following is the fastest means d) Cache memory
of memory access for CPU?
a) Registers Answer: a
b) Cache Explanation: The secondary memory is

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c) Main memory independent of the address bus. It increases
d) Virtual Memory the storage space. It is implemented in the
form of magnetic storage devices.
Answer: a
pa
Explanation: Registers are the fastest means
of access for CPU. Registers are the small
7. ____________ storage is a system where a
robotic arm will connect or disconnect off-
memory locations which are present closest to line mass storage media according to the
the CPU. computer operating system demands.
a) Secondary
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4. The memory implemented using the b) Virtual
semiconductor chips is _________ c) Tertiary
a) Cache d) Magnetic
b) Main
c) Secondary Answer: c
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d) Registers Explanation: The tertiary storage is the

correct option. It is used in the realms of
Answer: b enterprise storage and scientific computing on
Explanation: The main memory is large computer systems and business
implemented using semiconductor chips. computer networks and is something a typical
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Main memory is located on the motherboard. personal computer never sees firsthand.
It mainly consists of RAM and small amount
of ROM. 8. What is the location of the internal
registers of CPU?
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5. Size of the ________ memory mainly a) Internal

depends on the size of the address bus. b) On-chip
a) Main c) External
w

b) Virtual d) Motherboard
c) Secondary
d) Cache Answer: b
Explanation: The internal registers are
present on-chip. They are therefore present

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inside the CPU. L1 cache is also present on- a) True

chip inside the CPU. b) False

9. MAR stands for ___________ Answer: b

a) Memory address register Explanation: The Cache memory is
b) Main address register implemented using the SRAM chips and not

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c) Main accessible register the DRAM chips. SRAM stands for Static
d) Memory accessible register RAM. It is faster and is expensive.

Answer: a 3. Whenever the data is found in the cache

Explanation: The MAR stands for memory memory it is called as _________
address register. It holds the address of the a) HIT
active memory location. b) MISS

.c
c) FOUND
10. If M denotes the number of memory d) ERROR
locations and N denotes the word size, then
an expression that denotes the storage Answer: a

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capacity is ______________ Explanation: Whenever the data is found in
a) M*N the cache memory, it is called as Cache HIT.
b) M+N CPU first checks in the cache memory since it
c) 2M+N is closest to the CPU.
d) 2M-N
pa 4. LRU stands for ___________
Answer: a a) Low Rate Usage
Explanation: Storage capacity is the product b) Least Rate Usage
of a number of memory locations that is the c) Least Recently Used
jin
number of words and the word size or the d) Low Required Usage
number of bits stored per location. Storage
capacity should be as large as possible. Answer: c
Explanation: LRU stands for Least Recently
Used. LRU is a type of replacement policy
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TOPIC 4.3 CACHE MEMORY used by the cache memory.

1. What is the high speed memory between 5. When the data at a location in cache is
the main memory and the CPU called? different from the data located in the main
a) Register Memory memory, the cache is called _____________
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b) Cache Memory a) Unique

c) Storage Memory b) Inconsistent
d) Virtual Memory c) Variable
d) Fault
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Answer: b
Explanation: It is called the Cache Memory. Answer: b
The cache memory is the high speed memory Explanation: The cache is said to be
w

between the main memory and the CPU. inconsistent. Inconsistency must be avoided
as it leads to serious data bugs.
2. Cache Memory is implemented using the
DRAM chips. 6. Which of the following is not a write
policy to avoid Cache Coherence?

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a) Write through sign bit, 8 bits for the exponent and 23 bits
b) Write within for the mantissa.
c) Write back
d) Buffered write 10. The transfer between CPU and Cache is
______________
Answer: b a) Block transfer

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Explanation: There is no policy which is b) Word transfer
called as the write within policy. The other c) Set transfer
three options are the write policies which are d) Associative transfer
used to avoid cache coherence.
Answer: b
7. Which of the following is an efficient Explanation: The transfer is a word transfer.
method of cache updating? In the memory subsystem, word is transferred

.c
a) Snoopy writes over the memory data bus and it typically has
b) Write through a width of a word or half-word.
c) Write within
d) Buffered write

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TOPIC 4.4 VIRTUAL MEMORY
Answer: a
Explanation: Snoopy writes is the efficient 1. Because of virtual memory, the memory
method for updating the cache. In this case, can be shared among ____________
pa
the cache controller snoops or monitors the
operations of other bus masters.
a) processes
b) threads
c) instructions
8. In ____________ mapping, the data can be d) none of the mentioned
mapped anywhere in the Cache Memory.
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a) Associative Answer: a
b) Direct Explanation: None.
c) Set Associative
d) Indirect 2. _____ is the concept in which a process is
copied into the main memory from the
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Answer: a secondary memory according to the

Explanation: This happens in the associative requirement.
mapping. In this case, a block of data from a) Paging
the main memory can be mapped anywhere in b) Demand paging
the cache memory. c) Segmentation
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d) Swapping
9. The number of sign bits in a 32-bit IEEE
format is ____ Answer: b
a) 1 Explanation: None.
w

b) 11
c) 9 3. The pager concerns with the
d) 23 ____________
a) individual page of a process
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Answer: a b) entire process

Explanation: There is only 1 sign bit in all c) entire thread
the standards. In a 32-bit format, there is 1 d) first page of a process

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Answer: a d) counting based page replacement

Explanation: None. algorithm

4. Swap space exists in ____________ Answer: c

a) primary memory Explanation: None.
b) secondary memory

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c) cpu 9. A process is thrashing if ____________
d) none of the mentioned a) it is spending more time paging than
executing
Answer: b b) it is spending less time paging than
Explanation: None. executing
c) page fault occurs
5. When a program tries to access a page that d) swapping can not take place

.c
is mapped in address space but not loaded in
physical memory, then ____________ Answer: a
a) segmentation fault occurs Explanation: None.
b) fatal error occurs

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c) page fault occurs 10. Working set model for page replacement
d) no error occurs is based on the assumption of ____________
a) modularity
Answer: c b) locality
Explanation: None.
pa c) globalization
d) random access
6. Effective access time is directly
proportional to ____________ Answer: b
a) page-fault rate Explanation: None.
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b) hit ratio
c) memory access time
d) none of the mentioned
TOPIC 4.5 PARALLEL BUS
ARCHITECTURES
Answer: a
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Explanation: None. 1. The main virtue for using single Bus

structure is ____________
7. In FIFO page replacement algorithm, when a) Fast data transfers
a page must be replaced ____________ b) Cost effective connectivity and speed
a) oldest page is chosen c) Cost effective connectivity and ease of
b) newest page is chosen
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attaching peripheral devices

c) random page is chosen d) None of the mentioned
d) none of the mentioned
Answer: c
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Answer: a Explanation: By using a single BUS

Explanation: None. structure we can minimize the amount of
hardware (wire) required and thereby
8. Which algorithm chooses the page that has
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reducing the cost.

not been used for the longest period of time
whenever the page required to be replaced? 2. ______ are used to overcome the
a) first in first out algorithm difference in data transfer speeds of various
b) additional reference bit algorithm devices.
c) least recently used algorithm

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a) Speed enhancing circuitory b) American National Standard Interface

b) Bridge circuits c) American Network Standard Interfacing
c) Multiple Buses d) American Network Security Interrupt
d) Buffer registers
Answer: a
Answer: d Explanation: None.

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Explanation: By using Buffer registers, the
processor sends the data to the I/O device at 7. _____ register Connected to the Processor
the processor speed and the data gets stored in bus is a single-way transfer capable.
the buffer. After that the data gets sent to or a) PC
from the buffer to the devices at the device b) IR
speed. c) Temp
d) Z

.c
3. To extend the connectivity of the processor
bus we use ________ Answer: d
a) PCI bus Explanation: The Z register is a special
b) SCSI bus register which can interact with the processor

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c) Controllers BUS only.
d) Multiple bus
8. In multiple Bus organisation, the registers
Answer: a are collectively placed and referred as ______
pa
Explanation: PCI BUS is used to connect
other peripheral devices that require a direct
a) Set registers
b) Register file
connection with the processor. c) Register Block
d) Map registers
4. IBM developed a bus standard for their line
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of computers ‘PC AT’ called _____ Answer: b
a) IB bus Explanation: None.
b) M-bus
c) ISA 9. The main advantage of multiple bus
d) None of the mentioned organisation over a single bus is _____
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a) Reduction in the number of cycles for

Answer: c execution
Explanation: None. b) Increase in size of the registers
c) Better Connectivity
5. The bus used to connect the monitor to the d) None of the mentioned
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CPU is ______
a) PCI bus Answer: a
b) SCSI bus Explanation: None.
c) Memory bus
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d) Rambus 10. The ISA standard Buses are used to

connect ___________
Answer: b a) RAM and processor
b) GPU and processor
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Explanation: SCSI BUS is usually used to

connect video devices to the processor. c) Harddisk and Processor
d) CD/DVD drives and Processor
6. ANSI stands for __________
a) American National Standards Institute Answer: c
Explanation: None.

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TOPIC 4.6 INTERNAL a) True

b) False
COMMUNICATION
METHODOLOGIES Answer: a
Explanation: The statement is true. Both
1. Which of these is the external sounds encoding and decoding of message are

om
present in the channels of communication? influenced by our emotions. Emotions play a
a) Noise very important role in our lives.
b) Semantic problems
5. In which of these problems, is the actual
c) Cultural barriers
message lost in the abundance of transmitted
d) Over communication
information?
Answer: a a) Selecting perception

.c
Explanation: Noise is the external sounds b) Over communication
present in the channels of communication, c) Under communication
which results in the reduction of the audibility d) Filtering

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or omission of some words from the message.
Answer: b
2. Which of these should not be avoided for Explanation: In the case of over
effective communication? communication, the actual message is lost in
the jungle of information whereas in under
a) Noise
b) Planning
c) Semantic problems
pa communication the sender is blamed for
sharing less information.
d) Wrong assumptions
6. Communication should serve as a conflict-
Answer: b reduction exercise.
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Explanation: Lack of planning must be a) True
avoided for effects communication. There are b) False
innumerable examples of people who would
Answer: a
give an ill planned, long winding lecture
Explanation: The statement is true.
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while a short presentation with tables or

Communication should serve as a conflict-
graphs would be sufficient.
reduction exercise. When people start
3. __________ are problems arising from competing for the fulfillment of their narrow
expression. interests communication suffers.
a) Cultural barriers
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7. _______ means to impart understanding of

b) Semantic problems
the message.
c) Wrong assumptions
a) Encoding
d) Selecting perception
b) Receiver
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Answer: b c) Decoding
Explanation: The correct statement is: d) Feedback
Semantic problems are problems arising from
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Answer: c
expression or transmission of meaning in
Explanation: The correct statement is:
communication.
Decoding means to impart understanding of
4. Both encoding and decoding of message the message. Receiver has to identify the
are influenced by our emotions. person, words symbols, etc..

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8. When is the communication process Answer: b

complete? Explanation: In order to ensure an effective
a) When the sender transmits the message communication one must take care of ten
b) When the message enters the channel commandments: Clarity in language, home
c) When the message leaves the channel communication skills, listen attentively, etc..
d) When the receiver understands the

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message.
TOPIC 4.7 SERIAL BUS
Answer: d ARCHITECTURES
Explanation: Communication is complete
only when the receiver understands the 1. The main virtue for using single Bus
message. Many communication problems structure is ____________
arise because of misunderstandings. a) Fast data transfers

.c
b) Cost effective connectivity and speed
9. ______ is the first enemy of c) Cost effective connectivity and ease of
communication. attaching peripheral devices
a) Noise

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d) None of the mentioned
b) Clarity
c) Politeness Answer: c
d) Completeness pa Explanation: By using a single BUS
structure we can minimize the amount of
Answer: a hardware (wire) required and thereby
Explanation: The correct statement is: Noise reducing the cost.
is the first and foremost enemy of
communication. Every possible effort must be 2. ______ are used to overcome the
made to eliminate the element of noise that difference in data transfer speeds of various
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distorts communication. devices.
a) Speed enhancing circuitory
10. Which of these must be avoided for b) Bridge circuits
effective communication? c) Multiple Buses
a) Sharing of activity
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d) Buffer registers
b) Listening
c) Ambiguity Answer: d
d) Politeness Explanation: By using Buffer registers, the
processor sends the data to the I/O device at
Answer: c the processor speed and the data gets stored in
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Explanation: Ambiguity must be avoided. the buffer. After that the data gets sent to or
Clarity and crispness of the message is very from the buffer to the devices at the device
important. The sender of the message should speed.
be careful to see that the receiver does not
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have to go beyond the text of the message. 3. To extend the connectivity of the processor
bus we use ________
11. Which of these is not a commandment of a) PCI bus
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effective communication? b) SCSI bus

a) Clarity in language c) Controllers
b) Listen poorly d) Multiple bus
c) Home communication skills
d) Adequate medium

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Answer: a a) Set registers

Explanation: PCI BUS is used to connect b) Register file
other peripheral devices that require a direct c) Register Block
connection with the processor. d) Map registers

4. IBM developed a bus standard for their line Answer: b

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of computers ‘PC AT’ called _____ Explanation: None.
a) IB bus
b) M-bus 9. The main advantage of multiple bus
c) ISA organisation over a single bus is _____
d) None of the mentioned a) Reduction in the number of cycles for
execution
Answer: c b) Increase in size of the registers

.c
Explanation: None. c) Better Connectivity
d) None of the mentioned
5. The bus used to connect the monitor to the
CPU is ______ Answer: a

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a) PCI bus Explanation: None.
b) SCSI bus
c) Memory bus 10. The ISA standard Buses are used to
d) Rambus connect ___________

Answer: b
pa a) RAM and processor
b) GPU and processor
Explanation: SCSI BUS is usually used to c) Harddisk and Processor
connect video devices to the processor. d) CD/DVD drives and Processor
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6. ANSI stands for __________ Answer: c
a) American National Standards Institute Explanation: None.
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
TOPIC 4.8 MASS STORAGE
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Answer: a 1. Tertiary storage is built with

Explanation: None. ____________
a) a lot of money
7. _____ register Connected to the Processor b) unremovable media
bus is a single-way transfer capable. c) removable media
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a) PC d) secondary storage
b) IR
c) Temp Answer: c
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d) Z Explanation: None.

Answer: d 2. Floppy disks are examples of

Explanation: The Z register is a special ____________
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register which can interact with the processor a) primary storage

BUS only. b) secondary storage
c) tertiary storage
8. In multiple Bus organisation, the registers d) none of the mentioned
are collectively placed and referred as ______

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Answer: c Answer: b
Explanation: None. Explanation: None.

3. What is a magneto-optic disk? 8. A tape holds _______ data than optical or

a) primary storage magnetic disk cartridge.
b) secondary storage a) lesser

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c) removable disk b) more
d) none of the mentioned c) much lesser
d) none of the mentioned
Answer: c
Explanation: None. Answer: b
Explanation: None.
4. The magneto-optic head flies ___________

.c
the disk surface than a magnetic disk head 9. Random access to tape is _______ a disk
does. seek.
a) much farther from a) much slower than
b) much closer to b) much faster than

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c) at the same distance as c) comparable to
d) none of the mentioned d) none of the mentioned

Answer: a Answer: a
Explanation: None.
pa Explanation: None.

5. Optical disks ______ magnetism. 10. A typical tape drive is ________ a typical
a) use disk drive.
b) do not use a) more expensive than
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c) may use b) cheaper than
d) none of the mentioned c) of the same cost as
d) none of the mentioned
Answer: b
Explanation: None. Answer: a
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Explanation: None.
6. The phase change disk is coated with a
material that can freeze into either _______ 11. The surface area of tape is ________ the
or ________ state. surface area of a disk.
a) crystalline, solid a) much lesser than
b) ice, amorphous b) much larger than
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c) crystalline, liquid c) equal to

d) crystalline, amorphous d) none of the mentioned
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Answer: d Answer: b
Explanation: None. Explanation: None.

7. WORM stands for ____________

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a) write only, read mandatory TOPIC 4.9 INPUT AND OUTPUT

b) write once, read many times DEVICES.
c) write only once, read multiple
d) none of the mentioned

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1. Input Devices that use a special ink that predefined set of characters and print one line
contains magnetizable particles of iron oxide at a time. Drum plotters is an ideal device for
are ____ architects and others who need to generate
a) Optical disks high-precision hard copy graphics output of
b) Magnetic disks widely varying sizes.
c) MICR

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d) Magnetic drives 5. Name the device that converts text
information into spoken sentences.
Answer: c a) Speech Sensors
Explanation: MICR reads data on cheques b) Compact convertors
and sorts them for distribution to other banks c) Speech Synthesizers
or for further processing. MICR stands for d) Voice systems
Magnetic-Ink-Character Recognition.

.c
Answer: c
2. MICR character set consists of only 2 Explanation: A speech synthesizer converts
digits 0 and 1. text information into spoken sentences. It is
a) True used for reading out text information to blind

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b) False people. Allowing people to communicate
effectively.
Answer: b
Explanation: The statement is false. It 6. Which of the following is not a part of a
pa
consists of numerals from 0 to 9 and 4 special
characters. It supports only 14 symbols.
digitizer?
a) Digitizing tablet
b) Cursor
3. A printer that prints one line at a time and c) Stick
has a predefined set of characters is called d) Stylus
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_______
a) Laser Answer: c
b) Drum Explanation: A digitizer consists of a
c) Inkjet digitizing tablet, a stylus in the form of a
d) Impact cross-hair cursor. A digitizer is used in the
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areas of GIS.
Answer: b
Explanation: The drum printers print one line 7. Which is the device used for converting
at a time. They have a cylindrical drum with maps, pictures and drawings into digital form
characters embossed on its surface in the for storage in computers?
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form of circular bands. a) Digitizer

b) Scanner
4. Which of the following is a name of plotter c) Image Scanner
as well as a printer? d) MICR
w

a) Flatbed
b) Laser Answer: a
c) Drum Explanation: A digitizer serves the purpose
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d) Impact given in the question. Digitizers are generally

used in the area of Computer Aided Design
Answer: c by architects and engineers to design cars,
Explanation: Drum is the name of a plotter buildings, etc.
as well as a printer. Drum printers have a

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8. The process in which a file is partitioned

into smaller parts and different parts are
ARCHITECTURE
stored in different disks is called _________
a) RAID TOPIC 5.1 PARALLEL
b) Mirroring PROCESSING
c) Stripping
ARCHITECTURES AND

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d) RAID classification
CHALLENGES
Answer: c
Explanation: Enhanced reliability is achieved 1. Execution of several activities at the same
by using techniques like mirroring and time.
stripping in case of disk arrays. Stripping is a) processing
the division of a large file into smaller parts b) parallel processing

.c
and then storing them on different disks. c) serial processing
d) multitasking
9. Which of the following Printers have a
speed in the range of 40-300 characters per

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Answer: b
second? Explanation: Execution of several activities
a) Inkjet at the same time is referred to as parallel
b) Laser pa processing. Like, Two multiplications at the
c) Dot matrix same time on 2 different processes.
d) Drum
2. Parallel processing has single execution
Answer: a flow.
Explanation: The inkjet printers are non- a) True
impact printers. Hence, they cannot produce b) False
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multiple copies of a document in a single
printing. Can be both monochrome and color. Answer: b
Explanation: The statement is false.
10. Which of the following is a temporary Sequential programming specifically has
output?
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single execution flow.

a) Hard copy
b) Soft copy 3. A term for simultaneous access to a
c) Duplicate copy resource, physical or logical.
d) On paper a) Multiprogramming
b) Multitasking
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Answer: b c) Threads
Explanation: There are only two types of d) Concurrency
outputs: hard copy and soft copy. Soft copy
output is temporary and vanishes after use. Answer: d
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Hard copy output is permanent in nature and Explanation: Concurrency is the term used
can be kept in paper files, etc. for the same. When several things are
accessed simultaneously, the job is said to be
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concurrent.

4. ______________ leads to concurrency.

UNIT V ADVANCED a) Serialization
COMPUTER b) Parallelism

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c) Serial processing c) Scalabilty

d) Distribution d) Effectiveness

Answer: b Answer: c
Explanation: Parallelism leads naturally to Explanation: The measure of the “effort”
Concurrency. For example, Several processes needed to maintain efficiency while adding

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trying to print a file on a single printer. processors is called as scalabilty.

5. A parallelism based on increasing 9. The rate at which the problem size need to
processor word size. be increased to maintain efficiency.
a) Increasing a) Isoeffciency
b) Count based b) Efficiency
c) Bit based c) Scalabilty

.c
d) Bit level d) Effectiveness

Answer: d Answer: a
Explanation: Bit level parallelism is based on Explanation: Isoefficiency is the rate at

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increasing processor word size. It focuses on which the problem size need to be increased
hardware capabilities for structuring. to maintain efficiency.

6. A type of parallelism that uses micro 10. Several instructions execution

architectural techniques.
a) instructional
pa simultaneously in ________________
a) processing
b) bit level b) parallel processing
c) bit based c) serial processing
d) increasing d) multitasking
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Answer: a Answer: b
Explanation: Instructional level uses micro Explanation: In parallel processing, the
architectural techniques. It focuses on several instructions are executed
program instructions for structuring. simultaneously.
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7. MIPS stands for?

a) Mandatory Instructions/sec TOPIC 5.2 HARDWARE
b) Millions of Instructions/sec MULTITHREADING
c) Most of Instructions/sec
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d) Many Instructions / sec 1. Multithreading is also called as

____________
Answer: b a) Concurrency
Explanation: MIPS stands for Millions of b) Simultaneity
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Instructions/sec. MIPS is a way to measure c) Crosscurrent

the cost of computing. d) Recurrent
8. The measure of the “effort” needed to
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Answer: a
maintain efficiency while adding processors. Explanation: Concurrency is often used in
a) Maintainablity place of multithreading. Multitasking allows
b) Efficiency multiple threads to run at a time.

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2. Multiprocessing allows single processor to b) start()

run several concurrent threads. c) stop()
a) True d) paint()
b) False
Answer: a
Answer: a Explanation: run()method must be

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Explanation: The statement is false. overridden (It is similar to main method of
Multitasking allows single processor to run sequential program).
several concurrent threads.
7. An interface that is implemented while
3. A single sequential flow of control within a using threads.
program is ________ a) java.lang.Run
a) Process b) java.lang.Runnable

.c
b) Task c) java.lang.Thread
c) Thread d) java.lang.Threads
d) Structure
Answer: b

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Answer: c Explanation: java.lang.Runnable is correct.
Explanation: A thread is a sequential flow of Any thread class implements runnable.
control within a program. Single-threaded
program can handle one task at any time. 8. A thread becomes non runnable when?
pa
4. Both client and server release _________
a) Its stop method is invoked
b) Its sleep method is invoked
connection after a page has been transferred. c) Its finish method is invoked
a) IP d) Its init method is invoked
b) TCP
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c) Hyperlink Answer: b
d) Network Explanation: A thread becomes Not
Runnable when one of these events occurs:
Answer: b • Its sleep method is invoked.
Explanation: The answer is TCP. TCP stands • The thread calls the wait method to wait for
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for Transmission Control Protocol. Servers a specific condition to be satisfied.

receive requests from clients. • The thread is blocking on I/O.

5. Java extension used in threads? 9. A method used to temporarily release time

a) java.lang.Thread for other threads.
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b) java.language.Thread a) yield()
c) java.lang.Threads b) set()
d) java.Thread c) release()
d) start()
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Answer: a
Explanation: java.lang.Thread is the class Answer: a
that is extended if any user wants to extend Explanation: We can use the yield() method
w

threads. to temporarily release time for other threads.

It is static by default.
6. A method that must be overridden while
extending threads. 10. A method used to force one thread to wait
a) run() for another thread to finish.

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a) join() 4. In the Many to One model, multiple

b) connect() threads are unable to run in parallel on
c) combine() multiprocessors because of ___________
d) concat() a) only one thread can access the kernel at a
time
Answer: a b) many user threads have access to just one

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Explanation: The answer is join(). We can kernel thread
use the join() method to force one thread to c) there is only one kernel thread
wait for another thread to finish. d) none of the mentioned

Answer: a
TOPIC 5.3 MULTICORE AND Explanation: None.
SHARED MEMORY

.c
MULTIPROCESSORS 5. The One to One model allows
___________
1. The model in which one kernel thread is a) increased concurrency
b) decreased concurrency

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mapped to many user-level threads is called
___________ c) increased or decreased concurrency
a) Many to One model d) concurrency equivalent to other models
b) One to Many model
Answer: a
c) Many to Many model
d) One to One model
pa Explanation: None.

6. In the One to One model when a thread

Answer: a
makes a blocking system call ___________
Explanation: None.
a) other threads are strictly prohibited from
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2. The model in which one user-level thread running
is mapped to many kernel level threads is b) other threads are allowed to run
called ___________ c) other threads only from other processes are
a) Many to One model allowed to run
d) none of the mentioned
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b) One to Many model

c) Many to Many model
Answer: b
d) One to One model
Explanation: None.
Answer: b
7. Which of the following is the drawback of
Explanation: None.
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the One to One Model?

3. In the Many to One model, if a thread a) increased concurrency provided by this
makes a blocking system call ___________ model
a) the entire process will be blocked b) decreased concurrency provided by this
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b) a part of the process will stay blocked, with model

the rest running c) creating so many threads at once can crash
c) the entire process will run the system
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d) none of the mentioned d) creating a user thread requires creating the

corresponding kernel thread
Answer: a
Explanation: None. Answer: d
Explanation: None.

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8. When is the Many to One model at an Answer: d

advantage? Explanation: Input devices positional
a) When the program does not need information to the system they often called
multithreading pointing devices.
b) When the program has to be multi-
threaded 2. The number of pixels stored in the frame

om
c) When there is a single processor buffer of a graphics system is known as
d) None of the mentioned a) Resolution
b) Depth
Answer: a c) Resalution
Explanation: None. d) Only a

9. In the Many to Many model true Answer: d

.c
concurrency cannot be gained because Explanation: Number of pixels determines
___________ the resolution .
a) the kernel can schedule only one thread at
a time 3. In graphical system, the array of pixels in

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b) there are too many threads to handle the picture are stored in
c) it is hard to map threads with each other a) Memory
d) none of the mentioned b) Frame buffer
c) Processor
Answer: a
Explanation: None.
pa d) All of the mentioned

Answer: a
10. In the Many to Many models when a Explanation: Frame buffer is mainly used to
thread performs a blocking system call store pixels.
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___________
a) other threads are strictly prohibited from 4. Heat supplied to the cathode by directing a
running current through a coil of wire is called
b) other threads are allowed to run a) Electron gun
c) other threads only from other processes are b) Electron beam
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allowed to run c) Filament

d) none of the mentioned d) Anode and cathode

Answer: b Answer: c
Explanation: None. Explanation: In CRT the filament is
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responsible for supply of power.

TOPIC 5.4 INTRODUCTION TO 5. The maximum number of points that can
GRAPHICS PROCESSING be displayed without overlap on a CRT is
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UNITS referred as
a) Picture
b) Resolution
1. Which devices provides positional
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c) Persistence
information to the graphics system ?
d) Neither b nor c
a) Input devices
b) Output devices Answer: b
c) Pointing devices Explanation: none.
d) Both a and c

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6.________ stores the picture information as 10. Which display devices allows us to walk
a charge distribution behind the phosphor- around an object and view it from different
coated screen. sides.
a) Cathode ray tube a) Direct view storage tubes
b) Direct-view storage tube b) Three-dimensional devices
c) Flat panel displays c) Flat panel display devices

om
d) 3D viewing device d) Plasma panel display devices

Answer: b Answer: b
Explanation: Instead of refreshing, DVST Explanation: 3D display devices allows user
stores the picture information behind the to view the object from different sides.
screen.
11. In LCD, the refresh rate of the screen is

.c
7. The devices which converts the electrical a) 60 frames/sec
energy into light is called b) 80 frames/sec
a) Liquid-crystal displays c) 30 frames/sec
b) Non-emitters d) 100 frames/sec

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c) Plasma panels
d) Emitters Answer: a
Explanation: LCD screen is refreshed at 60
Answer: d frames per second.
pa
Explanation: Emissive displays are devices
that convert electrical energy into light. 12. Random-scan system mainly designed for
a) Realistic shaded screen
8. In which system, the Shadow mask b) Fog effect
methods are commonly used c) Line-drawing applications
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a) Raster-scan system d) Only b
b) Random-scan system
c) Only b Answer: c
d) Both a and b Explanation: Random-scan system mainly
designed for Line-drawing applications.
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Answer: a
Explanation: Raster-scan system uses 13. The primary output device in a graphics
shadow-mask method because they produce system is_________
wide range of colors. a) Scanner
b) Video monitor
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9. The process of digitizing a given picture c) Neither a nor b

definition into a set of pixel-intensity for d) Printer
storage in the frame buffer is called
a) Rasterization Answer: b
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b) Encoding Explanation: The video monitor is the

c) Scan conversion commonly used output device.
d) True color system
14. On a black and white system with one bit
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Answer: c per pixel, the frame buffer is commonly

Explanation: The digitization process is called as
called scan conversion. a) Pix map
b) Multi map

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c) Bitmap c) Super computers

d) All of the mentioned d) Distributed systems

Answer: c Answer: d
Explanation: Bit map frame buffer is always Explanation: A distributed system is a
1 bit per pixel. computer system spread out over a

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geographic area.
15. Aspect ratio means
a) Number of pixels 4. The software which governs the group of
b) Ratio of vertical points to horizontal points computers is __________
c) Ratio of horizontal points to vertical points a) Driver Rd45
d) Both b and c b) Interface UI
c) Clustering middleware

.c
Answer: d d) Distributor
Explanation: none.
Answer: c
Explanation: The software helps to project a

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TOPIC 5.5 CLUSTERS AND single system image to the user.
WAREHOUSE SCALE
COMPUTERS 5. The simplest form of a cluster is
__________ approach.
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1. The set of loosely connected computers are
called as __________
a) Beowolf
b) Sequoia
a) LAN c) Stone
b) WAN d) None of the mentioned
c) Workstation
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Answer: a
d) Cluster
Explanation: None.
Answer: d
6. The cluster formation in which the work is
Explanation: In a computer cluster all the
divided equally among the systems is ______
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participating computers work together on a

a) Load-configuration
particular task.
b) Load-Division
2. Each computer in a cluster is connected c) Light head
using __________ d) Both Load-configuration and Load-
a) UTP Division
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b) Rj-45
Answer: a
c) STP
Explanation: This approach the work gets
d) Coaxial cable
divided among the systems equally.
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Answer: b
7. In the client server model of the cluster
Explanation: The computers are connected to
_________ approach is used.
each other using a LAN connector cable.
a) Load configuration
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3. The computer cluster architecture emerged b) FIFO

as a result of _________ c) Bankers algorithm
a) ISA d) Round robin
b) Workstation

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Answer: d Answer: b
Explanation: By using this approach the Explanation: It is referred to as a physical
performance of the cluster can be enhanced. LAN topology. LAN stands for Local Area
Network.
8. The beowolf structure follows the
__________ approach of a relationship 2. Bus is a type of topology.

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between the systems. a) True
a) Master-slave b) False
b) Asynchronous
c) Synchronous Answer: a
d) Isochronous Explanation: The statement is true. Bus
topology is an arrangement where all nodes
Answer: a are interconnected using a single-cable.

.c
Explanation: None.
3. _____ LAN topology describes the
9. The most common modes of possible connections between pairs of
communication in clusters are ______ networked end-points that can communicate.

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a) Message queues a) Complex
b) Message passing interface b) Physical
c) PVm c) Logical
d) Both Message passing interface and PVm d) Incremental

Answer: d
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Explanation: None. Explanation: A logical LAN topology
describes the possible connections. LAN
10. The method followed in case of node stands for Local Area Network.
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failure, wherein the node gets disabled is
_________ 4. A term that refers to the way in which the
a) STONITH nodes of a network are linked together.
b) Fibre channel a) network
c) Fencing b) topology
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d) None of the mentioned c) connection

d) interconnectivity
Answer: a
Explanation: None. Answer: b
Explanation: Topology is a term that refers
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to the way in which the nodes are connected.

TOPIC 5.6 INTRODUCTION TO There are 4 major topology networks.
MULTIPROCESSOR NETWORK
TOPOLOGIES. 5. A network comprising o multiple
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topologies.
1. A topology that is responsible for a) Complex
describing the geometric arrangement of b) Hybrid
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components that make up the LAN. c) Bus

a) Complex d) Star
b) Physical
Answer: b
c) Logical
Explanation: A hybrid network consists of
d) Incremental

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multiple topologies. It can comprise a ring, a c) Two-tiered

star and other topologies. We call this d) Three-tiered
arrangement as a hybrid network.
Answer: b
6. The participating computers in a network Explanation: A peer-to-peer WAN topology
are referred to as: is a relatively simple way of interconnecting a

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a) Clients small number of sites. It has the least-cost
b) Servers solution for WANs that contain a small
c) Nodes number of internetworked locations.
d) CPUs
9. A serially connected system of all the hubs
Answer: c of networks.
Explanation: They are referred to as the a) Bus

.c
nodes. There are several topologies designed b) Ring
for arrangements of these nodes like bus, star, c) Daisy chains
etc. d) Star

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7. A topology that involves Tokens. Answer: c
a) Star Explanation: The correct option is Daisy
b) Ring chain. This simple approach uses ports on
c) Bus existing hubs for interconnecting the hubs.
d) Daisy Chaining
pa 10. A piece of information which is sent
Answer: b along with the data to the source computer.
Explanation: Ring topology involves sending a) data
and receiving of data with the help of tokens. b) module
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Ring started out as a simple peer-to-peer c) token
LAN topology. d) element

8. A ____________WAN can be developed Answer: c

using leased private lines or any other Explanation: Token is the information that is
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transmission facility sent to the source computer along with the

a) Hybrids data. This token is then passed to the next
b) peer-to-peer node.
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