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VLSI DESIGN Bit Paper

The document is an exam for a VLSI Design course. It contains 20 multiple choice and fill in the blank questions testing knowledge of topics like CMOS fabrication processes, characteristics of different transistor technologies like MOSFETs and Bipolar Junction Transistors, and concepts in VLSI like integration scales. The questions cover topics such as the p-well CMOS fabrication process, advantages and disadvantages of different technologies, steps in IC manufacturing, applications of CMOS and MOSFETs, definitions of VLSI, causes of latchup in CMOS circuits, and characteristics of inverters.

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359 views2 pages

VLSI DESIGN Bit Paper

The document is an exam for a VLSI Design course. It contains 20 multiple choice and fill in the blank questions testing knowledge of topics like CMOS fabrication processes, characteristics of different transistor technologies like MOSFETs and Bipolar Junction Transistors, and concepts in VLSI like integration scales. The questions cover topics such as the p-well CMOS fabrication process, advantages and disadvantages of different technologies, steps in IC manufacturing, applications of CMOS and MOSFETs, definitions of VLSI, causes of latchup in CMOS circuits, and characteristics of inverters.

Uploaded by

venkiscribd444
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

IV B.Tech. I Sem., I Mid-Term Examinations, December - 2020


VLSI DESIGN
[Branch: ECE]
Objective Exam
Name: Hall Ticket No. A
Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.

I. Choose the correct alternative:

1. In the p-well process of CMOS fabrication substrate is used. [ ]


a)P-type b)N-type c) C-type d) none

2. Main drawback of BICMOS technology [ ]


a)Low speed b)Higher power dissipation c) High cost d)High speed

3. Steps involved in manufacturing of IC [ ]


a)Oxidation b) Photolithography c)Ion implantation d)all

4. is ideally suited for applications using battery power or battery backup power. [ ]
a) MOS b) P-MOS c) N-MOS d) CMOS

5. Identify different CMOS technologies [ ]


a) N-well process b) P-well process c) Twin-tub process d)all

6. VLSI means [ ]
a) a device containing transistors between 103 and 10 5

b) a device containing transistors between 105 and 107


c) a device containing transistors between 103 and 104
d) a device containing transistors between 105 and 109

7. Latch up problems occurs in CMOS circuits due to [ ]


a) Parasitic capacitance b) Parasitic bipolar transistors c) Parasitic resistance d)none

8. VLSI technology uses ________ to form integrated circuit. [ ]

a) Transistors b) switches c) diodes d) buffers

9. Medium scale integration has ____________ [ ]


a) ten logic gates b) fifty logic gates c) hundred logic gates d) thousands logic gates

10. The has a physical channel between the drain and source. [ ]
a)D-MOSFET b)E-MOSFET c)V-MOSFET d)None

Cont…..2
:2:

II Fill in the Blanks:

11. In basic NMOS Inverter circuit Gate is connected to _________

12. MOSFET is used as Current source or Voltage source _________


13. What is the ratio of Zp.u/Zp.d an inverter driven directly by another inverter_________

14. In bipolar transistor, which is terminal is heavily doped

15. In p-well CMOS fabrication well is formed.

16. Based on law number of transistors doubles for every 18 months.

17. CMOS transistor is combination of transistors.

18. Input impedance of MOS Transistor compared to BJT.

19. Steps involved in twin tub process

20. An inverter driven through one or more pass transistors has Zp.u /Zp.d ratio of

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