A NEW TEST PATTERN GENERATEOR BY ALTERING THE

STRUCTURE OF 2-D LFSR FOR BUILT IN SELF TEST

APPLICATION
S.H. Rasouli1, A. Afzali-Kusha1, A.Khadem-zadeh2, M.H. Tehranipour3, M. Nourani3
1
IC Design Laboratory, Electrical and Computer Engineering Dept., University of Tehran, Tehran,
Iran
2
Iran Telecom. Research Center (ITRC)
3
Department of Electrical Engineering, University of Texas at Dallas
Emails: [email protected], [email protected],[email protected], [email protected],
[email protected]

testing due to high cost of external test equipment. In

ABSTRACT many cases testing with the frequency of normal
In this paper a ROM-less deterministic test operation of circuit under test (CUT) is achievable
pattern generator (TPG) has been proposed for test with BIST but it is not practical with external testing.
per clock scheme. This TPG consists of a two In particular, some faults such as delay faults only
dimensional linear feedback shift register (2-D can be detected when testing is performed in normal
LFSR) and a controller. The controller configures the operating frequency of CUT.
structure of 2-D LFSR and it has a quite simple Testing in higher frequency leads to more power
structure and a very low area overhead. Simulated consumption compared to external testing. Therefore
annealing algorithm is used to find the coefficient several techniques have been proposed to minimize
matrix of 2-D LFSR. Test application time and power the power consumption during test mode. Reducing
consumption is significantly reduced using this the power consumption without sacrificing the fault
technique while keeping fault coverage at 100%. coverage and minimum area overhead of BIST circuit
Compared to the previous works, the proposed is the goal of a test designer. The main motivation for
method is able to generate a much larger set of considering power consumption during test
deterministic test vectors with approximately the application is that, power and energy of a digital
same number of flip flops. Experimental results are system are considerably higher in test mode than in
shown for ISCAS’85 benchmarks. normal mode. The reason is that test patterns cause as
many nodes switching as possible while a power
saving normal mode only activates a few modules at
1. INTRODUCTION the same time. Another reason is that successive
Test is one of the most complicated and costly functional input vectors applied to a given circuit
tasks in today’s VLSI. Modern design and package during normal mode have a significant correlation,
technologies make external testing more difficult. while the correlation between consecutive patterns
Built-in self-test (BIST) has emerged as a promising can be very low during test.
solution to the VLSI testing problem [2]. The cost of A test vector inhibiting technique to filter the non-
testing with BIST is very low compared to external detecting subsequences of a pseudo-random test
This work is supported by Iran Telecommunication sequence generated by an LFSR is presented in [2]. A
Research center (ITRC). decoding logic is used to store the first and last
vectors of the non-detecting subsequences to be
filtered and a D-type flip-flop working in the toggle others vectors. So the power consumption and the
mode is used to switch the enable/disable mode of the test application time increase due to generating non-
LFSR outputs in order to perform a selective filtering detecting vectors. In this paper a new TPG is
action. Reductions in the energy consumption are in proposed that consists of a new configurable 2-D
the range from 18% to 78% with a low cost in terms LFSR and a controller. The controller has a very
of area overhead of the BIST structure. An simple structure and its area overhead is very low. In
enhancement to this technique is proposed in [3], this structure a much more deterministic vectors can
where the filtering action is extended to all the non- be generated with the mainly same number of flip
detecting subsequences. The key idea is based on the flops.
unification of all the decoding logic modules. Energy This paper is organized as follows. In Section 2,
and average power consumption savings can reach a the structure of TPG is explained and compared with
level of 90% for some of the experimented previous work. The controller is described in Section
benchmarks [2]. 3. Section 4 discusses the experimental results. The
Yuan and Chen proposed a 2-D LFSR structure to paper ends with conclusions in Section 5.
be used as TPG [1]. Chen proposed a reconfigurable
2. STRUCTURE OF TPG
2-D LFSR that produces deterministic vectors and
used Branch and Bound algorithm for determining Conventional LFSR has a very simple structure as
the coefficient matrix of 2-D LFSR [5]. Multiplexer shown in Figure 1. It consists of D-type flip flops and
is used to choose the suitable structure. In the case of XORs. LFSR can be expressed with a polynomial
large circuits, when the number of test vectors shown in Equation 1. Feedback gi=1 when the
increases the size of 2-D LFSR significantly feedback exists, otherwise gi=0. The vectors can be
increases as well as the number and the size of determined when the polynomial and initial state are
multiplexers. To avoide large area overhead, vectors known. A deterministic set of patterns can not be
that detect resistant–pattern-faults is generated, and produced with LFSR unless a complicated controller
there is no control on generating the is used.

Equation 2. If aijk=1, the signal vjDK is connected to

XOR gate to generate Vi. if ci =0, the output of the
XOR gate is Connected to the shift register directly.
If ci =1, an inverter is added to the input of the shift
register for generating complementary feedback
signal. For finding the coefficient (aijk),
coefficient matrix of 2-DLFSR is determined using
Branch and Bound algorithm [5].

Figure 1: Conventional LFSR structure.

N −1
G(x) =1+g1x+g2x2+… + gN-1xN-1 =1+ ∑g x
i =1
i
i
(1)

The structure of 2-D LFSR is shown in Figure 2

and its equation is based on N primitive polynomial
is given in Equation 2. We can write Equation 2 in
another form as seen in Equation 3. A and B are
deterministic matrices and X is coefficient matrix.
The circuit consists of N shift register, each one has
M stages. Vi (i=1 to N) represents an N-bit vector and
ViDK (k=1 to M) represents the Kth delay of a vector
Figure 2. Structure of 2-D LFSR.
Vi . Vi is generated by feedback network given by
 N M maximum zero in matrix. The cost function for
V(i)= ∑ ∑a
j =1 k =1
ijk v j D + c i
k
i={1,…,N} (2) finding other matrices is defined based on maximum
similarity between coefficient matrices. Also when
A= X ×B (3) the number of inputs is high, partitioning is applied to
In previous work the depth of the 2-D LFSR is the inputs.
increased in the case of higher number of test vectors. For example, in C432 of ISCAS’85 benchmark,
Furthermore if number of vectors increases, the number of inputs is 36 and the number of test
multiplexers are used to generate the vectors and thus vectors is 27 for achieving 100% fault coverage. The
area overhead increases. The main idea is that the vectors are first rearranged for achieving minimum
vectors are partitioned into several sets and each set hamming distance between successive vectors. Then
is generated by choosing the corresponding 2-D inputs are partitioned into 4 sets, each contains of 9
LFSR structure as shown in Figure 3 therefore, the inputs. Then for each set, the corresponding vector is
area of 2-D LFSR increases due to the increase of the partitioned into 3 sets and the coefficients of 2-D
number of test vectors. To have an acceptable level of LFSR are determined for each set with simulated
area overhead, only the vectors that detect resistant- annealing. In Section 4, the simulation results based
faults are generated by using multiplexer and the on two cost functions (maximum zero and maximum
other vectors are generated randomly. similarity) are given. When the coefficient matrices
are determined, the state of each element is specified.
In the case of C432, there are three coefficient
matrices and eight states for each element. By
determining the state of elements, the suitable control
signal is applied to 2-D LFSR structure. If control
signal for one element is high, the output of related
flip flop is attached to the input of the corresponding
XOR gate. For example in C432, we have :
V5(IN1set1)=V 1D2+ V 3D2+ V 7D2+ V 9D2
V5(IN1set2)=V1D2+V2D+ V3D2+V4D+V5D+V5D2
+V7D2+ V9D +V9D2
Figure 3. Configurable 2-D LFSR. V5(IN1set3)=V1D2+V1D+V3D2+ V3D+ V4D2 +V5D2
+V7D2+V8D2 + V9D +V9D2
CU When we find the state of the element, we apply
the related control signal to the gate of the transistor
between two lines as shown in Figure 5.
N FFA CUT
CN (N*M)

N*M

Figure 4. Altering the coefficient matrix of 2-D

LFSR. Figure 5. Applying the signal control to 2-D LFSR .
In this work, vectors are partitioned into different 3. CONTROLLER STRUCTURE
sets and the coefficient matrix of corresponding 2-D
Control signal changes the coefficient of 2-D
LFSR is found using simulated annealing algorithm.
LFSR structure for producing the vector of related
If the coefficient matrices be similar to each other
set. Let’s explain the structure of controller in C432.
then the number of coefficients that must be changed
As mentioned in previous section, there are four input
is small. To achieve this aim, for finding the first
sets called IN1, IN2, IN3 and IN4. For each set of
coefficient matrix, cost function is defined based on
inputs, three sets of test vectors must be produced. c16. Furthermore, the states c9-c15 can be generated
Let’s assume that coefficient matrices for first input by inverting states c2-c8, so we only show c1-c8 in
set (IN1) are IN1A, IN1B, and IN1C. IN1A produces Figure 8.
the first set of test vectors for IN1 and IN1B produces
the second set of test vector for IN1, while IN1C A B C D
produces the third set. Assume that a(i,j) is an c1 0 0 0 0
element of coefficient matrix. There are eight states c2 0 0 0 1
for a(i,j) in three matrices is shown in the Figure 6: c3 0 0 1 0
c4 0 0 1 1
A B C Example to V5 c5 0 1 0 0
c1 0 0 0 {V2D2 ,V8D,V7D} c6 0 1 0 1
c2 0 0 1 {V1D,V3D} c7 0 1 1 0
c3 0 1 0 {V2D,V4D,V5D} c8 0 1 1 1
c4 0 1 1 {V5D2 ,V9D} Figure 8. States of coefficient matrix’s element when
c5 1 0 0 the number of sets is 4.
c6 1 0 1
c7 1 1 0
c8 1 1 1 {V1D2,V3D2,V7D2,V9D2 }
We can easily generate some of these states by
using OR gate. For example, c4=OR(c2,c3),
Figure 6. States of coefficient matrix’s element when c6=OR(c5,c2), c7=OR(c5,c3) and
the number of sets is 3. c8=OR(c5,c4)=OR(c2,c3,c4). It is obvious that we
only need to generate c2, c3 and c5 and the other
State c1 (c8) means that a(i,j) is never (all the control signals can be generated using OR gate. The
time) connected to the corresponding XOR input. control circuit is shown in Figure 9. In general, when
Therefore, no control signal is required for these there is N vector sets for each input set we only need
states and c1 and c8 can be removed from the list. It to generate c(i)=2i-1. The other signals are generated
is obvious that there are complement signals in using OR and inverter gates. The frequency of
Figure 6. c7 is complement of c2 and c6 is control circuit is 1/N of the operating frequency of
complement of c3. If we produce c2 and c3, we can the CUT, where N is the number of test vectors in
produce c6 and c7 with an inverter. Furthermore, if each set.
we use a 2-input OR gate and produce OR (c2,c3), c4
is generated and by inverting c4 generation of c5 is
completed. Therefore, we only need to generate c2
and c3. The structure of the controller is illustrated in
Figure 7.

Figure 9. Structure of controller when the number of

sets is 4.
4. SIMULATION RESULTS
Figure 7. Structure of controller when the number of sets is 3. We apply simulated annealing to the some of the
ISCAS’85 benchmarks. The test vectors are obtained
Let’s explore the controller structure when the using Synopsys [7]. Fault coverage is 100% for all
number of vector sets increases. Assume that for these benchmarks. Table 1 shows the result of the
input set of IN1, there are four vector sets IN1A, simulated annealing simulation for C432 benchmark.
IN1B, IN1C and IN1D. In this case, there are 16 This circuit has 36 inputs and the number of test
states for a(i,j). It is not necessary to generate c1 and vector to achieve 100% fault coverage is 27. The
second column shows the simulation results when the LFSR patterns whose generate 100% fault coverage.
cost function is based on maximum zero and the third Comparing the number of test patterns for these two
column shows the results when the cost function is LFSR’s indicates that the test application time of 2-D
based on maximum similarity between coefficient LFSR is extremely less than LFSR because the
matrices. number of test patterns of 2-D LFSR is much less
than LFSR’s. It also shows that the WSA (average
Table 1. Number of coefficient matrix in each state. and peak) for 2-D LFSR is significantly less than the
States Maximum Maximum WSA of a conventional LFSR.
Zero (A) Similarity (B)
000 269 257 5. SUMMARY AND CONCLUSION
001 89 92
010 80 88 A new TPG based on 2-D LFSR is proposed in
011 35 36 this paper. It has very low area overhead compared to
100 83 15 the previous work. A controller for changing the
101 32 34 coefficient matrix of 2-D LFSR is proposed that has
110 47 31
very simple structure and very low area overhead.
111 13 95
With this structure, the generating of every set of
As seen, the number of elements that do not have deterministic vectors is possible without using ROM.
transition is 282 in case A and 355 in case B. Simulations on ISCAS benchmark showed that the
Therefore the load of control circuit is less in case B. fault coverage is 100% and the power is significantly
So it is better that the coefficient matrix is determined reduced. It also reduces the number of test patterns
base on maximum similarity. and eventually the test application time compared to a
Table 2 shows the number of flip flops in TPG for conventional LFSR.
ISCAS’85 benchmarks. The second and third REFERENCES
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 Table 3: Implementation results.
LFSR 2-D LFSR
Circuits Np FC% WSAavg WSApeak Np FC% WSAavg WSApeak
C432 365 98.9 93 153 27 100 87 134
C499 495 99.2 128 203 52 100 93 184
C880 491 98.6 167 288 16 100 115 259
C1355 998 99.1 305 421 84 100 165 368
C3540 950 96.5 950 1278 84 100 832 1229
C6288 765 99.6 2034 2561 12 100 2011 2160