PD703003A, 703004A, 703025A: Mos Integrated Circuit
PD703003A, 703004A, 703025A: Mos Integrated Circuit
PD703003A, 703004A, 703025A: Mos Integrated Circuit
The µPD703003A, 703004A, and 703025A are members of the V850 Family TM of 32-bit single-chip microcontrollers
designed for real-time control operations. These microcontrollers provide on-chip features including a 32-bit CPU
core, ROM, RAM, an interrupt controller, a real-time pulse unit, a serial interface, an A/D converter, a D/A converter,
and PWM.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
FEATURES
• Number of instructions: 74
• Minimum instruction execution time: 30 ns (@ 33 MHz operation)
• General-purpose registers: 32 bits × 32 registers
• Instruction set optimized for control applications
• On-chip memory ROM: 256 KB ( µPD703025A)
128 KB ( µPD703003A)
96 KB (µPD703004A)
RAM: 8 KB ( µPD703025A)
4 KB (µPD703003A, 703004A)
• Advanced on-chip interrupt controller
• Real-time pulse unit suitable for control operations
• Powerful serial interface (on-chip dedicated baud rate generator)
• On-chip clock generator
• 10-bit resolution A/D converter: 8 channels
• 8-bit resolution D/A converter: 2 channels
• 8-/9-/10-/12-bit resolution PWM: 2 channels
• Power saving functions
APPLICATIONS
• AV: Camcorders, VCRs, etc.
• Office equipment: PPCs, LBPs, printers, etc.
• Industrial equipment: Motor controllers, NC machine tools, etc.
• Communications equipment: Mobile telephones, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
ORDERING INFORMATION
PIN CONFIGURATION
P22/TXD0/SO0
P26/RXD1/SI1
P23/RXD0/SI0
P14/INTP120
P12/TCLR12
P30/TO130
P11/TO121
P10/TO120
P21/PWM1
P20/PWM0
P27/SCK1
P24/SCK0
P77/ANI7
P76/ANI6
P13/TI12
AVREF1
AVDD
AVSS
NMI
VDD
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P31/TO131 1 75 P75/ANI5
P32/TCLR13 2 74 P74/ANI4
P33/TI13 3 73 P73/ANI3
P34/INTP130 4 72 P72/ANI2
P35/INTP131/SO3 5 71 P71/ANI1
P36/INTP132/SI3 6 70 P70/ANI0
P37/INTP133/SCK3 7 69 ANO0
P63/A19 8 68 ANO1
P62/A18 9 67 AVREF2
P61/A17 10 66 AVREF3
P60/A16 11 65 P07/INTP113/ADTRG
VSS 12 64 P06/INTP112
VDD 13 63 P05/INTP111
P57/AD15 14 62 P04/INTP110
P56/AD14 15 61 P03/TI11
P55/AD13 16 60 P02/TCLR11
P54/AD12 17 59 P01/TO111
P53/AD11 18 58 P00/TO110
P52/AD10 19 57 P117/INTP143
P51/AD9 20 56 P116/INTP142
P50/AD8 21 55 P115/INTP141
P47/AD7 22 54 P114/INTP140
P46/AD6 23 53 P113/TI14
P45/AD5 24 52 P112/TCLR14
P44/AD4 25 51 P111/TO141
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P43/AD3
P42/AD2
VSS
VDD
P41/AD1
P40/AD0
P90/LBEN
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
WAIT
IC
MODE
RESET
CVDD/CKSEL
X2
X1
CVSS
CLKOUT
VSS
VDD
P110/TO140
PIN NAMES
SIO
SO0/TXD0
SI0/RXD0 UART0/CSI0
SCK0
BRG0
SO1/TXD1
SI1/RXD1 UART1/CSI1 CKSEL
A/D D/A Port
SCK1 CG CLKOUT
converter converter
BRG1 X1
P110 to P117
P90 to P96
P70 to P77
P60 to P63
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P17
P00 to P07
X2
ANI0 to ANI7
AVREF1
AVSS
AVDD
ADTRG
ANO0, ANO1
AVREF2, AVREF3
SO2 MODE
SI2 CSI2 RESET
SCK2
BRG2 VDD
SO3 VSS
SI3 CSI3 CVDD
SCK3 CVSS
CONTENTS
2. PIN FUNCTIONS
(2/2)
Pin Name I/O Function Alternate Function
P60 to P63 I/O Port 6 A16 to A19
4-bit I/O port
Input/output can be specified in 1-bit units.
P70 to P77 Input Port 7 ANI0 to ANI7
8-bit input port
P90 I/O Port 9 LBEN
P91 7-bit I/O port UBEN
Input/output can be specified in 1-bit units.
P92 R/W
P93 DSTB
P94 ASTB
P95 HLDAK
P96 HLDRQ
P110 I/O Port 11 TO140
P111 8-bit I/O port TO141
Input/output can be specified in 1-bit units.
P112 TCLR14
P113 TI14
P114 INTP140
P115 INTP141
P116 INTP142
P117 INTP143
(2/2)
Pin Name I/O Function Alternate Function
SCK0 I/O Serial clock I/O (3-wire) for CSI0 to CSI3 P24
SCK1 P27
SCK2 P17/INTP123
SCK3 P37/INTP133
TXD0 Output Serial transmit data output for UART0 and UART1 P22/SO0
TXD1 P25/SO1
RXD0 Input Serial receive data input for UART0 and UART1 P23/SI0
RXD1 P26/SI1
PWM0 Output PWM pulse signal output P20
PWM1 P21
AD0 to AD7 I/O 16-bit multiplexed address/data bus for external memory expansion P40 to P47
AD8 to AD15 P50 to P57
A16 to A19 Output Higher address bus used for external memory expansion P60 to P63
LBEN Output External data bus’s lower byte enable signal output P90
UBEN External data bus’s higher byte enable signal output P91
R/W Output External read/write status output P92
DSTB External data strobe signal output P93
ASTB External address strobe signal output P94
HLDAK Output Bus hold acknowledge output P95
HLDRQ Input Bus hold request input P96
ANI0 to ANI7 Input Analog input to A/D converter P70 to P77
ANO0, ANO1 Output Analog output from D/A converter —
NMI Input Non-maskable interrupt request input —
CLKOUT Output System clock output —
CKSEL Input Input for specifying clock generator’s operation mode CVDD
WAIT Input Control signal input for inserting wait in bus cycle —
MODE Input Operation mode specification —
RESET Input System reset input —
X1 Input Resonator connection for system clock. Input is via X1 when using an —
X2 — external clock. —
ADTRG Input A/D converter external trigger input P07/INTP113
AVREF1 Input Reference voltage input for A/D converter —
AVREF2 Input Reference voltage input for D/A converter —
AVREF3 —
AVDD — Positive power supply for A/D converter —
AVSS — Ground potential for A/D converter —
CVDD — Positive power supply for on-chip clock generator CKSEL
CVSS — Ground potential for on-chip clock generator —
VDD — Positive power supply —
VSS — Ground potential —
IC — Internally connected pin (Connect directly to VSS) —
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
P110/TO140, P111/TO141
P112/TCLR14, P113/TI14 8
P114/INTP140 to P117/INTP143
ANO0, ANO1 12 Leave open.
NMI 2 Connect directly to VSS.
Type 1 Type 8
VDD
Type 2 Type 9
P-ch
IN + Comparator
–
IN N-ch
Input enable
VDD Pull-up
P-ch
enable
VDD
P-ch
OUT Data
P-ch
N-ch IN/OUT
Open drain
N-ch
Output disable
Type 5 Type 12
VDD
Data P-ch
IN/OUT
P-ch
Output N-ch Analog output voltage OUT
disable N-ch
Input
enable
3. ELECTRICAL SPECIFICATIONS
Cautions 1. Be sure to avoid direct connections among the IC device output (or I/O) pins and between
VDD or VCC and GND. However, open-drain pins and open collector pins can be directly
connected. A direct connection to an external circuit can be made to avoid conflicting output
from high-impedance pins if the external circuit is designed for the correct timing.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
Operating Conditions
Recommended Oscillator
X1 X2
Rd
C1 C2
(b) µPD703025A
X1 X2
Rd
C1 C2
X1 X2
Open
Cautions 1. Put the high-speed CMOS inverter as close to the X1 pin as possible.
2. Sufficiently evaluate the matching between the µPD703003A, 703004A, or 703025A
and the high-speed CMOS inverter.
Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V.
2. φ = Internal system clock frequency
Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V. The power supply current
does not include AVREF1 to AVREF3 or the current that flows across a software pull-up resistor.
2. φ = Internal system clock frequency
Remark TYP. values are reference values for when TA = 25°C and VDD = 5.0 V.
VDD VDD
VDD
VDDDR
tDREL
tHVD tFVD tRVD
RESET (input)
VIHDR
NMI (input)
(Released at falling edge) VIHDR
NMI (input)
(Released at rising edge)
VILDR
VDD
0.8VDD Point of 0.8VDD
mesurement
0.2VDD 0.2VDD
0V
2.4 V
2.2 V Point of 2.2 V
2.2 V 2.2 V
Point of
0.8 V mesurement 0.8 V
Load condition
DUT
(Device under testing)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert
a buffer or other element to reduce the device’s load capacitance to below 50 pF.
PLL mode 15 10 ns
Remark T = tCYK
<1>
<2> <3>
X1 (input)
<4> <5>
<6>
<11> <11> <7> <8>
CLKOUT (output)
<9> <10>
VDD
0.8VDD 0.8VDD
Input signal
0.2VDD 0.2VDD
0V
<13> <12>
2.4 V
2.2 V 2.2 V
Input signal
0.8 V 0.8 V
0.4 V
<15> <14>
2.2 V 2.2 V
Output signal
0.8 V 0.8 V
<16> <17>
<18> <19>
RESET (input)
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle.
4. Maintain at least one of the two data input hold times, either tHKID (<25>) or tHDID (<35>).
T1 T2 TW T3
CLKOUT (output)
<20> <28>
<78>
R/W (output)
UBEN (output)
LBEN (output)
<32>
<21> <24> <25>
<22> <35>
ASTB (output)
<40> <37>
<23><31>
<34> <33> <23> <36>
DSTB (output)
<38>
<39>
<47>
<46>
<48>
WAIT (input)
<41>
<43>
<42>
<44>
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
T1 T2 TW T3
CLKOUT (output)
<20> <28>
<78>
R/W (output)
UBEN (output)
LBEN (output)
<49> <51>
<22>
ASTB (output)
DSTB (output)
<39>
<47>
<46>
<48>
WAIT (input)
<41>
<43>
<42>
<44>
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
TH TH TH TH TI
CLKOUT (output)
<54>
<54><55>
<57>
HLDRQ (input)
<56> <56>
<61> <62>
HLDAK (output)
<58>
<60>
<59>
D0 to D15
AD0 to AD15 (I/O)
(input or output)
ASTB (output)
DSTB (output)
R/W (output)
Remark T = tCYK
<63> <64>
NMI (input)
<65> <66>
INTPn (input)
Remark n = 0 to 2
Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines.
Remark n = 0 to 2
Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines.
<67>
<69> <68>
SCKn (I/O)
<70> <71>
<72>
<73>
Remark T = tCYK
<74> <75>
TI1n (input)
<76> <77>
TCLR1n (input)
Remark n = 1 to 4
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
4. PACKAGE DRAWING
A
B
75 51
76 50
C D
Q R
100 26
1 25
F
G H I M J
P K
S
N S
L
M
NOTE ITEM MILLIMETERS
Each lead centerline is located within 0.08 mm of A 16.00±0.20
its true position (T.P.) at maximum material condition. B 14.00±0.20
C 14.00±0.20
D 16.00±0.20
F 1.00
G 1.00
H 0.22 +0.05
−0.04
I 0.08
J 0.50 (T.P.)
K 1.00±0.20
L 0.50±0.20
M 0.17 +0.03
−0.07
N 0.08
P 1.40±0.05
Q 0.10±0.05
R 3° +7°
−3°
S 1.60 MAX.
S100GC-50-8EU, 8EA-2
The µPD703003A, 703004A, and 703025A should be soldered and mounted under the following recommended
conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales represen-
tatives.
Note After opening a dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Santa Clara, California Benelux Office Hong Kong
Tel: 408-588-6000 Eindhoven, The Netherlands Tel: 2886-9318
800-366-9782 Tel: 040-2445845 Fax: 2886-9022/9044
Fax: 408-588-6130 Fax: 040-2444580
800-729-9288 NEC Electronics Hong Kong Ltd.
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NEC Electronics (Germany) GmbH Velizy-Villacoublay, France Seoul, Korea
Duesseldorf, Germany Tel: 01-30-67 58 00 Tel: 02-528-0303
Tel: 0211-65 03 02 Fax: 01-30-67 58 99 Fax: 02-528-4411
Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd.
NEC Electronics (UK) Ltd. Spain Office United Square, Singapore 1130
Milton Keynes, UK Madrid, Spain Tel: 65-253-8311
Tel: 01908-691-133 Tel: 91-504-2787 Fax: 65-250-3583
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Milano, Italy Scandinavia Office Tel: 02-2719-2377
Tel: 02-66 75 41 Taeby, Sweden Fax: 02-2719-5951
Fax: 02-66 75 42 99 Tel: 08-63 80 820
Fax: 08-63 80 388 NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of March, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
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M8E 00. 4