AD6620

ACCESS PROTOCOLS Write Pseudocode

The AD6620 external accesses may be performed through either void write_micro(ext_address, int data);
the Microprocessor Port or the Serial Port. The Microport and main();
the serial port both use a three-bit address and eight-bit data to {
access these registers. The three-bit address provides access to /* This code shows the programming of the NCO frequency
seven register locations (External Interface Registers). These register using the write_micro function as defined above. The
register locations are used to access the internal address space of variable address is the External Address A[2:0] and data is the
the AD6620 shown in the Control Register section. The seven value to be placed in the external interface register. The NCO
registers are the LAR (Low Address Register), the AMR (Address register is located at Internal Address = 0x303
Mode Register), and the five data registers (DR4–DR0). */
// holding registers for NCO byte wide access data
Table XI. External Interface Registers
int d3, d2, d1, d0;
A[2:0] Name Comment // NCO frequency word (32-bits wide)
000 Data Register 0 (DR0) D[7:0] NCO_FREQ = 0xCBEFEFFF;
001 Data Register 1 (DR1) D[15:8] // write AMR
010 Data Register 2 (DR2) D[23:16] write_micro(7, 0x03);
011 Data Register 3 (DR3) D[31:24]
100 Data Register 4 (DR4) D[35:32] // write LAR
101 Reserved Reserved write_micro(6, 0x03);
110 Low Address Register (LAR) A[7:0]
// DR4 is not needed because NCO_FREQ is only 32-bits, not
111 Address Mode Register (AMR) 1-0: A[9:8]
36
5-2: Reserved
// write DR3 with high byte of 32 bit word (D[31:24]
6: Read Increment
d3 = (NCO_FREQ & 0xFF000000) >> 24;
7: Write Increment
write_micro(3, d3);
The internal address space is accessed using a 10-bit internal // write DR2 with high byte of 32 bit word (D[23:16]
address. Many of these address locations are more than a byte d2 = (NCO_FREQ & 0xFF0000) >> 16;
wide and require multiple accesses to the seven External Inter- write_micro(2, d2);
face Registers, which are each only 8 bits wide (only 4 bits of
DR4 are used). Accesses to these registers are accomplished // write DR1 with D[15:8]
using the 3-bit address and 8-bit data lines the manner described d1 = (NCO_FREQ & 0xFF00) >> 8;
below. The source of these values depends on the control port write_micro(1, d1);
method used. // write DR0 with D[7:0]
All internal accesses are accomplished by first writing the inter- // Writing to DR0 causes all data to be transferred to the
nal address of the register or memory location to be accessed. internal address.
The lower eight address bits are written to the LAR register //Therefore, DR1, DR2 and DR3 should already be written
and the upper two address bits to the LSBs of the AMR. This d0 = NCO_FREQ & 0xFF;
defines the internal address of the location to be accessed as write_micro(0, d0);
shown in the memory map shown in the Control Registers and
} // end of main
On-Chip RAM section.
Internal Read Access
Internal Write Access
A read is performed by first writing the LAR and AMR as with a
Up to 36 bits of data (as needed) can be written by the process
write. The data registers (DR4–DR0) are then read in the reverse
described below. Any high order bytes that are needed are writ-
order that they were written. First, the least significant byte of
ten to the corresponding data registers defined in the external
the data (D[7:0]) is read from DR0. On this transaction the
3-bit address space. The least significant byte is then written to
high bytes of the data are moved from the internal address
DR0 at address (000). When a write to DR0 is detected, the
pointed to by the LAR and AMR into the remaining data regis-
internal microprocessor port state machine then moves the data
ters (DR4–DR1). This data can then be read from the data
in DR4–DR0 to the internal address pointed to by the address
registers using the appropriate 3-bit addresses. The number of
in the LAR and AMR.
data registers used depends solely on the amount of data to be
read or written. Any unused bit in a data register should be
masked out for a read.

REV. A –31–
AD6620
Read Pseudocode Auto Increment Feature
int read_micro(ext_address); To increase throughput, an auto increment feature is provided.
main(); This feature is controlled by Bits 6 and 7 of the AMR. If these
{ bits are set to 00, the address remains the same after an internal
/* This code shows the reading of the NCO frequency register access. If set to 01, the address is incremented after a read access
using the read_micro function as defined above. The variable has been performed. If set to 10, the address is incremented
address is the External Address A[2..0] and data is the value to after a write access is performed. If set to 11, the address is incre-
be placed in the external interface register. The NCO register is mented after each access, read or write. This allows the AD6620
located at Internal Address = 0x303. to be initialized in a much shorter time since the access to the
*/ LAR and AMR must occur only once to initialize or read-back
// holding registers for NCO byte wide access data the entire device.
int d3, d2, d1, d0;
MICROPORT CONTROL
// NCO frequency word (32-bits wide) External reads and writes are accomplished in one of two modes
// write AMR via the Microprocessor Port. The CS, RD (DS), RDY (DTACK),
write_micro(7, 0x03 ); WR (R/W) and MODE pins are used to control the access. The
specific function of these pins depends on whether the access is
// write LAR MODE 0 or MODE 1. The Mode 1 signal names are those
write_micro(6, 0x03); listed on the pinout. The access mode is controlled by the
MODE input as described in the following sections.
/* read D[7:0] from DR0, All data is moved from the Internal
Registers to the interface registers on this access. Reading
Table XII. Microprocessor Control Signals
should be initiated with a read from DR0. Therefore, DR1,
DR2 and DR3 can be read after DR0 */ MODE 0 MODE 1
d0 = read_micro(0) & 0xFF;
A[2:0] (Address Lines) A[2:0] (Address Lines)
// read D[15:8] from DR1 D[7:0] (Data Lines) D[7:0] (Data Lines)
d1 = read_micro(1) & 0xFF; CS (Chip Select) CS (Chip Select)
// read D[23:16] from DR2 RD (Read Strobe) DS (Data Strobe)
d2 = read_micro(2) & 0xFF; WR (Write Strobe) R/W (Read/Write Select)
RDY (Ready Signal) DTACK (Data Acknowledge)
// read D[31:24] from DR3 MODE (Mode Select) MODE (Mode Select)
d3 = read_micro(3) & 0xFF;
The Microport is synchronous with the master clock (CLK) of
// DR4 is not needed because NCO_FREQ is only 32-bits
the AD6620, but the interface is not required to be. If the speed
// Assemble 32-bit NCO_FREQ word from the 4 byte of the interface is significantly slower than CLK, synchronicity
components should not be an issue. If the interface is relatively fast com-
NCO_FREQ = d0 + (d1 << 8) + (d2 << 16) + (d3 << 24); pared to CLK, the user may need to synchronize the Microport
to CLK or add wait states to the controlling processor. The
} // end of main timing diagrams show the relationship of the control signals to
clock and the user should use these as a guide to implement a
Microport interface.

–32– REV. A
 AD6620
Mode = 0 is accessing the chip, the RDY line goes low at the start of
If MODE is low during the access, the interface is in Mode 0. the access. When the internal cycle is complete the RDY line
In Mode 0 the CS, RD and the WR lines control the access is released.
type. While an access is being performed, or if the serial port
t DD t HC

CLK1 N N+1 N+2 N+3 N+4 N

WR2

t SC

RD2

t HC

CS3
t ZD
t ZR
D[7:0] DATA VALID

t SAM t HA

A[2:0] ADDRESS VALID

t RDY
t RDY
RDY1

NOTES:
1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE
OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N+2" OTHERWISE.
2 THE SIGNAL, WR, MAY REMAIN HIGH AND RD MAY REMAIN LOW TO CONTINUE READ MODE.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE READ.

Figure 43. Mode 0 Read (MODE = GND)

t SC t HC

CLK1 N N+1 N+2 N+3 N*

WR2

RD2
t SC

t HC

CS3

t SAM t HM

D[7:0] DATA VALID

t SAM t HA

A[2:0] ADDRESS VALID

t RDYL t RDYH
RDY

NOTES:
1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY WR AND CS GOING LOW AND RETURNS HIGH ON THE
RISING EDGE OF CLK "N+2".
2 THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE.
*THE NEXT WRITE MAY BE INITIATED ON CLK, N.

Figure 44. Mode 0 Write (MODE = GND)

REV. A –33–
AD6620
Mode = 1 mode the DTACK signal goes low when data is available during
If the MODE input is held high the interface is in Mode 1. In a read or when data has been latched during a write. The DTACK
Mode 1 the RD signal becomes the data strobe (DS) and the signal stays low until the DS signal is released.
WR signal becomes a read/write (R/W) select signal. In this
t DD
t HC

CLK1 N N+1 N+2 N+3 N+4 N

R/W2 t SC

DS2

t SC t HC

CS3

t ZD
t ZR
D[7:0] DATA VALID

t SAM t HA

A[2:0] ADDRESS VALID

t DTACK t DTACK

DTACK

NOTES:
1 DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),

CLK "N=2" OTHERWISE.

2 THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS

AND FORCE DTACK HIGH.

Figure 45. Mode 1 Read (MODE = VDD)

t SC t HC

CLK1 N N+1 N+2 N+3 N*

R/W2

DS2

t SC t HC

CS3

t SAM t HM

D[7:0] DATA VALID

t SAM t HA

A[2:0] ADDRESS VALID

t DTACK

DTACK
t DTACK

NOTES:
1 ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW.
2 THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE

AND FORCE DTACK HIGH.

*THE NEXT WRITE MAY BE INITIATED ON CLK, N*

Figure 46. Mode 1 Write (MODE = VDD)

–34– REV. A
 AD6620
SERIAL PORT CONTROL The data is contained in the low byte of the 16 significant bits.
In addition to providing access to the complex output data stream This data will be placed into the external interface register
of the AD6620, the Serial Port can also be used for Dynamic pointed to by A[2 . . 0] for a write and will be ignored for a read.
Control of the device. The dynamic registers of the AD6620 Serial Port Writes
that are typically programmed while the chip is processing are If the WRITE bit is high and the READ bit is low then a write
listed in the table below. In order to use the serial port control, access is performed to the external interface register pointed to
the chip must first be booted using the microprocessor interface. by A[2 . . 0]. A write to an internal register takes place by first
Table XIII. Dynamic Registers writing the AMR and LAR. The data registers DR4–DR1 are
then written as needed. A final write to DR0 then moves the
Bit data to the internal register.
Address Width Name
Serial Port Reads
300 8 MODE CONTROL REGISTER If the READ bit is high, then a read to the register indicated is
302 32 NCO SYNC CONTROL REGISTER performed and the data will appear in the RDATA word appended
303 32 NCO_FREQ to the serial frame. The internal data read is loaded into the
304 16 NCO PHASE_OFFSET serial data word in FIFO fashion. The first byte read is loaded
305 8 INPUT/CIC2 SCALE REGISTER into the first eight bits, the second read during the frame is
307 5 CIC5 SCALE REGISTER loaded into the second byte, etc. Since the serial data is shifted
309 4 OUTPUT/RCF CONTROL REGISTER MSB first, the first byte will actually be loaded into the most
30B 8 RCF ADDRESS OFFSET REGISTER significant byte of the serial data word.
The internal address and data structure are shared between During a frame (the period between SDFS rising edges) up to
the microprocessor port and the serial port. When accessing four reads may occur. When a read is requested through the
the internal RAM or registers, the serial port is given priority serial port, a data word is appended to the end of the serial string.
over a microprocessor request. If a Mode 0 access occurs on Even if AD is not asserted (see below for AD description) a word is
the microport while the serial port is accessing the internal address added to the end of the IQ data stream. Therefore, if the chip is
space, the RDY line will go low and stay low until the serial in single channel mode, the I and Q data are sent followed by a
access has been completed. If a Mode 1 access occurs on the read word. If the chip is in diversity channel mode, the IQ pairs
microport during a serial access, the DTACK signal will not go are followed by a read word. Thus the serial port responds with
low until the serial access has been completed. The microport is either three or five serial words in a frame, respectively. If AD is
used for booting the AD6620 and either the microport or the asserted, the read word is sent each frame regardless of a request. If
serial port can be used to dynamically change the system param- no requests are made, the appended word is all zeros.
eters. Both ports may be used in the same design provided that The number of reads accomplished in a frame is limited by the
the handshaking rules described above are observed. serial word length. If the serial word length is 16 bits, only two
For each word shifted out of the serial port there is a word reads can be performed during a frame. If the serial word length
shifted in. Each input word can provide one internal access. Each is 24 bits, three reads can occur in a frame. If the serial word
access can be a read or a write. All reads and writes are per- length is 32 bits, then up to four reads can occur in a frame.
formed via the same 8-bit registers used by the microprocessor The RDATA word format is shown below. Rows three and four
port. Each bit in the SDI words has a predefined meaning and will not be present when 16-bit words are used, and row four
are used to decode which of these registers are being accessed will not be present when 24-bit words are used.
and whether the access is a read or a write. The bits are defined Table XV. RDATA Word Definition
according to the table below.
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Table XIV. SDI Input Word Definition DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
READ WRITE x x x A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D7 D6 D5 D4 D3 D2 D1 D0 DD7 DD6 DD5 DD4 DD3 DD3 DD1 DD0
x x x x x x x x The number of words in the serial frame depends on the operat-
x x x x x x x x ing mode of the chip (one or two I/Q pairs) and whether or not
a read access occurs. It also depends on the Append Data pin,
Only the first 16 bits of the SDI word contain significant data AD. When this signal is asserted, then the RDATA word is
regardless of the serial word length. The first two bits shifted in appended to the Serial Frame regardless of whether or not a
are the READ and WRITE indicator signals. These bits control read was performed in the frame. This allows time-slotted sys-
the access type as described below and should not be asserted tems where multiple AD6620s or other devices share a serial
simultaneously. If the Serial Port is not used for control then the port of a DSP without hardware handshakes. When AD is
SDI pin should be tied low to disable register reads and writes. high and there has not been a read during the active frame,
The three address bits are the three least significant bits of the the RDATA word is driven low and SDFE is held off for another
upper byte in the 16-bit word. These three bits A[2:0] define serial word length.
which of the seven external registers are accessed by the serial At all times, the serial interface must have time to shift all bits.
port according to Table XI. The section below Serial Port Guidelines should be consulted to
determine if sufficient time exists.
REV. A –35–